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  lxt36x/35x master clock requirements application note january 2001 order number: 249172-001 as of january 15, 2001, this document replaces the level one document known as an087 .
application note information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ? reserved ? or ? undefined. ? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt36x/35x may contain design defects or errors known as errata which may cause the product to deviate from published speci fications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
application note 3 lxt36x/35x master clock requirements contents 1.0 general description ......................................................................................................... 5 1.1 addressing master clock 20 year accuracy issue ..............................................5 figures 1 t1 jitter attenuation characteristics ..................................................................... 6 2 e1 jitter attenuation characteristics ..................................................................... 7 tables 1 lxt36x/35x t1 jitter transfer measured per att pub. 62411............................... 6 2 lxt36x/35x e1 jitter transfer measured per g.736............................................. 8

lxt36x/35x master clock requirements application note 5 1.0 general description the lxt360/61 and lxt350/51 require an external master clock (mclk) independent from rclk. the mclk was originally defined to be jitter free and its accuracy to be better than 32 ppm. a master clock (mclk) with 32 ppm accuracy requires a clock oscillator with a standard accuracy of 25 ppm. this requirement makes the clock oscillator relatively expensive. mclk is used as timing reference in the jitter attenuator and the clock recovery system. its accuracy has an impact on the ja performance. early analysis suggested that 32 ppm is the minimum clock accuracy requirement for reliable performance against g.736 and pub.62411 jitter transfer requirements. this report summarizes jitter transfer performance tests on the lxt35x/36x transceivers with worst case frequency offsets. tests have been done with mclk specified with 50 ppm and 32 ppm accuracy. from the device theory of operation, it is known that the jitter attenuator performance is sensitive to frequency offsets between the frequency of the incoming signal and the frequency of the mclk. the signal on the line is specified to be 32ppm for t1 systems (per ansi t1.408) and 50 ppm for e1 systems (per itu-g.703). in t1 applications, the maximum delta is (1.544 mhz 50 ppm) - (1.544 mhz 32 ppm) = 82 ppm. the equivalent maximum frequency deviation is 126.6 hz. table 1 on page 6 represents the jitter transfer performance measured per att pub.62411 with both 32 ppm and 50 ppm mclk stability. in both cases the performance stays well within pub62411 limits, although there is an insignificant degradation of the performance with 50 ppm vs. 32 ppm. figure 1 on page 6 shows t1 jitter transfer performance against pub. 62411. in e1 systems, the line signal stability is 50ppm. the maximum delta for e1 systems is (2.048 mhz 50 ppm) -(2.048 50 ppm) = 100 ppm. the equivalent maximum frequency deviation is 204.8 hz. table 2 on page 8 shows e1 jitter transfer performance measured per g.736 with mclk of 32 ppm and 50 ppm stability. the performance degrades insignificantly with 50 ppm but it is still well above the g.736 requirements as shown in figure 2 on page 7 . jitter tolerance performance in both t1 and e1 applications is not affected by relaxing the mclk from 32 ppm to 50 ppm. 1.1 addressing master clock 20 year accuracy issue although, today the life cycle of telecom equipment gets shorter, some systems will operate for the next 20 years. in the previous section, we concluded that the lxt36x/35x needs 50 stability on mclk. every clock oscillator undergoes an aging process and its stability will change over time. it is important to select a clock oscillator with 20 years stability with 50 ppm or better. we recommend two manufacturers of clock oscillators meeting long term (20 years) stability requirements.
lxt36x/35x master clock requirements 6 application note manufacturer part # for t1 application part # for e1 application ecliptek corp. ecx0-842- 1.544m ecx0-843-2.048m epson corp. hg-1012ja- 1544000-bx hg-1012ja- 2048000-bx figure 1. t1 jitter attenuation characteristics table 1. lxt36x/35x t1 jitter transfer measured per att pub. 62411 freq jitter atten w/mclk = 1.544 mhz 32ppm jitter atten w/mclk = 1.544 mhz 50 ppm 2-2.20 -1.50 5-6.12 -5.07 10 -13.10 -11.32 50 -21.21 -18.74 100 -28.04 -26.11 300 -32.70 -29.91
lxt36x/35x master clock requirements application note 7 500 -34.18 -32.09 1000 -53.10 -51.81 2000 -54.02 -52.12 5000 -54.31 -52.28 10000 -53.81 -51.75 40000 -54.08 -52.10 50000 -53.15 -50.91 70000 -53.04 -50.80 figure 2. e1 jitter attenuation characteristics table 1. lxt36x/35x t1 jitter transfer measured per att pub. 62411 freq jitter atten w/mclk = 1.544 mhz 32ppm jitter atten w/mclk = 1.544 mhz 50 ppm
lxt36x/35x master clock requirements 8 application note table 2. lxt36x/35x e1 jitter transfer measured per g.736 freq jitter atten w/mclk = 2.048 mhz 32ppm [db] jitter atten w/ mclk = 2.048 mhz 50 ppm [db] 2 -1.72 -1.30 5 -7.78 -6.22 10 -11.38 -9.63 50 -21.09 -18.81 100 -33.18 -30.12 300 -42.55 39.22 500 -50.97 -48.51 1000 -57.64 -56.31 2000 -58.01 -56.41 5000 -58.08 -56.51 10000 -58.90 -56.50 40000 -58.81 -56.53 50000 -59.10 -56.82 70000 -58.72 -55.94


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