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? semiconductor components industries, llc, 2003 april, 2003 - rev. 3 1 publication order number: nb100lvep56/d nb100lvep56 2.5v / 3.3v / 5vecl dual differential 2:1 multiplexer the nb100lvep56 is a dual, fully differential 2:1 multiplexer. the differential data path makes the device ideal for multiplexing low skew clock or differential data signals. the device features both individual and common select inputs to address both data path and random logic applications. common and individual selects can accept both ecl and cmos input voltage levels. multiple v bb pins are provided. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input operation, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? maximum input clock frequency > 2.5 ghz typical ? maximum input data rate > 2.5 gb/s typical ? 525 ps typical propagation delays ? low profile qfn package ? pecl mode operating range: v cc = 2.375 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = -2.375 v to -5.5 v ? separate, common select, and individual select (compatible with ecl and cmos input voltage levels) ? q output will default low with inputs open or at v ee ? multiple v bb outputs device package shipping ordering information NB100LVEP56Dt tssop-20 75 units/rail NB100LVEP56Dtr2 2500 tape & reel tssop-20 dt suffix case 948e marking diagrams* *for additional information, see application note and8002/d n100 lp56 alyw 20 1 tssop-20 1 20 http://onsemi.com a = assembly location l = wafer lot y = year w = work week n100 lp56 alyw 1 24 24 pin qfn mn suffix case 485l 24 1 nb100lvep56mn qfn-24 92 units/rail nb100lvep56mnr2 3000 tape & reel qfn-24
nb100lvep56 http://onsemi.com 2 table 1. pin description pin no. default tssop qfn name i/o defa u lt state description 14,20 3,9,18,19, 20 v cc - - positive supply voltage. all vcc pins must be externally con- nected to power supply to guarantee proper operation. 11 15,24 v ee - - negative supply voltage. all vee pins must be externally con- nected to power supply to guarantee proper operation. 3,8 6,12 v bb0 , v bb1 - - ecl reference voltage output 1 4 d0a ecl input low noninverted differential data a input to mux 0. internal 75 k to v ee . 2 5 d0a ecl input high inverted differential data a input to mux 0. internal 75 k to v ee and 37 k to v cc . 4 7 d0b ecl input low noninverted differential data b input to mux 0. internal 75 k to v ee . 5 8 d0b ecl input high inverted differential data b input to mux 0. internal 75 k to v ee and 37 k to v cc . 6 10 d1a ecl input low noninverted differential data a input to mux 1. internal 75 k to v ee . 7 11 d1a ecl input high inverted differential data a input to mux 1. internal 75 k to v ee and 37 k to v cc . 9 13 d1b ecl input low noninverted differential data b input to mux 1. internal 75 k to v ee . 10 14 d1b ecl input high inverted differential data b input to mux 1. internal 75 k to v ee and 37 k to v cc . 19 2 q0 ecl output - noninverted differential output mux 0. typically terminated with 50 to v tt = v cc - 2 v. 18 1 q0 ecl output - inverted differential output mux 0. typically terminated with 50 to v tt = v cc - 2 v. 13 17 q1 ecl output - noninverted differential output mux 1. typically terminated with 50 to v tt = v cc - 2 v. 12 16 q1 ecl output - inverted differential output mux 1. typically terminated with 50 to v tt = v cc - 2 v. 17 23 sel0 ecl, cmos input low noninverted differential select input to mux 0. internal 75 to v ee . 16 22 com_sel ecl, cmos input low noninverted differential common select input to both mux. in- ternal 75 to v ee . 15 21 sel1 ecl, cmos input low noninverted differential select input to mux 1. internal 75 to v ee . n/a - ep - exposed pad. (note 1) 1. the thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.
nb100lvep56 http://onsemi.com 3 d0b d0b d0b d1a v bbo q0 sel0 sel1 v cc q1 q1 v ee d0a v cc q0 d1a d0a com_sel v bb1 d1b d1b sel0 x l l h h table 2. truth table q0, q0 a b b a a sel1 x l h h l com_sel h l l l l q1, q1 a b a a b 17 18 16 15 14 13 12 4 3 5678 9 11 10 19 20 2 1 nb100lvep56 figure 1. tssop-20 lead pinout (top view) q1 q1 v cc q0 18 12 4 3 5 6 789 d0b 11 10 v cc d0a v ee sel0 sel1 2 1 d1a d1a v cc com sel v cc 17 16 15 14 13 v cc 19 24 23 22 20 21 nb100lvep56 figure 2. qfn-24 lead pinout (top view) v ee q0 d0a v bb0 v bb1 d1b d1b exposed pad (ep) d0b d0b d1a q0 sel0 sel1 q1 q1 v ee d0a q0 d1a d0a com_sel d1b d1b 1 0 1 0 figure 1. logic diagram v cc r 1 r 2 r 1 r 2 r 1 r 2 r 1 r 2 r 1 r 1 r 1 r 1 r 1 r 1 r 1 table 3. attributes characteristics value internal input pulldown resistor (r1) 75 k internal input pullup resistor (r2) 37 k esd protection human body model machine model charged device model > 2 kv > 150 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 354 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
nb100lvep56 http://onsemi.com 4 table 4. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating unit v cc positive mode power supply v ee = 0 v 6 v v ee negative mode power supply v cc = 0 v -6 v v i positive mode input voltage negative mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 -6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) jedec 51-3 (1s - single layer test board) 0 lfpm 500 lfpm 20 tssop 20 tssop 140 50 c/w c/w ja thermal resistance (junction-to-ambient) jedec 51-6 (2s2p-multi layer test board) with filled thermal vias 0 lfpm 500 lfpm 24 qfn 24 qfn 37 32 c/w c/w jc thermal resistance (junction-to-case) standard board 20 tssop 24 qfn 23 to 41 11 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. table 5. dc characteristics, pecl v cc = 2.5 v, v ee = 0 v (note 3) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 35 45 55 35 45 55 35 48 58 ma v oh output high voltage (note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 4) 555 775 900 555 775 900 555 775 900 mv v ih input high voltage (sel0, sel1, com_sel) input high voltage (d inputs) (note 5) 1335 1335 v cc 1620 1335 1335 v cc 1620 1275 1275 v cc 1620 mv v il input low voltage (sel0, sel1, com_sel) input low voltage (d inputs) (note 5) v ee 555 875 875 v ee 555 875 875 v ee 555 875 875 mv v ihcmr input high voltage common mode range (differential configuration) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current (@v ih ) 150 150 150 a i il input low current (@v il )d d sel 0.5 -150 -150 0.5 -150 -150 0.5 -150 -150 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to -1.3 v. 4. all loading with 50 to v cc -2.0 v. 5. do not use v bb at v cc < 3.0 v. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep56 http://onsemi.com 5 table 6. dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 7) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 35 45 55 35 45 55 35 48 58 ma v oh output high voltage (note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 8) 1355 1575 1700 1355 1575 1700 1355 1575 1700 mv v ih input high voltage (sel0, sel1, com_sel) input high voltage (d inputs) 2135 2135 v cc 2420 2135 2135 v cc 2420 2135 2135 v cc 2420 mv v il input low voltage (sel0, sel1, com_sel) input low voltage (d inputs) v ee 1355 1675 1675 v ee 1355 1675 1675 v ee 1355 1675 1675 mv v bb output reference voltage (note 9) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current (@v ih ) 150 150 150 a i il input low current (@v il )d d sel 0.5 -150 -150 0.5 -150 -150 0.5 -150 -150 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 7. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to -0.5 v. 8. all loading with 50 to v cc -2.0 v. 9. single-ended input operation is limited to v cc 3.0 v in pecl mode. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 7. dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 11) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 40 50 60 40 50 60 45 55 65 ma v oh output high voltage (note 12) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 12) 3055 3275 3400 3055 3275 3400 3055 3275 3400 mv v ih input high voltage (sel0, sel1, com_sel) input high voltage (d inputs) 3775 3775 v cc 4120 3775 3775 v cc 4120 3775 3775 v cc 4120 mv v il input low voltage (sel0, sel1, com_sel) input low voltage (d inputs) v ee 3055 3375 3375 v ee 3055 3375 3375 v ee 3055 3375 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential configuration) (note 13) 1.2 5.0 1.2 5.0 1.2 5.0 v i ih input high current (@v ih ) 150 150 150 a i il input low current (@v il )d d sel 0.5 -150 -150 0.5 -150 -150 0.5 -150 -150 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to -0.5 v. 12. all loading with 50 ohms to v cc -2.0 v. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep56 http://onsemi.com 6 table 8. dc characteristics, necl v cc = 0 v, v ee = -3.8 v to -2.375 v (note 14) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 35 45 55 35 45 55 35 48 58 ma v oh output high voltage (note 15) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mv v ol output low voltage (note 15) -1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600 mv v ih input high voltage (sel0, sel1, com_sel) input high voltage (d inputs) -1 165 -1 165 v cc -880 -1 165 -1 165 v cc -880 -1 165 -1 165 v cc -880 mv v il input low voltage (sel0, sel1, com_sel) input low voltage (d inputs) v ee -1945 -1600 -1600 v ee -1945 -1600 -1600 v ee -1945 -1600 -1600 mv v bb output reference voltage (note 16) -1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 17) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current (@v ih ) 150 150 150 a i il input low current (@v il )d d sel 0.5 -150 -150 0.5 -150 -150 0.5 -150 -150 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 14. input and output parameters vary 1:1 with v cc . 15. all loading with 50 to v cc -2.0 v. 16. single-ended input operation is limited to v ee from -3.0 v to -5.5 v in necl mode. 17. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 9. dc characteristics, necl v cc = 0 v, v ee = -3.8 v to -5.5 v (note 18) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 40 50 60 40 50 60 45 55 65 ma v oh output high voltage (note 19) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mv v ol output low voltage (note 19) -1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600 mv v ih input high voltage (sel0, sel1, com_sel) input high voltage (d inputs) -1 165 -1 165 v cc -880 -1 165 -1 165 v cc -880 -1 165 -1 165 v cc -880 mv v il input low voltage (sel0, sel1, com_sel) input low voltage (d inputs) v ee -1945 -1600 -1625 v ee -1945 -1600 -1625 v ee -1945 -1600 -1625 mv v bb output reference voltage (note 20) -1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 21) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current (@v ih ) 150 150 150 a i il input low current (@v il )d d sel 0.5 -150 -150 0.5 -150 -150 0.5 -150 -150 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. input and output parameters vary 1:1 with v cc . 19. all loading with 50 to v cc -2.0 v. 20. single-ended input operation is limited to v ee from -3.0 v to -5.5 v in necl mode. 21. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep56 http://onsemi.com 7 table 10. ac characteristics v cc = 0 v; v ee = -2.375 v to -3.8 v or v cc = 2.375 v to 3.8 v; v ee = 0 v (note 22) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v outpp output voltage amplitude f in 1 ghz (see figure 2) f in = 2 ghz f in = 2.5 ghz 525 500 400 700 600 500 550 500 350 700 600 450 500 400 200 700 500 300 mv t plh , t phl propagation delay to output differential d to q, q sel to q, q com_sel to q, q 375 575 550 500 775 750 625 975 950 400 625 600 525 825 800 650 1025 1000 450 700 700 575 900 900 700 1100 1100 ps t skew pulse skew (note 23) within device input skew (note 24) within device output skew (note 25) device-to-device skew (note 26) 10 5 15 50 50 30 50 200 10 5 15 50 10 5 15 50 50 30 50 200 ps t jitter rms random clock jitter f in = 2.5 ghz (note 27) peak-to-peak data dependent jitter f in =1.5 gb/s (note 28) f in = 2.5 gb/s 5 15 1 10 25 1 10 25 1 ps v inpp input voltage swing (differential configuration) (note 29) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times @ 50 mhz q, q (20% - 80%) 60 110 150 60 120 170 90 140 230 ps 22. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc -2.0 v. input edge rates 150 ps (20% - 80%). 23. pulse skew |t plh - t phl | 24. worst case difference between d0a and d0b (or between d1a or d1b), when both output come from same input. 25. worst case difference between q0 and q1 outputs. 26. skew is measured between outputs under identical transitions. 27. additive rms jitter with 50% duty cycle clock signal at f in = 2.5 ghz. 28. additive peak-to-peak jitter with input nrz data at prbs 2 31 -1 at f in = 2.5 gb/s. 29. input voltage swing is a single-ended measurement operating in differential mode. table 11. ac characteristics v cc = 0 v; v ee = -4.2 v to -5.5 v or v cc = 4.2 v to 5.5 v; v ee = 0 v (note 30) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v outpp output voltage amplitude f in 1 ghz (see figure 3) f in = 2 ghz f in = 2.5 ghz 600 550 400 750 650 550 600 500 350 750 600 450 600 400 200 750 500 300 mv t plh , t phl propagation delay to output differential d to q, q sel to q, q com_sel to q, q 375 575 550 500 775 750 625 975 950 400 625 600 525 825 800 650 1025 1000 450 700 700 575 900 900 700 1100 1100 ps t skew pulse skew (note 31) within device input skew (note 32) within device output skew (note 33) device-to-device skew (note 34) 5 15 20 50 50 30 50 200 5 15 20 50 50 30 50 200 5 15 20 50 50 30 50 200 ps t jitter rms random clock jitter f in = 2.5 ghz (note 35) peak-to-peak data dependent jitter f in =1.5 gb/s (note 36) f in = 2.5 gb/s 5 15 1 10 25 1 10 20 1 ps v inpp input voltage swing (differential configuration) (note 37) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times @ 50 mhz q, q (20% - 80%) 60 110 150 60 120 170 90 140 230 ps 30. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc -2.0 v. input edge rates 150 ps (20% - 80%). 31. pulse skew |t plh - t phl | 32. worst case difference between d0a and d0b (or between d1a or d1b), when both output come from same input. 33. worst case difference between q0 and q1 outputs. 34. skew is measured between outputs under identical transitions. 35. additive rms jitter with 50% duty cycle clock signal at f in = 2.5 ghz. 36. additive peak-to-peak jitter with input nrz data at prbs 2 31 -1 at f in = 2.5 gb/s. 37. input voltage swing is a single-ended measurement operating in differential mode.
nb100lvep56 http://onsemi.com 8 figure 2. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at v cc = 2.5 v, 25 c input frequency (ghz) output voltage amplitude (mv) 250 350 450 550 650 750 850 0.5 1.0 1.5 2.0 2.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 rms jitter (ps) q amp (mv) jitter (ps) 250 350 450 550 650 750 850 0.5 1.0 1.5 2.0 2.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 input frequency (ghz) output voltage amplitude (mv) rms jitter (ps) q amp (mv) jitter (ps) figure 3. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at v cc = 5.0 v, 25 c figure 4. ac reference measurement d d q q t phl t plh v inpp = v ih (d) - v il (d) v outpp = v oh (q) - v ol (q)
nb100lvep56 http://onsemi.com 9 q v tt = v cc - 2.0 v driver device receiver device qd 50 50 v tt figure 5. typical termination for output driver and device evaluation (see application note and8020 - termination of ecl logic devices.) d resource reference of application notes an1404 - eclinps circuit performance at non-standard v ih levels an1405 - ecl clock distribution techniques an1406 - designing with pecl (ecl at +5.0 v) an1504 - metastability and the eclinps family an1568 - interfacing between lvds and ecl an1672 - the ecl translator guide and8002 - marking and date codes and8009 - eclinps plus spice i/o model kit and8020 - termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
nb100lvep56 http://onsemi.com 10 package dimensions tssop-20 dt suffix plastic tssop package case 948e-02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 110 11 20 pin 1 ident a b -t- 0.100 (0.004) c d g h section n-n k k1 jj1 n n m f -w- seating plane -v- -u- s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. icontrolling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-.
nb100lvep56 http://onsemi.com 11 package dimensions qfn 24 mn suffix 24 pin qfn, 4x4 case 485l-01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d b 0.15 c a2 a a3 a e pin 1 identification 2x 0.15 c 2x 0.08 c 0.10 c a1 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.23 0.28 d 4.00 bsc d2 2.70 2.90 e 4.00 bsc e2 2.70 2.90 e 0.50 bsc l 0.35 0.45 24x l d2 b 1 6 7 18 13 19 e 12 e2 e 24 0.10 b 0.05 a c c ref
nb100lvep56 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nb100lvep56/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada

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