philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) 17 october 22, 1993 8531508 11164 description the plus15310 pld is a high speed, combinatorial programmable logic array . the philips semiconductors state-of-the-art oxide isolated bipolar fabrication process is employed to produce maximum propagation delays of 10ns or less. the 20-pin plus153 device has a programmable and array and a programmable or array. unlike pal ? devices, 100% product term sharing is supported. any of the 32 logic product terms can be connected to any or all of the 10 output or gates. most pal ics are limited to 7 and terms per or function; the plus15310 can support up to 32 input wide or functions. the polarity of each output is user- programmable as either active-high or active-low, thus allowing and-or or and-nor logic implementation. this feature adds an element of design flexibility , particularly when implementing complex decoding functions. the plus15310 device is user- programmable using one of several commercially available, industry standard pld programmers. features ? i/o propagation delays (worst case) plus15310 10ns max. ? functional superset of 16l8 and most other 20-pin combinatorial pal devices ? two programmable arrays supports 32 input wide or functions ? 8 inputs ? 10 bi-directional i/o ? 42 and gates 32 logic product terms 10 direction control terms ? programmable output polarity active-high or active-low ? security fuse ? 3-state outputs ? power dissipation: 825mw (typ.) ? ttl compatible applications ? random logic ? code converters ? fault detectors ? function generators ? address mapping ? multiplexing pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 n package i0 i1 i2 i3 i4 i5 i6 i7 b0 b2 gnd b3 b4 b5 b6 b7 b8 b9 v cc b1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a package n = plastic dip (300mil-wide) a = plastic leaded chip carrier b4 b5 b6 b7 b8 b2 b3 b1 b0 gnd i3 i4 i5 i6 i7 i0 i1 i2 b9 v cc ordering information description t pd (max) order code drawing number 20-pin plastic dual-in-line 300mil-wide 10ns plus15310n 0408d 20-pin plastic leaded chip carrier 10ns plus15310a 0400e ? pal is a registered trademark of advanced micro devices corporation.
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 18 logic diagram notes: 1. all programmed `and' gate locations are pulled to logic a1o. 2. all programmed `or' gate locations are pulled to logic a0o. 3. programmable connection. (logic termsp) (control terms) 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 i0 i1 i2 i3 i4 i5 i6 i7 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 31 24 23 16 15 8 7 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 19 functional diagram p 31 p 0 d 0 d 9 i0 i7 b0 b9 b9 b0 s 0 s 9 x 9 x 0 absolute maximum ratings 1 thermal ratings rating symbol parameter min max unit v cc supply voltage +7 v dc v in input voltage +5.5 v dc v out output voltage +5.5 v dc i in input currents 30 +30 ma i out output currents +100 ma t amb operating free-air temperature range 0 +75 c t stg storage temperature range 65 +150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise 75 c ambient to junction
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 20 dc electrical characteristics 0 c t amb +75 c, 4.75 v cc 5.25v limits symbol parameter test conditions min typ 1 max unit input voltage 2 v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v ic clamp v cc = min, i in = 12ma 0.8 1.2 v output voltage 2 v cc = min v ol low 4 i ol = 15ma 0.4 0.5 v v oh high 5 i oh = 2ma 2.4 2.9 v input current 9 v cc = max i il low v in = 0.45v 20 100 m a i ih high v in = v cc 1 40 m a output current v cc = max i o(off) hi-z state 8 v out = 2.7v 0 80 m a v out = 0.45v 15 140 i os short circuit 3, 5, 6 v out = 0v 15 30 70 ma i cc v cc supply current 7 v cc = max 165 200 ma capacitance v cc = 5v c in input v in = 2.0v 8 pf c b i/o v b = 2.0v 15 pf notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. test one at a time. 4. measured with inputs i0 i2 = 0v , inputs i3 i5 = 4.5v , inputs i7 = 4.5v and i6 = 10v . for outputs b0 b4 and for outputs b5 b9 apply the same conditions except i7 = 0v. 5. same conditions as note 4 except i7 = +10v . 6. duration of short circuit should not exceed 1 second. 7. i cc is measured with inputs i0 i7 and b0 b9 = 0v . 8. leakage values are a combination of input and output leakage. 9. i il and i ih limits are for dedicated inputs only (i0 i7).
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 21 ac electrical characteristics 0 c t amb +75 c, 4.75v v cc 5.25v, r 1 = 300 w , r 2 = 390 w test limits symbol parameter from to condition min typ max unit t pd propagation delay 2 input +/ output +/ c l = 30pf 8 10 ns t oe output enable 1 input +/ output c l = 30pf 8 10 ns t od output disable 1 input +/ output + c l = 5pf 8 10 ns notes: 1. for 3-state output; output enable times are tested with c l = 30pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf . high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 2. all propagation delays are measured and specified under worst case conditions. voltage waveforms measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. 90% 10% 5ns 5ns 5ns 5ns 90% 10% +3.0v +3.0v 0v 0v t r t f input pulses timing definitions symbol parameter t pd propagation delay between input and output. t od delay between input change and when output is off (hi-z or high). t oe delay between input change and when output reflects specified output level. test load circuit timing diagram +5v c l r 1 r 2 s 1 gnd b z b y inputs i0 i7 b w b x outputs c 2 c 1 dut note: c 1 and c 2 are to bypass v cc to gnd. v cc +3v 0v v oh v ol i, b b t pd 1.5v 1.5v 1.5v 1.5v 1.5v t od t oe v t
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 22 logic programming the plus15310 is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software package. abel ? and cupl ? design software packages also support the plus15310 architecture. all packages allow boolean and state equation entry formats. snap, abel and cupl also accept, as input, schematic capture format. plus15310 logic designs can also be generated using the program table entry format, which is detailed on the following page. this program table entry format is supported by snap only. t o implement the desired logic functions, the state of each logic variable from logic equations (i, b, o, p, etc.) is assigned a symbol. the symbols for true, complement, inactive, preset, etc., are defined below. programming and software support refer to section 9 (development software) and section 10 (third-party programmer/software support) of this data handbook for additional information. and array (i, b) code o state inactive 1, 2 code state code state code state i, b h l p, d i, b i , b i, b i , b p, d i, b i , b i, b p, d i, b i , b i, b p, d i, b i , b i, b don't care or array (b) virgin state a factory shipped virgin device contains all fusible links intact, such that: 1. all outputs are at aho polarity. 2. all p n terms are disabled. 3. all p n terms are active on all outputs. notes: 1. this is the initial unprogrammed state of all links. 2. any gate p n will be unconditionally inhibited if both the true and complement of an input (either i or b) are left intact. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc. code active level low (inverting) l code active level high 1 (non-inverting) h s x b s x b output polarity (b) code inactive a code p n status active 1 ? p s p n status p s
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 23 program table 8 polarity 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pin t e r m and or active inactive control high low a inactive h l b(0) (pol) don't care i, b i, b i, b(i) customer name philips device # program t able # rev date 0 h l e variable name and or b(0) 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 b(i) 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9 19 18 17 16 15 14 13 12 11 9 purchase order # cf(xxxx) customer symbolized p art # total number of p arts i 0 notes in the unprogrammed state: output polarity is noninverting. unused i and b bits in the and array should be programmed unused product terms in the or array should be as don't care (). all and gates are pulled to a logic a0o (low). programmed as inactive (o).
philips semiconductors programmable logic devices product specification plus15310 programmable logic array (18 42 10) october 22, 1993 24 snap resource summary designations cand p 31 p 0 d 0 d 9 i0 i7 b0 b9 b9 b0 s 0 s 9 x 9 x 0 din153 nin153 or tout153 and exor153 din153 nin153
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