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64mx72 bits low profile registered ddr sdram dimm this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.2/may. 02 1 hymd264g726a(l)8m-m/k/h/l description hynix hymd264g726a(l)8m-m/k/h/l series is low profile registered 184-pin double data rate synchronous dram dual in-line memory modules (dimms) which are organized as 64mx72 high-speed memory arrays. hynix hymd264g726a(l)8m-m/k/h/l series consists of eighteen 32mx8 ddr sdram in 400mil tsop ii packages on a 184pin glass-epoxy substrate. hynix hymd264g726a(l)8m-m/k/h/l series provide a high performance 8-byte inter- face in 5.25" width form factor of industry standard. it is suitable for easy interchange and addition. hynix hymd264g726a(l)8m-m/k/h/l series is designed for high speed of up to 133mhz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. high speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. hynix hymd264g726a(l)8m-m/k/h/l series incorporates spd(serial presence detect). serial presence detect function is implemented via a serial 2,048-bit eeprom. the first 128 bytes of serial pd data are programmed by hynix to iden- tify dimm type, capacity and other the information of dimm and the last 128 bytes are available to the customer. features o rdering information part no. power supply clock frequency interface form factor hymd264g726a(l)8m-m v dd =2.5v v ddq =2.5v 133mhz (*ddr266:2-2-2) sstl_2 184pin low profile registered dimm 5.25 x 1.2 x 0.15 inch hymd264g726a(l)8m-k 133mhz (* ddr266a) hymd264g726a(l)8m-h 133mhz (* ddr266b) hymd264g726a(l)8m-l 100mhz (* ddr200) ? 512mb (64m x 72) low profile registered ddr dimm based on 32mx8 ddr sdram ? jedec standard 184-pin dual in-line memory module (dimm) ? error check correction (ecc) capability ? registered inputs with one-clock delay ? phase-lock loop (pll) clock driver to reduce loading ? 2.5v +/- 0.2v vdd and vddq power supply ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock operations (ck & /ck) with 100mhz/125mhz/133mhz ? programmable cas latency 2 / 2.5 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? tras lock-out function supported ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms * jedec defined specifications compliant preliminary
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 2 pin description pin assignment pin pin description pin pin description ck0, /ck0 differential clock inputs vddq dqs power supply cs0, cs1 chip select input vss ground cke0, cke1 clock enable input vref reference power supply /ras, /cas, /we commend sets inputs vddspd power supply for spd a0 ~ a12 address sa0~sa2 e 2 prom address inputs ba0, ba1 bank address scl e 2 prom clock dq0~dq64 data inputs/outputs sda e 2 prom data i/o cb0~cb7 data strobe inputs/outputs wp write protect flag dqs0~dqs7 data strobe inputs/outputs vddid vdd identification flag dm0~8 data-in mask du do not use vdd power supply nc no connection /reset reset enable feten fet enable pin name pin name pin name pin name pin name pin name 1 vref 32 a5 62 vddq 93 vss 124 vss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 vss 34 vss 64 dq41 95 dq5 126 dq28 156 vddq 4 dq1 35 dq25 65 /cas 96 vddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 vss 97 dm0 128 vddq 158 /cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 vdd 38 vdd 68 dq42 99 dq7 130 a3 160 vss 8 dq3 39 dq26 69 dq43 100 vss 131 dq30 161 dq46 9 nc 40 dq27 70 vdd 101 nc 132 vss 162 dq47 10 /reset 41 a2 71 nc 102 nc 133 dq31 163 nc 11 vss 42 vss 72 dq48 103 a13* 134 cb4 164 vddq 12 dq8 43 a1 73 dq49 104 vddq 135 cb5 165 dq52 13 dq9 44 cb0 74 vss 105 dq12 136 vddq 166 dq53 14 dqs1 45 cb1 75 du 106 dq13 137 ck0 167 nc, feten* 15 vddq 46 vdd 76 du 107 dm1 138 /ck0 168 vdd 16 du 47 dqs8 77 vddq 108 vdd 139 vss 169 dm6 17 du 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 vss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 vss 80 dq51 111 cke1 142 cb6 172 vddq 20 dq11 51 cb3 81 vss 112 vddq 143 vddq 173 nc 21 cke0 52 ba1 82 vddid 113 ba2* 144 cb7 174 dq60 22 vddq key 83 dq56 114 cb7 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 vss 176 vss 24 dq17 54 vddq 85 vdd 116 vss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 vss 56 dqs4 87 dq58 118 a11 148 vdd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 vddq 28 dq18 58 vss 89 vss 120 vdd 150 dq38 181 sa0 29 a7 59 ba0 90 wp 121 dq22 151 dq39 182 sa1 30 vddq 60 dq35 91 sda 122 a8 152 vss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd * these are not used on this module but may be used for other module in 184pin dimm family
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 3 functional block diagram / rcs1 dqs0 / rcs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 / cs dm dm0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d9 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 / cs dm dm1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d10 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 / cs dm dm2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d11 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 / cs dm dm3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d12 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 / cs dm dm4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d13 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 / cs dm dm5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d14 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 / cs dm dm6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d15 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 / cs dm dm7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d16 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dqs5 dqs6 dqs7 dqs1 dqs2 dqs3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 / cs dm dm8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq - to - i/o wiring may be changed within a byte 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 18 ohms. 4. vddid strap connections(for memory device vdd, vddq); strap out :(open) : vdd=vddq strap in ( vss ) : vdd=vddq 5. /rs0 and /rs1 alternate btw the back and front sides of the d imm 6. address and control resistors should be 22 ohms scl serial pd a0 a1 a2 sa0 sa1 sa2 wp sda / rcs0 -- >/cs0 : sdrams d0 - d8 /rcs1 -- >/cs1 : sdrams d9 - d17 rba0 - rba1 -- > : ba0 - ba1: sdrams d0 - d17 ra0 - r a12 -- >a0 - a12 : sdrams d0 - d17 /rras -- > /ras : sdrams d0 - d17 /rcas -- > /cas : sdrams d0 - d17 rcke0 -- > cke : sdrams d0 - d8 rcke1 -- > cke : sdrams d9 - d17 /rwe -- > /we : sdrams d0 - d17 / cs0 /cs1 ba0 - ba1 a0 - a12 /ras /cas cke0 cke1 /we r e g pck / pck / reset ck0, /ck0 --------- pll* * wire per clock loading table/wiring diagrams . . vddspd vref vss vddid d0 - d17 d0 - d17 d0 - d17 d0 - d17 = . = . . = . . . . . strap:see note 4 vdd spd vddq = . . / rcs1 dqs0 / rcs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 / cs dm dm0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d9 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 / cs dm dm1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d10 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 / cs dm dm2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d11 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 / cs dm dm3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d12 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 / cs dm dm4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d13 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 / cs dm dm5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d14 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 / cs dm dm6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d15 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 / cs dm dm7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d16 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dqs5 dqs6 dqs7 dqs1 dqs2 dqs3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 / cs dm dm8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq - to - i/o wiring may be changed within a byte 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 18 ohms. 4. vddid strap connections(for memory device vdd, vddq); strap out :(open) : vdd=vddq strap in ( vss ) : vdd=vddq 5. /rs0 and /rs1 alternate btw the back and front sides of the d imm 6. address and control resistors should be 22 ohms scl serial pd a0 a1 a2 sa0 sa1 sa2 wp sda / rcs0 -- >/cs0 : sdrams d0 - d8 /rcs1 -- >/cs1 : sdrams d9 - d17 rba0 - rba1 -- > : ba0 - ba1: sdrams d0 - d17 ra0 - r a12 -- >a0 - a12 : sdrams d0 - d17 /rras -- > /ras : sdrams d0 - d17 /rcas -- > /cas : sdrams d0 - d17 rcke0 -- > cke : sdrams d0 - d8 rcke1 -- > cke : sdrams d9 - d17 /rwe -- > /we : sdrams d0 - d17 / cs0 /cs1 ba0 - ba1 a0 - a12 /ras /cas cke0 cke1 /we r e g pck / pck / reset ck0, /ck0 --------- pll* * wire per clock loading table/wiring diagrams . . vddspd vref vss vddid d0 - d17 d0 - d17 d0 - d17 d0 - d17 = . = . . = . . . . . strap:see note 4 vdd spd vddq = . . dqs0 / rcs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 / cs dm dm0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d9 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 / cs dm dm1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d10 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 / cs dm dm2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d11 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 / cs dm dm3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d12 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 / cs dm dm4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d13 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 / cs dm dm5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d14 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 / cs dm dm6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d15 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 / cs dm dm7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d16 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dqs5 dqs6 dqs7 dqs1 dqs2 dqs3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 / cs dm dm8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs / cs dm dqs d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq - to - i/o wiring may be changed within a byte 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 18 ohms. 4. vddid strap connections(for memory device vdd, vddq); strap out :(open) : vdd=vddq strap in ( vss ) : vdd=vddq 5. /rs0 and /rs1 alternate btw the back and front sides of the d imm 6. address and control resistors should be 22 ohms scl serial pd a0 a1 a2 sa0 sa1 sa2 wp sda / rcs0 -- >/cs0 : sdrams d0 - d8 /rcs1 -- >/cs1 : sdrams d9 - d17 rba0 - rba1 -- > : ba0 - ba1: sdrams d0 - d17 ra0 - r a12 -- >a0 - a12 : sdrams d0 - d17 /rras -- > /ras : sdrams d0 - d17 /rcas -- > /cas : sdrams d0 - d17 rcke0 -- > cke : sdrams d0 - d8 rcke1 -- > cke : sdrams d9 - d17 /rwe -- > /we : sdrams d0 - d17 / cs0 /cs1 ba0 - ba1 a0 - a12 /ras /cas cke0 cke1 /we r e g pck / pck / reset ck0, /ck0 --------- pll* * wire per clock loading table/wiring diagrams . . vddspd vref vss vddid d0 - d17 d0 - d17 d0 - d17 d0 - d17 = . = . . = . . . . . strap:see note 4 vdd spd vddq = . .
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. the value of v ref is approximately equal to 0.5v ddq . ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the s ame. parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 18 w soldering temperature time t solder 260 / 10 o c / sec parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 3 parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 5 ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 w series resistor (r s ) 25 w output load capacitance for access time measurement (c l ) 30 pf
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 6 v ref v tt r t =50 w zo =50 w c l =30 pf output capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, vodc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input capacitance a0 ~ a12, ba0, ba1 c in1 tbd tbd pf input capacitance /ras, /cas, /we c in2 tbd tbd pf input capacitance cke0, cke1 c in3 tbd tbd pf input capacitance cs0, cs1 c in4 tbd tbd pf input capacitance ck0, /ck0 c in5 tbd tbd pf input capacitance dm0 ~ dm8 c in6 tbd tbd pf data input / output capacitance dq0 ~ dq63, dqs0 ~ dqs8 c io1 tbd tbd pf data input / output capacitance cb0 ~ cb7 c io2 tbd tbd pf
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 7 dc characteristics i (ta=0 to 70c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pins are not tested under v in =0v 2. d out is disabled, v out =0 to 2.7v parameter symbol min. max unit note input leakage current add, cmd, /cs, /cke i li -2 2 ua 1 ck, /ck -4 4 output leakage current i lo -10 10 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol - v tt - 0.76 v i ol = +15.2ma
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 8 dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition speed unit note -m -k -h -l operating current idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2135 1955 1955 1910 ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 2540 2270 2270 2180 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 1010 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 1550 1370 1370 1280 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 1100 ma active standby current i dd3n /cs=high; cke=high; one bank; active- precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 1730 1550 1550 1550 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck (min); iout=0ma 3800 3350 3350 2810 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm, and dqs inputs changing twice per clock cycle 3800 3350 3350 2810 auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 2960 2690 2690 2555 self refresh current i dd6 cke=<0.2v; external clock on; tck =tck(min) normal 404 ma low power 377 ma operating current - four bank operation i dd7 four bank interleaving with bl=4 refer to the following page for detailed test condition 4025 3845 3845 3620 ma
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 9 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol ddr266(2-2-2) ddr266a ddr266b ddr200 unit note min max min max min max min max row cycle time t rc 60 - 65 - 65 - 70 - ns auto refresh row cycle time t rfc 75 - 75 - 75 - 80 - ns row active time t ras 45 120k 45 120k 45 120k 50 120k ns active to read with auto precharge delay t rap 15 - 20 - 20 - 20 - ns 16 row address to column address delay t rcd 15 - 20 - 20 - 20 - ns row active to row active delay t rrd 15 - 15 - 15 - 15 - ns column address to column address delay t ccd 1 - 1 - 1 - 1 - ck row precharge time t rp 15 - 20 - 20 - 20 - ns write recovery time t wr 15 - 15 - 15 - 15 - ns write to read command delay t wtr 1 - 1 - 1 - 1 - ck auto precharge write recovery + precharge time t dal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - ck 15 system clock cycle time cl = 2.5 t ck 7.5 12 7.5 12 7.5 12 8.0 12 ns cl = 2 7.5 12 7.5 12 10 12 10 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs t qh t hp -t qhs - t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - ns 1, 10 clock half period t hp min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - ns 1,9 data hold skew factor t qhs - 0.75 - 0.75 - 0.75 - 0.75 ns 10 valid data output window t dv t qh -t dqsq t qh -t dqsq t qh -t dqsq t qh -t dqsq ns data-out high-impedance window from ck, /ck t hz -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17 data-out low-impedance window from ck, /ck t lz -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 10 ac characteristics (ac operating conditions unless otherwise noted) - continued - n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. parameter symbol ddr266(2-2-2) ddr266a ddr266b ddr200 unit note min max min max min max min max input setup time (fast slew rate) t is 0.9 - 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.9 - 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input setup time (slow slew rate) t is 1.0 - 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input hold time (slow slew rate) t ih 1.0 - 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input pulse width t ipw 2.2 2.2 2.2 2.5 ns 6 write dqs high level width t dqsh 0.35 - 0.35 - 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - 0.35 - 0.35 - ck clock to first rising edge of dqs- in t dqss 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.5 - 0.6 - ns 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.5 - 0.6 - ns 6,7, 11~13 dq & dm input pulse width t dipw 1.75 - 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0 - 0 - 0 - 0 - ck write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2 - 2 - 2 - 2 - ck exit self refresh to any execute command t xsc 200 - 200 - 200 - 200 - ck 8 average periodic refresh interval t refi - 15.6 - 15.6 - 15.6 - 15.6 us input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 11 5. ck, /ck slew rates are >=1.0v/ns 6. these parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. 7. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to com plete self refresh exit and lock the internal dll circuit of ddr sdram. 9. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the devi ce (i.e. this value can be greater than the minimum specification limits for tcl and tch). 10. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists o f tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-c hannel to n-channel variation of the output drivers. 11 . this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat b elow vref +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq a nd dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/slewrate2). for example, if slew rate 1=0.5v/ns and slew rate2 = 0.4v/n then the delta inverse slew rate = -0.5ns/v. 14. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transi tions through the dc region must be monotonic. 15. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest integer. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clock 16. for the parts which do not has internal ras lockout circuit, active to read with auto precharge delay should be tras - bl/2 x tck. 17. thz and tlz transitions occur in the same access time windows as valid data trasitions. these parameters are not refere nced to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz). input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 0 0 0 +/-0.25 +50 +50 +/- 0.5 +100 +100
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 12 simplified command truth table note : 1. dm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 12 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+t rp ). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+t dpl +t rp ). last data-in to prechage delay(t dpl ) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a 10 /ap is high when row precharge command being issued, ba 0 /ba 1 are ignored and all banks are selected to be precharged. command cken-1 cken /cs /ras /cas /we addr a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect h x h x x x x 1 no operation l h h h bank active h x l l h h ra v 1 read h x l h l h ca l v 1 read with autoprecharge h 1,3 write h x l h l l ca l v 1 write with autoprecharge h 1,4 precharge all banks h x l l h l x h x 1,5 precharge selected bank l v 1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h h x x x 1 l h h h precharge power down mode entry h l h x x x x 1 l h h h 1 exit l h h x x x 1 l h h h 1 active power down mode entry h l h x x x x 1 l v v v 1 exit l h x 1 ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation )
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 13 package dimensions note) all dimension are typical unless otherwise stated. millimeters inches front 1.2 back 30.48 133.35 5.25 register register pll side 3.99 0.157max (front) 1.27 0.050 4.24 0.167
serial presence detect rev. 0.2/may. 02 14 spd specification (64mx72 low profile reg. ddr dimm )
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 15 serial presence detect byte# function description function supported hexa value note m k h l m k h l 0 number of bytes written into serial memory at module manufacturer 128 bytes 80h 1 total number of bytes in spd device 256 bytes 08h 2 fundamental memory type ddr sdram 07h 3 number of row address on this assembly 13 0dh 1 4 number of column address on this assembly 10 0ah 1 5 number of physical banks on dimm 2bank 02h 6 module data width 72 bits 48h 7 module data width (continued) - 00h 8 module voltage interface levels(vddq) sstl 2.5v 04h 9 ddr sdram cycle time at cas latency=2.5(tck) 7.5ns 7.5ns 7.5ns 8.0ns 75h 75h 75h 80h 2 10 ddr sdram access time from clock at cl=2.5 (tac) +/-0.75ns +/-0.8ns 75h 75h 75h 80h 2 11 module configuration type ecc 02h 12 refresh rate and type 7.8us & self refresh 82h 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width x8 08h 15 minimum clock delay for back-to-back random column address(tccd) 1 clk 01h 16 burst lengths supported 2,4,8 0eh 17 number of banks on each ddr sdram 4 banks 04h 18 cas latency supported 2, 2.5 0ch 19 cs latency 0 01h 20 we latency 1 02h 21 ddr sdram module attributes registered, pll 26h 22 ddr sdram device attributes : general +/-0.2voltage tolerance, concurrent auto precharge tras lock out c0h 23 ddr sdram cycle time at cl=2.0(tck) 7.5ns 7.5ns 10ns 10ns 75h 75h a0h a0h 2 24 ddr sdram access time from clock at cl=2.0(tac) +/-0.75ns +/-0.8ns 75h 75h 75h 80h 2 25 ddr sdram cycle time at cl=1.5(tck) - 00h 2 26 ddr sdram access time from clock at cl=1.5(tac) - 00h 2 27 minimum row precharge time(trp) 15ns 20ns 20ns 20ns 3ch 50h 50h 50h 28 minimum row activate to row active delay(trrd) 15ns 15ns 15ns 15ns 3ch 3ch 3ch 3ch 29 minimum ras to cas delay(trcd) 15ns 20ns 20ns 20ns 3ch 50h 50h 50h 30 minimum active to precharge time(tras) 45ns 45ns 45ns 50ns 2dh 2dh 2dh 32h 31 module row density 256mb 40h 32 command and address signal input setup time(tis) 0.9ns 0.9ns 0.9ns 1.1ns 90h 90h 90h b0h 33 command and address signal input hold time(tih) 0.9ns 0.9ns 0.9ns 1.1ns 90h 90h 90h b0h 34 data signal input setup time(tds) 0.5ns 0.5ns 0.5ns 0.6ns 50h 50h 50h 60h 35 data signal input hold time(tdh) 0.5ns 0.5ns 0.5ns 0.6ns 50h 50h 50h 60h 36~40 reserved for vcsdram undefined 00h 41 minimum active / auto-refresh time ( trc) 60ns 65ns 65ns 70ns 3ch 41h 41h 46h 42 minimum auto-refresh to active/auto-refresh command period(trfc) 75ns 75ns 75ns 80ns 4bh 4bh 4bh 50h 43 maximum cycle time (tck max) 12ns 12ns 12ns 12ns 30h 30h 30h 30h 44 maximim dqs-dq skew time(tdqsq) 0.5ns 0.5ns 0.5ns 0.6ns 32h 32h 32h 3ch 45 maximum read data hold skew factor(tqhs) 0.75ns 0.75ns 0.75ns 0.75ns 75h 75h 75h 75h 46~61 superset information(may be used in future) undefined 00h 62 spd revision code initial release 00h 63 checksum for bytes 0~62 - a3h d0h fbh 95h bin sort :m(ddr266(2-2-2),k(ddr266a@cl=2) h(ddr266b@cl=2.5),l(ddr200@cl=2)
hymd264g726a(l)8m-m/k/h/l rev. 0.2/may. 02 16 serial presence detect - continued - note : 1. the bank address is excluded 2. this value is based on the component specification 3. these bytes are programmed by code of date week & date year 4. these bytes apply to hynix?s own module serial number system 5. these bytes undefined and coded as ?00h? 6. refer to hynix web site byte 85~86, low power part byte # function description function supported hexa value note m k h l m k h l 64 manufacturer jedec id code hynix jedec id adh 65~71 --------- manufacturer jedec id code - 00h 72 manufacturing location hynix(korea area) hsa(united states area) hse(europe area) hsj(japan area) singapore asia area 0*h 1*h 2*h 3*h 4*h 5*h 6 73 manufacture part number(hynix memory module) h 48h 74 -------- manufacture part number(hynix memory module) y 59h 75 -------- manufacture part number(hynix memory module) m 4dh 76 manufacture part number (ddr sdram) d 44h 77 manufacture part number(memory density) 2 32h 78 manufacture part number(module depth) 6 36h 79 ------- manufacture part number(module depth) 4 34h 80 manufacture part number(module type) g 47h 81 manufacture part number(data width) 7 37h 82 -------manufacture part number ( data width) 2 32h 83 manufacture part number(refresh, # of bank.) 6(8k refresh,4bank) 36h 84 manufacture part number(component generation) a 41h 85 manufacture part number(component configuration) 8 38h 86 manufacture part number(low profile) m 4dh 87 manufacture part number(hyphen) ?-? 2dh 88 manufacture part number(minimum cycle time) m k h l 4dh 4bh 48h 4ch 89~90 manufacture part number(t.b.d) blank 20h 91 manufacture revision code(for component) blank 20h 92 manufacture revision code (for pcb) 0 30h 93 manufacturing date(year) - - 3 94 manufacturing date(week) - - 3 95~98 module serial number - - 4 99~127 manufacturer specific data (may be used in future) undefined 00h 5 128~255 open for customer use undefined 00h 5 byte # function description function supported hexa value note m k h l m k h l 85 manufacture part number(low power part) l 4ch 86 manufacture part number(component configuration) 8 38h

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