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data sheet powerpc 403gcx 32-bit risc embedded controller features powerpc ? risc cpu and instruction set architecture glueless interfaces to dram, sram, rom, and peripherals, including byte and half-word devices 16kb instruction cache and 8kb write- back data cache, two-way set-associative memory management unit ?4-entry, fully associative tlb array ?ariable page size (1kb-16mb) ?lexible tlb management individually programmable on-chip control- lers for: four dma channels dram, sram, and rom banks external interrupts dram controller supports edo dram flexible interface to external bus masters cpu core can run at 2x the external bus speed applications set-top boxes and network computers consumer electronics and video games telecommunications and networking of?e automation (printers, copiers, fax) speci?ations cpu core frequency of 76 mhz, i/os to 38 mhz interfaces to both 3v and 5v technologies low-power 3.3v operation with built-in power management and stand-by mode low-cost 160 lead pqfp package 0.45 m triple-level-metal cmos overview the powerpc 403gcx 32-bit risc embedded controller offers high performance and functional integration with low power consumption. the 403gcx risc cpu executes at sustained speeds approaching one cycle per instruction. on-chip caches and integrated dram and sram control functions reduce chip count and design complexity in systems, while improving system throughput. external i/o devices or sram/dram memory banks can be directly attached to the 403gcx bus interface unit (biu). interfaces for up to eight memory banks and i/o devices, including a max- imum of four dram banks, can be con?ured individually, allowing the biu to manage devices or memory banks with differing control, timing, or bus width requirements. risc execution unit cache unit instruction cache unit data 4-channel dma controller serial port jtag port dram controller i/o controller bus interface unit sram, rom, i/o controls controls address bus data bus timers (address and control) on-chip peripheral bus dram interrupt controller memory management unit
ibm powerpc 403gcx 2 the 403gcx risc controller consists of a pipe- lined risc processor core and several peripheral interface units: biu, dma controller, asynchro- nous interrupt controller, serial port, and jtag debug port. the risc processor core includes the internal 16kb instruction cache and 8kb data cache, reducing overhead for data transfers to or from external memory. the instruction queue logic manages branch prediction, folding of branch and condition register logical instructions, and instruction prefetching to minimize pipeline stalls.the integrated memory management unit provides robust memory management and pro- tection functions, optimized for embedded envi- ronments. risc cpu the risc core comprises four tightly coupled functional units: the execution unit (exu), the memory management unit (mmu), the data cache unit (dcu), and the instruction cache unit (icu). each cache unit consists of a data array, tag array, and control logic for cache manage- ment and addressing. the execution unit con- sists of general purpose registers (gpr), special purpose registers (spr), alu, multiplier, divider, barrel shifter, and the control logic required to manage data ?w and instruction execution within the exu. the 403gcx core can operate at either 1x or 2x the speed of the external buses, which run at the sysclk input rate. the exu handles instruction decoding and exe- cution, queue management, branch prediction, and branch folding. the instruction cache unit passes instructions to the queue in the exu or, in the event of a cache miss, requests a fetch from external memory through the bus interface unit. the mmu provides translation and memory pro- tection for instruction and data accesses, using a uni?d 64-entry, fully associative tlb array. general purpose registers data transfers to and from the exu are handled through the bank of 32 gprs, each 32 bits wide. load and store instructions move data operands between the gprs and the data cache unit, except in the cases of noncacheable data or cache misses. in such cases the dcu passes the address for the data read or write to the biu.when noncacheable operands are being transferred, data can pass directly between the exu and the biu, which interfaces to the external memory being accessed. special purpose registers special purpose registers are used to control debug facilities, timers, interrupts, the protection mechanism, memory cacheability, and other architected processor resources. sprs are accessed using move to/from special purpose register (mtspr/mfspr) instructions, which move operands between gprs and sprs. supervisory programs can write the appropriate sprs to con?ure the operating and interface modes of the execution unit. the condition regis- ter (cr) and machine state register (msr) are written by internal control logic with program exe- cution status and machine state, respectively. status of external interrupts is maintained in the external interrupt status register (exisr). fixed- point arithmetic exception status is available from the exception register (xer). device control registers device control registers (dcr) are used to man- age i/o interfaces, dma channels, sram and dram memory con?urations and timing, and status/address information regarding bus errors. dcrs are accessed using move to/from device control register (mtdcr/mfdcr) instructions, which move operands between gprs and dcrs. instruction set table 1 summarizes the 403gcx instruction set by categories of operations. most instructions execute in a single cycle, with the exceptions of load/store multiple, load/store string, multiply, and divide instructions. bus interface unit the bus interface unit integrates the functional controls for data transfers and address opera- tions other than those which the dma controller handles. dma transfers use the address logic in the biu to output the memory addresses being accessed.
ibm powerpc 403gcx 3 control functions for direct-connect i/o devices and for dram, sram, or rom banks are pro- vided by the biu. burst access for sram, rom, and page-mode dram devices is supported for cache ?l and ?sh operations. the biu controls the transfer of data between the external bus and the instruction cache, the data cache, or registers internal to the processor core. the biu also arbitrates among external bus mas- ter and dma transfers, the internal buses to the cache units and the register banks, and the serial port on the on-chip peripheral bus (opb). memory addressing regions the 403gcx can address an effective range of 4gb, mapped to 3.5gb (256mb for sram/rom or other i/o, 256mb dram, and 3gb opb/ reserved) of physical address space containing twenty-eight 128mb regions. cacheability with respect to the instruction or data cache is pro- grammed via the instruction and data cache con- trol registers, respectively. within the dram and sram/rom regions, a total of eight banks of devices are supported. each bank can be con?ured for 8-, 16-, or 32-bit devices. for individual dram banks, the number of wait states, bank size, ras -to- cas timing, use of an external address multiplexer (for external bus masters), and refresh rate are user-programma- ble. for each sram/rom bank, the bank size, bank location, number of wait states, and timings of chip selects, byte enables, and output enables are all user-programmable. memory management unit the memory management unit (mmu) supports address translation and protection functions for embedded applications. when used with appro- priate system level software, the mmu provides the following functions: translation of 4gb logical address space into physical addresses, indepen- dent enabling of instruction and data translation/ protection, page level cacheability and access control via the translation mechanism, software control of page replacement strategy, and addi- tional control over protection via zones. the fully associative 64-entry tlb array handles both instruction and data accesses. the transla- tion for any virtual address can be placed in any one of the 64 entries, allowing maximum ?xibil- ity by tlb management software. each tlb entry contains a translation for a page that can be any one of eight sizes from 1kb to 16mb, incrementing by powers of 4. the tlb can simultaneously contain any mix of page sizes. this feature enables the use of small pages when maximum granularity is required, reducing the amount of wasted memory when compared to the more common ?ed 4kb page size. table 1. 403gcx instructions by category category base instructions data movement load, store arithmetic / logical add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional condition condition register logical rotate/shift rotate, rotate and mask, shift left, shift right cache control invalidate, touch, zero, ?sh, store interrupt control write to external interrupt enable bit, move to/from machine state register, return from interrupt, return from critical interrupt processor management system call, synchronize, move to/from device control registers, move to/ from special purpose registers
ibm powerpc 403gcx 4 instruction cache unit the instruction cache unit (icu) is a two-way set- associative 16kb cache memory unit with enhancements to support branch prediction and folding. the icu is organized as 512 sets of 2 lines, each line containing 16 bytes. a separate bypass path is available to handle cache-inhib- ited instructions and to improve performance dur- ing line ?l operations. the cache can send two cached instructions per cycle to the execution unit, allowing instructions to be folded out of the queue without interrupting normal instruction ?w. when a branch instruc- tion is folded and executed in parallel with another instruction, the icu provides two more instructions to replace both of the instructions just executed so that bandwidth is balanced between the icu and the execution unit. data cache unit the data cache unit is provided to minimize the access time of frequently used data items in main store. the 8kb cache is organized as a two-way set associative cache. there are 256 sets of 2 lines, each line containing 16 bytes of data. the cache features byte-writeability to improve the performance of byte and halfword store operations. cache operations are performed using a write- back strategy. a write-back cache only updates locations in main storage that corresponds to changed locations in the cache. data is ?shed from the cache to main storage whenever changed data needs to be removed from the cache to make room for other data. the data cache may be disabled for a 128mb memory region via control bits in the data cache control register or on a per-page basis if the mmu is enabled for data translation. a separate bypass path is available to handle cache-inhib- ited data operations and to improve performance during line ?l operations. cache ?shing and ?ling are triggered by load, store, and cache control instructions executed by the processor. cache blocks are loaded starting at the requested fullword, continuing to the end of the block and then wrapping around to ?l the remaining fullwords at the beginning of the block. dma controller the four-channel dma controller manages block data transfers in buffered, ?-by and memory-to- memory transfer modes with options for burst- mode operation. in ?-by and buffered modes, the dma controller supports transactions between memory and peripheral devices. each dma channel provides a control register, a source address register, a destination address register, a transfer count register, and a chained count register. peripheral set-up cycles, wait cycles, and hold cycles can be programmed into each dma channel control register. each chan- nel supports chaining operations. the dma sta- tus register holds the status of all four channels. exception handling table 2 summarizes the 403gcx exception prior- ities, types, and classes. exceptions are gener- ated by interrupts from internal and external peripherals, instructions, the internal timer facility, debug events or error conditions. six external interrupt signals are provided on the 403gcx: one critical and ?e general-purpose, all individu- ally maskable. all exceptions fall into three basic classes: asyn- chronous imprecise exceptions, synchronous precise exceptions, and asynchronous precise exceptions. asynchronous exceptions are caused by events external to processor execu- tion, while synchronous exceptions are caused by instructions. except for a system reset or machine check, all 403gcx exceptions are handled precisely. pre- cise handling implies that the address of the excepting instruction (synchronous exceptions other than system call) or the address of the next sequential instruction (asynchronous exceptions and system call) is passed to the exception han- dling routine. precise handling also implies that all instructions prior to the excepting instruction have completed execution and have written back their results.
ibm powerpc 403gcx 5 asynchronous imprecise exceptions include sys- tem resets and machine checks. synchronous precise exceptions include most debug excep- tions, program exceptions, data storage viola- tions, tlb misses, system calls, and alignment error exceptions. asynchronous precise excep- tions include the critical interrupt exception, external interrupts, and internal timer facility exceptions and some debug events. only one exception is handled at a time. if multi- ple exceptions occur simultaneously, they are handled in priority order. the 403gcx processes exceptions as reset, crit- ical, or noncritical. four exceptions are de?ed as critical: machine check exceptions, debug exceptions, exceptions caused by an active level on the critical interrupt pin, and the ?st time-out from the watchdog timer. when a noncritical exception is taken, special purpose register save/restore 0 (srr0) is loaded with the address of the excepting instruc- tion (synchronous exceptions other than system call) or the next sequential instruction to be pro- cessed (asynchronous exceptions and system call). if the 403gcx is executing a multicycle instruction (load/store multiple, load/store string, multiply or divide), the instruction is terminated and its address stored in srr0. save/restore register 1 (srr1) is loaded with the contents of the machine state register. the msr is then updated to re?ct the new context of the machine. the new msr contents take effect beginning with the ?st instruction of the excep- tion handling routine. at the end of the exception handling routine, exe- cution of a return from interrupt (r? instruction forces the contents of srr0 and srr1 to be loaded into the program counter and the msr, respectively. execution then begins at the address in the program counter. the four critical exceptions are processed in a similar manner. when a critical exception is taken, srr2 and srr3 hold the next sequential address to be processed when returning from the exception and the contents of the machine state register, respectively. after the critical exception handling routine, return from critical interrupt (rfci) forces the contents of srr2 and srr3 to be loaded into the program counter and the msr, respectively. timers the 403gcx contains four timer functions: a time base, a programmable interval timer (pit), a ?ed interval timer (fit), and a watchdog timer. the time base is a 64-bit counter incremented at the timer clock rate. the timer clock may be driven by either an internal signal equal to the processor clock rate or by a separate external timer clock pin. no interrupts are generated when the time base rolls over. table 2. 403gcx exception priorities, types and classes priority exception type exception class 1 system reset asynchronous imprecise 2 machine check asynchronous imprecise 3 debug synchronous precise (except ude and exc) 4 critical interrupt asynchronous precise 5 watchdogtimer time-out asynchronous precise 6 program exception, data storage exception,tlb miss, and system calls synchronous precise 7 alignment exceptions synchronous precise 8 external interrupts asynchronous precise 9 fixed interval timer asynchronous precise 10 programmable interval timer asynchronous precise
ibm powerpc 403gcx 6 the programmable interval timer is a 32-bit regis- ter that is decremented at the same rate as the time base is incremented. the user preloads the pit register with a value to create the desired delay. when the register is decremented to zeros, the timer stops decrementing, a bit is set in the timer status register (tsr), and a pit interrupt is generated. optionally, the pit can be pro- grammed to reload automatically the last value written to the pit register, after which the pit begins decrementing again.the timer control register (tcr) contains the interrupt enable for the pit interrupt. the ?ed interval timer generates periodic inter- rupts based on selected bits in the time base. users may select one of four intervals for the timer period by setting the correct bits in the tcr. when the selected bit in the time base changes from 0 to 1, a bit is set in the tsr and a fit interrupt is generated. the fit interrupt enable is contained in the tcr. the watchdog timer generates a periodic inter- rupt based on selected bits in the time base. users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an interven- ing clear from software. if enabled, the watchdog timer generates a system reset unless an excep- tion handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals. serial port the 403gcx serial port is capable of supporting rs232 standard serial communication, as well as high-speed execution (bit speed at a maximum of one-sixteenth of the sysclk processor clock rate). the serial clock which drives the serial port can come from the internal sysclk or an external clock source at the external serial clock pin (max- imum of one-half the sysclk rate). the 403gcx serial port contains many features found only on advanced communications control- lers, including the capability of being a peripheral for dma transfers. an internal loopback mode supports diagnostic testing without requiring external hardware. an auto echo mode is included to retransmit received bits to the exter- nal device. auto-resynchronization after a line break and false start bit detection are also pro- vided, as well as operating modes that allow the serial port to react to handshaking line inputs or control handshaking line outputs without soft- ware interaction. program generation mode allows the serial port transmitter to be used for pulse width modulation with duty cycle variation controlled by frame size, baud rate, and data pat- tern. jtag port the jtag port has been enhanced to allow it to be used as a debug port. through the jtag test access port, debug software on a workstation or pc can single-step the processor and interrogate internal processor state to facilitate software debugging. the standard jtag boundary-scan register allows testing of circuitry external to the chip, primarily the board interconnect. alterna- tively, the jtag bypass register can be selected when no other test data register needs to be accessed during a board-level test operation. real-time debug port the real-time debug port supports tracing the instruction stream being executed out of the instruction cache in real time. the trace status signals provide trace information while in real- time trace debug mode. this mode does not alter the performance of the processor. p/n code note: the characters following the dash indicate reli- ability grade (3), package type (j), revision level (c), maximum internal cpu core clock rate (76), commer- cial version (c), and the ratio of internal cpu core clock rate to external bus speed (2 times the maximum exter- nal bus clock rate). table 3. ppc403gcx part number mhz part number package 76 403GCX-3JC76C2 pqfp
ibm powerpc 403gcx 7 logic symbol signals in brackets are multiplexed. sysclk serclk dsr [cts ] recvd xmitd dtr [r ts ] holdreq holdack busreq/ int0 int4 error bootw cint b userr or reset ready dmar0 dmar3 [xreq ] dmaa0 dmaa3 [xa ck ] eo t0 [tc0 ] eo t3 [tc3 ][xsize0] r/w cs0 cs3 cs4 [ras3 ] cs7 [ras0 ] cas0 cas3 amuxcas tck tms tdi tdo dramoe dramwe d0 d31 a6 a29 hal t ts0 ts2 ts1 address bus data bus serial port external master interrupts trace jtag dram controls sram/dram controls sram controls dma controls timerclk status [dmadxfer ] testc/ [holdpri] ppc403gcx risc controller wbe0 [a4][be0 ] wbe1 [a5][be1 ] wbe2 [a30][be2 ] wbe3 [a31][be3 ] oe [xsize1][blast ] ts3[dp3] ts4[dp2] ts5[dp1] ts6[dp0]
ibm powerpc 403gcx 8 pin/ball functional descriptions active-low signals are shown with overbars: dmar0 . multiplexed signals are alphabetized under the ?st (unmultiplexed) signal names on the same pins/balls. the logic symbol on the preceding page shows all 403gcx signals arranged by functional groups. table 4. 403gcx signal descriptions signal name pin ball i/o type function a6 92 k12 i/o address bus bit 6. when the 403gcx is bus master, this is an address output from the 403gcx. when the 403gcx is not bus master, this is an address input from the external bus master, to determine bank register usage. a7 93 k11 i/o address bus bit 7. see description of a6. a8 94 j13 i/o address bus bit 8. see description of a6. a9 95 j14 i/o address bus bit 9. see description of a6. a10 96 j12 i/o address bus bit 10. see description of a6. a11 97 j11 i/o address bus bit 11. see description of a6. a12 98 h13 o address bus bit 12. when the 403gcx is bus master, this is an address output from the 403gcx. a13 99 h14 o address bus bit 13. see description of a12. a14 103 g14 o address bus bit 14. see description of a12. a15 104 g13 o address bus bit 15. see description of a12. a16 105 g11 o address bus bit 16. see description of a12. a17 106 f14 o address bus bit 17. see description of a12. a18 107 f12 o address bus bit 18. see description of a12. a19 108 f13 o address bus bit 19. see description of a12. a20 109 f11 o address bus bit 20. see description of a12. a21 110 e14 o address bus bit 21. see description of a12. a22 112 e13 i/o address bus bit 22. when the 403gcx is bus master, this is an address output from the 403gcx. when the 403gcx is not bus master, this is an address input from the external bus master, to determine page crossings. a23 113 e11 i/o address bus bit 23. see description of a22. a24 114 d14 i/o address bus bit 24. see description of a22. a25 115 d12 i/o address bus bit 25. see description of a22. a26 116 d13 i/o address bus bit 26. see description of a22. a27 117 c14 i/o address bus bit 27. see description of a22. a28 118 c12 i/o address bus bit 28. see description of a22.
ibm powerpc 403gcx 9 a29 119 c13 i/o address bus bit 29. see description of a22. amuxcas 139 a8 o dram external address multiplexer select. amuxcas controls the select logic on an external multiplexer. if amuxcas is low, the multi- plexer should select the row address for the dram and when amuxcas is 1, the multiplexer should select the column address. bootw 11 e1 i boot-up rom width select. bootw is sampled while the reset pin is active and again after reset becomes inactive to determine the width of the boot-up rom. if this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed. if bootw is tied to 1, a 32- bit boot width is assumed. for 16-bit boot widths, this pin should be tied to the reset pin. buserror 12 e3 i bus error input. a logic 0 input to the buserror pin by an external device signals to the 403gcx that an error occurred on the bus transaction. buserror is only sampled during the data transfer cycle or the last wait cycle of the transfer. busreq/ dmadxfer 135 a9 o bus request. while holdack is active, busreq is active when the 403gcx has a bus operation pending and needs to regain control of the bus. dma data transfer. when holdack is not active, dmadxfer indi- cates a valid data transfer cycle. for dma use, dmadxfer con- trols burst-mode ?-by dma transfers between memory and peripherals. dmadxfer is not meaningful unless a dma acknowl- edge signal (dmaa0:3 ) is active. for transfer rates slower than one transfer per cycle, dmadxfer is active for one cycle when one transfer is complete and the next one starts. for transfer rates of one transfer per cycle, dmadxfer remains active throughout the transfer. cas0 142 c8 o dram column address select 0. cas0 is used with byte 0 of all dram banks. cas1 143 a7 o dram column address select 1. cas1 is used with byte 1 of all dram banks. cas2 144 b7 o dram column address select 2. cas2 is used with byte 2 of all dram banks. cas3 145 d7 o dram column address select 3. cas3 is used with byte 3 of all dram banks. cint 36 l2 i critical interrupt. to initiate a critical interrupt, the user must main- tain a logic 0 on the cint pin for a minimum of one sysclk clock cycle followed by a logic 1 on the cint pin for at least one sysclk cycle. cs0 155 c4 o sram chip select 0. bank register 0 controls an sram bank, cs0 is the chip select for that bank. cs1 154 a4 o sram chip select 1. see description of cs0 but controls bank 1. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 10 cs2 153 d5 o sram chip select 2. see description of cs0 but controls bank 2. cs3 152 b5 o sram chip select 3. see description of cs0 but controls bank 3. cs4 /ras3 151 c5 o chip select 4/ dram row address select 3. when bank register 4 is con?ured to control an sram bank, cs4 /ras3 functions as a chip select. when bank register 4 is con?ured to control a dram bank, cs4 /ras3 is the row address select for that bank. cs5 /ras2 148 b6 o chip select 5/ dram row address select 2. see description of cs4 /ras3 but controls bank 5. cs6 /ras1 147 c6 o chip select 6/ dram row address select 1. see description of cs4 /ras3 but controls bank 6. cs7 /ras0 146 a6 o chip select 7/ dram row address select 0. see description of cs4 /ras3 but controls bank 7. d0 42 n2 i/o data bus bit 0 (most signi?ant bit). d1 43 p2 i/o data bus bit 1. d2 44 n3 i/o data bus bit 2. d3 45 p3 i/o data bus bit 3. d4 46 n4 i/o data bus bit 4. d5 47 m4 i/o data bus bit 5. d6 48 p4 i/o data bus bit 6. d7 51 p5 i/o data bus bit 7. d8 52 m5 i/o data bus bit 8. d9 53 l5 i/o data bus bit 9. d10 54 n6 i/o data bus bit 10. d11 55 p6 i/o data bus bit 11. d12 56 m6 i/o data bus bit 12. d13 57 l6 i/o data bus bit 13. d14 58 n7 i/o data bus bit 14. d15 62 m7 i/o data bus bit 15. d16 63 p8 i/o data bus bit 16. d17 64 n8 i/o data bus bit 17. d18 65 l8 i/o data bus bit 18. d19 66 p9 i/o data bus bit 19. d20 67 m9 i/o data bus bit 20. d21 68 n9 i/o data bus bit 21. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 11 d22 71 m10 i/o data bus bit 22. d23 72 n10 i/o data bus bit 23. d24 73 l10 i/o data bus bit 24. d25 74 p11 i/o data bus bit 25. d26 75 m11 i/o data bus bit 26. d27 76 n11 i/o data bus bit 27. d28 77 p12 i/o data bus bit 28. d29 78 m12 i/o data bus bit 29. d30 79 n12 i/o data bus bit 30. d31 82 n13 i/o data bus bit 31. dmaa0 156 b4 o dma channel 0 acknowledge. dmaa0 has an active level when a transaction is taking place between the 403gcx and a peripheral. dmaa1 157 a3 o dma channel 1 acknowledge. see description of dmaa0 . dmaa2 158 c3 o dma channel 2 acknowledge. see description of dmaa0 . dmaa3 / xa ck 159 b3 o dma channel 3 acknowledge / external master transfer acknowl- edge. when the 403gcx is bus master, this signal is dmaa3; see description of dmaa0. when the 403gcx is not the bus master, this signal is xa ck , an output from the 403gcx which has an active level when data is valid during an external bus master trans- action. dmar0 2 b2 i dma channel 0 request. external devices request a dma transfer on channel 0 by putting a logic 0 on dmar0 . dmar1 3 b1 i dma channel 1 request. see description of dmar0 . dmar2 4 c2 i dma channel 2 request. see description of dmar0 . dmar3 / xreq 5 c1 i dma channel 3 request. when the 403gcx is the bus master, external devices request a dma transfer on channel 3 by putting a logic 0 on dmar3 . see description of dmar0 . when the 403gcx is not the bus master, dmar3 is used as the xreq input. the external bus master places a logic 0 on xreq to initiate a transfer to the dram controlled by the 403gcx dram controller. dramoe 137 d9 o dram output enable. dramoe has an active level when either the 403gcx or an external bus master is reading from a dram bank. this signal enables the selected dram bank to drive the data bus. dramwe 138 b8 o dram write enable. dramwe has an active level when either the 403gcx or an external bus master is writing to a dram bank. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 12 dsr /cts 28 j2 i data set ready / clear to send. the function of this pin as either dsr or cts is selectable via the serial port con?uration bit in the iocr. dtr /r ts 88 l14 o data terminal ready / request to send. the function of this pin as either dtr or r ts is selectable via the serial port con?uration bit in the iocr. eo t0 /tc0 128 a11 i/o end of transfer 0 / terminal count 0. the function of the eo t0 /tc0 is controlled via the eo t /tc bit in the dma channel 0 control reg- ister. when eo t0 /tc0 is con?ured as an end of transfer pin, external users may stop a dma transfer by placing a logic 0 on this input pin. when con?ured as a terminal count pin, the 403gcx signals the completion of a dma transfer by placing a logic 0 on this pin. eo t1 /tc1 131 a10 i/o end of transfer 1 / terminal count 1. see description of eo t0 /tc0 . eo t2 /tc2 132 c10 i/o end of transfer 2 / terminal count 2. see description of eo t0 /tc0 . eo t3 /tc3 / xsize0 133 d10 i/o end of transfer 3 / terminal count 3 / external master transfer size 0. when the 403gcx is bus master, this pin has the same function as eo t0 /tc0 . when the 403gcx is not bus master, eo t3 /tc3 /xsize0 is used as one of two external transfer size input bits, xsize0:1. error 136 c9 o system error. error goes to a logic 1 whenever a machine check error is detected in the 403gcx. the error pin then remains a logic 1 until the machine check error is cleared in the exception syn- drome register and/or bus error syndrome register. gnd 1 g7 ground. all ground pins must be used. 10 e2 ground. all ground pins must be used. 15 f1 ground. all ground pins must be used. 29 j4 ground. all ground pins must be used. 30 k1 ground. all ground pins must be used. 41 h7 ground. all ground pins must be used. 50 n5 ground. all ground pins must be used. 59 p7 ground. all ground pins must be used. 60 l7 ground. all ground pins must be used. 70 p10 ground. all ground pins must be used. 81 h8 ground. all ground pins must be used. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 13 gnd 90 k13 ground. all ground pins must be used. 101 g12 ground. all ground pins must be used. 102 h12 ground. all ground pins must be used. 111 e12 ground. all ground pins must be used. 121 g8 ground. all ground pins must be used. 130 b10 ground. all ground pins must be used. 141 c7 ground. all ground pins must be used. 150 a5 ground. all ground pins must be used. halt 9 d4 i halt from external debugger, active low. holdack 134 b9 o hold acknowledge. holdack outputs a logic 1 when the 403gcx relinquishes its external buses to an external bus master. holdack outputs a logic 0 when the 403gcx regains control of the bus. holdreq 14 f2 i hold request. external bus masters can request the 403gcx bus by placing a logic1 on this pin. the external bus master relinquishes the bus to the 403gcx by deasserting holdreq. int0 31 k3 i interrupt 0. int0 is an interrupt input to the 403gcx and users may program the pin to be either edge-triggered or level-triggered and may also program the polarity to be active high or active low. the iocr contains the bits necessary to program the trigger type and polarity. int1 32 k2 i interrupt 1. see description of int0. int2 33 k4 i interrupt 2. see description of int0. int3 34 l1 i interrupt 3. see description of int0. int4 35 l3 i interrupt 4. see description of int0. ivr 39 m2 i reserved for manufacturing test. tied high for normal operation. oe /xsize1/ blast 126 b11 o/i/o output enable / external master transfer size 1. when the 403gcx is bus master, oe enables the selected srams to drive the data bus. the timing parameters of oe relative to the chip select, cs , are programmable via bits in the 403gcx bank registers. when the 403gcx is not bus master, oe /xsize1 is used as one of two external transfer size input bits, xsize0:1. in byte enable mode, burst last (blast ) goes active to indicate the last transfer of a memory access, whether burst or nonburst. ready 13 e4 i ready. ready is used to insert externally generated (device-paced) wait states into bus transactions. the ready pin is enabled via the ready enable bit in 403gcx bank registers. recvd 27 j3 i serial port receive data. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 14 reset 91 k14 i/o reset . a logic 0 input placed on this pin for one sysclk cycle causes the 403gcx to begin a system reset. when a system reset is invoked, the reset pin becomes a logic 0 output for 2048 sysclk cycles. r/w 127 c11 i/o read / write. when the 403gcx is bus master, r/w is an output which is high when data is read from memory and low when data is written to memory. when the 403gcx is not bus master, r/w is an input from the external bus master which indicates the direction of data transfer. serclk 26 j1 i serial port clock. through the serial port clock source bit in the input/output con?uration register (iocr), users may choose the serial port clock source from either the input on the serclk pin or processor sysclk. the maximum allowable input frequency into serclk is half the sysclk frequency. sysclk 22 g3 i sysclk is the processor system clock input. the 403gcx can also be programmed to operate at a 2x internal clock rate while the external bus interface runs at the sysclk input rate. tck 6 d2 i jtag test clock input. tck is the clock source for the 403gcx test access port (tap). the maximum clock rate into the tck pin is one half of the processor sysclk clock rate. tdi 8 d1 i test data in. the tdi is used to input serial data into the tap. when the tap enables the use of the tdi pin, the tdi pin is sampled on the rising edge of tck and this data is input to the selected tap shift register. tdo 16 f3 o test data output. tdo is used to transmit data from the 403gcx tap. data from the selected tap shift register is shifted out on tdo. testa 23 h1 i reserved for manufacturing test. tied low for normal operation. t estb 24 h2 i reserved for manufacturing test. tied high for normal operation. testc/hold- pri 37 m1 i testc. reserved for manufacturing test during the reset interval. while reset is active, this signal should be tied low for normal oper- ation. holdreq priority. when reset is not active, this signal is sampled to determine the priority of the external bus master signal holdreq. if holdpri = 0 then the holdreq signal is considered high priority, oth- erwise holdreq is considered low priority. testd 38 m3 i reserved for manufacturing test. tied low for normal operation. timerclk 25 h4 i timer facility clock. through the timer clock source bit in the input/output con?uration register (iocr), users may choose the clock source for the timer facility from either the input on the timer- clk pin or processor coreclk. the maximum input frequency into timerclk is half the coreclk frequency. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 15 tms 7 d3 i test mode select. the tms pin is sampled by the tap on the rising edge of tck. the tap state machine uses the tms pin to deter- mine the mode in which the tap operates. ts0 17 f4 o trace status 0. ts1 18 g2 o trace status 1. ts2 19 g1 o trace status 2. ts3/dp3 86 l13 o/i/o trace status 3 / data parity 3. when parity checking and generation are enabled, this signal represents odd parity for read/write opera- tions using byte 3 (d24:31) of the data bus. the parity error status bit is set in the besr when a parity error is detected. ts4/dp2 85 m14 o/i/o trace status 4 / data parity 2 for byte 2 (d16:23). see ts3/dp3 description above. ts5/dp1 84 m13 o/i/o trace status 5 / data parity 1 for byte 1 (d8:15). see ts3/dp3 description above. ts6/dp0 83 n14 o/i/o trace status 6 / data parity 0 for byte 0 (d0:7). see ts3/dp3 description above. v dd 20 g4 power. all power pins must be connected to 3.3v supply. 21 h3 power. all power pins must be connected to 3.3v supply. 40 n1 power. all power pins must be connected to 3.3v supply. 49 l4 power. all power pins must be connected to 3.3v supply. 61 m8 power. all power pins must be connected to 3.3v supply. 69 l9 power. all power pins must be connected to 3.3v supply. 80 p13 power. all power pins must be connected to 3.3v supply. 89 l11 power. all power pins must be connected to 3.3v supply. 100 h11 power. all power pins must be connected to 3.3v supply. 120 b14 power. all power pins must be connected to 3.3v supply. 129 d11 power. all power pins must be connected to 3.3v supply. 140 d8 power. all power pins must be connected to 3.3v supply. 149 d6 power. all power pins must be connected to 3.3v supply. 160 a2 power. all power pins must be connected to 3.3v supply. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 16 wbe0 /a4/ be0 122 b13 o/i/o write byte enable 0 / address bus bit 4 / byte enable 0. when the 403gcx is bus master, the write byte enable outputs, wbe0:3 , select the active byte(s) in a memory write access to sram. the byte enables can also be programmed as read/write byte enables, depending on the mode set in the iocr. note 5 on page 35 summarizes the functional and timing differences in these sig- nals when programmed as read/write byte enables. for 8-bit memory regions, wbe2 and wbe3 become address bits 30 and 31 and wbe0 is the byte-enable line. for 16-bit memory regions, wbe2 and w be3 become address bits 30 and 31 and wbe0 and wbe1 are the high byte and low byte enables, respec- tively. for 32-bit memory regions, wbe0:3 are byte enables for bytes 0-3 on the data bus, respectively. when the 403gcx is not bus master, wbe0:1 are used as the a4:5 inputs (for bank register selection) and wbe2:3 are used as the a30:31 inputs (for byte selection and page crossing detection). wbe1 /a5/ be1 123 a13 o/i/o write byte enable 1 / address bus bit 5 / byte enable 1. see description of wbe0 / a4 above. wbe2 /a30/ be2 124 b12 o/i/o write byte enable 2 / address bus bit 30 / byte enable 2. see description of wbe0 / a4 above. wbe3 /a31/ be3 125 a12 o/i/o write byte enable 3 / address bus bit 31 / byte enable 3. see description of wbe0 / a4 above. xmitd 87 l12 o serial port transmit data. table 4. 403gcx signal descriptions signal name pin ball i/o type function
ibm powerpc 403gcx 17 table 5. pqfp package signals ordered by pin number pin signal name pin signal name pin signal name pin signal name pin signal name 1 gnd 33 int2 65 d18 97 a11 129 v dd 2 dmar0 34 int3 66 d19 98 a12 130 gnd 3 dmar1 35 int4 67 d20 99 a13 131 eo t1 /tc1 4 dmar2 36 cint 68 d21 100 v dd 132 eo t2 /tc2 5 dmar3 /xreq 37 testc/holdpri 69 v dd 101 gnd 133 eo t3 /tc3 /xsize0 6 tck 38 testd 70 gnd 102 gnd 134 holdack 7 tms 39 ivr 71 d22 103 a14 135 busreq/ dmadxfer 8 tdi 40 v dd 72 d23 104 a15 136 error 9 halt 41 gnd 73 d24 105 a16 137 dramoe 10 gnd 42 d0 74 d25 106 a17 138 dramwe 11 bootw 43 d1 75 d26 107 a18 139 amuxcas 12 buserror 44 d2 76 d27 108 a19 140 v dd 13 ready 45 d3 77 d28 109 a20 141 gnd 14 holdreq 46 d4 78 d29 110 a21 142 cas0 15 gnd 47 d5 79 d30 111 gnd 143 cas1 16 tdo 48 d6 80 v dd 112 a22 144 cas2 17 ts0 49 v dd 81 gnd 113 a23 145 cas3 18 ts1 50 gnd 82 d31 114 a24 146 cs7 /ras0 19 ts2 51 d7 83 ts6/dp0 115 a25 147 cs6 /ras1 20 v dd 52 d8 84 ts5/dp1 116 a26 148 cs5 /ras2 21 v dd 53 d9 85 ts4/dp2 117 a27 149 v dd 22 sysclk 54 d10 86 ts3/dp3 118 a28 150 gnd 23 testa 55 d11 87 xmitd 119 a29 151 cs4 /ras3 24 t estb 56 d12 88 dtr /r ts 120 v dd 152 cs3 25 timerclk 57 d13 89 v dd 121 gnd 153 cs2 26 serclk 58 d14 90 gnd 122 wbe0 /a4/ be0 154 cs1 27 recvd 59 gnd 91 reset 123 wbe1 /a5/ be1 155 cs0 28 dsr /cts 60 gnd 92 a6 124 wbe2 /a30/ be2 156 dmaa0 29 gnd 61 v dd 93 a7 125 wbe3 /a31/ be3 157 dmaa1 30 gnd 62 d15 94 a8 126 oe /xsize1/ blast 158 dmaa2 31 int0 63 d16 95 a9 127 r/w 159 dmaa3 /xa ck 32 int1 64 d17 96 a10 128 eo t0 /tc0 160 v dd
ibm powerpc 403gcx 18 pqfp mechanical drawing (top view) index mark 140 41 80 81 120 121 160 0.3 0.1 0.012 0.004 0.65 basic 0.0256 dimensions: mm inches 3.95 max 0.155 see detail note: english dimensions are for reference only. 0.25 min 0.01 0 - 7 0.015 0.05 0.006 0.002 0.8 0.15 0.032 0.006 28 0.2 1.102 0.008 31.2 0.25 1.228 0.01
ibm powerpc 403gcx 19 package thermal specications the 403gcx is designed to operate within the case temperature range from -40?c to 120?c. thermal resistance values are shown in table 6: notes: 1. case temperature tm c is measured at top center of case surface with device soldered to circuit board. 2. tm a = tm c ?p ca , where tm a is ambient temperature. 3. tm cmax = tm jmax ?p jc , where tm jmax is maximum junction temperature and p is power consumption. 4. the above assumes that the chip is mounted on a card with at least one signal and two power planes. electrical speci?ations absolute maximum ratings the absolute maximum ratings in table 7 below are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. table 6. thermal resistance (?c/watt) parameter air?w-ft/min (m/sec) 0 (0) 100 (0.51) 200 (1.02) jc junction to case 222 ca case to ambient pqfp (no heatsink) 37.2 31.6 29.8 table 7. 403gcx maximum ratings parameter maximum rating supply voltage with respect to gnd -0.5v to +3.8v voltage on other pins with respect to gnd -0.5v to +5.5v case temperature under bias -40?c to +120?c storage temperature -65?c to +150?c
ibm powerpc 403gcx 20 operating conditions the 403gcx can interface to either 3v or 5v technologies. the range for supply voltages is speci?d for ?e-percent margins relative to a nominal 3.3v power supply. device operation beyond the conditions speci?d in table 8 is not recommended. extended operation beyond the recommended conditions may affect device reliability: note: these frequencies do not account for t cs . see table 11. power considerations power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. typical power dissipation is 0.49 w at 38/76 mhz, with an average 50pf capacitive load. derating curves are provided in the section, "output derating for capacitance and voltage," on page 29. recommended connections power and ground pins should all be connected to separate power and ground planes in the circuit board to which the 403gcx is mounted. unused input pins must be tied inactive, either high or low. the ivr pin should be tied to v dd for normal operation. table 8. operating conditions symbol parameter min max unit v dd supply voltage: 403gcx-3jc76 3.14 3.47 v f c clock frequency 1 : 403gcx-3jc76 24 38 mhz tm c case temperature under bias: 403gcx-3jc76 -40 85 c
ibm powerpc 403gcx 21 dc specications notes: 1. the 403gcx drives its outputs to the level of v dd and, when not driving, the 403gcx outputs can be pulled up to 5v by other devices in a system. 2. i cc max is measured at worst-case recommended operating conditions for temperature, frequency and voltage as speci?d in table 8 on page 20, and a capacitive load of 50 pf. 3. the input leakage current is dependent on the applied. see "input leakage current," on page 32 for details. . note: 1. c out is speci?d as the load capacitance of a ?ating output in high impedance. table 9. 403gcx dc characteristics symbol parameter min max units v il input low voltage (except for sysclk) gnd - 0.1 0.8 v v ilc input low voltage for sysclk gnd - 0.1 0.8 v v ih input high voltage (except for sysclk) 2.0 5.1 v v ihc input high voltage for sysclk 2.0 5.1 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v dd v i oh output high current 2 ma i ol output low current 4 ma i li input leakage current 3 150 a i lo output leakage current 10 a i cc supply current (i cc max at f core of 76mhz) 305 ma table 10. 403gcx i/o capacitance symbol parameter min max units c in input capacitance (except for sysclk) 5 pf c inc input capacitance for sysclk 15 pf c out output capacitance 1 7pf c i/o i/o pin capacitance 8 pf
ibm powerpc 403gcx 22 ac speci?ations clock timing and switching characteristics are speci?d in accordance with recommended operating conditions in table 8 on page 20. ac speci?ations are characterized at v dd = 3.14v and t j = 85?c with the 50pf test load shown in the ?ure at right. derating of outputs for capacitive loading is shown in the ?ure "output derating for capacitance and voltage," on page 29. sysclk timing notes: 1. these values do not include the allowable tolerance for clock edge instability represented by t cs . 2. cycle-to-cycle jitter allowed between any two edges. 3. rise and fall times measured between 0.8v and 2.0v. table 11. 403gcx system clock timing symbol parameter 38 mhz units min max f c sysclk clock input frequency 1 24 38 mhz t c sysclk clock period 1 27.8 41.7 ns t cs clock edge stability 2 0.2 ns t ch clock input high time 11 ns t cl clock input low time 11 ns t cr clock input rise time 3 0.5 2.5 ns t cf clock input fall time 3 0.5 2.5 ns output pin c l c l = 50 pf for all signals t cr t cf t cl t ch t c 2.0v 1.5v 0.8v
ibm powerpc 403gcx 23 serial clock timing characteristics timer clock timing characteristics note: 1. output times are measured with a standard 50 pf capacitive load, unless otherwise noted. table 12. 403gcx serial clock timings symbol parameter min max units f sc serclk input frequency 0.5 f c mhz t sc serclk period 2t c ns t sch serclk input high time t c ns t scl serclk input low time t c ns table 13. 403gcx timer clock timings symbol parameter iocr[2xc] = 1 coreclk doubled mode iocr[2xc] = 0 coreclk non-doubled mode units min max min max f tc timerclk input frequency f c 0.5 f c mhz t tc timerclk period t c 2 t c ns t tch timerclk input high time 0.5 t c t c ns t tcl timerclk input low time 0.5 t c t c ns table 14. 403gcx serial port output timings symbol parameter 38 mhz units t ohmin t ovmax t oh , t ov output hold, output valid t ohsp1 , t ovsp1 t ohsp2 , t ovsp2 dtr /r ts xmitd 12 10 ns
ibm powerpc 403gcx 24 input setup and hold waveform notes: 1. the 403gcx may be programmed to latch data from the data bus with respect to sysclk, or with respect to cas . when iocr[drc] = 1, the 403gcx is programmed to latch data on the rise of cas . when iocr[edo] = 1, the 403gcx is programmed to latch data on either the fall of cas or the fall of the internal duty cycle corrected sysclk, depending on the parameters set in the bank register and the type of transfer. when neither of these spe- cial modes are set, the 403gcx will latch data on the rise of sysclk. note that it is invalid to concurrently set iocr[drc] = 1 and iocr[edo] = 1. 2. t cas2clk 13.5 ns. when iocr[drc] = 1 or iocr[edo] = 1, the capacitive load on the cas outputs must not delay the cas transition such that the period from the cas data latching edge to the next sysclk rising edge becomes less than 13.5 ns. the maximum value of cas capacitive loading can be determined by using the output time for cas from table 17 on page 27, and applying the appropriate derating factor for your application. see the ?ure, "output derating for capacitance and voltage," on page 29. 1.5v + sysclk valid 1.5v + t is t ih min min inputs cas0:3 outputs valid min min data bus (inputs) d0:31 min t cas2clk valid 1.5v + valid min t cas2clk t isedo min t iscas min t ihcas min t ihcas min t ihedo t iscas 1.5v +
ibm powerpc 403gcx 25 all t is and t ih timings in table 15 are speci?d with respect to the rise of the external sysclk signal. internal system clocks are duty-cycle corrected so the falling edge of the external sysclk signal may not be the same as the falling edge of the internally corrected system clock. notes: 1. parity setup and hold times are the same as for the data bus. 2. for detailed edo dram timing waveforms, refer to "edo dram 2-1-1-1 burst read followed by single transfer read," on page 42 and "edo dram 3-1-1-1 burst read followed by single transfer read," on page 44. 3. data bus input setup and hold times t is3 and t ih3 are the speci?ations to use for all modes except dram read on cas and edo dram read modes (controlled via iocr[drc] and iocr[edo], respectively). 4. in edo mode, the data bus input setup and hold times with respect to sysclk. use the following equations to determine the minimum input setup and hold times for this signal: t isedo min = tc/2 + 3; t ihedo min = -tc/2 + 3. valid for tc greater than 25ns and less than 41.7 ns. 5. guaranteed by design and not tested. table 15. 403gcx synchronous input timings symbol parameter 38 mhz units min max t is input setup: t is1 t is2 t is3 t isedo t iscas t is4 t is5 t is6 t is7 t is8 t is9 t is10 a4:11,a22:31 buserror d0:31 (to sysclk) 3 d0:31 (to sysclk) 4,5 d0:31 (to cas ) 5 holdpri holdreq r/w ready ready(sor mode) xreq xsize0:1 3 5 4 16.2 3 3 3 3 5 10 4 3 ns t ih input hold: t ih1 t ih2 t ih3 t ihedo t ihcas t ih4 t ih5 t ih6 t ih7 t ih8 t ih9 t ih10 a4:11,a22:31 buserror d0:31 (after sysclk) 3 d0:31 (after sysclk) 4,5 d0:31 (after cas ) 5 holdpri holdreq r/w ready ready(sor mode) xreq xsize0:1 2 2 3 -10.2 3 2 2 2 2 2 2 2 ns t r ,t f input rise/fall time 0.5 2.5 ns
ibm powerpc 403gcx 26 notes: 1. during a system-initiated reset, reset must be taken low for a minimum of 2048 sysclk cycles. 2. the bootw input has a maximum rise time requirement of 10 ns when it is tied to reset . 3. input hold times are measured at 3.47v and t j = 0 c. output delay and float timing waveform table 16. 403gcx asynchronous input timings symbol parameter 38 mhz units min max t is input setup time t is11 t is12 t is13 t is14 t is15 t is16 t is17 cint dmar0:3 eo t0:3 hal t int0:4 reset ready 3 3 3 3 4 8 5 ns t ih input hold time t ih11 t ih12 t ih13 t ih14 t ih15 t ih16 t ih17 cint dmar0:3 eo t0:3 hal t int0:4 reset ready t c t c t c t c t c note 1,2 t c valid t ov t oh 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v
ibm powerpc 403gcx 27 all t oh and t ov timings in table 17 are speci?d with respect to the rise of the sysclk input signal. inter- nal system clocks are duty-cycle corrected so the falling edge of the external sysclk signal may not be the same as the falling edge of the internally corrected system clock. t ohxr /t ovxr speci?ations are for signals which transition relative to the rising edge of sysclk, while t ohxf /t ovxf apply to falling edge tran- sitions. refer to the appropriate timing diagram to determine the appropriate clock edge for signal transi- tions. table 17. 403gcx synchronous output timings symbol parameter 38 mhz units t ohmin t ovmax t oh , t ov output hold, output t oh1r , t ov1r t oh1f , t ov1f t oh2 , t ov2 t oh3 , t ov3 t oh4r , t ov4r t oh4f , t ov4f t oh5 , t ov5 t oh6 , t ov6 t oh7 , t ov7 t oh8 , t ov8 t oh9r , t ov9r t oh9f , t ov9f t oh10 , t ov10 t oh11 , t ov11 t oh12 , t ov12 t oh13 , t ov13 t oh14r , t ov14r t oh14f , t ov14f t oh15 , t ov15 t oh16 , t ov16 t oh17 , t ov17 t oh18 , t ov18 t oh19 , t ov19 t oh20 , t ov20 t oh21 , t ov21 t oh22 , t ov22 valid a6:31 a6:31 2,3,8 amuxcas busreq cas0:3 8 cas0:3 2,3 cs0:7 d0:31 dmaa0:3 dmadxfer dramoe dramoe 2,3,8 dramwe error holdack oe ras0:3 ( turn-off ) 8 ras0:3 ( turn-on ) 3 ras0:3 ( early, turn-on ) 4 reset r/w tc0:3 parity(dma) 5,8 wbe0:3 [be0:3 ] xac k blast 8 3 16.2 3 3 3 16.2 3 3 3 3 3 16.2 3 3 3 3 3 16.2 10 2 3 3 4 3 3 4 10 23.2 9 9 9 22.3 9 12 9 10 9 23.2 9 10 9 10 9 23.2 16.9 10 9 10 13 9 10 14 ns t of output ?at time t of1 t of4 t of5 t of6 t of9 t of10 t of13 t of14 t of16 t of17 t of20 a6:31 cas0:3 cs0:7 d0:31 dramoe dramwe oe ras0:3 reset r/w wbe0:3 [be0:3 ] min 2 3 3 3 3 3 3 3 2 3 3 max 8 10 10 10 9 9 9 10 9 9 9 ns
ibm powerpc 403gcx 28 notes: 1. for all output timing, t oh and t ov are relative to the rising edge of sysclk. 2. for detailed edo dram timing waveforms, refer to "edo dram 2-1-1-1 burst read followed by single transfer read," on page 42 and "edo dram 3-1-1-1 burst read followed by single transfer read," on page 44. 3. the address bus, ras , cas and dramoe output timings (with respect to the falling edge of the internal duty cycle corrected sysclk) vary with the 403gcx operating frequency. use the following equations to determine the worst-case output delay and hold times for these signals: t ovf max = tc/2 + t ovr max; t ohf min = tc/2 + t ohr min, where t ovr max and t ohr min correspond to the speci?ations for the speed grade of the part. valid for tc greater than 25 ns and less than 41.7 ns. 4. in early ras mode, the ras output delay varies with the 403gcx operating frequency. use the following equation to determine the worst-case output delay for this signal: t ov15 max = tc/4 + t oh15 min, where t oh15 min corre- sponds to the speci?ation for the speed grade of the part. t oh min remains unchanged. valid for tc greater than 25 ns and less than 41.7 ns. 5. parity timings are for dma buffered mode. for normal memory accesses, use the data bus timings for parity. 6. output times are measured with a standard 50 pf capacitive load, unless otherwise noted. output hold times are measured as t ovmin at 3.47v and tj=0 c. 7. all output hold and ?at times are guaranteed by design and not tested. 8. noted output valid times guaranteed by design and not tested. note: 1. relationships are guaranteed by design and are not tested. relationships also assume 50 pf capacitive loading on interface signals. 2. for detailed dram interface timing waveforms, refer to "dram interface timing diagram," on page 29. table 18. 403gcx dram interface timing relationships symbol parameter 38 mhz units min t asr row address setup time to ras : brn[erm] = 0 brn[erm] = 1 0.5t c -4.0 0.25t c -2.5 ns t rah row address hold time: brn[erm] = 0 brn[erm] = 1 0.5t c -1.5 0.67t c -0.5 ns t asc column address setup time to cas 0.5t c -4.0 ns t cah column address hold time 0.5t c -2.0 ns t cas available cas access time: 2-1-1-1 access 3-2-2-2 access 3-1-1-1 access 0.5t c -2.5 1.5t c -2.5 0.5t c -2.5 ns t cp cas precharge time 0.5t c -2.5 ns t ds write data setup time to cas 0.5t c -4.0 ns t rp ras precharge time: brn[erm] = 0 and brn[pcc] = 0 brn[erm] = 0 and brn[pcc] = 1 brn[erm] = 1 and brn[pcc] = 0 brn[erm] = 1 and brn[pcc] = 1 1.5t c -2.5 2.5t c -2.5 1.25t c -1.0 2.25t c -1.0 ns t ras ras active during refresh: br[rar] = 0 br[rar] = 1 1.5t c -1.5 2.5t c -1.5 ns
ibm powerpc 403gcx 29 dram interface timing diagram output derating for capacitance and voltage 1.5v address t asr t cah t ras t rp t asc t rah t cas t cp t ds ras cas write data note: test conditions v t = 1.5v at t j = 85?c 0 50 100 150 0 -10 +10 +20 ? output delay (ns) c l (pf) tp zl ? c = 0.14 c l - 1.2ns tp lh ? c = 0.04 c l - 1.9ns tp hl ? c = 0.06 c l - 2.3ns output propagation delay derating derating equations for output delays: 1. ? tp lh (c l , v) = tp lh ? c + tp lh ? v 2. ? tp hl (c l , v) = tp hl ? c + tp hl ? v 3 . ? tp zl5v (c l , v) = tp zl ? c + tp hl ? v (from 5.5v)
ibm powerpc 403gcx 30 output propagation delay derating vs output voltage level output rise and fall time derating 1.5 3 0 0 +2 +4 +6 tp lh ? v (c l = 25 pf) tp lh ? v (c l = 50pf) tp lh ? v (c l = 100 pf) v out (v) note: test condition t j = 85?c ? output delay (ns) tp hl ? v (c l = 100 pf) tp hl ? v (c l = 50pf) tp hl ? v (c l = 25 pf) note: test conditions v t = 0.8v to 2v at t j = 85?c 0 +6 +2 0 50 100 150 +4 -2 ? output transition (ns) c l (pf) tp r ? c tp f ? c output transition time derating 4. t r (c l ) = 2ns + tp r ? c 5. t f (c l ) = 2.5ns + tp f ? c derating equations for output rise and fall times:
ibm powerpc 403gcx 31 output voltage vs output current supply current vs operating frequency 3.5 3 2.5 2 3 2 1 0 i ol (ma) 0.6 0.3 0 0 1 2 3 4 i oh (ma) v oh min (v) v ol max (v) note: test conditions 3.14v at t j = 85?c i cc (ma) 0 260 ma 33 f c (mhz) test conditions: 3.47v at t j = 85?c 127 ma (worst case) 25 103 ma 200 ma 155 ma 320 ma 40 test conditions: (typical) 3.3v at t j = 55?c 0
ibm powerpc 403gcx 32 input leakage current +200 -200 0 0 3.0 see note 3 in "403gcx dc characteristics," on page 21. input voltage (v) 1.5 leakage current ( a) +100 -100 0.5 1.0 2.0 2.5
ibm powerpc 403gcx 33 reset and holdack the following table summarizes the states of signals on output pins when reset or holdack is active. note: 1. signal may be active while holdack is asserted, depending on the operation being performed by the 403gcx. 2. signal may be placed in high impedance, depending on dram 3-state control setting in iocr. bus waveforms the waveforms in this section represent external bus operations, including sram and dram accesses, dma transfers, and external master operations. write byte enable encoding the 403gcx provides four write byte enable signals (wbe0:3 ) to support 8-, 16-, and 32-bit devices, as shown in table 20. for an eight-bit memory region, wbe2:3 are encoded as a30:31 and wbe0 is the byte-enable line. for a 16-bit region, wbe0 is the high-byte enable, wbe1 is the low-byte enable and wbe2:3 are encoded as a30:31. for a 32-bit region, address bits 6:29 select the word address and wbe0:3 select data bytes 0:3, respectively. table 19. signal states during reset or hold acknowledge signal names state when reset active state when holdack active a6:29 amuxcas busreq cas0:3 floating inactive (low) inactive (low) inactive (high) floating (set to input mode) operable (see note 1) operable (see note 1) operable (see notes 1 and 2) cs0:3 cs4:7 /ras3:0 d0:31 dmaa0:3 floating floating floating inactive (high) floating cs ?ating, ras operable (notes 1 and 2) floating (external master drives bus) inactive (high) xac k dramoe dramwe inactive (high) inactive (high) inactive (high) operable (see note 1) operable (see notes 1 and 2) operable (see notes 1 and 2) error holdack oe reset inactive (low) inactive (low) floating floating unless initiating system reset operable (see note 1) active floating (input for xsize1) floating unless initiating system reset r/w tc0:2 tc3 tdo floating floating (set to input) floating (set to input) floating floating (set to input) inactive (high) floating (input for xsize0) operable (see note 1) ts0:2 ts3:6[dp3:0] wbe0:3 [be0:3 ] xmitd inactive (low) floating floating inactive (high) operable (see note 1) operable (see note 1)[?ating when parity mode is enabled] operable (inputs for a4:5, a30:31) operable (see note 1)
ibm powerpc 403gcx 34 address bus multiplexing to support dram memories with differing con?urations and bus widths, the 403gcx provides an inter- nally multiplexed address bus controlled by the biu. table 21 shows the multiplexed address outputs ref- erenced by waveforms later in this section. when the 403gcx is bus master and there are no bus operations in progress, the states of the address bus outputs are determined by the setting of iocr[atc]. if this bit is set to zero, the address bus will be placed in high impedance. if this bit is set to one, the last address held in the biu address register will be driven out on the address bus until bus operations resume. table 20. write byte enable encoding 8-bit bus width transfer size address wbe0 = we wbe1 = 1 wbe2 = a30 wbe3 = a31 byte 0 0100 byte 1 0101 byte 2 0110 byte 3 0111 16-bit bus width transfer size address wbe0 = bhe wbe1 = ble wbe2 = a30 wbe3 =a31 half-word 0 0000 half-word 2 0010 byte 0 0100 byte 1 1001 byte 2 0110 byte 3 1011 32-bit bus width transfer size address wbe0 wbe1 wbe2 wbe3 word00000 half-word 0 0011 half-word 2 1100 byte 0 0111 byte 1 1011 byte 2 1101 byte 3 1110 table 21. multiplexed address outputs address pins a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 addr bits out in ras cycle a6 a7 a8 a9 a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 addr bits out in cas cycle xx a6 a7 a8 a9 a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
ibm powerpc 403gcx 35 sram read-write-read with zero wait and one hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 20 on page 34 for wbe signal de?itions based on bus width. 3. byte enable mode iocr[bem] = 1. wbe0:3 /be0:3 are byte enables and blast is the signal which appears on the multiplexed oe [xsize1][blast ] output. 4. when in byte enable mode iocr[bem] = 1, the blast signal appears on the multiplexed oe [xsize1][blast ] out- put, as described in table 4 on page 8. 5. not byte enable mode iocr[bem] = 0. wbe0:3 /be0:3 are write byte enables and oe is the signal which appears on the multiplexed oe [xsize1][blast ] output. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0000 0 0 0 0 001 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx oe 4 wbe0:3 2,4 d0:31 read address sysclk 1 2 3 4 5 6 7 8 data in data out data in write address read address buserror error? error? error? valid ?be be0:3 5 valid ?be valid ?be blast 5
ibm powerpc 403gcx 36 sram, rom, or i/o write request with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 20 for wbe signal de?itions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of iocr[bem]. see waveform and note 3 on page 35. 4. when in byte enable mode iocr[bem] = 1, the blast signal appears on the multiplexed oe [xsize1][blast ] out- put, as described in table 4 on page 8. 5. wait must be programmed to a value (cson + weon + weoff) and (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 4 until the wait time expires. 6. if hold is programmed > 001, all signals retain the values shown in cycle 6 until the hold timer expires. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0011 0 or 1 0 or 1 0 or 1 0 or 1 001 sysclk a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3,5 d0:31 address valid data out cson=0 cson=1 cson=0 weon=0 cson=1,0 weon=0,1 cson=1 weon=1 wait + 1 cycle hold weoff=1 weoff=0 1 2 3 4 5 6 7 8 buserror error? cson=0 oeon=0 cson=1,0 oeon=0,1 cson=1 oeon=1
ibm powerpc 403gcx 37 sram, rom, or i/o read request, wait extended with ready bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 20 on page 34 for wbe signal de?itions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of iocr[bem]. see waveform and note 3 on page 35. 4. when in byte enable mode iocr[bem] = 1, the blast signal appears on the multiplexed oe [xsize1][blast ] out- put, as described in table 4 on page 8. 5. wait must be programmed to a value (cson + oeon). if wait > (cson + oeon), then all signals will retain the values shown in cycle 4 until the wait timer expires. 6. if hold is programmed > 001, all output signals retain the values shown in cycle 7 until the hold timer expires. 7. if wait = 00 0000, the ready input is ignored and single-cycle transfers occur. if wait > 00 0000, ready is sampled starting after the wait cycles have expired. 8. iocr[sor] = 0. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 1 00 0010 0 or 1 0 or 1 0 or 1 x 001 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3 d0:31 address valid data in cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 cson=1 oeon=1 ready 7 wait not ready not ready sample ready sample data ready hold sysclk 1 2 3 4 5 6 7 8 buserror error?
ibm powerpc 403gcx 38 sram read extended with ready (asynchronous ready mode) bank register settings notes: 1. wbe 2:3 are address bits a30:31 if the bus width is programmed as byte or halfword. 2. not byte enable mode (iocr[bem] = 0). wbe0:3 /be0:3 are write byte enables and oe /blast is oe . 3. byte enable mode (iocr[bem] = 1). wbe0:3 /be0:3 are byte enables and oe /blast is blast 4. arrows indicate when ready is sampled. 5. iocr[are] is set. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 x o xx 1 000010 0 or 1 0 or 1 x 0 001 wait=000010 sample ready cycle sysclk a6:29 1 wbe2 /a30 wbe3 /a31 r/w csx oe 2 blast 3 wbe0 :3 2 be0:3 3 d0:d31 ready cson=0 cson=1 cson=0 oeon=0 cson=1, oeon=0 or cson=0, oeon=1 1 2 3 4 5 6 7 8 9 latch data data in hold=01 valid cson=0 oeon=0 cson=1, oeon=0 or cson=0, oeon=1 4
ibm powerpc 403gcx 39 sram, rom or i/o burst read with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 20 on page 34 for wbe signal de?itions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of iocr[bem]. 4. when in byte enable mode (iocr[bem] = 1), the blast signal appears on the multiplexed oe [xsize1][blast ] out- put, as described in table 4 on page 8. 5. wait must be programmed to a value (cson + oeon). if wait > (cson + oeon), then all signals will retain the values shown in cycle 3 until the wait timer expires. 6. if hold is programmed > 001, all output signals retain the values shown in cycle 7 until the hold timer expires. 7. data parity is only checked when iocr[rdm] = 11 and brhx[pce] is set. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0001 00 0 or 1 0 or 1 x x 001 valid be be be valid be a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3 cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 sysclk 1 2 3 4 5 6 7 8 address1 addr2 addr3 address4 d1 d2 d3 d4 wait + 1 cycles 5 hold burst + 1 cycles burst + 1 cycles burst + 1 cycles 6 buserror error? error? error? error? d0:31 be0:3 3 blast 4
ibm powerpc 403gcx 40 sram, rom or i/o burst write with wait, burst wait, and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 20 on page 34 for wbe signal de?itions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. 4. when in byte enable mode (iocr bit 20 = 0), the blast signal appears on the multiplexed oe [xsize1][blast ] out- put, as described in table 4 on page 8. 5. wait must be programmed to a value (cson + weon + weoff) and (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 3 until the wait timer expires. 6. if hold is programmed > 001, all output signals retain the values shown in cycle 12 until the hold timer expires. 7. data parity is only generated when iocr[rdm] = 11. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0100 01 0 or 1 0 or 1 0 or 1 0 or 1 001 2 3 4 5 6 7 8 9 10 11 12 13 14 1 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 blast 4 wbe0:3 2,3 sysclk address1 addr2 addr3 address4 data1 data2 data3 data4 wait + 1 cycles hold burst + 1 cycles burst + 1 cycles burst + 1 cycles weon=0,1 weon=0 cson=1,0 cson=0 weon=1 cson=1 weoff=1 weoff=1 weoff=1 weoff=1 weoff=0 cson=1 cson=0 buserror error error error error oeon=0,1 oeon=0 cson=1,0 cson=0 oeon=1 cson=1 ? ? ? ? d0:31 valid be be be valid be be0:3 3 oe 4,5
ibm powerpc 403gcx 41 dram 2-1-1-1 page mode read bank register bit settings notes: 1. for burst access, the addresses represented by columns 1 to 4 does not necessarily indicate that they are in incremental address order. typically, burst access is target word ?st. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 21 on page 34. 3. during internal mux mode access, a6:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. 7. data is latched on the rising edge of sysclk when iocr[drc] = 0 (default setting). 8. data is latched later (on the rising edge of cas ) if iocr[drc] = 1. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 00 00 0 x xxxx 1 2 3 4 5 6 7 8 sysclk a11:29, r/w ras cas0:3 dramoe dramwe d0:31 amuxcas ras cas cas cas cas pre-charge row column2 column3 column4 column1 data1 data2 data3 data4 wbe2 [a30], wbe3 [a31] buserror error error error error ? ? ?? note 8 note 7
ibm powerpc 403gcx 42 edo dram 2-1-1-1 burst read followed by single transfer read bank register bit settings notes: 1. iocr[edo] is set and iocr[drc] is cleared. 2. data is latched with respect to the fall of the internal system clock (duty-cycle corrected). 3. data parity, if enabled, matches the timing of data bus transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 x 0 10 0 0 0 1 00 00 0 1 xxxx ? error? cycle sysclk a6:29 1 wbe2 /a30 wbe3 /a31 r/w 1 2 3 4 5 6 7 8 9 10 11 12 13 ras cas dr amoe dr amwe d0:31, dp0:3 row addr col 1 row addr column addr col 2 col 3 col 4 ras cas0 cas1 cas2 cas3 pre-charge ras cas0 pre-chg note 2 d0 d1 d2 d3 d4 amuxcas buserror error? ? ? ?
ibm powerpc 403gcx 43 dram 3-2-2-2 page mode write bank register bit settings notes: 1. for burst access, the addresses represented by columns 1 to 4 do not necessarily indicate that they are in incre- mental address order. typically, burst access is target word ?st. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 21 on page 34. 3. during internal mux mode access, a6:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. 7. dram read on cas , iocr[drc], and edo dram, iocr[edo], modes do not affect writes. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 01 01 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas row column1 column2 column3 column4 ras cas cas cas cas pre-chg cas cas cas cas data1 data2 data3 data4 buserror error? error? error? error?
ibm powerpc 403gcx 44 edo dram 3-1-1-1 burst read followed by single transfer read bank register bit settings notes: 1. iocr[edo] is set and iocr[drc] is cleared. 2. data is latched with respect to the fall of the internal system clock (duty-cycle corrected). 3. data parity, if enabled, matches the timing of data bus transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 x 0/1 10 0 0 0 1 01 00 0 x xxxx cycle sysclk a6:29 1 wbe2 /a30 wbe3 /a31 r/w 1 2 3 4 5 6 7 8 9 10 11 12 13 ras cas dr amoe dr amwe d0:31 row addr col 1 row addr col 2 col 3 ras cas0 cas1 cas2 cas3 pre-chg ras cas pre-chg latch data with fall of cas d0 d1 d2 d3 d4 14 15 16 cas column addr cas0 col 4 note 2 amuxcas buserror error? error? ??? ?
ibm powerpc 403gcx 45 dram read-write-read, one wait bank register bit settings notes: 1. if internal mux mode is used, address bits a11:29 represent address bits described in table 21 on page 34. 2. during internal mux mode access, a6:10 retain their unmultiplexed values. 3. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 4. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 5. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 0 01 xx 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 amuxcas data1 data2 data3 ras cas cas pre- charge ras cas cas pre- charge ras cas cas pre- charge row1 column1 row2 column2 row3 column3 buserror error error error ? ??
ibm powerpc 403gcx 46 dram three-state - refresh request before and after holdack bank register bit settings note: 1. iocr[edt] is set. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate x x 10 0 x 0 x x x x 0 xxxx cycle sysclk a6:29 wbe2 /a30 wbe3 /a31 holdreq 1 2 3 4 5 6 7 8 9 10 11 12 13 holdack ras0:3 cas0:3 dr amwe , 14 15 16 dr amoe , r/w , oe /xsize1 , eo t3 /tc3 /xsize0 , wbe0:3 f e f 0 f d f f0 f bank 4 refresh request gets in just before holdack external master has control of bus; refreshes held off until out of holdack bank 5 refresh counter expired while in holdack. refresh of bank as soon as out of holdack f f
ibm powerpc 403gcx 47 dma buffered single transfer from peripheral to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive inactive at the start of cycle 9 to guarantee a single transfer. 2. this waveform assumes that the internal address mux is used. 3. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 00 00 00 0000 000 dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 oe wbe0:3 1 2 3 4 5 6 7 8 9 10 11 12 sysclk sync sync biu req dma ack ras cas cas pre-chg row column data data
ibm powerpc 403gcx 48 dma fly-by single transfer, write to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive in cycle 7 (last dmaa cycle) to guarantee a single transfer. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 01 note 3 xx xxxx xxx 1 sysclk dmar dmaa 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 s=2 sync sync biu req ras cas cas pre-chg (s = peripheral setup time) a11:29 r/w ras cas0:3 dramoe dramwe d0:31 row column data dmadxfer
ibm powerpc 403gcx 49 dma fly-by continuous burst to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive at the end of cycle 10 (last dmaa cycle) to guarantee three transfers. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. 6. numbers ( 1 , 2 , 3 ,...) in the dmar signal represent when dmar is sampled and accepted. numbers ( 1 , 2 , 3 ,...) in the dmaa signal represent the transfers associated with the accepted dmar . slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 1 01 01 0 x xxxx transfer direction transfer width transfer mode peripheral setup peripheral wait peripheral hold burst mode bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 bit 25 1 10 01 note 3 xx xxxx xxx 1 1 sysclk dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 (s = peripheral setup time) dmadxfer sync sync biu req ras cas cas cas cas cas cas pre-chg row column1 column2 column3 data1 data2 data3 1 2 3 1 1 1 2 2 3 3
ibm powerpc 403gcx 50 external master nonburst dram read with holdreq/holdack bank register bit settings notes: 1. xreq , xsize0, xsize1, and xac k are multiplexed with dmar3 , eo t3 /tc3 , oe , and dmaa3 , respectively. 2. a4, a5, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 0 01 xx 0 x xxxx sysclk r/w rasx cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas ras cas pre- charge cas holdreq holdack xsize0:1 1 xreq bsel ext bus master dram contr ol 10 valid address - ext master 403 address 403 data hiz hiz 403 master 403 master dram drives bus a4:31 2 xreq 1 xac k 1
ibm powerpc 403gcx 51 external master dram burst write, 3-2-2-2 page mode bank register bit settings notes: 1. xreq , xsize0, xsize1, and xac k are multiplexed with dmar3 , eo t3 /tc3 , oe , and dmaa3 , respectively. 2. xsize0:1 = 11 indicates a burst transfer at the width of the dram device. 3. the burst is terminated in cycle 12 by deasserting the xreq input signal. a burst may also be terminated by deas- serting either xsize0 or xsize1. 4. a4, a5, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 1 01 01 0 x xxxx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 sysclk r/w rasx cas0:3 dramoe dramwe d0:31 amuxcas holdreq holdack xsize0:1 1,2,3 ext bus master dram contr ol ras cas pre- chg cas xreq bsel cas cas cas cas cas cas 11 11 11 valid address1 - ext master valid data1 - ext master address2 address3 address4 data2 data3 data4 a4:31 4 xreq 3 xac k 17 18
ibm powerpc 403gcx 52 ordering information this section provides the part numbering nomenclature for the 403gcx. for availability, contact your local ibm sales of?e. table 22. ppc403gcx part number ibm part number oemls part number processor bus frequency package revision level 06k6173 ibm25403GCX-3JC76C2 76 mhz pqfp c ibm part number key for 403gcx 403 family ibm25403GCX-3JC76C2 package: clock doubler commercial j - pqfp b - pbga grade: 3 = 100 fits 2 = 25 fits revision level cpu speed: 50, 66, 80
ibm powerpc 403gcx 53
copyright ibm corporation 1996,2000. all rights reserved. printed in the usa on recycled paper. 8-00 ibm microelectronics, powerpc, powerpc architecture, and 403gcx are trademarks, ibm and the ibm logo are registered trademarks of ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility of liability for any use of the information contained herein. nothing in this docu- ment shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including but not limited to the implied warran- ties of merchantability or fitness for a particular purpose, are offered in this document. ibm microelectronics division 1580 route 52, bldg. 502 hopewell junction, ny 12533-6531 tel: (800) powerpc sc09-3033-sp 08.16.00

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