advance information 1.8v, 25-bit (1:1) or 14-bit (1:2 ) jedec-compliant data registe r cy2sstu3286 4 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07576 rev. ** revised september 9, 2003 features ? operating frequency: dc to 333 mhz supports ddrii sdram two operations modes: 25 bit (1:1) and 14 bit (1:2) 1.8v operation fully jedec-compliant 96-ball lfbga description all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8-v cmos drivers that have been optimized to drive the ddr-ii dimm load. the sstu32864 operates from a differential clock (ck and ck#). data are registered at the crossing of ck going high, and ck# going low. the c0 input controls the pinout configuration of the 1:2 pinout from a configuration (when low) to b configuration (when high). the c1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). c0 = 1 and c1 = 0 is not allowed and should default to the c0 = c1 = 0 state. the device monitors both dcs# and csr# inputs and will gate the qn outputs from changing states when both dcs# and csr# inputs are high. if either dcs# or csr# input is low, the qn outputs will function normally. the reset input has priority over the dcs# and csr# control and will force the outputs low. if the dcs#-control functionality is not desired, the csr# input can be hardwired to ground, in which case the set-up time requirement for dcs# would be the same as for the other d data inputs. the device supports low-power standby operation. when the reset input (reset#) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (vref) inputs are allowed. in addition, when reset# is low, all registers are reset and all outputs are forced low. the lvcmos reset# and cn inputs must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset# must be held in the low state during power-up. in the ddr-ii rdimm application, reset# is specified to be completely asynchronous with respect to ck and ck#. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. block diagram pin configuration
advance information cy2sstu3286 4 document #: 38-07576 rev. ** page 2 of 2 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document history page document title:CY2SSTU32864 1.8v, 25-bit (1:1) or 14-bit (1:2) jedec-compliant data register document number: 38-07576 rev. ecn no. issue date orig. of change description of change ** 129199 09/09/03 rgl new data sheet
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