pcix i/o system clock generator with em i control feature s c953 0 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07033 rev. *b revised may 9, 2003 features ? dedicated clock buffer power pins for reduced noise, crosstalk and jitter input clock frequency of 25 mhz to 33.3 mhz output frequencies of xinx1, xinx2, xinx3 and xinx4 output grouped in two banks of five clocks each one ref xin clock output smbus clock control interface for individual clock disabling and sscg control and individual back frequency selection output clock duty cycle is 50% ( 5%) < 250 ps skew between output clocks within a bank output jitter < 250 psec (175 psec with all outputs at the same frequency) spread spectrum feature for reduced electromagnetic interference (emi) oe pins for entire output bank enable control and testability 48-pin ssop and tssop packages note: 1. a and b banks have separate frequency select and output enable controls. xin is the frequency of the clock on the device?s xi n pin. oea and oeb will three-state ref. table 1. test mode logic table [1] input pins output pins oea sa1 sa0 clka ref oeb sb1 sb0 clkb high low low xin xin high low high 2 * xin xin high high low 3 * xin xin high high high 4 * xin xin low x x three-state three-state block diagram pin configuration xin clkb4 clkb3 clkb2 clkb1 clkb0 oeb clka3 clka2 clka1 clka0 /n sscg# clka4 sscg logic /n 1 1 0 0 xout i 2 c control logic sclk oea ia(0:2) agood# bgood# ref sdata sa(0,1) sb(0,1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 xin vdd xout vss sa1 vss clka0 vdda clka2 vss vdda clka4 vss clka1 agood# vss ia1 ia2 avdd oea oeb vss sscg# vss avdd bgood# avdd clkb4 vddb vss vddb clkb1 vss sb1 vss clkb3 clkb2 clkb0 sb0 vdd vss vdd sclk sdata ia0 c9530 ref 41 42 43 44 45 46 47 48 sa0 clka3
c953 0 document #: 38-07033 rev. *b page 2 of 10 notes: 2. pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. a bypass capacitor (0.1 f) should be placed as close as possible to each v dd pin. if these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. pwr = power connection, i = input, o = output and i/o = both input and output functionality of the pin(s). pin description [3] pin [2] name pwr [4] i/o description 3 xin vdda i crystal buffer input pin . connects to a crystal, or an external clock source. serves as input clock tclk, in test mode. 4 xout vdda o crystal buffer output pin . connects to a crystal only. when a can oscillator is used or in test mode, this pin is kept unconnected. 1 ref vdd o buffered inverted outputs of the signal applied at xin , typically 33.33 or 25.0 mhz 24* oea vdd i output enable for clock bank a . causes the clka output clocks to be in a three-state condition when driven to a logic low level. 25* oeb vdd i output enable for clock bank b . causes the clkb output clocks to be in a three-state condition when driven to a logic low level. 18 agood# vdd o when this output signal is a logic low level, it indicates that the output clocks of the a bank are locked to the input reference clock . this output is latched. 31 bgood# vdd o when this output signal is at a logic low level, it indicates that the output clocks of the b bank are locked to the input reference clock . this output is latched. 6*, 7* sa(0,1) vdd i clock bank a selection bits . these control the clock frequency that will be present on the outputs of the a bank of buffers. see table 1 for frequency codes and selection values. 43*, 42* sb(0,1) vdd i clock bank b selection bits . these control the clock frequency that will be present on the outputs of the b bank of buffers. see table 1 for frequency codes and selection values. 20*, 21*, 22* ia(0:2) vdd i smbus address selection input pins . see table 3 smbus address table. 27* sscg# vdd i enables spread spectrum clock modulation when at a logic low level, see spread spectrum clocking on page 6. 48 sdata vdd i/o data for the internal smbus circuitry . 47 sclk vdd i clock for the internal smbus circuitry . 11, 14 vdda ? pw r 3.3v common power supply pin for bank a pci clocks clka . 38, 35 vddb ? pw r 3.3v common power supply pin for bank b pci clocks clkb . 2, 44, 46 vdd ? pw r power supply for internal core logic . 23, 29, 30 avdd ? pw r power for internal analog circuitry . this supply should have a separately decoupled current source from vdd. 9, 10, 12, 15, 16 clka (0:4) vdda o a bank of five xinx1, xinx2, xinx3 and xinx4 output clocks . 40, 39, 37, 34, 33 clkb (0:4) vddb o a bank of five xinx1, xinx2, xinx3 and xinx4 output clocks . 5, 8, 13, 17, 19, 26, 28, 32, 36, 41, 45 vss ? pwr ground pins for the device .
c953 0 document #: 38-07033 rev. *b page 3 of 10 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. data protocol the clock driver serial protocol accepts block write a opera- tions from the controller. the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. the c9530 does not support the block read function. the block write protocol is outlined in table 2 . the addresses are listed in table 3 . serial control registers table 2. block read and block write protocol block write protocol bit description 1start 2:8 slave address ? 7 bits 9write = 0 10 acknowledge from slave 11:18 command code ? 8 bits ?00000000? stands for block operation 19 acknowledge from slave 20:27 byte count ? 8 bits 28 acknowledge from slave 29:36 data byte 1 ? 8 bits 37 acknowledge from slave 38:45 data byte 2 ? 8 bits 46 acknowledge from slave .... ...................... .... data byte (n?1) ? 8 bits .... acknowledge from slave .... data byte n ? 8 bits .... acknowledge from slave .... stop table 3. smbus address selection table smbus address of the device ia0 bit (pin 10) ia1 bit (pin 11) ia2 bit (pin 12) de 0 0 0 dc 1 0 0 da 0 1 0 d8 1 1 0 d6 0 0 1 d4 1 0 1 d0 0 1 1 d2 1 1 1 byte 0: function select register bit @pup name description 7 1 testen test mode enable. 1 = normal operation, 0 = test mode 6 0 ssen spread spectrum modulation control bit (effective only when bit 0 of this register is set to a 0) 0 = off, 1= on 5 1 sssel sscg spread width select. 1 = 0.5%, 0 = 1.0% see table 4 below for clarification 4 0 s1 sb1 bank msb frequency control bit (effective only when bit 0 of this register is set to a 0) 3 0 s0 sb0 bank lsb frequency control bit (effective only when bit 0 of this register is set to a 0)
c953 0 document #: 38-07033 rev. *b page 4 of 10 2 0 sa1 bank msb frequency control bit (effective only when bit 0 of this register is set to a 0) 1 0 sa0 bank lsb frequency control bit (effective only when bit 0 of this register is set to a 0) 0 1 hwsel hardware/smbus frequency control. 1 = hardware (pins 6, 7, 42, 43 and 27), 0 = smbus byte 0 bits 1-4, & 6 table 4. clarification table for byte0, bit 5 byte0, bit6 byte0, bit5 description 0 0 frequency generated from second pll 0 1 frequency generated from xin 1 0 spread @ ?1.0% 1 1 spread @ ?0.5% table 5. test table test function clock outputs clka clkb ref frequency xin/6 xin/4 xin byte 1: a bank and ref clock control register bit @pup name description 71 reserved 61 reserved 5 1 refen ref output enable 0 = disable, 1= enable 4 1 clka4 output enable 0 = disable, 1= enable 3 1 clka3 output enable 0 = disable, 1= enable 2 1 clka2 output enable 0 = disable, 1= enable 1 1 clka1 output enable 0 = disable, 1= enable 0 1 clka0 output enable 0 = disable, 1= enable byte 2: pci register bit @pup name description 71 reserved 61 reserved 51 reserved 4 1 18 clkb4 output enable 0 = disable, 1= enable 3 1 19 clkb3 output enable 0 = disable, 1= enable 2 1 22 clkb2 output enable 0 = disable, 1= enable 1 1 23 clkb1 output enable 0 = disable, 1= enable 0 1 24 clkb0 output enable 0 = disable, 1= enable byte 0: function select register (continued)
c953 0 document #: 38-07033 rev. *b page 5 of 10 internal crystal oscillator this device will operate in two input reference clock configu- rations. in its simplest mode a 33.33mhz fundamental cut parallel resonant crystal is attached to the xin and xout pins. in the second mode a 33.33-mhz input reference clock is driven in on the in clock from an external source. in this appli- cation the xout pin must be left disconnected. output clock three-state control all of the clocks in bank a (clka) and bank b(clkb) may be placed in a three-state condition by bringing their relevant oe pins (oea and oeb) to a logic low state. this transition to and from a state and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. this function is intended as a board level testing feature. when the output clocks are being enabled and disabled in active environments the smbus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. output clock frequency control all of the output clocks have their frequency selected by the logic state of the s0 and s1 control bits. the source of these control signals is determined by the smbus register byte 0 bit 0. at initial power up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the device?s s(0,1) pins. if the application does not use an smbus interface then hardware frequency selection s(0,1) must be used. if it is desired to control the output clocks using an smbus interface, then this bit (b0b0) must first be set to a low state. after this is done the device will use the contents of the internal smbus register bytes 0 bits 3 and 4 to control the output clock?s frequency. the following formula and schematic may be used to under- stand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal where: c xtal = the load rating of the crystal. c xinftg = the clock generators xin pin effective device internal capacitance to ground. c xoutftg = the clock generators xout pin effective device internal capacitance to ground. c xinpcb = the effective capacitance to ground of the crystal to device pcb trace. c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace. c xindisc = any discrete capacitance that is placed between the xin pin and ground. c xoutdisc = any discrete capacitance that is placed between the xin pin and ground. notes: 5. for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal m eets or exceeds these specifications. 6. larger values may cause this device to exhibit oscillator startup problems. table 6. suggested oscillator crystal parameters parameter description conditions min typ. max. unit f o frequency 33.0 33.33 33.5 mhz t c tolerance see note 5 ? ? 100 ppm t s stability (t a ?10 to +60c) note 5 ? ? 100 ppm t a aging (first year @ 25c) note 5 ??5ppm operating mode parallel resonant, note 5 ??? c xtal load capacitance the crystal?s rated load. note 5 ?20?pf r esr effective series resistance (esr) note 6 ? 40 ? ohms (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb ) + c xoutftg ) + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb ) + c xoutftg ) + c xoutdisc ) c l =
c953 0 document #: 38-07033 rev. *b page 6 of 10 as an example and using this formula for this data sheet?s device, a design that has no discrete loading capacitors (c disc ) and each of the crystal device pcb traces has a capacitance (c pcb ) to ground of 4 pf (typical value) would calculate as follows. therefore, to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20 pf. spread spectrum clocking down spread description spread spectrum is a modulation technique for distributing clock period over a certain bandwidth (called spread bandwidth). this technique allows the distribution of the undesirable electromagnetic energy (emi) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. as the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all it's harmonics. in this device, spread spectrum is enabled externally through pin 27 (sscg#) or internally via smbus byte 0 bit 0 and 6. spread spectrum is enabled externally when the sscg# pin is low. this pin has an internal device pull up resistor, which causes its state to default to a high (spread spectrum disabled) unless externally forced to a low. it may also be enabled by programming smbus byte 0 bit 0 low (to enable smbus control of the function) and then programming smbus byte 0 bit 6 low to set the feature active. c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator (4 pf + 36 pf + 0 pf) x (4 pf + 36 pf + 0 pf) (4 pf + 36 pf + 0 pf) x (4 pf + 36 pf + 0 pf) c l = 40 x 40 40 x 40 = = 1600 80 = 20 pf table 7. spectrum spreading selection table [7] output clock frequency % of frequency spreading mode smbus byte 0 bit 5 = 0 smbus byte 0 bit 5 = 1 33.3 mhz (xin) 1.0% (?1.0% + 0%) 0.5% (?0.5% + 0%) down spread 66.6 mhz (xin*2) 1.0% (?1.0% + 0%) 0.5% (?0.5% + 0%) down spread 100.0 mhz (xin*3) 1.0% (?1.0% + 0%) 0.5% (?0.5% + 0%) down spread 133.3 mhz (xin*4) 1.0% (?1.0% + 0%) 0.5% (?0.5% + 0%) down spread note: 7. when sscg is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. this means that for a 100-mhz output clock frequency will sweep through a spectral range from 99 to 100 mhz. spread off spread on center frequency, spread off c enter frequency, spread on figure 1. spread spectrum
c953 0 document #: 38-07033 rev. *b page 7 of 10 absolute maximum conditions parameter description condition min. max. unit v dd, v ddp core supply voltage ?0.5 4.6 v v dda analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 +150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 15 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 45 c/w ul?94 flammability rating at 1/8 in. v ? 0 msl moisture sensitivity level 1 multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description condition min. max. unit v dd , v dda, v ddb 3.3 operating voltage 3.3v 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? 1.0 v v ihi2c input high voltage sdata, sclk 2.2 ? ? v il input low voltage s(a,b)o, s(a,b)1, oe(a,b) v ss ? 0.5 0.8 v v ih input high voltage 2.0 v dd + 0. 5 v i il input leakage current except pull-ups or pull-downs 0 c953 0 document #: 38-07033 rev. *b page 8 of 10 test and measurement set-up t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns t ccj xin cycle to cycle jitter as an average over 1 s duration ?500ps l acc long-term accuracy over 150 ms 300 ppm clk t dc clk duty cycle measurement at 1.5v 45 55 % t period33 33mhz clk period measurement at 1.5v 29.5 30.5 ns t period66 66mhz clk period measurement at 1.5v 14.5 15.5 ns t period100 100mhz clk period measurement at 1.5v 9.5 10.5 ns t period133 133mhz clk period measurement at 1.5v 7.0 8.0 ns t r / t f clk rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skew any clk to any clk clock skew measurement at 1.5v ? 250 ps t ccj clk cycle to cycle jitter measurement at 1.5v ? 175 ps ref t dc ref duty cycle measurement at 1.5v 45 55 % t r / t f ref rise and fall times measured between 0.4v and 2.4v 1.0 4.0 ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 750 ps enable/disable and set-up tpzl,tpzh output enable delay (all outputs) ? 10.0 ns tplz,tpzh output disable delay (all outputs) ? 10.0 ns t stable clock stabilization from power-up ? 3.0 ms ac electrical specifications (continued) parameter description condition min. max. unit 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals td c - - probe o utput under test load cap lumped load lvttl signaling figure 2. test and measurement set-up table 8. loading output name max load (in pf) clk5 30 ref 20
c953 0 document #: 38-07033 rev. *b page 9 of 10 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams all product and company names mentioned in this document may be the trademarks of their respective holders. ordering information part number package type product flow imic9530cy 48-pin ssop commercial, 0 to 70c imic9530cyt 48-pin ssop ? tape and reel commercial, 0 to 70c IMIC9530CT 48-pin tssop commercial, 0 to 70c IMIC9530CTt 48-pin tssop ? tape and reel commercial, 0 to 70c 48-lead shrunk small outline package o48 51-85061-*c 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48 51-85059-*b
c953 0 document #: 38-07033 rev. *b page 10 of 10 document history page document title: c9530 pcix i/o system clock generator with emi control features document #: 38-07033 rev. ecn no. issue date orig. of change description of change ** 106961 06/12/02 ika convert from imi to cypress *a 122726 12/17/02 rbi added power-up requirements to maximum ratings information *b 126595 05/14/03 rgl converted from word to framemaker fixed ac and dc tables to match char data added 25-mhz operation.
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