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PIO-96 96 channel programmable input/output board user manual

PIO-96 user manual document part n 0127-1015 document reference 0127-1015.doc document issue level 1.2 manual covers pcbs identified PIO-96 rev b all rights reserved. no part of this publication may be reproduced, stored in any retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or otherwise, without the prior permission, in writing, from the publisher. for permission in the uk contact blue chip technology. information offered in this manual is correct at the time of printing. blue chip technology accepts no responsibility for any inaccuracies. this information is subject to change without notice. all trademarks and registered names acknowledged. blue chip technology ltd. chowley oak, tattenhall chester, cheshire ch3 9ex. telephone : 01829 772000 facsimile : 01829 772001.
amendment history issue level issue date author amendment details 1.1 first draft 1.2 24.11.97 sej window front cover and logo. see ecn 98/088
conten ts blue chip technology ltd. 01271015.doc 1.0 introduction ................................ ................................ .......... 1 electromagnetic compatibility (emc) ................................ . 2 emc specification ................................ ................................ ......... 3 2.0 user adjustments ................................ ................................ 4 2.1 selecting the base address (jp1) ................................ ............ 4 2.2 setting the interrupt channel (jp2) ................................ .......... 6 3.0 port map ................................ ................................ .................. 7 3.1 control port bit functions ................................ ........................ 8 4.0 electrical options ................................ .............................. 9 4.1 input conditioning ................................ ................................ .... 9 4.2 input/output connections ................................ ......................... 9 4.3 connector pin details ................................ ............................. 11 5.0 operating guide ................................ ................................ .. 12 5.1 using the device ................................ ................................ .... 12 5.2 programming guide ................................ ............................... 13 simple inputs ................................ ................................ ............... 13 simple outputs ................................ ................................ ............ 13 typical register setups ................................ ............................... 15 6.0 example programs ................................ ............................. 16 example program 1 ................................ ................................ ..... 16 example program 2 ................................ ................................ ..... 17 7.0 commercial data acquisition packages .................... 20 7.1 use of the PIO-96 board with asyst ................................ .... 20 appendix ................................ ................................ ....................... 21 a1 i/o address map for pc/xt/at computers ............................ 21 a2 hardware interrupt levels for pc/xt ................................ ...... 22 a3 hardware interrupt levels for pc/at ................................ ...... 23 dma channels ................................ ................................ ............. 23

introduction page 1 blue chip technology ltd. 01271015.doc page 1 1.0 introduction this card provides 96 programmable digital i/o lines. it is suitable for sensing or driving ttl connections only. there is provision for a set of on board pull up resistors to enable the board to be used to detect contact closures on push buttons, relay contacts etc. this manual refers to printed circuit boards identified (on the rear of the board) by the reference ?PIO-96 rev. b?. whilst every effort has been taken to ensure that the information provided is accurate, blue chip technology cannot assume responsibility for any errors in this manual or their consequences. should any errors be detected, the company would greatly appreciate being informed of them. a policy of continuous product development is operated, resulting in the contents of this document being subject to change without notice.
page 2 electromagnetic compatibility (emc) page 2 01271015.doc blue chip technology ltd. electromagnetic compatibility (emc) this product meets the requirements of the european emc directive (89/336/eec) and is eligible to bear the ce mark. it has been assessed operating in a blue chip technology icon industrial pc. however, because the board can be installed in a variety of computers, certain conditions have to be applied to ensure that the compatibility is maintained. it meets the requirements for an industrial environment ( class a product) subject to those conditions. the board must be installed in a computer system which provides screening suitable for the industrial environment. any recommendations made by the computer system manufacturer/supplier must be complied with regarding earthing and the installation of boards. the board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal-to-metal (i.e. earth) contact. most emc problems are caused by the external cabling to boards. with analogue boards particular attention must be paid to this aspect. it is imperative that any external cabling to the board is totally screened, and that the screen of the cable connects to the metal end bracket of the board and hence to earth. it is recommended that round screened cables with a braided wire screen are used in preference to those with a foil screen and drain wire. use metal connector shells which connect around the full circumference of the screen; they are far superior to those which earth the screen by a simple ?pig -tail?. standard ribbon cable w ill not be adequate unless it is contained wholly within the cabinetry housing the industrial pc. if difficulty with interference is experienced the cable should also be fitted with a ferrite clamp as close possible to the connector. the preferred type is the chomerics clip -on style, type h8fe-1004-as.
electromagnetic compatibility (emc) page 3 blue chip technology ltd. 01271015.doc page 3 it is recommended that cables are kept as short as possible, particularly when dealing with low level signals. ensure that the screen of the external cable is bonded to a good rf earth at the remote end of the cable. failure to observe these recommendations may invalidate the emc compliance. warning this is a class a product. in a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures. emc specification a blue chip technology icon industrial pc fitted with this card meets the following specification: emissions: en 55022:1995 radiated class a conducted class a & b immunity: en 50082-1:1992 incorporating electrostatic disc harge iec 801-2:1984 performance criteria b radio frequency susceptibility iec 801-3:1984 performance criteria a fast burst transients iec 801-4:1988 performance criteria b
page 4 user adjustments page 4 01271015.doc blue chip technology ltd. 2.0 user adjustments 2.1 selecting the base address (jp1) the board may be located in any 62 pin isa slot in the pc motherboard, but must be set up to appear at a specified position (or ?address?) in the computer?s port map. available positions are shown in the ibm-pc technical reference guide. however, for those who do not possess a copy of this document a good place is the location normally allocated to the prototyping card as supplied by ibm. this address is 300 (hex) or 768 (decimal). all blue chip technology cards are preset to this address at the factory. however, no two devices should be used while set to the same address since contention will occur and neither board will work. if your machine contains a card with a conflicting address then another reasonably safe address is 200 to 21f (hex). a set of links on the board set the base address of the board within the ibm-pc port map. the address is in binary with the presence of a link representing a 0 and the absence of a link representing a 1.
user adjustments page 5 blue chip technology ltd. 01271015.doc page 5 to set the base address to 300 hex (768 decimal) set the pattern on the links as indicated below: 100h 200h 40h 80h 10h 20h jp1 figure 1 - selecting the base address more example addresses are shown in appendix a. note: no two cards must occupy the same address.
page 6 user adjustments page 6 01271015.doc blue chip technology ltd. 2.2 setting the interrupt channel (jp2) the PIO-96 card supports the use of the interrupts generated from the m pd71055 chips. these chips are identical functionally to the intel 8255 integrated circuit. the use of the interrupts provides a means to monitor digital inputs only when there has been a change at the input signal lines. the use of interrupts requires the user to write an interrupt handler routine (either in c or assembler) and install it prior to using the PIO-96 card. to select an interrupt channel, a link must be set on jumper block jp2. an interrupt is selected by placing a jumper link on the pair of link pins corresponding to the desired interrupt channel. all other interrupt channel links must be left open. note: only one link is permitted on jp2. if more than one link is fitted then the computer system may not function correctly. figure 2 - setting the interrupt channel the above diagram shows the jumper block jp2 with a link placed on interrupt channel 3. please note that the silk screen printing of the interrupt numbers on the printed circuit board is incorrect. the diagram above shows the correct sequence.
port map page 7 blue chip technology ltd. 01271015.doc page 7 3.0 port map the PIO-96 has four m pd71055 (8255) chips. each chip has three 8 bit ports (a, b & c) which can be programmed as inputs or outputs by writing a control word to the control port. (see table 2). all ?a? ports and ?b? ports much each be all input or all output, i.e. they should not be programmed to mixed input and output bits within an individual port. port c may be split into two 4 bit sections each of which may be input or output. the board occupies sixteen read/write addresses (four for each m pd71055 chip) in the ibm-pc port map. address port base + 0 port a base + 1 port b base + 2 port c base + 3 command port 1 base + 4 port a? base + 5 port b? base + 6 port c? base + 7 command port 2 base + 8 port a?? base + 9 port b?? base + 10 port c?? base + 11 command port 3 base + 12 port a??? base + 13 port b??? base + 14 port c??? base + 15 command port 4 table 1 - port addresses
page 8 port map page 8 01271015.doc blue chip technology ltd. the function and operation of each of the input/output ports (a, b & c) are controlled by the control byte which is written to the appropriate command port. each bit within the byte has a specific function, shown in table 2. 3.1 control port bit functions bit no function settings 7 mode set flag 0=inactive 1=active 00=mode 0 5, 6 mode selection 01=mode 1 4 port a 0=output 1=input 3 port c (upper) 0=output 1=input 2 mode selection 0=mode 0 1=mode 1 1 port b 0=output 1=input 0 port c (lower) 0=output 1=input table 2 - control port - bit functions the software described in section 5 the operating guide gives examples of the more typical control bytes and their effects.
electrical options page 9 blue chip technology ltd. 01271015.doc page 9 4.0 electrical optio ns 4.1 input conditioning the 71055 has high impedance inputs. an option is provided to terminate external input lines. this is useful in an electrically noisy environment or where a load is required (e.g. open collector drive). the lines may be pulled up to the on-board +5v supply using 12 off sil resistor packs (identified on the pcb as ?rp1? to ?rp6? and ?rp11? to ?rp16? inclusive). the recommended values of each resistor to 10kohm. 4.2 input/output connections two 50 way insulation displacement connectors (idc) are provided for i/o channel signal connection. one connector is located on the rear bracket and carries signals 1 to 48. the second connector is located on the board and carries signals 49 to 96. this connector may be brought out to the rear of the computer via an adapter cable. if access to individual channels is required, a 50 way idc ribbon cable may be used to connect the i/o channels to a 50 way screw terminal block available from blue chip technology as part number st-24. the pins are numbered as shown in the following diagram. pins 1-48 contain the i/o signal lines and pins 49 and 50 are connected to digital ground. both connectors are identical in their pin-out.
page 10 electrical options page 10 01271015.doc blue chip technology ltd. when the connector is viewed from the back of the system odd numbered pins are on the left and even numbered pins are on the right with pin 1 at the top of the connector. figure 3 - connector pin details (p1 and p2) (view with gold edge connector facing downwards.)
electrical options page 11 blue chip technology ltd. 01271015.doc page 11 4.3 connector pin details port bit no. pin no. pin no. bit no. port a (1) 0 1 2 0 a (2) 1 3 4 1 2 5 6 2 3 7 8 3 4 9 10 4 5 11 12 5 6 13 14 6 7 15 16 7 b (1) 0 17 18 0 b (2) 1 19 20 1 2 21 22 2 3 23 24 3 4 25 26 4 5 27 28 5 6 29 30 6 7 31 32 7 c (1) 0 33 34 0 c (2) 1 35 36 1 2 37 38 2 3 39 40 3 4 41 42 4 5 43 44 5 6 45 46 6 7 47 48 7 digital ground 49 50 digital ground table 3 - signal pin connection details (pin out of both connectors is identical)
page 12 operating guide page 12 01271015.doc blue chip technology ltd. 5.0 operating guide 5.1 using the device a total of 24 i/o channel signals from each 71055 i/o device on the PIO-96 board provides twelve 8-bit ports. each signal is connected to one bit within one of these ports i.e.
operating guide page 13 blue chip technology ltd. 01271015.doc page 13 5.2 programming guide simple inputs the state of the input lines may be determined by using either of the following methods: microsoft basic a or gw basic. x=inp (p) returns the byte from port p and assigns this value to the variable x. 8088/8086 assembly language. port equ 0300h getdat: mov dx,port in al,dx ret simple outputs the state of the output lines may be modified by using either of the following methods: microsoft basic a or gw basic. out p,d outputs the byte d to port p
page 14 operating guide page 14 01271015.doc blue chip technology ltd. 8088/8086 assembly language port equ 0300h putdat: mov dx,port mov ax,data out dx,al ret the m pd71055 can operate in one of 3 modes (mode 0, 1 & 2). in the first mode (mode 0) the m pd71055 provides simple i/o for three 8 bit ports. data is simply written to, or read from a specified port (a, b or c) without the use of handshaking. mode 1 enables the transfer of data to or from a specified 8 bit port (a or b) in conjunction with strobes or handshaking signals provided by port c. in mode 2 data is transferred via one bi-directional 8 bit port (a) with handshakes (port c).
operating guide page 15 blue chip technology ltd. 01271015.doc page 15 the following table gives a summary of the most commonly used ?control words? which must be written to each control port to configure the m pd71055s before using this module. the table assumes mode 0. typical register setups control word (hex.) control word (dec.) sets all of port b as sets high 4 bits of port b as sets high 4 bits of port c as sets low 4 bits of port c as 80 128 output output output output 81 129 output output output input 82 130 output input output output 83 131 output input output input 88 136 output output input output 89 137 output output input input 8a 138 output input input output 8b 139 output input input input 90 144 input output output output 91 145 input output output input 92 146 input input output output 93 147 input input output input 98 152 input output input output 99 153 input output input input 9a 154 input input input output 9b 155 input input input input table 4 - simple i/o control words for a full explanation of the various modes of operating, and the use of the signal lines consult the intel 8255 or nec m pd71055 datasheet.
page 16 exampl e programs page 16 01271015.doc blue chip technology ltd. 6.0 example programs example program 1 the following program in microsoft basic will test the operation of the PIO-96 if a link is made between corresponding pins on the rear of the connector. 10 p1=&h300 : rem base of first pia 15 p2 = &h304 : rem base of second pia 20 gosub 60 30 p1 = &h304 : p2 = &h300 40 gosub 60 50 goto 10 : rem loop continuously 60 out p1+3, &h80 : out p2+3, &h9b 70 for p = 0 to 2 80 f = 0 90 a = 1 100 out p1+p,a 110 if inp(p2+p)<>a then print ?error?, p,a,inp(p2+p):f=f+1 120 a=a+a 130 if a=256 then goto 150 140 goto 100 150 if f>0 then print p, ?failed?, f:goto 170 160 print p,?passed? 170 next p 180 return the program runs continuously and can only be stopped by pressing control-break on the pc keyboard.
example programs page 17 blue chip technology ltd. 01271015.doc page 17 example program 2 this example program shows the use of interrupts generated from the m pd71055 pio chip. the program sets mode 1 operation which allows data to be strobed into port 0 of the first m pd71055 via a low signal on port 2 bit 4. to determine when data has been strobed into the data port, this example polls the m pd71055 port 2 register which in mode 1 acts as a control/status register. in normal use an interrupt handler routine written in c or assembler would be resident in memory to respond to the hardware interrupt generated by the pio card. notes: prior to using interrupts, an interrupt routine must be installed in memory by the application software. to use interrupts all unused ?int0? and ?int1? lines (bits 0 and 3 of each m pd71055 port 2) must be low. this means that if a m pd71055 has been set to (say) mode 0 with all ports as output then port 2 output lines 0 and 3 must be written to a zero (low) state. if the ports were set to inputs then interrupts will only occur if port 2 input lines 0 and 3 are low for each m pd71055 not being used in an interrupt mode. the above is necessary because each m pd71055 ?int0? and ?int1? lines are logically or- ed together.
page 18 exampl e programs page 18 01271015.doc blue chip technology ltd. cls bseaddr% = &h300 port0a% = bseaddr% + 0 port1a% = bseaddr% + 1 port2a% = bseaddr% + 2 ctrlprta% = bseaddr% + 3 port0b% = bseaddr% + 4 port1b% = bseaddr% + 5 port2b% = bseaddr% + 6 ctrlprtb% = bseaddr% + 7 port0c% = bseaddr% + 8 port1c% = bseaddr% + 9 port2c% = bseaddr% + 10 ctrlprtc% = bseaddr% + 11 port0d% = bseaddr% + 12 port1d% = bseaddr% + 13 port2d% = bseaddr% + 14 ctrlprtd% = bseaddr% + 15 rem set pd71055 no 2, 3 and 4 to mode 0 - all ports = outputs out ctrlprtb%, &h80 out ctrlprtc%, &h80 out ctrlprtd%, &h80 rem set all ports for pd71055 nos 2, 3 and 4 to low out port0b%, 0 out port1b%, 0 out port2b%, 0 out port0c%, 0 out port1c%, 0 out port2c%, 0 out port0d%, 0 out port1d%, 0 out port2d%, 0
example programs page 19 blue chip technology ltd. 01271015.doc page 19 rem set mode 1 for normal operation for pd71055 no 1 rem port 0 = input rem port 1 = input rem bits 7 and 6 of port c = input rem groups 0 and 1 set to mode 1 out ctrlprta%, &hb0 rem set bit manipulation mode to set up pd71055 chip no 1 rem and set bit 4 high to enable int0 out ctrlprta%, &h9 locate 1, 1: print "port 0 of pd71055 no1" rdval: rem get port data before interrupt dt% = inp(port0a%) pol: rem read input buffer full status (bit 5) for pd71055 no 1 rem this determines when the data strobe has occurred irq% = (inp(port2a%) and 32) if irq% = 0 then goto pol locate 3, 1: print "before interrupt"; dt% rddat: rem read data from port 0 dta% = inp(port0a%) locate 4, 1: print "after interrupt"; dta% sleep (1) goto rdval
page 20 commercial data acquisition packages page 20 01271015.doc blue chip technology ltd. 7.0 commercial data acquisition packages the blue chip technology PIO-96 can be used with almost any data acquisition package that can read information directly from a pc input port. 7.1 use of the PIO-96 board with asyst the board has been tested with and is installable as an 71055.port digital device in the asyst scientific software package by macmillan software company. for more details about this package and other pc data acquisition software, please contact blue chip technology.
appendices page 21 blue chip technology ltd. 01271015.doc page 21 appendix a1 i/o address map for pc/xt/at computers address allocated to (hex) 000-01f dma controller 1, 8237a-5 020-03f interrupt controller 1, 8259a 040-05f timer, 8254 060-06f keyboard controller 8742; control port b 070-07f rtc and cmos ram, nmi mask (write) 080-09f dma page register (memory mapper) 0a0-0bf interrupt controller 2, 8259 0f0 clear npx (80287) busy 0f1 reset npx, 80287 0f8-0ff numeric processor extension, 80287 1f0-1f8 hard disk drive controller 200-207 reserved 278-27f reserved for parallel printer port 2 2f8-2ff reserved for serial port 2 300-31f reserved 360-36f reserved 378-37f parallel printer port 1 380-38f reserved for sdlc comms, bisynch 2 3a0-3af reserved for bisynch 1 3b0-3bf reserved 3c0-3cf reserved 3d0-3df display controller 3f0-3f7 diskette drive controller 3f8-3ff serial port 1
page 22 appendices page 22 01271015.doc blue chip technology ltd. a2 hardware interrupt levels for pc/xt address allocated to (hex) 0 timer 1 keyboard 2 reserved 3 asynchronous communications (secondary) sdlc communications 4 asynchronous communications (primary) sdlc communications 5 fixed disk 6 diskette 7 parallel printer
appendices page 23 blue chip technology ltd. 01271015.doc page 23 a3 hardwa re interrupt levels for pc/at address allocated to (hex) 0 timer output 0 1 keyboard(output buffer full) 2 interrupt from controller 2:- 8 real time clock interrupt 9 software redirected to int(0ah) irq2 10 reserved 11 reserved 12 reserved 13 co-processor 14 fixed disk controller 15 reserved 3 serial port 2 4 serial port 1 5 parallel port 2 6 diskette controller 7 parallel port 1 dma channels 1 floppy disk drive. (may be used when disk inactive) 2 hard disk drive 3 spare

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