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? semiconductor components industries, llc, 2007 september, 2007 - rev. 3 1 publication order number: NB6L72/d NB6L72 2.5v / 3.3v differential 2 x 2 crosspoint switch with lvpecl outputs multi-level inputs w/ internal termination description the NB6L72 is a clock or data high-bandwidth fully differential 2 x 2 crosspoint switch with internal source termination and lvpecl output structure, optimized for low skew and minimal jitter. the differential inputs incorporate internal 50 termination resistors and will accept lvpecl, cml, lvds, lvcmos, or lvttl logic levels. the select inputs are single-ended and can be driven with lvcmos/lvttl. the differential lvpecl outputs provide 800 mv output swings when externally terminated with a 50 resistor to v cc C 2.0 v. the device is offered in a small 3 mm x 3 mm 16-pin qfn package. the NB6L72 is a member of the eclinps max family of high performance clock and data management products. features ? input clock frequency > 3.0ghz ? input data rate > 3 gb/s ? 425 ps typical propagation delay ? 100 ps typical rise and fall times ? 0.5 ps maximum rms clock jitter ? lvpecl, cml or lvds input compatible ? differential lvpecl outputs, 800 mv amplitude, typical ? operating range: v cc = 2.375 v to 3.63 v with gnd = 0 v ? internal 50 input termination provided ? functionally compatible with existing 2.5 v/3.3 v lvel, lvep, ep, and sg devices ? -40 c to +85 c ambient operating temperature ? these are pb-free devices a = assembly location l = wafer lot y = year w = work week = pb-free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. marking diagram* qfn-16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information 1 nb6l 72 alyw 16 1
NB6L72 http://onsemi.com 2 q0 q0 figure 1. logic/block diagram vtd0 d0 sel0 sel1 q1 22 22 2 2 2 2 2 2 v cc gnd + 50 50 75 k q1 d0 50 vtd1 d1 d1 50 + + 75 k
NB6L72 http://onsemi.com 3 vtd1 d1 d1 sel1 gnd q0 q0 v cc v cc q1 q1 gnd sel0 d0 d0 vtd0 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB6L72 exposed pad (ep) figure 2. pin configuration (top view) table 1. input/output select truth table sel0* sel1* q0 q1 l l d0 d0 h l d1 d0 l h d0 d1 h h d1 d1 *defaults high when left open table 2. pin description pin name i/o description 1 sel0 lvttl, lvcmos input select logic input control that selects d0 or d1 to output q0. see table 1, select input function table. pin defaults high when left open 2 d0 lvpecl, cml, lvds, lvttl, lvcmos, input noninverted differential input. note 1. 3 d0 lvpecl, cml, lvds, lvttl, lvcmos, input inverted differential input. note 1. 4 vtd0 - internal 50 termination pin. note 1. 5 vtd1 - internal 50 termination pin. note 1. 6 d1 lvpecl, cml, lvds, lvttl, lvcmos, input noninverted differential input. note 1. 7 d1 lvpecl, cml, lvds, lvttl, lvcmos, input inverted differential input. note 1. 8 sel1 lvttl,lvcmos input select logic input control that selects d0 or d1 to output q1. see table 1, select input function table. pin defaults high when left open 9 gnd - negative supply voltage 10 q1 lvpecl output inverted differential output. typically terminated with 50 resistor to v cc - 2.0 v. 11 q1 lvpecl output noninverted differential output. typically terminated with 50 resistor to v cc - 2.0 v. 12 v cc - positive supply voltage 13 v cc - positive supply voltage 14 q0 lvpecl output inverted differential reset input. typically terminated with 50 resistor to v cc - 2.0 v. 15 q0 lvpecl output noninverted differential reset input. typically terminated with 50 resistor to v cc - 2.0 v. 16 gnd - negative supply voltage - ep - the exposed pad (ep) on the qfn-16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat-sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to gnd on the pc board. 1. in the differential configuration when the input termination pin (vtdn, vtdn ) are connected to a common termination voltage or left open, and if no signal is applied on dn/dn input, then the device will be susceptible to self-oscillation. 2. all v cc and gnd pins must be externally connected to a power supply for proper operation.
NB6L72 http://onsemi.com 4 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v moisture sensitivity 16-qfn level 1 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count meets or exceeds jedec spec eia/jesd78 ic latchup test for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.0 v v io positive input/output voltage gnd = 0 v -0.5 v io v cc + 0.5 4.5 v v inpp differential input voltage |d - d | v cc - gnd v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current (lvpecl output) continuous surge 50 100 ma ma t a operating temperature range qfn-16 -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (note 3) 0 lfpm 500 lfpm qfn-16 qfn-16 42 35 c/w c/w jc thermal resistance (junction-to-case) (note 3) qfn-16 4 c/w t sol wave solder pb-free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board - 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB6L72 http://onsemi.com 5 table 5. dc characteristics, multi-level inputs v cc = 2.375 v to 3.63 v, gnd = 0 v, ta = -40 c to +85 c symbol characteristic min typ max unit power supply current i cc power supply current (inputs and outputs open) 40 60 80 ma lvpecl outputs (notes 4 and 5) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc - 1075 2225 1425 v cc - 950 2350 1550 v cc - 825 2475 1675 mv v ol output low voltage v cc = 3.3 v v cc = 2.5 v v cc - 1825 1475 675 v cc - 1725 1575 775 v cc - 1625 1675 875 mv differential input driven single-ended (see figures 4 and 5) (note 6) v th input threshold reference voltage range (note 7) 1125 v cc - 150 mv v ih single-ended input high voltage v th + 150 v cc mv v il single-ended input low voltage gnd v th - 150 mv v ise single-ended input voltage amplitude (v ih - v il ) 300 v cc - gnd mv differential inputs driven differentially (see figures 7 and 9) v ihd differential input high voltage 1050 v cc mv v ild differential input low voltage gnd v cc - 150 mv v id differential input voltage (dn, dn ) (v ihd - v ild ) 150 v cc - gnd mv v cmr input common mode range (differential configuration) (note 9) 950 v cc C 75 mv i ih input high current dn/dn , (vtdn/vtdn open) -150 +150 a i il input low current dn/dn , (vtdn/vtdn open) -150 +150 a single-ended lvcmos/lvttl control inputs v ih single-ended input high voltage 2000 v cc mv v il single-ended input low voltage gnd 800 mv i ih input high current -10 10 a i il input low current -150 0 a termination resistors r tin internal input termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. lvpecl outputs loaded with 50 to v cc - 2.0 v for proper operation. 5. input and output parameters vary 1:1 with v cc . 6. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 7. v th is applied to the complementary input when operating in single-ended mode. 8. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 9. v cmr minimum varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the dif ferential input signal.
NB6L72 http://onsemi.com 6 table 6. ac characteristics v cc = 2.375 v to 3.63 v, v ee = 0 v, or v cc = 0 v, v ee = -2.375 v to -3.63 v, t a = -40 c to +85 c; (note 10) symbol characteristic min typ max unit v outpp output voltage amplitude (@ v inppmin )f in 1.5 ghz (note 14) (see figure 16) f in 2.5 ghz f in 3.0 ghz 520 380 320 800 650 500 mv t plh , t phl propagation delay (@0.5ghz) dn to qn seln to qn 325 425 525 ps t skew duty cycle skew (note 11) within device skew device to device skew (note 12) 5 20 15 80 ps t dc output clock duty cycle f in 3.0 ghz (reference duty cycle = 50%) 40 50 60 % t jitter rms random clock jitter (note 13) f in = 2.5 ghz f in = 3.0 ghz data dependent jitter f data = 2.5 gb/s f data = 3.0 gb/s 0.2 0.3 12 15 0.5 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 14) 150 v cc - gnd mv t r ,t f output rise/fall times @ 0.5 ghz (20% - 80%) q, q 100 160 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inpp (minimum) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc C 2.0 v. input edge rates 40 ps (20% - 80%). 11. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw - and t pw + @ 0.5 ghz. 12. device to device skew is measured between outputs under identical transition @ 0.5 ghz. 13. additive rms jitter with 50% duty cycle clock signal. 14. input and output voltage swing is a single-ended measurement operating in differential mode.
NB6L72 http://onsemi.com 7 figure 3. input structure 50 50 vtd vtd v cc d d r c r c i d v th d v th figure 4. differential input driven single-ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 5. v th diagram d d figure 6. differential inputs driven differentially v ild v ihd(max) v ihd v ild v ihd(min) v ild(min) v cmr gnd v id = v ihd - v ild v cc d d q q t pd t pd v outpp = v oh (q) - v ol (q) v inpp = v ih (d) - v il (d) figure 7. differential inputs driven differentially figure 8. v cmr diagram figure 9. ac reference measurement v ihd v ild v id = |v ihd(d) - v ild(d)| d d
NB6L72 http://onsemi.com 8 lvpecl driver v cc gnd z o = 50 vt = v cc - 2 v z o = 50 NB6L72 d 50 50 d gnd figure 10. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 NB6L72 d 50 50 d gnd figure 11. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 NB6L72 d 50 50 d gnd v cc figure 12. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 NB6L72 d 50 50 d gnd v cc figure 13. capacitor-coupled differential interface (vt connected to v refac ) *v refac bypassed to ground with a 0.01 f capacitor single-ended driver v cc gnd z o = 50 vt = v refac * NB6L72 d 50 50 d gnd v cc figure 14. capacitor-coupled single-ended interface (vt connected to v refac ) (open)
NB6L72 http://onsemi.com 9 figure 15. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v output frequency (ghz) figure 16. output voltage amplitude (v outpp ) versus output frequency at ambient temperature (typical) 800 700 600 500 400 300 200 100 0 900 01234 output voltage amplitude (mv) figure 17. typical output wave form - data signal prbs 2 23 -1 room temperature, 400 mv input amplitude, v cc = 2.5 v, 2.488 gb/s (x-scale = 80 ps/div; y-scale = 100 mv/div) total jitter = 25 ps device jitter = 12 ps input jitter = 13 ps
NB6L72 http://onsemi.com 10 figure 18. typical output wave form - data signal prbs 2 23 -1 room temperature, 75 mv input amplitude, 3 gb/s (x-scale = 80 ps/div; y-scale = 100 mv/div) total jitter = 28 ps device jitter = 15 ps input jitter = 13 ps ordering information device package shipping ? NB6L72mng qfn-16 (pb-free) 123 units / rail NB6L72mnr2g qfn-16 (pb-free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB6L72 http://onsemi.com 11 package dimensions 16 pin qfn mn suffix case 485g-01 issue c 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ?? ?? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free usa/canada japan : on semiconductor, japan customer focus center ?2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 ? phone : 81-3-5773-3850 NB6L72/d eclinps max is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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