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this data sheet contains design specifications for product development. ramtron international corp oration these specifications may change in any manner without notice 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000, fax (719) 481 - 7058 www.ramtron.com 23 october 2000 1 / 14 fm25c160 16kb fram serial memory features 16k bit ferroelectric nonvolatile ram organized as 2,048 x 8 bits high endurance 10 billion (10 10 ) read/writes 10 year data retention at 85 c nodelay? writes advanced high - reliabi lity ferroelectric process very fast serial peripheral interface - spi up to 5 mhz maximum bus frequency direct hardware replacement for eeprom spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme hardware protection software pr otection low power consumption 10 m a standby current industry standard configuration industrial temperature - 40 c to +85 c 8 - pin sop or dip description the fm25c160 is a 16 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferr oelectric random access memory or fram is nonvolatile but operates in other respects as a ram. it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other n onvolatile memories. unlike serial eeproms, the fm25c160 performs write operations at bus speed. no write delays are incurred. data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. the next bus cycle may commence immediately. in addition, the product offers substantial write endurance compared with other nonvolatile memories. the fm25c160 is capable of supporting up to 1e10 - read/write cycles -- far more than most systems will require fro m a serial memory. these capabilities make the fm25c160 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm25c160 provides substantial benefits to users of serial eeprom, in a hardware drop - in replacement. the fm25c160 uses the high - speed spi bus, which enhances the high - speed write capability of fram technology. it is guaranteed over an industrial temperature range of - 40c to +85c. pin configuration cs so wp vss vdd hold sck si pin names function /cs chip select so serial data output /wp write protect vss ground si serial data input sck serial clock /hold hold vdd 5v ordering information fm25c160 - p 8 - pin plastic dip fm25c160 - s 8 - pin sop
ramtron fm25c160 23 october 2000 2 / 14 figure 1. block diagram instruction decode clock generator control logic write protect instruction register address register counter ` 512 x 32 fram array 11 data i/o register 8 nonvolatile status register 3 wp cs hold sck so pin description pin name pin number i/o pin description /cs 1 i chip select. activates the device. when high, all outputs are tri - state and the device ignores other inputs. the part remains in a low - power standby mode. when low, the part recognizes activity on the sck signal. a falling edge on /cs must occur prior to every op - code . so 2 o serial output. so is the data output pin. it is driven actively during a read and remains tri - state at all other times including when hold \ is low. data transitions are driven on the falling edge of the serial clock. * so can be connected to si for a single pin data interface since the part communicates in half - duplex. /wp 3 i write protect. this pin prevents write operations to the status register. this is critical since other write protection features are controlled through the status regis ter. a complete explanation of write protection is provided below. *note that the function of /wp is different from the fm25c160 where it prevents all writes to the part. vss 4 i ground si 5 i serial input. all data is input to the device on this pin. t he pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be connected to so for a single pin data interface. sck 6 i serial clock. all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. the part is static so the clock frequency may be any value between 0 and 5 mhz and may be interrupted at any time. /hold 7 i hold. the /hold s ignal is used when the host cpu must interrupt a memory operation for another task. taking the /hold signal to a low state pauses the current operation. the part ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. vdd 8 i supply voltage. 5v
ramtron fm25c160 23 october 2000 3 / 14 overview the fm25c160 is a serial fram memory. the memory array is logically organized as 2,048 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the fram is simila r to serial eeproms. the major difference between the fm25c160 and a serial eeprom with the same pin - out relates to its superior write performance. it also differs from ramtron?s 25160 by supporting spi mode 3 and the industry standard 16 - bit addressing pr otocol. this makes the fm25c160 a drop - in replacement for most 16kb spi eeproms that support modes 0 & 3. memory architecture when accessing the fm25c160, the user addresses 2,048 locations each with 8 data bits. these data bits are shifted serially. the a ddresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code and a two - byte address. the upper 5 bits of the address range are ?don?t care? values. the complete address of 11 - bits specifies each byte address uniquely. most functions of the fm25c160 either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation essentially is zero, beyond the time needed for the serial prot ocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the par t, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm25c160 due to its fast write cycle and high endurance as compared with eeprom. however there a re less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to nois e during much of the cycle. note that the fm25c160 contains no power management circuits other than a simple internal power - on reset. it is the user?s responsibility to ensure that vdd is within data sheet tolerances to prevent incorrect operation. se rial peripheral interface ? spi bus the fm25c160 employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 5 mhz. this high - speed serial bus provides high performance serial communication to a host microcontroller. many co mmon microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25c160 operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. it is possible to connect the two data lines together. figure 2 illustrates a typical system configuration using the fm25c160 with a microcontroller that offers an spi port. figure 3 shows a similar configu ration for a microcontroller that has no hardware support for the spi bus. protocol overview the spi interface is a synchronous serial interface using clock and data lines. it is intended to support multiple devices on the bus. each device is activated us ing a chip select. once chip select is activated by the bus master, the fm25c160 will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determ ination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25c160 supports modes 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm25c160 o n the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the part. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. certain op - codes are commands with no su bsequent data transfer. the /cs must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
ramtron fm25c160 23 october 2000 4 / 14 figure 2. system configuration with spi port figu re 3. system configuration without spi port figure 4. spi modes 0 & 3 spi mode 0: cpol=0, cpha=0 0 1 2 3 4 5 6 7 spi mode 3: cpol=1, cpha=1 0 1 2 3 4 5 6 7
ramtron fm25c160 23 october 2000 5 / 14 data transfer all data transfers to and from the fm25c160 occur in 8 - bit groups. they are synchronized to the clock signal (sck) and they transfer most significant bit (msb) first. serial inputs are clocked in on the rising edge of sck. outputs are driven on the falling edge of sck. command structure there ar e six commands called op - codes that can be issued by the bus master to the fm25c160. they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. last are commands for memory transactions followed by address an d one or more bytes of data. table 1. op - code commands name description op - code value wren set write enable latch 00000110b wrdi write disable 00000100b rdsr read status register 00000101b wrsr write status register 00000001b read read memory data 0 0000011b write write memory data 00000010b wren - set write enable latch the fm25c160 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel =1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 4 b elow illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verif ying that wel=0. figure 5 below illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
ramtron fm25c160 23 october 2000 6 / 14 rdsr - read status register the rdsr command allows the b us master to verify the contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op - code, the fm25c160 will return one byte with the contents of the status register. t he status register is described in detail in a later section. wrsr ? write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm25c160, /wp only prevents writing to the status register, not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a wri te operation and therefore clears the write enable latch. the bus configuration of rdsr and wrsr are shown below. figure 7. rdsr bus configuration figure 8. wrsr bus configuration status register & write pr otection the write protection features of the fm25c160 are multi - tiered. first, a wren op - code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the status register. as described ab ove, writes to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 an d can not be modified. note that the ready bit in many eeproms is unnecessary as the fram writes in real - time and is never busy. the wpen, bp1 and bp0 control write protection features. they are nonvolatile! the wel flag indicates the state of the write en able latch. writing the wel bit in the status register has no effect. bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write protected as shown in the following table. table 3. block memory write protection bp 1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper ?) 1 0 1000h to 1fffh (upper ?) 1 1 0000h to 1fffh (all)
ramtron fm25c160 23 october 2000 7 / 14 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register. t hus the status register is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is se t to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, with its relatively high maximum clock frequency, highlights the fast write capability of the fram technology. unlike spi - bus eeproms, the fm 25c160 can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code is followed by a two - byte address value. the upper 5 - bits of the address are don?t care. in total, the 11 - bits specify the address of the first byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the counter will roll over to 0000h. data is written msb first. unlike eeproms, any number of bytes can be written sequentially and each b yte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation. read operation after the falling edge of /cs, the bus master can issue a read op - code. following this instructi on is a two - byte address value. the upper 5 - bits of the address are don?t care. in total, the 11 - bits specify the address of the first byte of the read operation. after the op - code and address are complete, the si line is ignored. the bus master issues 8 c locks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs ter minates a read op - code operation. the bus configuration for read and write operations is shown below. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master takes the /hold pin low while sck is low, the curr ent operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
ramtron fm25c160 23 october 2000 8 / 14 figure 9. memory write figure 10. memory read data retention and endurance data retention is specified in the electrical specifications below. for purposes of clarity, this section contrasts the retention and endurance of fram with eeprom. the retention performance of fram is very comparable to eeprom in its characteristics. however, the effect of endurance cycles on retention is different. a typical eeprom has a write endurance specification that is fixed. surpassing the specified level of cycles on a n eeprom usually leads to a hard memory failure. by contrast, the effect of increasing cycles on fram produces an increase in the soft error rate. that is, there is a higher likelihood of data loss but the memory continues to function properly. a hard fail ure would not occur by simply exceeding the endurance specification; simply a reduction in data retention reliability. while enough cycles would cause an apparent hard error, this is simply a very high soft error rate. this characteristic makes it problema tic to assign a fixed endurance specification. endurance is a soft specification. therefore, the user may operate the device with different levels of endurance cycling for different portions of the memory. for example, critical data needing the highest r eliability level could be stored in memory locations that receive comparatively few cycles. data with shorter - term use could be located in an area receiving many more cycles. a scratchpad area, needing little if any retention can be cycled until there is v irtually no retention capability remaining. this would occur several orders of magnitude above the endurance spec. internally, a fram operates with a read and restore mechanism similar to a dram. therefore, endurance cycles are applied for each access: r ead or write. the fram architecture is based on an array of rows and columns. each access causes a cycle for an entire row. therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. in the fm25c160, there are 512 rows each 32 bits wide. each 4 bytes in the address mark the beginning of a new row.
ramtron fm25c160 23 october 2000 9 / 14 applications the versatility of fram technology fits into many diverse applications. clearly the strength of higher write endurance and faster w rites make fram superior to eeprom in all but one - time programmable applications. the advantage is most obvious in data collection environments where writes are frequent and data must be nonvolatile. the attributes of fast writes and high write endurance combine in many innovative ways. a short list of ideas is provided here. 1. data collection . in applications where data is collected and saved, fram provides a superior alternative to other solutions. it is more cost effective than battery backup for sram a nd provides better write attributes than eeprom. 2. configuration . any nonvolatile memory can retain a configuration. however, if the configuration changes and power failure is a possibility, the higher write endurance of fram allows changes to be recorded without restriction. any time the system - state is altered, the change can be written. this avoids writing to memory on power - down when the available time is short and power scarce. 3. high noise environments . writing to eeprom in a noisy environment can be challenging. when severe noise or power fluctuations are present, the long write time of eeprom creates a window of vulnerability during which the write can be corrupted. the fast write of fram is complete within a microsecond. this time is typically too s hort for noise or power fluctuations to disturb it. 4. time to market . in a complex system, multiple software routines may need to access the nonvolatile memory. in this environment the time delay associated with programming eeprom adds undue complexity to the software development. each software routine must wait for complete programming before allowing access to the next routine. when time to market is critical, fram can eliminate this simple obstacle. as soon as a write is issued to the fm25c160, it is eff ectively done -- no waiting. 5. rf/id . in the area of contactless memory, fram provides an ideal solution. since rf/id memory is powered by an rf field, the long programming time and high current consumption needed to write eeprom is unattractive. fram prov ides a superior solution. the fm25c160 is suitable for multi - chip rf/id products. 6. maintenance tracking . in sophisticated systems, the operating history and system - state during a failure is important knowledge. maintenance can be expedited when this infor mation has been recorded. due to the high write endurance, fram makes an ideal system log. in addition, the convenient interface of the fm25c160 allows memory to be distributed throughout the system using minimal additional resources.
ramtron fm25c160 23 october 2000 10 / 14 electrical specifications absolute maximum ratings description ratings ambient storage or operating temperature - 40 c to + 85 c voltage on any pin with respect to ground - 1.0v to +7.0v d.c. output current on any pin 5 ma lead temperature (solde ring, 10 seconds) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed i n the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability dc operating conditions ta = - 40 c to + 85 c, vdd = 4.5v to 5.5v unless otherwise specifie d symbol parameter min typ max units notes vdd main power supply 4.5 5.0 5.5 v 1 idd vdd supply current @ sck = 1.0 mhz @ sck = 2.0 mhz @ sck = 5.0 mhz 0.9 1.6 3.0 1.2 2.5 4.5 ma 2 isb standby current 1 10 m a 3 ili input leakage current 10 m a 4 ilo output leakage current 10 m a 4 vil input low voltage - 0.3 vdd x 0.3 v 1,5 vih input high voltage vdd x 0.7 vdd + 0.5 v 1,5 vol output low voltage @ iol = 2 ma 0.4 v 1,5 voh output high voltage @ ioh = - 2 ma vdd - 0.8 v 1,5 vhys input hysteresis vdd x .05 v 1,5 notes 1. referenced to vss. 2. sck toggling between vdd - 0.3v and vss, other inputs vss or vdd - 0.3v 3. sck = si = /cs=vdd. all inputs vss or vdd. 4. vin or vout = vss to vdd 5. characterized but not 100% tested in production.
ramtron fm25c160 23 october 2000 11 / 14 ac pa rameters ta = - 40 c to + 85 c, vdd = 4.5v to 5.5v unless otherwise specified symbol parameter min max units note fck sck clock frequency 0 5.0 mhz tch clock high time 90 ns tcl clock low time 90 ns tcsu chip select setup 90 ns tcsh chip sele ct hold 90 ns tod output disable 100 ns 2 todv output data valid 60 ns toh output hold 0 ns td deselect time 100 ns tr data in rise time 1 m s 1,2 tf data in fall time 1 m s 1,2 th data hold time 30 ns tsu data setup time 20 ns ths /h old setup time 70 ns thh /hold hold time 40 ns thz /hold low to hi - z 100 ns 2 tlz /hold high to data active 50 ns 2 notes 1. rise and fall times measured between 10% and 90% of waveform. 2. characterized but not 100% tested in production. capacitanc e ta = 25 c, f=1.0 mhz, vdd = 5v symbol parameter max units notes co output capacitance (sda) 8 pf 1 ci input capacitance 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. ac test conditions input pulse levels vdd * 0.1 to vdd * 0.9 input rise and fall times 10 ns input and output timing levels vdd*0.5 equivalent ac load circuit
ramtron fm25c160 23 october 2000 12 / 14 serial data bus timing 1 / f c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f /hold timing data retention ta = - 40 c to + 85 c , vdd = 4.5v to 5.5v unless otherwise specified parameter min units notes data retention 10 years 1 notes 1. data retention is specified at 85 c. the relationship between retention, temperature, and the associated reliability level is characterized separa tely.
ramtron fm25c160 23 october 2000 13 / 14 8 - pin sop jedec ms - 012 pin 1 index area e h d a1 a b e .10 mm .004 in. a h 45 l c selected dimensions refer to jedec ms - 012 for complete dimensions and notes. controlling dimensions is in millimeters. conversions to inches are not exact. symbol dim min nom. max a mm in. 1.35 .053 1.75 .069 a1 mm in. .10 .004 .25 .010 b mm i n. .33 .013 .51 .020 c mm in. .19 .007 .25 .010 d mm in. 4.80 .189 5.00 .197 e mm in. 3.80 .150 4.00 .157 e mm in. 1.27 bsc .050 bsc h mm in. 5.80 .228 6.20 .244 h mm in. .25 .010 .50 .197 l mm in. .40 .016 1.27 .050 a 0 8
ramtron fm25c160 23 october 2000 14 / 14 8 - pin dip jedec ms - 001 index area e1 d a1 e d1 b a2 a ea eb e selected dimensions refer to jedec ms - 001 for complete dimensions and notes. controlling dimensions is in inches. conversions to millimeters are not exact. symbol dim min nom. max a in. mm .210 5.33 a1 in. mm 0.015 .381 a2 in. mm 0.115 2.92 0.130 3.30 0.1 95 4.95 b in. mm 0.014 .356 0.018 .457 0.022 .508 d in. mm 0.355 9.02 0.365 9.27 0.400 10.2 d1 in. mm 0.005 .127 e in. mm 0.300 7.62 0.310 7.87 0.325 8.26 e1 in. mm 0.240 6.10 0.250 6.35 0.280 7.11 e in. mm .100 bsc 2.54 bsc ea in. mm .300 bsc 7.62 bsc eb in. mm 0.430 10.92 l in. mm 0.115 2.92 0.130 3.30 0.150 3.81

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