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| ibm processor for atm resources revision 2.1 databook
copyright and disclaimer ? copyright international business machines corporation 1999 all rights reserved printed in the united states of america august 1999 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo powerpc 401 other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com atmrm.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page i table of contents features ....................................................................................................................... ...... 1 description .................................................................................................................... .... 1 atm subsystem block diagram ...................................................................................... 1 conventions .................................................................................................................... .. 2 ordering information ........................................................................................................ 2 standards compliance ..................................................................................................... 3 environmental ratings ..................................................................................................... 4 absolute maximum ratings ......................................................................................................... .......... 4 recommended operating conditions ................................................................................................. .. 4 power dissipation ............................................................................................................... .................... 4 package diagram ................................................................................................................. ................... 5 pinout viewed from above .......................................................................................................... ........... 6 ground pin locations ............................................................................................................. ................ 6 pinout viewed from below .......................................................................................................... ........... 7 v dd pin locations ................................................................................................................... ................ 7 block diagram ................................................................................................................... ...................... 8 functional description ..................................................................................................... 9 subsystem blocks ................................................................................................................ ................ 10 external architecture ........................................................................................................... ................. 10 internal architecture ........................................................................................................... .................. 11 logical channel support .......................................................................................................... ........ 11 virtual memory support ........................................................................................................... ......... 11 queues ......................................................................................................................... .................... 12 scheduling ..................................................................................................................... ................... 12 block diagrams of possible systems ................................................................................................. 12 mpeg video compression and distribution considerations ........................................................... 13 atm subsystem dataflow ........................................................................................................... ......... 14 data flows ...................................................................................................................... .15 transmit path ................................................................................................................... ..................... 15 transmit scheduling capabilities ................................................................................................. ...... 16 receive path .................................................................................................................... ...................... 17 input/output definitions ................................................................................................. 19 pci bus connections .............................................................................................................. .............. 19 pci bus interface pin descriptions ................................................................................................. .... 20 dram memory bus interface ......................................................................................................... ...... 21 dram memory bus connections ....................................................................................................... .21 dram memory bus interface pin descriptions ................................................................................. 22 IBM2520L8767 ibm processor for atm resources table of contents page ii atmrm.toc.01 08/27/99 memory i/o cross reference by device type ....................................................................................23 possible memory configurations using dram with shared ecc ...................................................24 possible memory configurations using sram ..................................................................................24 npbus .......................................................................................................................... ..........................25 npbus connections ............................................................................................................... ..............25 npbus pin descriptions ........................................................................................................... ...........26 atm phy bus interface ............................................................................................................. ...........28 atm phy bus interface connections .................................................................................................. 28 phy bus pin descriptions .......................................................................................................... ..........29 transmit phy i/o cross reference ................................................................................................... ..31 receive phy i/o cross reference .................................................................................................... ... 31 clock, configuration, and lssd connections ...................................................................................32 clock, configuration, and lssd pin descriptions .............................................................................33 data structures ............................................................................................................... 35 packet header ................................................................................................................... .....................35 transmit packet header structure .................................................................................................. ....35 receive packet header structure ................................................................................................... .....36 transmit and receive packet header field descriptions ................................................................. 36 logical channel data structure .................................................................................................... .......38 transmit descriptor data structures ............................................................................................... ..39 scheduling portion of a transmit descriptor .....................................................................................40 transmit logical channel descriptor structure ................................................................................ 41 redefinition of shared and segmentation portion of transmit lcd for abr .................................42 redefinition of segmentation portion of transmit lcd for fixed size aal5 blocking ...................43 redefinition of segmentation portion of transmit lcd for mpeg2 .................................................44 redefinition of scheduling portion of transmit lcd for abr ..........................................................45 redefinition of scheduling portion of transmit lcd for timers .......................................................45 definition of lcd-based memory management of transmit lcd ....................................................45 field definitions ............................................................................................................... .................46 definition of abr code variables ................................................................................................... ......46 abr code variables definitions .................................................................................................... ......46 receive lcd data structure and modes ..........................................................................................53 transmit data structure linkage ................................................................................................... ......53 raw lcd ......................................................................................................................... ..................54 raw lcd layout ................................................................................................................... .................54 raw routed lcd ................................................................................................................... ...........55 raw routed lcd layout ............................................................................................................. .........55 raw cut through lcd ............................................................................................................... .......56 raw cut through lcd layout ......................................................................................................... ....56 raw fifo lcd ..................................................................................................................... ............57 raw fifo lcd layout ............................................................................................................... ............57 receive fifo buffer layouts ....................................................................................................... ........58 aal5 lcd ........................................................................................................................ .................59 aal5 lcd layout .................................................................................................................. ................59 aal5 routed lcd layout ............................................................................................................ ........60 aal5 cut-through mode 6 lcd .......................................................................................................6 1 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page iii aal5 cut-through mode 6 lcd layout ............................................................................................. 61 aal5 cut-through mode 6 lcd using hardware fifo registers .................................................. 62 aal5 cut-through mode 7 lcd ...................................................................................................... 63 aal5 cut-through mode 7 lcd layout ............................................................................................. 63 aal5 cut-through scatter mode lcd layout ................................................................................... 64 aal5 fifo mode lcd ................................................................................................................ ..... 65 aal5 fifo mode lcd layout .......................................................................................................... .... 65 lcd field definitions ............................................................................................................ ............ 66 common lcd field definitions ...................................................................................................... ..... 66 lcd raw mode field definitions ..................................................................................................... .... 67 aal5 field definitions ........................................................................................................... ............... 68 internal organization: entity descriptions ................................................................... 71 note on set/clear/read type registers .......................................................................................... 71 control processor bus interface entities ..................................................................... 71 the iop bus specific interface controller (pcint) ............................................................................ 71 pcint config word 0 ............................................................................................................... ........ 72 pcint config word 1 ............................................................................................................... ........ 73 pcint config word 2 ............................................................................................................... ........ 75 pcint config word 3 ............................................................................................................... ........ 76 pcint base address 1 (i/o for regs) ............................................................................................... 77 pcint base address 2 (mem for regs) ............................................................................................ 78 pcint base addresses 3-6 (memory) ............................................................................................. 79 pcint cardbus cis pointer ......................................................................................................... ... 80 pcint subsystem id/vendor id ...................................................................................................... 81 pcint rom base address ............................................................................................................ .. 82 pcint config word 15 .............................................................................................................. ....... 83 pcint endian control register ..................................................................................................... ... 84 pcint base address control register ............................................................................................ 85 pcint window offsets for base addresses 3-6 .............................................................................. 87 pcint count timeout register ...................................................................................................... .. 88 pcint 64bit control register ...................................................................................................... ..... 90 pcint perf counters control register ............................................................................................. 91 pcint perf counter 1 .............................................................................................................. ........ 93 pcint perf counter 2 .............................................................................................................. ........ 94 interrupt and status/control (intst) .............................................................................................. .... 95 intst interrupt 1 prioritized status ............................................................................................... ... 95 intst interrupt 2 prioritized status ............................................................................................... ... 96 intst control register ........................................................................................................... ......... 97 intst interrupt source ........................................................................................................... ......... 99 intst enable for interrupt 1 (minta) ............................................................................................ 100 intst enable for interrupt 2 (mint2) ............................................................................................ 101 intst interrupt source without enables ........................................................................................ 101 intst cpb status ................................................................................................................. ......... 102 intst cpb status enable ........................................................................................................... .. 104 intst IBM2520L8767 halt enable ................................................................................................ 104 intst cpb capture enable .......................................................................................................... .105 intst cpb captured address ....................................................................................................... 1 05 intst general purpose timer pre-scaler ..................................................................................... 106 IBM2520L8767 ibm processor for atm resources table of contents page iv atmrm.toc.01 08/27/99 intst general purpose timer compare .......................................................................................106 intst general purpose timer counter .........................................................................................106 intst general purpose timer status ............................................................................................107 intst general purpose timer mode control .................................................................................108 intst enable for pcore normal interrupt ...................................................................................109 intst enable for pcore critical interrupt ....................................................................................109 intst debug states control ........................................................................................................ ..110 dma queues (dmaqs) ............................................................................................................... ......112 dma descriptors ................................................................................................................. ............112 dma descriptor layout ............................................................................................................ .......... 112 dma types/options ............................................................................................................... .........113 dma types and flags ............................................................................................................... ..........113 descriptor based dmas ............................................................................................................ ......114 register based dmas .............................................................................................................. .......114 polling, interrupts, or events .................................................................................................... .......114 error detection and recovery ...................................................................................................... ... 114 dma/queue scheduling options ....................................................................................................1 14 initialization of dmaqs .......................................................................................................... .........115 delayed interrupts .............................................................................................................. .............115 dmaqs lower bound registers .................................................................................................... 116 dmaqs upper bound registers .................................................................................................... 117 dmaqs head pointer registers .....................................................................................................1 18 dmaqs tail pointer registers ...................................................................................................... .118 dmaqs length registers ........................................................................................................... ....119 dmaqs threshold registers ........................................................................................................ ..119 dmaqs interrupt status ........................................................................................................... ......120 dmaqs interrupt enable ........................................................................................................... .....122 dmaqs control register ........................................................................................................... .....122 dmaqs enqueue dma descriptor primitive .................................................................................. 124 dmaqs source address register ..................................................................................................124 dmaqs destination address register ...........................................................................................125 dmaqs transfer count and flag register .................................................................................... 125 dmaqs system descriptor address ..............................................................................................128 dmaqs checksum register .......................................................................................................... 128 dmaqs delayed int src/dst registers ...........................................................................................129 dmaqs local descriptor range registers .................................................................................... 130 dmaqs raall/csked queue number register ......................................................................... 130 dmaqs dma request size register ............................................................................................. 131 dmaqs enq fifo head ptr register .............................................................................................131 dmaqs enq fifo tail ptr register ...............................................................................................131 dmaqs enq fifo array .............................................................................................................. ... 132 general purpose dma (gpdma) ....................................................................................................... .133 gpdma interrupt status ........................................................................................................... ......133 gpdma interrupt enable ........................................................................................................... .....134 gpdma control register ........................................................................................................... .....135 gpdma source address register ..................................................................................................136 gpdma destination address register ...........................................................................................136 gpdma transfer count and flag register .................................................................................... 137 gpdma dma max burst time ........................................................................................................138 gpdma checksum register .......................................................................................................... 139 gpdma read dma byte count .....................................................................................................139 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page v gpdma write dma byte count ..................................................................................................... 139 gpdma array ..................................................................................................................... ............ 140 memory controlling entities ........................................................................................ 141 the dram controllers (comet/pakit) ............................................................................................ 141 memory reset sequence ............................................................................................................ ... 142 comet/pakit control register .................................................................................................... 1 43 comet/pakit status register ...................................................................................................... 146 comet/pakit interrupt enable register ...................................................................................... 147 comet/pakit lock enable register ............................................................................................ 147 comet/pakit memory error address register ............................................................................ 147 comet/pakit sdram command and status register ............................................................... 148 comet/pakit dram refresh rate register ............................................................................... 149 comet/pakit syndrome register ............................................................................................... 150 ecc syndrome bits ................................................................................................................ ............ 151 comet/pakit checkbit inversion register .................................................................................. 152 comet/pakit memory controller write enable register ............................................................. 152 atm virtual memory logic (vimem) .................................................................................................. 1 53 vimem virtual memory base address ........................................................................................... 153 vimem control memory base address .......................................................................................... 154 vimem packet memory base address .......................................................................................... 155 vimem virtual memory total bytes ................................................................................................ 156 vimem virtual/real memory buffer size ........................................................................................ 157 vimem packet memory offset ....................................................................................................... 1 58 vimem maximum buffer size ......................................................................................................... 158 vimem access control register .................................................................................................... 1 59 vimem access status register ...................................................................................................... 160 vimem access status interrupt enable register ........................................................................... 162 vimem memory lock enable register ........................................................................................... 162 vimem state machine current state ............................................................................................. 163 vimem last processor read real address ................................................................................... 164 vimem virtual buffer segment size register ................................................................................ 165 vimem buffer map base address .................................................................................................. 167 vimem real buffer base addresses .............................................................................................. 168 atm packet/control memory arbitration logic (arbit) ................................................................. 169 arbit control priority resolution register high ........................................................................... 169 arbit control priority resolution register low ............................................................................ 170 arbit control error mask register ............................................................................................... 171 arbit control error source register ............................................................................................. 172 arbit control winner register ..................................................................................................... .173 arbit control address register a ................................................................................................ 174 arbit control address register b ................................................................................................ 174 arbit control length register ..................................................................................................... .175 arbit control lock entity enable register ................................................................................... 176 arbit control config register ..................................................................................................... .. 177 arbit packet priority resolution register high ............................................................................ 178 arbit packet priority resolution register low ............................................................................. 179 arbit packet entity error mask register ...................................................................................... 180 arbit packet error source register ............................................................................................. 181 arbit packet winner register ...................................................................................................... 182 arbit packet address register a ................................................................................................. 183 IBM2520L8767 ibm processor for atm resources table of contents page vi atmrm.toc.01 08/27/99 arbit packet address register b .................................................................................................183 arbit packet length register ...................................................................................................... .184 arbit packet lock entity enable register .................................................................................... 185 arbit packet config register ...................................................................................................... ..186 the bus dram cache controller (bcach) ......................................................................................187 bcach control register ........................................................................................................... .....188 bcach status register ............................................................................................................ ......190 bcach interrupt enable register .................................................................................................. 1 91 bcach high priority timer value ..................................................................................................19 1 bcach line tag registers .......................................................................................................... ..192 bcach line valid bytes register ..................................................................................................19 3 bcach line status register ........................................................................................................ ..194 bcach cache line array ............................................................................................................ ... 195 buffer pool management (pools) .................................................................................................... 196 basic operation in real memory mode ..........................................................................................196 basic operation in virtual memory mode .......................................................................................196 resource controls ............................................................................................................... ...........196 virtual memory overview .......................................................................................................... ......197 virtual address buffer map ........................................................................................................ ........198 buffer/virtual memory allocation structure in memory ..................................................................199 virtual address buffer map ........................................................................................................ ........200 resources and variables example ................................................................................................... .201 pools get pointer primitive ....................................................................................................... ... 201 pools free pointer primitive ...................................................................................................... ..202 pools common pools count registers .......................................................................................203 pools client thresholds array ..................................................................................................... 204 pools user threshold and client active packet count array ......................................................205 pools pointer queues dram head pointer offset address register ......................................... 206 pools pointer queues dram tail pointer offset address register ............................................ 207 pools pointer queues dram lower bound address register ................................................... 208 pools pointer queues dram upper bound register ................................................................. 209 pools pointer queues length registers ..................................................................................... 211 pools interrupt enable register ................................................................................................... 211 pools event enables .............................................................................................................. .....212 pools event hysteresis register .................................................................................................21 2 pools event data register ......................................................................................................... .213 pools status register ............................................................................................................ ......215 pools control register ........................................................................................................... ......217 pools buffer threshold registers 0-4 ..........................................................................................219 pools index threshold registers 0-4 ..........................................................................................219 pools last primitive trap register ..............................................................................................220 pools last buffer map read on free register ............................................................................220 pools error lock enable register ...............................................................................................220 pools packet and control memory access threshold ................................................................220 pools buffer map group ............................................................................................................ ..221 transmit data path entities ......................................................................................... 223 transmit cell scheduler (csked) ................................................................................................... ..223 operational description ......................................................................................................... .........223 scheduling options .............................................................................................................. ...........223 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page vii transmit enqueue primitive ....................................................................................................... .... 224 resume transmission primitive .................................................................................................... .224 close connection primitive ....................................................................................................... ..... 225 start/stop timer primitive ....................................................................................................... ........ 225 timeslot prescaler register ...................................................................................................... ..... 226 current timeslot counter ......................................................................................................... ...... 226 timing data base address .......................................................................................................... ... 227 csked control register ........................................................................................................... ..... 227 transmit segmentation throttle register ....................................................................................... 229 transmit segmentation throttle counter ....................................................................................... 230 mpeg conversion register ......................................................................................................... .. 230 gfc reset values ................................................................................................................. ......... 231 abr timer prescaler register ...................................................................................................... .232 rm cell timer .................................................................................................................... ............. 232 performance registers ........................................................................................................... ............ 233 high priority bandwidth limit register ........................................................................................... 23 3 medium priority bandwidth limit register ...................................................................................... 234 low priority bandwidth limit register ............................................................................................ 23 4 high priority cells transmitted counter ......................................................................................... 235 medium priority cells transmitted counter .................................................................................... 235 low priority cells transmitted counter .......................................................................................... 236 debugging register access ........................................................................................................ ...... 237 high priority serviced counter .................................................................................................... ... 237 medium priority serviced counter .................................................................................................. 237 low priority serviced counter ..................................................................................................... ... 238 slow serviced counters ........................................................................................................... ...... 238 timer serviced counters .......................................................................................................... ...... 239 csked status register ............................................................................................................ ...... 240 csked interrupt enable register .................................................................................................. 2 41 timing data array ................................................................................................................ ........... 241 state machine variables .......................................................................................................... ....... 242 atm transmit buffer segmentation (segbf) .................................................................................. 243 segbf block diagram .............................................................................................................. .......... 243 segbf software lcd enqueue ..................................................................................................... 245 segbf force hec value ............................................................................................................. .246 segbf control register ........................................................................................................... ..... 247 segbf status register ............................................................................................................ ...... 249 segbf invalid lcd register ........................................................................................................ .250 segbf software lcd complete .................................................................................................... 251 segbf interrupt enable register .................................................................................................. 2 51 segbf total user cells transmitted ............................................................................................. 252 segbf total user cells transmitted with clp=0 ......................................................................... 252 segbf total nud cells transmitted ............................................................................................. 253 segbf cell queue status ........................................................................................................... .. 254 segbf last active lcd data registers ........................................................................................ 255 segbf pid high and low limit register ...................................................................................... 256 segbf last active lcd address 0 ............................................................................................... 257 segbf last active lcd address 1 ............................................................................................... 258 mpeg-2 pcr increment register .................................................................................................. 259 mpeg-2 local pcr high ............................................................................................................. .. 260 mpeg-2 local pcr low .............................................................................................................. .. 261 IBM2520L8767 ibm processor for atm resources table of contents page viii atmrm.toc.01 08/27/99 mpeg-2 pid invalidation time ...................................................................................................... .261 pre-pended header byte steering register ...................................................................................262 segbf maximum lcd size ...........................................................................................................2 63 segbf internal status ............................................................................................................ ........264 segbf cell staging array .......................................................................................................... ....264 receive data path entities .......................................................................................... 265 cell re-assembly (reasm) ......................................................................................................... .......265 reasm block diagram .............................................................................................................. .........265 vpi/vci -? lct entry mapping function ...........................................................................................266 reasm control register ........................................................................................................... .....267 reasm status register ............................................................................................................ ......268 reasm interrupt enable register .................................................................................................. 2 69 reasm logical channel table base register ............................................................................... 270 reasm logical channel translate table base register ............................................................... 270 reasm cell address out of range counter ..................................................................................270 reasm cell hec correctable error counter/non-user cell counter ............................................ 271 reasm cell hec uncorrectable error counter/rm cell counter ..................................................271 reasm total user cells received counter ...................................................................................271 reasm total user cells received with clp=0 counter ...............................................................272 reasm out of range lcd register ............................................................................................. 272 reasm state machine register .....................................................................................................2 73 reasm cell staging array .......................................................................................................... ...273 receive aal processing (raal) ..................................................................................................... ..274 functional description .......................................................................................................... ..........274 reassembly timeout (rto) processing ........................................................................................275 lc statistics ................................................................................................................... .................275 oam f5 blocking support ........................................................................................................... ... 276 bad cell support (bad hec, vp/vc out of range, and vc index equal zero) ............................. 276 raw cell routing support .......................................................................................................... .....276 general packet/cell buffer layout ................................................................................................. .276 packet/cell layout in packet buffer ................................................................................................ ..277 shutting down an lcd .............................................................................................................. .....278 performing an lcd shutdown of a cut-through lcd .................................................................... 278 aal5 packet thresholding for cut-through support .....................................................................280 rx aal 5/6/7 cut-through support ................................................................................................ 280 setting up an lcd for rx cut-through support .............................................................................280 dma descriptors used for header dmas .......................................................................................281 doing software assisted dmas on packet completion ..................................................................281 alternate header dma method ....................................................................................................... 281 receive aal0 and non-user data cut-through support .............................................................. 281 aal5 scatter support ............................................................................................................. ........282 scatter packet buffer layout ...................................................................................................... .......283 raall max sdu length register .................................................................................................. 285 raall lc reassembling count register ...................................................................................... 285 raall lc reassembling threshold register ................................................................................286 raall scatter page size and queue register .............................................................................. 286 raall scatter dma list free destination register .......................................................................287 raall non-user data config register ..........................................................................................287 raall raw mode early drop pool-id register ..............................................................................288 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page ix raall interrupt enable register ................................................................................................... 288 raall status register ............................................................................................................ ....... 289 raall control register ........................................................................................................... ...... 290 raall lc table bound registers ................................................................................................. 292 raall reassembly timeout value register ................................................................................. 293 raall reassembly timeout pre-scaler register ......................................................................... 293 raall lc statistics overflow register .......................................................................................... 294 raall fifo sync operation register ........................................................................................... 294 raall lcd update data registers ............................................................................................... 295 raall lcd update mask registers .............................................................................................. 295 raall lcd update op register ................................................................................................... 296 raall cut through desc address registers ................................................................................ 296 raall cut through op (ctop) registers .................................................................................... 297 raall cut through hardware fifo registers ............................................................................. 298 raall - dma flag registers ......................................................................................................... 299 receive queues (rxque) ........................................................................................................... ....... 300 functional description .......................................................................................................... .......... 300 receive queue interface .......................................................................................................... ...... 300 raall rxque event structure ....................................................................................................... .300 event summary and routing info ..................................................................................................... 301 aal5 packet events ............................................................................................................... ........ 303 cell events ..................................................................................................................... ................ 304 lc events ....................................................................................................................... ................ 305 abr events ...................................................................................................................... .............. 305 miscellaneous .................................................................................................................. ............... 306 general queue, event, and data structure linkage ........................................................................ 308 rxque structure ................................................................................................................. .......... 309 general rxque queue structure ..................................................................................................... .309 rxque initialization ............................................................................................................ ........... 310 rxque initialization code ........................................................................................................ .......... 310 rxque event routing .............................................................................................................. ..... 311 rxque normal operation ........................................................................................................... .. 311 rxque queue full operation ....................................................................................................... 3 12 rxque event timestamping ......................................................................................................... 312 rxque dequeue event loop .......................................................................................................... ... 312 rxque lower bound registers .................................................................................................... 313 rxque upper bound registers .................................................................................................... 314 rxque head pointer registers ..................................................................................................... 3 15 erxque tail pointer registers ..................................................................................................... 316 rxque length registers ........................................................................................................... .... 317 rxque threshold registers ........................................................................................................ .. 318 rxque dequeue registers .......................................................................................................... .319 rxque enqueue registers .......................................................................................................... .319 rxque last event dropped register ............................................................................................ 320 rxque timestamp register ......................................................................................................... .320 rxque timestamp pre-scaler register ........................................................................................ 320 rxque timestamp shift register ................................................................................................. 321 rxque event routing registers ................................................................................................... 32 1 rxque event latency timer register .......................................................................................... 322 rxque interrupt enable registers ................................................................................................ 32 2 rxque status and enabled status registers ............................................................................... 323 IBM2520L8767 ibm processor for atm resources table of contents page x atmrm.toc.01 08/27/99 rxque control register ........................................................................................................... .....325 rxque control 2 register .......................................................................................................... ...326 debugging register access ........................................................................................................ ....327 rxque rxq state machine variable register ..............................................................................327 rxque rxq enq state machine variable register .....................................................................327 rxque enq fifo head ptr register .............................................................................................328 rxque enq fifo tail ptr register ................................................................................................328 rxque enq fifo array .............................................................................................................. ... 328 phy level interfaces .................................................................................................... 329 the phy interface (linkc) ......................................................................................................... ........329 functional description .......................................................................................................... ..........329 linkc control register ........................................................................................................... .......330 linkc transmitted hec control byte ............................................................................................333 linkc interrupt/status register .................................................................................................. ... 334 linkc interrupt enable register ................................................................................................... .335 linkc prioritized interrupts ..................................................................................................... .......335 linkc transmit state machine register ........................................................................................336 linkc receive state machine register .........................................................................................336 linkc unassigned cell payload data ............................................................................................337 linkc unassigned cell payload data -- bit reversed .............................................................337 linkc passed tx data register ....................................................................................................33 8 linkc pdh interface register ...................................................................................................... .339 nodal processor bus interface (npbus) ..........................................................................................340 npbus control register ........................................................................................................... ......340 npbus status register ............................................................................................................ ......343 npbus interrupt enable register ................................................................................................... 344 npbus eprom address/command register ...............................................................................345 npbus eprom data register ......................................................................................................346 phy 1 registers .................................................................................................................. ...........346 phy 2 registers .................................................................................................................. ...........346 hardware protocol assist entities .............................................................................. 347 on-chip checksum and dram test support (chksm) ...................................................................347 functional description .......................................................................................................... ..........347 chksm base address register .....................................................................................................34 7 chksm read/write count register ...............................................................................................348 chksm tcp/ip checksum data register .....................................................................................349 chksm ripple base register ........................................................................................................ 349 chksm ripple limit register ....................................................................................................... ..350 chksm interrupt enable register ..................................................................................................3 50 chksm status register ............................................................................................................ .....351 chksm control register ........................................................................................................... .....352 chksm internal state ............................................................................................................. ........353 software use of chksm ............................................................................................................. ... 354 running a tcp/ip checksum in packet/control memory ............................................................... 355 processor core (pcore) ........................................................................................................... ........356 dcr interface ................................................................................................................... ..............356 pcore block diagram .............................................................................................................. .........356 interrupt controller ............................................................................................................ ..............357 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page xi clock & power management .......................................................................................................... 357 processor local bus(plb) ......................................................................................................... .... 357 bridge ......................................................................................................................... .................... 357 sram ........................................................................................................................... .................. 357 control memory .................................................................................................................. ............ 357 packet memory ................................................................................................................... ............ 357 pci master interface-external .................................................................................................... .... 357 IBM2520L8767 register space ...................................................................................................... 357 pci slave interface .............................................................................................................. ........... 358 address translation examples ..................................................................................................... .. 358 pcore control register ........................................................................................................... ..... 358 pcore status register ............................................................................................................ ..... 360 pcore user status register ........................................................................................................ .361 pcore 401 external status register ............................................................................................ 362 pcore IBM2520L8767 shadow status register .......................................................................... 363 pcore IBM2520L8767 shadow rxque status register .............................................................. 363 pcore interrupt enable register .................................................................................................. 3 64 pcore user interrupt enable ....................................................................................................... .364 pcore 401 interrupt enable register ........................................................................................... 364 pcore error lock enable register ............................................................................................... 365 pcore user error lock enable register ...................................................................................... 365 pcore transaction dead man timer value register ................................................................... 365 pcore address translation base address array ......................................................................... 366 pcore address transaction type and range array .................................................................... 367 pcore last plb address register ............................................................................................... 368 pcore last plb error register .................................................................................................... 36 9 pcore sram ...................................................................................................................... ......... 370 pcore sram base address ........................................................................................................ 370 pcore read data transfer registers .......................................................................................... 371 pcore write data transfer registers .......................................................................................... 371 pcore IBM2520L8767 polling register ....................................................................................... 372 pcore integer input rate conversion register ........................................................................... 372 pcore abr output rate register ................................................................................................ 373 plb pacr register ................................................................................................................ ....... 373 rs-232 interface logic (rs-232) ................................................................................................... ..... 374 rs-232 line status register ....................................................................................................... ... 374 rs-232 handshake status register ............................................................................................... 375 rs-232 baud rate divisor high register ....................................................................................... 376 rs-232 baud rate divisor low register ....................................................................................... 376 rs-232 serial port control register ............................................................................................... 3 77 rs-232 receive command register ............................................................................................. 378 rs-232 transmit command register ............................................................................................ 379 rs-232 byte transmit/receive buffer ............................................................................................ 380 rs-232 mode register ............................................................................................................. ...... 381 rs-232 four byte transmit/receive buffer ................................................................................... 382 reset and power-on logic (crset) ................................................................................................. 38 3 reset status register ............................................................................................................ ......... 383 software reset enable register .................................................................................................... 384 software reset register .......................................................................................................... ....... 384 memory type register ............................................................................................................. ...... 385 crset pll range debug ............................................................................................................. 386 crset control register ........................................................................................................... ..... 387 IBM2520L8767 ibm processor for atm resources table of contents page xii atmrm.toc.01 08/27/99 clock control register (nibble aligned) ......................................................................................... 388 cbist prpg results ............................................................................................................... ......389 cbist misr results ............................................................................................................... .......389 select a clock" selection matrix ................................................................................................... ....389 cbist bist rate .................................................................................................................. ............390 cbist prpg expected signature .................................................................................................. 390 cbist misr expected signature ................................................................................................... 39 1 cbist cyct load value ............................................................................................................. ..391 jtag interface logic (cjtag) ...................................................................................................... .....392 scanning ....................................................................................................................... ..................392 instruction format .............................................................................................................. .............393 idcode ......................................................................................................................... .................394 sample/preload ................................................................................................................. ......394 extest ......................................................................................................................... .................394 bypass ......................................................................................................................... .................394 runbist ........................................................................................................................ ................394 bist_results ................................................................................................................... .......... 395 walnut_mode .................................................................................................................... ........395 compliant_mode ................................................................................................................. .....395 stop ........................................................................................................................... ...................395 scan ........................................................................................................................... ...................395 scan_in ........................................................................................................................ ................395 scan_out ....................................................................................................................... .............395 sonet framer core ....................................................................................................... 397 gppint architecture ............................................................................................................. ..............397 reset register .................................................................................................................. ..............397 interrupt registers ............................................................................................................. .............397 framr chiplet address mapping ..................................................................................................... 397 handshaking error registers ...................................................................................................... ....398 clock monitor status registers .................................................................................................... ... 398 local gppint configuration registers ..........................................................................................398 global static configuration registers ............................................................................................. 398 status registers ................................................................................................................ ..............398 gppint chiplet address mapping overview: base address = x?c00 ............................................399 gppint register description ...................................................................................................... .......400 chiplet reset register (resgp) .................................................................................................... 400 chiplet interrupt and mask registers (irqgp1, irmgp1) .............................................................401 handshaking error indication and mask registers (hshake1, hsmask1) ..................................... 402 clock monitor status and mask registers (clkstat1, clkmask1) ...................................................404 clock monitor test period register (cmongp1) ............................................................................405 watchdog timer period register (wdtgp1) ................................................................................. 405 gppint local configuration registers (confgp1) ........................................................................406 vital macro data register (vpd) .................................................................................................... 407 static configuration register (gatmcs) .......................................................................................407 gcasc .......................................................................................................................... ...................408 glooptx ........................................................................................................................ .................408 glooprx ........................................................................................................................ .................409 gextres ........................................................................................................................ ..................409 ofptxgp ........................................................................................................................ ...............410 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page xiii ofprxgp1 ....................................................................................................................... ............. 410 ofprxgp2 ....................................................................................................................... ............. 411 pimrconf2 ...................................................................................................................... ............... 411 simstat ........................................................................................................................ ................... 412 gpphandler architecture ......................................................................................................... .......... 413 counter registers ............................................................................................................... ............ 413 reset registers ................................................................................................................. ............. 413 command registers ............................................................................................................... ........ 413 gpphandler architecture ......................................................................................................... .......... 413 event latch registers ............................................................................................................ ........ 414 interrupt registers ............................................................................................................. ............. 414 configuration registers ......................................................................................................... ......... 414 atm cell handler architecture: transmit direction ........................................................................ 415 ach_tx gpp handler address mapping .......................................................................................... 415 counter registers ............................................................................................................... ............ 416 rofmid ......................................................................................................................... ................. 416 rofhi .......................................................................................................................... ................... 416 acbc ........................................................................................................................... ................... 417 iuc ............................................................................................................................ ..................... 417 acbe ........................................................................................................................... ................... 418 acbeth11- ...................................................................................................................... .............. 418 cnten1 ......................................................................................................................... ................... 419 reset register (reset) ........................................................................................................... ..... 419 status registers ................................................................................................................ ............. 420 stat1 .......................................................................................................................... .................. 420 iucstat1 ....................................................................................................................... ............... 421 interrupt request and mask registers ........................................................................................... 421 mainirq ........................................................................................................................ ................. 421 m_mainirq ...................................................................................................................... .............. 422 cntrirq1 ....................................................................................................................... ................. 422 m_cntrirq1 ..................................................................................................................... .............. 423 configuration registers ......................................................................................................... ......... 423 celltenable .................................................................................................................... .......... 423 acbtxthrpae .................................................................................................................... ......... 425 sdbtxthrpaf .................................................................................................................... ......... 425 headerbyte1 .................................................................................................................... ......... 426 headerbyte2 .................................................................................................................... ......... 426 headerbyte3 .................................................................................................................... ......... 427 headerbyte4 .................................................................................................................... ......... 427 headerbyte5 .................................................................................................................... ......... 428 payloadbyte .................................................................................................................... ......... 428 hecenctrl ...................................................................................................................... ............ 429 hecoffset ...................................................................................................................... ............ 430 hecmaskand ..................................................................................................................... ......... 430 hecmaskor ...................................................................................................................... .......... 431 atm cell handler architecture: receive direction .......................................................................... 432 ach_rx gpp handler address mapping .......................................................................................... 432 counter registers ............................................................................................................... ............ 433 rofmid ......................................................................................................................... ................. 433 rofhi .......................................................................................................................... ................... 433 fhr ............................................................................................................................ .................... 434 IBM2520L8767 ibm processor for atm resources table of contents page xiv atmrm.toc.01 08/27/99 ihr ............................................................................................................................ ......................434 ehr1 ........................................................................................................................... ...................435 ehr1th11 ....................................................................................................................... ...............435 eht1th12 ....................................................................................................................... ................436 bhr ............................................................................................................................ ....................436 bhrth11 ........................................................................................................................ ................437 bhrth12 ........................................................................................................................ ................437 cnten1 ......................................................................................................................... ...................438 reset register (reset) ........................................................................................................... ......438 command register (cmd1) .......................................................................................................... .439 status register (stat1) .......................................................................................................... .......440 interrupt request and mask registers ........................................................................................... 441 mainirq ........................................................................................................................ ..................441 m_mainirq ...................................................................................................................... ...............441 cntrirq1 ....................................................................................................................... ..................442 m_cntrirq1 ..................................................................................................................... ...............443 configuration registers ......................................................................................................... .........444 conf5 .......................................................................................................................... ..................444 conf6 .......................................................................................................................... ..................445 confc .......................................................................................................................... .................445 h1conf ......................................................................................................................... ................446 h2conf ......................................................................................................................... ................446 h3conf ......................................................................................................................... ................447 h4conf ......................................................................................................................... ................447 h5conf ......................................................................................................................... ................448 overhead frame processor architecture: transmit direction ....................................................... 449 ofp_tx gpp handler address mapping ...........................................................................................449 counter registers ............................................................................................................... ............452 ptrinc ......................................................................................................................... ..................452 ptrdec ......................................................................................................................... ................452 nd_evcnt ....................................................................................................................... ..............453 juscnt ......................................................................................................................... .................453 juscntth11 ..................................................................................................................... .............454 cnten1 ......................................................................................................................... ...................454 reset register .................................................................................................................. ..............455 reset .......................................................................................................................... ..................455 command register ................................................................................................................ .........455 cmd1 ........................................................................................................................... ...................455 status registers ................................................................................................................ ..............456 stat1 .......................................................................................................................... ...................456 stat2 .......................................................................................................................... ...................456 interrupt and mask registers ...................................................................................................... ....457 mainirq ........................................................................................................................ ..................457 m_mainirq ...................................................................................................................... ...............458 cntrirq1 ....................................................................................................................... ..................459 m_cntrirq1 ..................................................................................................................... ...............460 irq3 ........................................................................................................................... .....................461 m_irq3 ......................................................................................................................... ..................462 configuration registers ......................................................................................................... .........463 conf1 .......................................................................................................................... ..................463 conf2 .......................................................................................................................... ..................464 conf3 .......................................................................................................................... ..................464 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page xv conf4 .......................................................................................................................... ................. 465 conf5 .......................................................................................................................... ................. 465 conf6 .......................................................................................................................... ................. 466 conf7 .......................................................................................................................... ................. 467 conf8 .......................................................................................................................... ................. 467 conf9 .......................................................................................................................... ................. 468 conf10 ......................................................................................................................... ................ 468 overhead frame processor architecture: receive direction ......................................................... 469 ofp_rx gpp handler address mapping .......................................................................................... 469 counter registers ............................................................................................................... ............ 473 rofmid ......................................................................................................................... ................. 473 b1bitcnt ....................................................................................................................... ............... 473 b1bitcntth11 ................................................................................................................... ........... 474 b1bitcntth12 ................................................................................................................... ........... 474 b1blkcnt ....................................................................................................................... .............. 475 b1blkcntth11 ................................................................................................................... .......... 475 b1blkcntth12 ................................................................................................................... .......... 476 b2bitcnt ....................................................................................................................... ............... 476 b2bitcntth11 ................................................................................................................... ........... 477 b2bitcntth12 ................................................................................................................... ........... 477 b2bitcntth21 ................................................................................................................... ........... 478 b2bitcntth22 ................................................................................................................... ........... 478 b2blkcnt ....................................................................................................................... .............. 479 b2blkcntth11 ................................................................................................................... .......... 479 b2blkcntth12 ................................................................................................................... .......... 480 b2blkcntth21 ................................................................................................................... .......... 480 b2blkcntth22 ................................................................................................................... .......... 481 b3bitcnt ....................................................................................................................... ............... 481 b3bitcntth11 ................................................................................................................... ........... 482 b3bitcntth12 ................................................................................................................... ........... 482 b3blkcnt ....................................................................................................................... .............. 483 b3blkcntth11 ................................................................................................................... .......... 483 b3blkcntth12 ................................................................................................................... .......... 484 msreicnt ....................................................................................................................... .............. 484 msreicntth11 ................................................................................................................... .......... 485 msreicntth12 ................................................................................................................... .......... 485 hpreicnt ....................................................................................................................... .............. 486 hpreicntth11 ................................................................................................................... .......... 486 hpreicntth12 ................................................................................................................... .......... 487 pj_evcnt ....................................................................................................................... .............. 487 nj_evcnt ....................................................................................................................... .............. 488 nd_evcnt ....................................................................................................................... ............. 488 cnten1 ......................................................................................................................... ................... 489 cnten2 ......................................................................................................................... ................... 490 reset register (reset) ........................................................................................................... ..... 490 status registers ................................................................................................................ ............. 491 stat1 .......................................................................................................................... .................. 491 stat2 .......................................................................................................................... .................. 491 stat3 .......................................................................................................................... .................. 492 stat4 .......................................................................................................................... .................. 493 interrupt and mask registers ...................................................................................................... ... 494 IBM2520L8767 ibm processor for atm resources table of contents page xvi atmrm.toc.01 08/27/99 mainirq ........................................................................................................................ ..................494 m_mainirq ...................................................................................................................... ...............495 cntrirq1 ....................................................................................................................... ..................496 m_cntrirq1 ..................................................................................................................... ...............497 cntrirq2 ....................................................................................................................... ..................498 m_cntrirq2 ..................................................................................................................... ...............499 cntrirq3 ....................................................................................................................... ..................500 m_cntrirq3 ..................................................................................................................... ...............501 irq6 ........................................................................................................................... .....................502 m_irq6 ......................................................................................................................... ..................503 irq7 ........................................................................................................................... .....................504 m_irq7 ......................................................................................................................... ..................505 irq8 ........................................................................................................................... .....................506 m_irq8 ......................................................................................................................... ..................507 configuration registers ......................................................................................................... .........508 conf1 .......................................................................................................................... ..................508 conf2 .......................................................................................................................... ..................509 conf3 .......................................................................................................................... ..................510 conf4 .......................................................................................................................... ..................511 conf7 .......................................................................................................................... ..................512 conf8 .......................................................................................................................... ..................513 conf9 .......................................................................................................................... ..................513 printed circuit board considerations .............................................................................................. .515 memory map for registers and arrays .............................................................................................515 pin assignments and dc characteristics .........................................................................................516 signal pin listing by family ....................................................................................................... ........516 book definitions ................................................................................................................ ..................530 ac timing characteristics ........................................................................................... 532 phy timing ...................................................................................................................... ....................532 npbus sideband interface timing ................................................................................................... .533 i/o pci bus timing ................................................................................................................ ..............533 npbus timing .................................................................................................................... .................533 pci bus timing ................................................................................................................... .................533 synchronous dram timing .......................................................................................................... .....535 sdram read cycle ................................................................................................................. ............535 sdram read cycle ................................................................................................................. ............535 sdram read cycle ................................................................................................................. ............536 sdram read cycle ................................................................................................................. ............536 sdram write cycle ................................................................................................................ .............537 sdram write cycle ................................................................................................................ .............538 sdram write cycle ................................................................................................................ .............539 sdram write cycle ................................................................................................................ .............540 sdram write of 64-byte burst with cas latency=2 .........................................................................541 sdram write of 64-byte burst with cas latency=3 .........................................................................542 sram timing ..................................................................................................................... ..................543 sram read cycle .................................................................................................................. .............543 sram write cycle ................................................................................................................. ..............544 IBM2520L8767 ibm processor for atm resources atmrm.toc.01 08/27/99 table of contents page xvii sram read cycle with byte enables ............................................................................................... 545 sram write cycle with byte enables ............................................................................................... 546 eprom timing .................................................................................................................... ................ 547 parallel eprom read .............................................................................................................. ........... 547 parallel eprom write ............................................................................................................. ............ 548 serial eprom read ................................................................................................................ ............ 549 serial eprom write ............................................................................................................... ............. 550 phy timing ...................................................................................................................... .................... 551 phy read ........................................................................................................................ ..................... 551 phy write ....................................................................................................................... ...................... 552 revision log ................................................................................................................. 553 IBM2520L8767 ibm processor for atm resources table of contents page xviii atmrm.toc.01 08/27/99 atmrm.chapt01.01 08/27/99 IBM2520L8767 ibm processor for atm resources features page 1 of 553 features ? optimized for server applications. configurable for sustained performance of up to 400mb/s at full duplex. - up to 65,534 independent logical chan- nels. - individual or group allocation of resources. - firewall protection of packet memory stor- age and channel bandwidth. - extensive support for virtual paths with vc bandwidth sharing. scalablephyinterface - 8 and 16-bit utopia interface (1 to 622mhz). - cell hec generation, checking, and correc- tion included. pci 32-bit interface up to 33mhz. streaming 32-bit bus transfers with peak rate of 132mb/s. two internal memory controllers for packet and control memory. each supports 1-8mb of sram or zbt sram or 4-128mb of edo dram, sdram or esdram. the controllers are inde- pendent: one can use sram devices while the other uses dram devices. a single array of memory can be used in systems whose sus- tained full-duplex total bandwidth requirement is less than 102mb/s. supports aal1, 2, 5, and null aals with framing and scheduling extensions for mpeg-ii. supports cell, stream, fifo, and frame based queuing. supports reception in cell, fifo and frame increments. received frames can be queued by logical channel or group. received frames can be queued after full recep- tion or after header reception. event queue warns of potential problems and predicts the need for data movement without interrupt overhead. configurable interrupts on events. tcp/ip checksum built into memory controller. jtag test interface description ibmIBM2520L8767 is an asynchronous transfer mode resource manager (IBM2520L8767). it acts as an interface and translator between a peripheral component interconnect (pci) bus and an atm utopia or similar interface to an atm phy. this device supports an integrated packet/frame memory (integrated dram controller; no glue required) and performs the segmentation and reassembly (sar) functions for several of the atm adaptation layers (aals). atm subsystem block diagram (please see page 10 for descriptions of subsystems.) virtual/real memory interfaces each supports up to 8mb sram or 128mb dram dma engine phy interface sar transmit queuing interface powerpc 401 33mhz (abr & user fxn) 33mhzpcibusinterface control bus control memory packet memory eprom (init) cell scheduling & segmentation cell buffering frame reassembly receive queuing interface high performance atm resource manager sonet framer (155mb/s) utopia(upto622mb/s) . IBM2520L8767 ibm processor for atm resources ordering information page 2 of 553 atmrm.chapt01.01 08/27/99 conventions throughout this book the bit notation is non-ibm, meaning that bit zero is the least significant bit and bit 31 is the most significant bit for a four-byte word. the internal addressing view of IBM2520L8767 registers and memory is big-endian. in most cases, a system will wire its pci bus interface to make the register view transparent, i.e. , the most significant bit in this specifi- cation will be the most significant bit in the register. if registers are read and written 32 bits at a time (which is the only way to access many of the registers), then the endian-ness should not be a programming issue with respect to the registers. the ibm processor for atm resources dma controller can transfer data in either big-endian or little-endian mode. (see gpdma control register on page 135 for details.) overbars, eg. cas , designate signals that are asserted ?low?. ordering information part number description IBM2520L8767 asynchronous transfer mode resource manager IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 standards compliance page 3 of 553 standards compliance the ibm ibm processor for atm resources, part number IBM2520L8767, has been designed with a number of standards in mind. for additional information, please see: at the network side, ibmIBM2520L8767 complies with the atm standards and recommendations defined by itu-ts (formerly ccitt), ansi and atm forum. the following is a list of standard documents that the ibm processor for atm resources design point is based on: - itu rec. i-361 - b-isdn atm layer specification - itu rec. i.362 - b-isdn atm adaptation layer (aal) functional description - itu rec. i.363 - b-isdn atm adaptation layer (aal) specification - itu rec. i.413 - b-isdn user-network interface - itu rec. i-432 - b-isdn user-network interface - physical layer specification - itu rec. i-610 - oam principles of b-isdn access - ansi t1.atm-199x draft, broadband isdn - atm layer functionality and specification - ansi t1.cbr-199x draft, broadband isdn - atm adaptation layer for constant bit rate service functionality and specification - atm forum 93-620r2 - atm user-network interface specification - version 2.3 (july 27, 1993) - bellcore ta-nwt-001248 generic requirements for operations of broadband switching systems (october 1993) at the system interface side, ibmIBM2520L8767 complies with the following pci-bus architecture: - pci local bus specification, production version, revision 2.1, june 1, 1995. interface technical ref- erence, 11/89, part number 15f2160. the phy interface of ibmIBM2520L8767 conforms to the following specifications: - saturn user network interface, pmc-sierra, inc., february 1995 - atm forum 93-727 an atm phy data path interface, version 2.01, march 24, 1994 - am7968/am7969 taxichip(tm) handbook, transparent asynchronous transmitter/receiver inter- face, published by advanced micro devices, 1994. IBM2520L8767 ibm processor for atm resources environmental ratings page 4 of 553 atmrm.chapt01.01 08/27/99 environmental ratings absolute maximum ratings parameter rating unit note supply voltage -0.5 to 3.6 volt 1 input voltage applied -0.5 to 5.5 volt 1 storage temperature -65 to 150 c 1 ambient temperature with power applied -40 to 100 c 1 esd voltage 3000 volt 1 1. these are the maximum ratings that can be applied to the device without damage. the device function and specifications are valid only within the recommended operating conditions. recommended operating conditions parameter rating unit junction temperature 0to85 c supply voltage (v dd ) with respect to ground 3.3 2 % volt power dissipation parameter rating unit total (nominal) 2watt total (maximum) 3watt IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 package diagram page 5 of 553 package diagram this view 1.75 min 2.15 max also no ball a01 locator 20l8767 linear tolerances: +- 0.5mm top view 0.9 0.1 side view 25mm 0.2 32.5mm 0.2 IBM2520L8767 ibm processor for atm resources pinout viewed from above page 6 of 553 atmrm.chapt01.01 08/27/99 pinout viewed from above pin functions are listed in input/output definitions on page 19. complete lists of pin assignments are in pin assignments and dc characteristics on page 516. ground pin locations 0a19 0b06 0b10 0b14 0e02 0e08 0e12 0e18 0g06 0g10 0g14 0j04 0j08 0j12 0j16 0l06 0l10 0l14 0n04 0n08 0n10 0n12 0n16 0r06 0r10 0r14 0u04 0u08 0u12 0u16 0w06 0w10 0w14 aa02 aa08 aa12 aa18 ad06 ad10 ad14 ae01 ae19 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 01 1.06 max 0.62 min 1.06 max 0.62 min 22.86mm 18 x 1.27mm linear tolerances: 0.5mm 32 0.2mm 30.48mm gnd no connect v dd this view 25 0.2mm IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 pinout viewed from below page 7 of 553 pinout viewed from below pin functions are listed in input/output definitions on page 19. complete lists of pin assignments are listed in pin assignments and dc characteristics on page 516. v dd pin locations 0c04 0c08 0c12 0c16 0e06 0e10 0e14 0g04 0g08 0g12 0g16 0j02 0j06 0j10 0j14 0j18 0l04 0l08 0l12 0l16 0m09 0m11 0n02 0n06 0n14 0n18 0p09 0p11 0r04 0r08 0r12 0r16 0u02 0u06 0u10 0u14 0u18 0w04 0w08 0w12 0w16 aa06 aa10 aa14 ac04 ac08 ac12 ac16 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 gnd no connect v dd this view IBM2520L8767 ibm processor for atm resources block diagram page 8 of 553 atmrm.chapt01.01 08/27/99 block diagram crset cbist sclck cjtag interrupt status intst pcint dmaq dma gpdma sram 401 core bcach bus cache dram control arbiter comit/vmem rxque rx queue management raal aal processing reasm reassembly internal sonet framer npbus asynchronous cell interface linkc cell scheduler segmentation segbf csked memory pool control pools and dma chksm control dram frame dram phy control/ eprom access 8/16 bit phy interface serial interface internal memory bus checksum pci bus IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 functional description page 9 of 553 functional description the ibm processor for atm resources acts as a conversion unit from a bus memory interface (which is work queue oriented) to a phy level atm. to accomplish this, the IBM2520L8767 contains the major functional units listed below and shown in the block diagram on page 8. control processor bus interface pcint pci interface entity intst interrupt status entity gpdma general purpose dma entity dmaqs queue control for dma activity memory control comet/pakit dram controlling entity vimem virtual memory controller arbit memory subsystem arbitration requestor bcach bus cache entity pools memory pool manager transmit data path csked cell scheduler segbf cell segmentation entity receive data path reasm cell re-assembly entity raall aal processor rxque receive queue manager phy level interfaces linkc asynchronous physical layer interface npbus nodal processor bus interface framr full sonet framing support logic hardware protocol assist chksm tcp/ip checksum logic pcore embedded 401 processor core base device functions sclck the system clock generation and repowering entity crset hardware and software reset controlling entity cbist built-in self test logic entity cjtag jtag test interface logic entity IBM2520L8767 ibm processor for atm resources subsystem blocks page 10 of 553 atmrm.chapt01.01 08/27/99 subsystem blocks the ibm ibm processor for atm resources has the following four interfaces. the ibm processor for atm resources provides the host bus interfacing, memory management for buffers and control, cell segmentation and reassembly, and phy hardware control for an atm adapter. external memory , consisting of two dram, sdram, or sram arrays used for the storage of packet data and the control structures used by the ibm processor for atm resources. both the packet and control mem- ory arrays consist of two, 32-bit wide banks. when running at 102mb/s or slower (full duplex aggregate throughput), a single array of memory can be used. both control and data store would be contained in this single array of memory. for a detailed descrip- tion of the external memory organization refer to the dram controllers (comet/pakit) on page 141. the phy (physical) layer , which connects to several available hardware support devices. this layer of hardware converts a parallel data stream into a serial data stream to be shipped to and from the pmd layer. the phy and pmd end of a card design can be implemented as one of several encoding schemes and speeds, supporting both copper and fiber optic serial links. the interface will support the atm forum ?utopia spec,? the pmc chip, the amd taxi chip set, and possibly a 25mb/s serial interface to the ibm utp solution. (see standards compliance on page 3 for documents which describe these interfaces.) the pmd (physical media dependent) layer , which connects to the line drivers and receivers. this could be either a copper or a fiber optic transceiver. external architecture the ibm ibm processor for atm resources has four major interfaces: a system bus which will act as an actively cached memory slave and and as a master for the pci 32-bit bus. the physical (phy) interface which supports several physical layer hardware devices that perform parallel to serial data conversion and the rest of the transmission convergence. an external dram interface that controls one or two arrays of 2-bank interleaved dram with 60-ns access time for packet and control memory. the interface is direct drive to the dram. the control and configuration interface which covers a number of functions. it gives access from the sys- tem bus to the phys and to eprom. the eprom can also be used to hold initial device configuration, up to and including pvc configurations. these four interfaces allow the ibm processor for atm resources to be used in both "deep" and "shallow" adaptors with minimal external logic. (see block diagrams of possible systems on page 12 for examples.) IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 internal architecture page 11 of 553 internal architecture logical channel support the logical channel is the unit of resource allocation in atm. at one level, the end station negotiates with the network interface to determine the characteristics of each end station to end station connection. the resources that may be reserved in the network are defined in the atm uni (user network interface) specifi- cation (see references in standards compliance on page 3). these resources include (but are not limited to) the peak and average bandwidth to be used by the logical channel, the maximum burst length that may be transmitted at the burst rate, the latency and variance of the connection, and the loss probability. the term logical channel rather than virtual circuit or vpi/vci is used in this databook to provide a level of abstraction from these specific instances. a switched virtual circuit (svc) can be negotiated with specific characteristics specifically for it. a virtual path can be negotiated with the network, and several virtual circuits within that path can then be mul- tiplexed using the vci on that single vpi without having to renegotiate for each additional vci. the logical channel with respect to the network would be the virtual path. there would be multiple logical channels inter- nal to the end station based on the virtual circuits used within the path. using atm adaptation layers 3 and 4, a multiplexing identifier (mid) can be used to provide multiple logical channels across a single vpi/vci. all of these logical channels are dealt with uniformly in the IBM2520L8767. a hierarchy of logical channel descriptors can be built up, and frames or buffer can be queued to each of the lcds. see transmit cell scheduler (csked) on page 223 for details. virtual memory support the packet memory space appears on the bus as if it is up to 64k buffers each of which can (architecturally) appear to be 64k bytes long. a level of indirection has been added to the addressing of packet memory to provide these large frame buffers without requiring memory behind all of them at the same time. this has been done for a number of reasons: the frames on the network can be up to 64kb long. the receiver does not know how long a frame will be until it is completely received. software generally has a much easier time of dealing with contiguous memory. the memory does not page or swap. there two major efficiencies used internally: the first n bytes of memory in a buffer are directly referenced. the blocks that make up the buffers are of multiple sizes. IBM2520L8767 ibm processor for atm resources block diagrams of possible systems page 12 of 553 atmrm.chapt01.01 08/27/99 queues the IBM2520L8767 makes extensive use of three types of cached single memory operation atomic queues: scheduling there is extensive support for transmit scheduling. please see transmit descriptor data structures on page 39 and transmit packet header structure on page 35 for details. transmit queues the interface to the scheduling entity. blocks and frames can be queued to logical channels. receive queues based on the settings in the logical channel descriptor (receive side), cells arriving can be queued indi- vidually, collected into frames, of stored in fifo buffers. event queues when a frame is transmitted, its memory can be ?garbage collected? or a reference to the frame can be placed on an event queue for software to handle. if either a fifo buffer scheme or frame buffer scheme is used to source or sink data on a logical channel, it is possible to set thresholds on the buffering that will cause events to be queued. when a threshold is crossed, for instance if a transmitting lc is about to run out of data to transmit, an event will be queued. software can read these events either by polling or by being interrupted and can schedule tasks to provide more data. events can be scheduled on the reception of the first n bytes of a frame so that header processing can begin even before the complete frame is received. this will allow ?cut-through? routing to be supported. block diagrams of possible systems memory 2-256mb ecc optical transceiver atm-rm device memory 2-256mb ecc short pci card pci bus shallow adapter for 155mb/s optical transceiver transmit device atm-rm device short pci card pci bus receive device 100 mb/sec card using a taxi chipset IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 mpeg video compression and distribution considerations page 13 of 553 mpeg video compression and distribution considerations the atm forum has specified mechanisms to be used for the delivery of video streams. they are based on the mpeg-ii video compression standard which produces a variable rate video stream. the challenge is to ensure that the delivery of this stream is performed effectively. the figure below shows a six-second sequence of an mpeg encoded video. it clearly shows the scheme employed mpeg encoding; every twelfth frame transmitted is an "i" or image frame. this frame is a complete compressed version of its basis frame. in between each "i" frame there are three "p" or predicted frames that predict, based on the previous ?i? and ?p? frames, what the image should look like, and then compare the pre- diction with the actual basis frame. what is transmitted in the ?p? frame is the difference between the predic- tion and the actual data. the third frame type is the "b" or between/both frame. these frames are also difference-from-prediction frames, but they use information about frames in both directions in time. because the ?b? frames are interpolations rather than projections, the predictions are usually much more accurate than the ?p? frames, so the differences from the predictions are generally smaller. the variations in frame size can be seen due to differences in the compression quality, or compressibility, of the sepecific video. a number of issues require consideration in the attempt to support digital delivery of video. one "hook" that the ibm processor for atm resources includes is a delivery mode that stays within the traffic specification for traffic shaping, but attempts to deliver these variable sized frames on fixed time intervals. IBM2520L8767 ibm processor for atm resources atm subsystem dataflow page 14 of 553 atmrm.chapt01.01 08/27/99 as shown in the figure, data, in the form of application objects or control structures, are divided into commu- nication frames at the communication stack interface. the stack may further partition the frames to fit reliabil- ity, efficiency, latency, and protocol requirements. in most cases, the communication stack encapsulates the data frame with protocol headers and/or trailers. these header blocks are often located in memory in areas apart from the data frames. a device driver is often given the task of moving this scattered memory to the actual transmission device. scatter dma is often used to make this operation efficient. with an IBM2520L8767 in the atm subsystem, the data can be dmaed into virtually contiguous buffers con- nected to and controlled by the IBM2520L8767. it is also possible to write the frame headers directly from the processor to the IBM2520L8767 memory. the fully assembled frame is queued for transmission over a par- ticular logical channel. (see more on the richness of logical channels in atm and the IBM2520L8767 in data structures on page 35). the logical channels with pending work are serviced by the atm segmentation layer which breaks the enqueued data into 48-byte chunks (depending on the atm adaptation layer (aal)) and prefixes it with a five-byte header in preparation for transmission (yielding 53-byte packets). a transmission convergence (tc) sublayer appropriate for the physical layer (phy) and physical media dependent (pmd) connection is then exercised, making atm cells suitable for transmission. the receiving process is the reverse of the transmission process, except that the scheduling performed dur- ing transmission is replaced by an identification-demultiplexing step during the reception of cells. isochronous/time-based support: note that not all of these separate parts or steps described in this section are necessary for a dedicated function system. the IBM2520L8767 can easily be used in dedicated systems due to it goal of minimal processor intervention for steady state operations. atm subsystem dataflow object data object data application data frames frame headers and data packet memory local channels lan emulation tcp/ip mapping communication stack device driver at m cells segmentation scheduling physical layer (tc) pmd / transceiver control memory application IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 data flows page 15 of 553 data flows this section describes the data and control flow to and through the ibm processor for atm resources. in order for cell traffic to flow through an atm interface, the cells require that logical channels be allocated. for information on logical channels, please see data structures on page 35. feature summary virtual memory memory pools register read/write interface for memory allocation transmit path scheduling receive path demultiplexing event queues operation summary basic assurance tests (bats) initialize and cconfigure test path to switch permanent virtual circuit setup identify lan servers initialize svcs run, initializing circuits (q.93b) and transmitting data. transmit path a typical transmit operation begins with the software requesting a buffer from pools and filling it with data via slave dma, master dma, or processor writes. if virtual buffers are being used, the data write operation can fail due to lack of physical buffers. in the event of a failure, the header of the packet is updated to indicate the failure. the software can audit the header after the buffer has been completely transferred, and either take action to recover the data immediately, or allow csked to generate an event later in the transmit cycle for any buffers that have had a data write failure. before the data can be transmitted, the buffer header must be updated to contain information required for cor- rect transmission. information such as data length, starting offset, and logical channel (lc) address are just a few of the fields that must be correctly reflected in the buffer header. for a complete list of the fields in the buffer header refer to packet header on page 35. in addition to the fields in the buffer header, the scheduling and segmentation sections of the logical channel descriptor (lcd) such as peak rate, average rate, and aal type must also be set up correctly prior to trans- mission. for a complete list of the fields in the lcd, refer to transmit descriptor data structures on page 39. after the data has been transferred into packet storage and both the buffer header and the lcd structure have been correctly initialized, the buffer address is queued to csked. when it receives a buffer, c sked checks the buffer header (packet memory) to make sure that the data transfer operation that filled the buffer completed without error. if it finds an error, csked posts an event to software and does nothing further with this buffer. if it does not find an error, csked fetches several fields from the lcd (control memory) indicated in the buffer header to determine the current state of that lcd. if the lcd is busy sending another buffer, the new buffer is queued to this lcd and will be processed when all previously enqueued buffers have been transmitted. if the lcd is not busy, csked updates the lcd based on several fields in the buffer header and queues the lcd to the next time slot on the time wheel (control memory). IBM2520L8767 ibm processor for atm resources transmit scheduling capabilities page 16 of 553 atmrm.chapt01.01 08/27/99 when csked detects a previously enqueued lcd on the time wheel, several fields are retrieved from the lcd. among other things, these fields are used by csked to determine where on the time w heel to resched- ule this lcd. the lcd address is then provided to segbf for processing. when csked provides an lcd address to segbf, the segmentation portion of the lcd is retrieved from control memory to determine both the current address at which to continue buffer segmentation and the type of cell to construct. depending on the aal type bits in the segmentation portion of the lcd, the cell is con- structed in an internal array using data from the lcd as well as data fetched from packet memory. when the cell construction is complete, status is raised to linkc indicating that a new cell is available for transmission. transmit opportunities are repeatedly provided to segbf by csked at the desired rate until all the data in the buffer has been passed to linkc via the cell buffer array. when segbf detects that no more data exists for a buffer, the lcd address is passed back to csked, indicating buffer completion. if no more buffers are queued, csked removes the lcd from the time wheel. if more buffers are queued, the lcd is updated and the segmentation process continues until all buffers on the lcd queue are used. a bit in the buffer header generates a transmit complete event when no buffers remain in the queue. transmit scheduling capabilities vci desc. frame frame frame head pointer tai l pointer frame frame frame frame vci desc. vci desc. pointer fifo extra pin external control fixed rate vci start variable length frames as fixed intervals vpi/vci vpi 3 level priority scheduling wheels cell based transmission stream based transmission frame based transmission transmit queues and logical channel traffic shaping add block byte count threshold IBM2520L8767 ibm processor for atm resources atmrm.chapt01.01 08/27/99 receive path page 17 of 553 receive path as cells arrive, they pass from linkc to reasm. reasm uses a portion of the atm header to look up the lcd address for this cell. the lcd address is then passed to raall. raall reads the receive portion of the lcd, and then processes the cell based on the lcd information. for example, the lcd specifies what aal to use and maintains the current reassembly state. using the current reassembly state, the cell data is written to packet memory. while the data is written to packet memory, other functions such as crc generation and ver- ification are performed in parallel. if a packet is complete, all trailer verification is performed. if the packet is good, an event is placed on a receive queue in the rxque entity. for error scenarios, see entity 14: receive queues (rxque) on page 300 and entity 13: receive aal processing (raal) on page 274. at this point, software can dequeue the packet event from rxque using the dequeue operation. it can then examine headers, dma the data into user space, and perform tcp checksums. when these actions are complete, the buffer is returned to the IBM2520L8767 by performing a pools free buffer operation. IBM2520L8767 ibm processor for atm resources receive path page 18 of 553 atmrm.chapt01.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 page 19 of 553 input/output definitions the several interfaces to the ibm processor for atm resources are described in the following sections. there are 383 active i/o pins, assigned as follows: 89forthepcibus, 21forthenpbus, 57 for the phy bus, 142 for the dram memory interface, and 42 strictly for configuration and testing. cross references between the physical pin assignments and pin signal names are listed in pin assignments and dc characteristics on page 516. pci bus connections IBM2520L8767 mframe pcbe(3-0) mserr pa d ( 3 1 - 0 ) ppar mperr minta mint2 pidsel mdevsel mtrdy mirdy mlock/msreq mstop mgnt mreq pad64(64-32)/enstate pcbe64(7-4)/enstate mreq64/enstate mack64/enstate ppar64/enstate pci bus IBM2520L8767 ibm processor for atm resources page 20 of 553 atmrm.chapt02.01 08/27/99 pci bus interface pin descriptions quantity pin name input/output pin description 1mframe s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. 4 pcbe(3-0) t/s bus command and byte enables are multiplexed on the same pci pins. during address phase they define the bus command and during the data phase they define the byte enables. 1mserr o/d system error reports address parity errors, data parity errors on the special cycle com- mand, or any other system error where the result will be catastrophic. 32 pad(31-0) s/t/s address and data are multiplexed on the same pins. a bus transaction consists of one address phase and one or more data phases. 1ppar t/s parity is even parity across ad(31-0) and c/be(3-0). parity generation is required by all pci agents. 1 mperr s/t/s parity error is for reporting data parity errors during all pci bus transactions except spe- cial cycle. 1 minta o/d interrupt a is used to request an interrupt. 1 mint2 o/d or s/t/s the is an interrupt line that will go active low when sources within the IBM2520L8767 go active. it can be optionally connected to pci interrupt b. see entity 2: interrupt and sta- tus/control (intst) on page 95 for more details. 1 pidsel input initialization device select is a chip select during configuration transactions. 1 mdevsel s/t/s device select indicates the driving device has decoded its address as the target of the current transaction. 1 mtrdy s/t/s target ready signals the target agent's ability to complete the current data phase of the transaction. 1 mirdy s/t/s initiator ready indicates the bus master's ability to complete the current data phase. 1mlock s/t/s lock indicates an atomic operation that may require multiple transactions to complete. if this is IBM2520L8767 cascade mode, this bit functions as msreq (secondary request), which the primary IBM2520L8767 will receive from the secondary IBM2520L8767 to then request the main pci bus, or as msgntgi (secondary grant gate in). see pcint cas- cade control register for more details. 1 mstop s/t/s stop indicates the current target is requesting the master to stop the current transaction. 1 mgnt in receives the bus grant line after a request has been made. 1 mreq s/t/s requests the bus for an initiator transfer. 32 pad64(63-32) s/t/s address and data are multiplexed on the same pins and provide 32 additional bits. also, this pins are multiplexed with the enstate outputs, that allow debug of various internal state machines and signals. 4 pcbe64(7-4) t/s bus command and byte enables are multiplexed on the same pci pins for 64 bit transfer support. 1 mreq64 s/t/s request 64-bit transfer. has the same timing as mframe. 1 mack64 s/t/s acknowledge 64-bit transfer. has the same timing as mdevsel. 1 ppar64 s/t/s parity upper dword is the even parity bit that protects mad64(63-32) and pcbe(7-4). when not on a pci bus supporting 64 bits, this will drive enstate outputs. IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 dram memory bus interface page 21 of 553 dram memory bus interface one control memory and one packet memory bus provide the attachment to the external dram. up to two arrays of 32 data bits plus potential error detection bits may be connected to each bus. each bus consists of address, data, and control lines as illustrated below. see memory i/o cross reference by device type on page 23 for the use of a particular signal with a particular memory type. dram memory bus connections IBM2520L8767 pmras (1 downto 0) pmcas (1 downto 0) pmwe (1 downto 0) pmcs (7 downto 4) pmsynras pmsyncas pmclk pmaddr(17 downto 0) pmdata(35 downto 0) pmdata2(38 downto 36) pmclki cmras (1 downto 0) cmcas (1 downto 0) cmwe (1 downto 0) cmcs (7 downto 4) cmsynras cmsyncas cmclk cmaddr(17 downto 0) cmdata(35 downto 0) cmdata2(38 downto 36) cmclki packet memory bus control memory bus IBM2520L8767 ibm processor for atm resources dram memory bus interface page 22 of 553 atmrm.chapt02.01 08/27/99 dram memory bus interface pin descriptions quantity pin name input/output pin function pin description 2pmras (1:0) output pmras (1:0) used for the two packet memory arrays. 2cmras (1:0) output cmras (1:0) used for the two control memory arrays. 2pmcas (1:0) output pmcas (1:0) used by the two packet memory arrays. 2cmcas (1:0) output cmcas (1:0) used by the two control memory arrays. 1 pmsynras output pmsynras the ras signal for packet synchronous dram. 1 cmsynras output cmsynras the ras signal for control synchronous dram. 1 pmsyncas output pmsyncas the cas signal for packet synchronous dram. 1 cmsyncas output cmsyncas the cas signal for control synchronous dram. 2pmwe (1:0) output packet memory write enable. 2cmwe (1:0) output control memory write enable. 4pmcs (7:4) output packet memory sram chip selects. 4cmcs (7:4) output control memory sram chip selects. 1 pmclk output packet memory clock. 1 pmclkrp output packet memory clock repowered. 1 cmclk output control memory clock. 1 cmclkrp output packet memory clock repowered. 18 pmaddr(17:0) output address signals to packet memory. when 1mx16 dram modules are used:12 row- address bits latched by the row address strobe (ras). 8 column-address bits latched by the col- umn address strobe (cas). when 256kx16 mod- ules are used: 9 row-address bits latched by the row address strobe (ras). 9 column-address bits latched by the column address strobe (cas). 18 cmaddr(17:0) output address bus to control memory. when 1mx16 dram modules are used:12 row- address bits latched by the row address strobe (ras). 8 column-address bits latched by the col- umn address strobe (cas). when 256kx16 dram modules are used: 9 row-address bits latched by the row address strobe (ras). 9 column-address bits latched by the column address strobe (cas). 36 pmdata(35:0) input/output data signals to and from the packet memory. 3 pmdata2(38:36) input/output data signals to and from the packet memory. 36 cmdata(35:0) input/output data signals to and from the control memory. 3 cmdata2(38:36) input/output data signals to and from the control memory. IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 dram memory bus interface page 23 of 553 memory i/o cross reference by device type IBM2520L8767 i/o edo dram sync dram 2-bank device sync dram 4-bank device sram xxaddr(17:13) address(17:13) address(16:12) address(15:11) address(17:13) xxaddr(12) address(12) address(11) bank select 1 address(12) xxaddr(11) address(11) bank select 0 bank select 0 address(11) xxaddr(10:0) address(10:0) address(10:0) address(10:0) address(10:0) xxras (1:0) ras(1:0) chip select(1:0) chip select(1:0) chip select(1:0) xxcas (1:0) cas(1:0) dqm(1:0) dqm(1:0) chip select(3:2) xxcs (6:4) n/a n/a n/a chip select(6:4) xxcs (7) n/a cke cke chip select(7) xxwe (1:0) we(1:0)* we(1:0)* we(1:0)* we(1:0)* xxsynras n/a ras ras n/a xxsyncas n/a cas cas byte enable(3) xxdata(31:0) data(31:0) data(31:0) data(31:0) data(31:0) xxdata(35:32) ecc(3:0) ecc(3:0) ecc(3:0) parity(3:0) xxdata2(38:36) ecc(6:4) ecc(6:4) ecc(6:4) byte enable(2:0) notes: xx = cm for control memory or pm for packet memory. all signal groups marked by an asterisk are active at the same time. for sdrams with shared ecc configurations, the dqm signals are active independently. for sdrams with split ecc, the dqms are usually active unless doing burst length 2 and the dqm is needed to terminate a burst. IBM2520L8767 ibm processor for atm resources dram memory bus interface page 24 of 553 atmrm.chapt02.01 08/27/99 possible memory configurations using dram with shared ecc module size 1 array 2 arrays storage size ecc size number of devices storage size ecc size number of devices 256kx16 1mb 1mb 3 2mb 512kb 5 1mx16 4mb 4mb 3 8mb 2mb 5 2mx8 (16mb) 8mb 8mb 5 16mb 4mb 10 4mx4 (16mb) 16mb 16mb 10 32mb 8mb 20 4mx16 (64mb) 16mb 16mb 3 32mb 8mb 5 8mx8 (64mb) 32mb 32mb 5 64mb 16mb 10 16mx4 (64mb) 64mb 64mb 10 128mb 32mb 20 possible memory configurations using sram module size number of devices for 1mb number of devices for 2mb number of devices for 4mb number of devices for 8mb notes 256kx18 2 4 8 16 128kx36 2 4 8 n/a (see note below) 2 1. for x18 sram modules, half the data bus goes to one module, and the other half goes to a second module. the chip select to the two modules is common. therefore, one chip select is needed per mb of memory. 2. 2. with x36 modules, a chip select is required for each module (0.5mb of memory). with eight chip selects available, the maxi- mum memory allowed is 8mb for x18 modules and 4mb for x36 modules. IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 npbus page 25 of 553 npbus the npbus consists of an eight-bit multiplexed addr/data bus plus generic transfer control signals to work with the phy level hardware microprocessor interface. npbus connections pbphy1 pbphy2 /pbdatap/mpmdsel/pidselo pbeprm pbale1 pbale2 pbaddr16/pbale3 pbaddr17/msgnt pbsclk pbsdata pbrnwrt pbrdrdy pbdata(7-0)/mled(3-0) pbintra pbphyrst IBM2520L8767 npbus signals 8 IBM2520L8767 ibm processor for atm resources npbus page 26 of 553 atmrm.chapt02.01 08/27/99 npbus pin descriptions (page1of2) quantity pin name input/output pin function pin description 1 pbphy1 output select phy 1 when low, indicates that IBM2520L8767 has selected phy 1 to write to control registers inside phy 1 or to read either the control or status registers. 1 pbphy2 output select phy 2 when low, indicates that IBM2520L8767 has selected phy2 to write to control registers inside ph 2 or to read either the control or status registers. see npbus control register for more details. if configured, this pin can also be: odd parity across the eight-bit wide bidirectional data bus. this pin can also be configured as mpmdsel - this control pin, under regis- ter bit control, can drive a logical value out. the intention is to select between the different pmd types on the 155 mb/s copper card (utp verses stp). if it is in cascade mode, this bit functions as pidselo (+idsel out), which the primary IBM2520L8767 will drive to the secondary IBM2520L8767 when trying to update con- figuration space via configuration cycles. this multiplexec pin also carries the pbdatap signal. 32 enstate (63-32) output when programmed, drives out the real-time state of entity state machines, counters, etc. for debug purposes. the lower 16 bits of this bus are also pbaddr(15 - 0), which are the address lines for the external parallel eprom. 1 pbeprm output eprom select when low, indicates that IBM2520L8767 has selected the exter- nal eprom to read from. after reset, IBM2520L8767 will start accessing the optional on-card rom/eprom and do the chip ini- tialization function if it does not find a serial eprom attached. 1 pbale1 output address latch enable 1 when high, indicates that IBM2520L8767 has generated an address on the pbdata bus and should be latched by either a phy that supports this muxing or an external octal latch ttl part. for an external eprom, it will also latch bits 7-0 of the address for an external eprom access. 1 pbale2 output address latch enable 2 when high, indicates that IBM2520L8767 has generated an address on the pbdata bus and should be latched by an external octal latch ttl part that holds bits 15-8 of the address for an exter- nal eprom access. 1 pbaddr16 output address send 16 supplies address 16 to an external eprom. the pin will also func- tion as pbale3, an address latch enable, that indicates that the IBM2520L8767 has generated an address on the pbdata bus and should be latched by an external octal latch ttl part that holds bits 23-16 of the address for an external eprom access. the mechanism used to set this mode is to put a pull-down resistor on this pin. at reset time, it will be detected and set this bit in pbale3 mode. otherwise it will be in pbaddr16 mode. 1 pbaddr17 output address send 17 supplies address 17 to an external eprom. if it is in cascade mode, this bit functions as msgntgo (secondary grant gate out) that the primary IBM2520L8767 will drive to allow a bus grant to the secondary IBM2520L8767 . see pcint cascade control register for more details. 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin low must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner that one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be pro- vided by the central resource. IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 npbus page 27 of 553 1 pbsclk output clock for the i 2 cserial eprom accesses. 1 pbsdata output or data this is the data bit that connects to the external serial eprom to read from or write to. it must have a pullup resistor attached and supports the i 2 c protocol. the range of suported serial eprom is from 256 to 2k bytes. after reset, the IBM2520L8767 will start accessing the optional on-card serial eprom and do the chip ini- tialization function. if this chip is pulled down (or no pullup), the IBM2520L8767 will assume that no serial eprom is attacted and will go try to fetch from a parallel eprom. 1 pbrnwrt output read or write this pin allows the IBM2520L8767 to read from or write to internal registers of the phy parts. this signal acts as the write strobe when talking to pmc-sierra chips such as the suni-lite . 1 pbrdrdy s/t/s 1 this pin allows the IBM2520L8767 to read from or write into inter- nal registers of the phys by acting as a data acknowledge signal from the memory slaves. 8 pbdata(7-0) input or output the pb-bus is an eight-bit wide bidirectional data bus used to inter- face the phys to the IBM2520L8767 when a data transfer is not happening, the lower four bits act as: mled(3-0) - four control pins that, under register bit control, can drive general status to led devices. 1 pbintra input this input from phy a is an attention line that, when low, indi- cates that one or more unmasked flags are set in the status regis- ters of phy 1 if additional phy parts are added, they should also dot their inter- rupt line onto this input. 1 pbphyrst output implements the network safety features of the device this signal is the ored value of reset and all of the status bits that cause the IBM2520L8767 to stop transferring data. it is asserted for a pulse, and then removed. this signal is asserted low. npbus pin descriptions (page2of2) quantity pin name input/output pin function pin description 1. s/t/s = a sustained tri-state pin owned and driven by one and only one agent at a time. the agent that drives the s/t/s pin low must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner that one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be pro- vided by the central resource. IBM2520L8767 ibm processor for atm resources atm phy bus interface page 28 of 553 atmrm.chapt02.01 08/27/99 atm phy bus interface the phy bus consists of a transmit data path, receive data paths, and control signals. atm phy bus interface connections 16 fytdat(15 downto 0) fytpar(1 downto 0) fytwrb fytsoc fyrrdb fyrenb fytenb fyful fydiscrd fysetclp fydtct fyrdat(15 downto 0) fyrpar(1 downto 0) fyrca fytca fyrsoc fyemp IBM2520L8767 npbus signals 2 16 2 16 IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 atm phy bus interface page 29 of 553 : phy bus pin descriptions (page 1 of 2) quantity pin name input/output pin function pin description 16 fytdat (15 - 0) output phy transmit data. when using an external phy, this 16 pin bus carries the atm cell octets that are loaded in the phy transmit fifo. when using the internal framer, the lower eight bits carry the sonet/ sdh octets bound for the network, while bits 15, 14, and 13 are used for the rx hdlc interface signals ofprxr1data, ofprxr1ds and ofprxrclk, respectively. 2 fytpar (1 - 0) output transmit data parity. when using an external phy, these are byte parity signals for fytdat. when using the internal framer, bit one provides the rx out-of-frame indication, oof, and bit 0 provides the opti- cal/electrical module transmit shutdown control signal, ofptx- sdown. 1 fytsoc output transmit start of cell. when using an external phy, this indicates the start of cell on fytdat. when using the internal framer, this provides the tx hdlc interface signal, ofptxt1dclk. 1 fytwrb output transmit write strobe. whenusinganexternalphy,thissignalisusedtowriteatm cells to the transmit fifo. when using the internal framer, this signal provides the 19.44 mhz tx clock, refclkt. 1 fytenb output transmit write enable. when using an external phy, this indicates that transmit data to the phy is valid. when using the internal framer, this pro- vides the tx hdlc interface signal, ofptxt1ds. when inter- facing to the IBM2520L8767, it should be connected to -tdval. 1fyrenb output receive write enable. when using an external phy, this indicates to the phy that the IBM2520L8767 is ready to accept data. when using the internal framer, this provides the clock recovery reset signal, rstcrec1. when using the ibm atm-tc phy, this should be connected to +rload. 1 fyrrdb output receive ready strobe. whenusinganexternalphy,thisisusedtoreadatmcells from the phy receive fifo. when using the internal framer, this signal provides the 19.44 mhz rx clock, rxbyclk. when using the ibm atm-tc (25 mb/s), this should be connected to rbclk. 16 fyrdat(15 - 0) input phy receive data . when using an external phy, this 16 pin bus carries the atm cell octets that are read from the phy receive fifo. when using the internal framer, the lower eight bits carry the sonet/ sdh octets received from the network. 2 fyrpar(1 - 0) input phy receive data parity. when using an external phy, these are byte parity signals for fyrdat. when using the internal framer, bit 1 provides the optical/electrical module low power indication signal, ofptx- lpow, and bit 0 is not used. 1 fyrsoc input receive start of cell. when using an external phy, this signal indicates the start of cell on the fyrdat bus. when using the ibm atm-tc phy, thisinputshouldbepulleddowntotheinactivestate.when using the internal framer, this is the receive frame pulse input signal, fpulse. indicates when a cell is available in the receive fifo. when using the internal framer, this signal is not used. when using ibm atm-tc, it should be connected to +rdval. IBM2520L8767 ibm processor for atm resources atm phy bus interface page 30 of 553 atmrm.chapt02.01 08/27/99 note: because some of the phy transmit i/os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. if the transmit path is using an external phy and the receive path is using the internal framer, fytpar(1) will assume the oof function and not be available as a parity output. this is only a concern if the phy uses a 16-bit data interface and parity is being used. 2. if the receive path is using an external phy and the transmit path is using the internal framer, fyrpar(1) will assume the ofptxlpow function and not be available as a parity input. this is only a concern if the phy uses a 16-bit data interface. 3. if the transmit path is using an external phy and the receive path is using the internal framer and the external phy has a 16-bit data interface, then the receive hdlc interface cannot be used. the three i/o for the rx hdlc interface will instead take on the function of fytdat(15-13). 1 fytca input transmit cell available. when using an external phy, this indicates that a cell is avail- able in the phy transmit fifo. when using the internal framer, this provides the tx hdlc interface signal, ofptxt1data. when interfacing to ibm atm-tc, it should be connected to +tload. 1fyful input phy transmit full. when using an external phy, this is asserted low by the phy when it can accept no more than four more data transfers before it is full. this pin should be pulled up to the inactive state when using a phy that does not drive it. when using the inter- nal framer, this provides the tx hdlc interface signal, ofptxt1dfrm. 1fyemp input phy receive empty. when using an external phy, this is asserted low by the phy to indicate that in the current cycle there is no valid data for delivery to the IBM2520L8767. when the phy does not drive fy0emp, this input should be tied to the inactive state. when using the internal framer, this signal is not used. 1 fytsdatp/n input serdes transmit data (differential). when using the internal framr and the internal serdes, these signals provide the serial transmit data stream. 1fytsclkp/ninput serdes transmit clock (differential). when using the internal framr and the internal serdes, the ref- erence 155.52mhz clock is supplied on these signals. when notinuse,theseshouldbetiedto(tbd). 1 fyrsdatp/n input serdes receive data (differential). when using the internal framr and the internal serdes, the recovered receive data is supplied on these signals. when not in use, these should be tied to (tbd). 1 fyrsclkp/n input serdes receive clock (differential). when using the internal framr and the internal serdes, the recovered 155.52mhz clock is supplied on these signals. when not in use, these should be tied to (tbd). 1 fydtct input phy carrier detect. when using an external phy, the phy uses this signal to indi- cate carrier detect. when using the internal framer, this signal provides the deserializer lock detect signal, elockdet, from the deserializer. 1 fydiscrd input phy cell discard. when using an external phy, this signal causes the current cellbeingreceivedtobediscarded.inthiscaseitshouldonly be asserted for the duration of one of the 53 bytes of the atm cell. when using the internal framer, this signal provides the optical/electrical module loss-of-signal indication, losssig. 1 fysetclp input phy clp bit set when high, causes the current cell being received to have its clp bit set to 1. this signal should only be asserted for the duration of one of the 48 data bytes of the atm cell. phy bus pin descriptions (page 2 of 2) quantity pin name input/output pin function pin description IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 atm phy bus interface page 31 of 553 transmit phy i/o cross reference IBM2520L8767 i/o suni-lite utopia atm-tc internal framer fytwrb tfclk txclk n/a refclkt fytca tca txclav tload ofptxt1data fyful n/a txfull n/a ofptxt1dfrm fytenb twrenb txenb tdval ofptxt1ds fytsoc tsoc txsoc n/a ofptxt1dclk fytdat(15) n/a txdata(15) n/a ofprxr1data fytdat(14) n/a txdata(14) n/a ofprxr1ds fytdat(13) n/a txdata(13) n/a ofprxr1dclk fytdat(12-8) n/a txdata(12-8) n/a n/a fytdat(7-0) tdat(7-0) txdata(7-0) tdata(7-0) txextdat(7-0) fytpar(1) n/a txprty(1) n/a oof fytpar(0) n/a txprty(0) tdprty ofptxsdown signalsmarkedwithanoverbarareactivelow. inputs listed as n/a should be tied to their inactive utopia state. receive phy i/o cross reference IBM2520L8767 i/o suni-lite utopia atm-tc internal framer fyrrdb rfclk rxclk rbclk rxbyclk fyrca rca rxclav rdval n/a fyemp n/a rxempty n/a n/a fyrenb rrdenb rxenb rload rstcrec1 fyrsoc rsoc rxsoc n/a fpulse fyrdat(15-8) n/a rxdata(15-8) n/a n/a fyrdat(7-0) rdat(7-0) rxdata(7-0) rdata(7-0) rxextdat(7-0) fyrpar(1) n/a rxprty(1) n/a ofptxlpow fyrpar(0) n/a rxprty(0) rdprty n/a signalsmarkedwithanoverbarareactivelow. inputs listed as n/a should be tied to their inactive utopia state. IBM2520L8767 ibm processor for atm resources atm phy bus interface page 32 of 553 atmrm.chapt02.01 08/27/99 clock, configuration, and lssd connections mpcirst pciclk txclk rxclk mpegclk testm testct tmmcore mbypass pffcfg(2:0) pffosc pllti pvdda nselt jtagrst jtagtck jtagtms jtagtmsc jtagdi jtagdo jtagdoc pintclk pabisto ppllout bistodi mforcebp enstate(63-32)/pbaddr(15-0) ibdinh1 ibdinh2 ibdrinh 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 p dtr cts txd rxd rts dsr jtagrstc jtagtckc jtagtdic mhalt401 leaktst 1 1 1 1 normal value 16 IBM2520L8767 npbus signals IBM2520L8767 ibm processor for atm resources atmrm.chapt02.01 08/27/99 atm phy bus interface page 33 of 553 clock, configuration, and lssd pin descriptions (page1of2) quantity pin name input/output pin description 1mpcirst input this signal will cause a hardware reset when asserted low. see entity 20: reset and power-on logic (crset) on page 383 for more details on resets. 1 pciclk input the pciclk is a 40-50% duty cycle 30-ns clock. 1 txclk input this is the linkc asynchronous transmit clock. 1 rxclk input this is the linkc asynchronous receive clock. 1 mpegclk input this is the mpeg asynchronous clock. 1 testm input when the test mode pin is not asserted, this chip will run as specified. when the test mode pin is asserted, the chip is in lssd test mode. transparent latches become clocked latches and i/os change to primary test inputs and test out- puts. this signal is asserted low and should be tied to a ?1?b for normal opera- tion. 1testct input when the test clock tree pin is not asserted, this chip will run as specified. when the testclock tree pin is asserted, the clock tree will use this input to control the clock tree outputs. this signal is asserted low and should be tied to a ?1?b for normal operation. 1 tmmcore input test mode matrix for the 401 core. this signal is asserted low and should be tied to a ?1?b for normal operation. 1 jtagtdic input this is the tdi to the 401 jtag tap controller. 1 mhalt401 input used by riscwatch to halt the 401 core for debug purposes. 1 mbypass input when tied to ?0?b on the card, the pll function will not multiply the chip input (pci clock). instead, it will just pass the clock input frequency to the internal clock tree. normal mode for this pin is ?1?b. a 1-k pullup must be used. 3pffcfg(2-0) input these bits control the "find frequency" function which sets the range bits of the pll. below is the encoded meaning of these bits. table, but some examples are provided here. - 000 = force to 66mhz operation: set range to 11 and adjust rom fetch speed - 001 = disable auto range function: set range to 01 (<16mhz bypass mode) - 010 = disable auto range function: set range to 10 (16-31.5mhz) - 011 = disable auto range function: set range to 11 (31.5-66mhz) - 100 = enable auto range function for 19.44mhz - 101 = reserved - 110 = enable auto range function for 25.00mhz - 111 = enable auto range function for 32.00mhz 1pffosc input this input is the auto range known frequency input that is used to time the pci clock input. this should be connected to some oscillator on the the card. a typi- calexamplewouldbethephyoscillator. 1pllti input when tied to ?1?b, this input will cause the pll to do a parametric testing at the wafer and module level. normal mode for this pin is a ?0?b. 1 pvdda input filtered vdd source to the pll logic. see technology application notes for filter circuit. 1 nselft input minus active selftest input. normal mode is a ?1?b. 1jtagrst input jtag test reset provides an asynchronous initialization of the tap controller. 1jtagtck input jtag test clock is used to clock state information and test data into and out of the device during operation of the tap. IBM2520L8767 ibm processor for atm resources atm phy bus interface page 34 of 553 atmrm.chapt02.01 08/27/99 1jtagtms input jtag test mode select is used to control the state of the tap controller in the device. 1 jtagtmsc input jtag test mode select is used to control the state of the tap controller in the 401 core. 1jtagtdi input jtag test data input is used to serially shift test data and test instructions into the device during tap operation. 1 jtagtdo output test data output is used to serially shift test data and test instructions out of the device during tap operation. 1jtagtdoc output test data output - core is used to serially shift test data and test instructions during processor core tap operations. 1pintclk output this is the external test point to measure the jitter effects of the phase-lock loop circuit. 1 pdblclk output this is the external test point that is double the frequency of the pintclk. it is used to clock enstate state signals at this frequency. 1 ppllout output this is an observation output only. this will make the output of the pll observ- able. this is also the dtr signal when the selrs232 is active. 1 bistdi1 output drives the di input during bist 1 mforcebp output allows IBM2520L8767 to bypass the internal pll. see printed circuit board considerations on page 515. 1 dtr input or output rs232 dtr for the core debugger. 1 cts input or output rs232 cts for the core debugger. 1 txd input or output rs232 txd for the core debugger. 1 rxd input or output rs232 rxd for the core debugger. 1 rts input or output rs232 rts for the core debugger. 1 dsr input or output rs232 dsr for the core debugger. 1jtagrstc input or output jtag test reset provides an asynchronous initialization of the processor core tap controller. 1 jtagtckc input or output jtag test clock is used to clock state information and test data into and out of the device during operation of the processor core tap controller. latchtclkc in test mode. 1 ibdinh1 input this is the boundary scan input for bsinh1. 1 ibdinh2 input this is the boundary scan input for bsinh2(*). 1 ibdrinh input this is the boundary scan input for rinh. 1 leaktst input this is the sti driver/receiver leak test input. clock, configuration, and lssd pin descriptions (page2of2) quantity pin name input/output pin description IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 35 of 553 data structures these structures reside in control memory for each of the logical channels that are set up for transmission or reception. packet header each packet buffer consists of two parts. the first part is the control information used by the IBM2520L8767. the second portion of the packet buffer is used to hold the actual packet data. the following figures show the structure of the transmit and receive packet headers: the minimum transmit packet header size (and transmit offset) is 0xc bytes. transmit packet header structure struct tx_min_packhead { struct tx_packhead { bit32 next_buffer; bit32 next_buffer; bit8 aal5_user_byte1; bit8 aal5_user_byte; bit8 buffer_offset; bit8 buffer_offset; bit16 buffer_length; bit16 buffer_length; bit25 lc_address; bit25 lc_address; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 dma_on_xmit; bit1 dma_on_xmit; bit1 generate_crc10; bit1 generate_crc10; bit1 free_on_xmit; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 queue_on_xmit; bit1 cell_loss_priority; bit1 cell_loss_priority; }; bit32 dma_desc_addr; bit24 reserved; bit8 aal5_user_byte2; }; IBM2520L8767 ibm processor for atm resources packet header page 36 of 553 atmrm.chapt03.01 08/27/99 receive packet header structure struct rx_packhead { struct rx_packhead { bit16 rx_label; bit16 rx_label; bit4 reserved; bit4 reserved; bit1 toobig_status; bit1 toobig_status; bit1 memchk_status; bit1 memchk_status; bit1 fabort_status; bit1 fabort_status; bit1 badlen_status; bit1 badlen_status; bit1 badcpi_status; bit1 badcpi_status; bit1 badcrc_status; bit1 badcrc_status; bit1 timout_status; bit1 timout_status; bit1 fifopk_status; bit1 fifopk_status; bit1 congestion_status; bit1 congestion_status; bit1 route_status; bit1 route_status; bit1 error_status; bit1 error_status; bit1 done_status; bit1 done_status; bit8 aal5_user_byte; bit8 aal5_user_byte; bit8 buffer_offset; bit8 buffer_offset; bit16 buffer_length; bit16 buffer_length; bit25 lc_address; bit25 lc_address; bit6 reserved; bit6 reserved; bit1 cell_loss_priority; bit1 cell_loss_priority; bit32 rx_atm_header; bit32 rx_atm_header; bit32 host_data; bit24 host_data; bit8 aal5_user_byte2; bit32 cut_thru_addr; bit32 cut_thru_addr; }; }; transmit and receive packet header field descriptions (page1of2) field name field description next_buffer this field is used by the hardware to chain buffers together on queues. it contains the address of the next buffer if one exists. for transmit buffers allocated in virtual memory, this field will be written by the hardware with a dis- tinctive pattern (?zzzzzbad?x) where zzzzz is the offset of the failure when a write operation was not able to complete due to a shortage of the real buffers needed to map into the virtual address space. this field can be checked after all buffer write operations and the appropriate recovery actions taken immediatly, or when a buffer that has had a write failure is enqueued to csked, an event will be generated and the buffer will not be processed by csked. a status bit also exists in the bcach status register indicating that a write to virtual memory has failed. with cache performance in mind, this status bit could be checked first, and if it is not set, there is no need to access the header of the packet. note: this automatic error recovery mechanism results in the restriction that this first four bytes of a transmit packet must never be written via programmed io or dma during preparation for transmission. if this field is writ- ten by a software or dma operation, the automatic error detection will not work properly and undesirable results are likely. aal5_user_byte1 this field contains the value to be sent in the user byte in the last cell of an aal5 packet if intst is configured for one user byte. dma_on_xmit if this bit is set, a dma descriptor address placed in the packet header (offset ?c?x) will be queued for execution. generate_crc10 if this bit is set, crc10 will be generated over the cell(s) in this packet. free_on_xmit if this bit is set, the buffer will be freed after the transmission completes. queue_on_xmit if this bit is set, the buffer will be queued on the transmit complete queue after the transmission completes. IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 37 of 553 cell_loss_priority this bit is used on both transmit and receive: txiif this bit is set, the cell loss priority bit in the atm cell header will be set for each cell in this packet rxthis bit contains theor?d cell loss priority bits across all the cells that comprised this packet if this lcd is using aal5. buffer_offset this field contains the offset into the buffer where the data starts. buffer_length this field contains the length of the packet. lc_address this is the address of the logical connection descriptor that this packet was received on. rx_atm_header on reception, the four-byte atm header (no hec) is copied from the first and last cell into this area. aal5_user_byte2 (tx) this field contains the value to be sent in the user bytes in the last cell of an aal5 packet if intst is configured fortwo-userbyte. aal5_user_byte2 (rx) this field contains the second aal5 user byte in the last cell of an aal5 packet if intst is configured for two-user byte. bit16 rx_label this field is written with "ra" in ascii (0x5241) to signal that this buffer was used by raall. bit4 reserved this field is always zero bit1 routed_status this bit is set if this packet or cell was internally routed. bit1 toobig_status indicates the current packet exceeded the maximum packet size. bit1 memchk_status indicates the current packet had a memory check (real size exceeded or virtual error). bit1 fabort_status indicates the current packet was aborted (aal5 forward abort). bit1 badlen_status indicates the current packet had a bad aal5 length in the trailer. bit1 badcpi_status indicates the current packet had a bad aal5 cpi field (not zero). bit1 badcrc_status indicates the current packet had a bad aal5 crc. bit1 timout_status indicates the current packet had a reassembly timeout error. bit1 fifopk_status indicates the current packet is a fifo packet (see mpeg fifo mode). bit1 congestion_status this bit is written when the packet is completed. it contains the or?d congestion bit across an aal5 packet. bit1 route_status this bit is written when the packet is completed if it is internally routed. bit1 error_status this bit is written when the packet is completed if an error condition occurs. bit1 done_status this bit is written when the packet is completed. it can be used when thresholding. host_data if host data is enabled in raall, then the 32/24 bits of host data is read from the lcd and written to this area for each packet. the size is based on how many user bytes are used. cut_thru_addr this field is only used in one of the cut-through modes and has two purposes. when the packet is first received, the packet address is written to this field. this information can then be used by software to do a further cut-through operation or free the packet. when a cut-through operation is performed, and the packet is not com- plete yet, the descriptor address is placed in this field . when in scatter mode, the low-order bits specify how many pages are in the dma list that follows the packet header. dma_desc_addr if the dma_on_xmit bit is set in the packet header, this field contains the address of the dma descriptor that will be queued when transmission is complete. transmit and receive packet header field descriptions (page2of2) field name field description IBM2520L8767 ibm processor for atm resources packet header page 38 of 553 atmrm.chapt03.01 08/27/99 logical channel data structure transmit portion receive portion user data offset 0x00 0x50 0x78 csked scheduling information (3) 64-bit words csked/segbf shared information (2) 64-bit words segbf segmentation (0-3) 64-bit words 128-byte lcd if lcd-based memory management is used, a 64-bit section with the following layout is inserted at byte offset 18x: threshold threshold pool id1 bytes waiting to be transmitted 12 pool id1 four different formats, determined by whether scheduling is based on virtual path parameters or is configured for abr. see scheduling portion of a transmit descriptor on page 68. tx length misc. flags atm header 16 16 4 4 24 16 16 32 total user cells total user cells 32 32 segmentation pointer partial crc 16 32 oam data fixed blocking data 32 32 oam data fixed blocking data 32 32 mpeg-2 or abr data 32 32 unused abr 56 8 with clp=0 lcd cell status total user cells total user cells 32 32 with clp=0 lcd cell status total user cells total user cells 32 32 with clp=0 lcd cell status oam data fixed blocking data 32 32 abr code variables 64 variables on abr connections, the abr code running in pcore uses 10 bytes of the lcd starting at offset 0x46 for managing the connection. for aal type 0x7 for aal types 0x4 and 0x6 for all other aal types abr code portion information IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 39 of 553 transmit descriptor data structures logical channel data structure on page 38 and scheduling portion of a transmit descriptor on page 40 show the layout of the transmit portion of a logical channel descriptor. when initializing an lcd, any loca- tions that are not written to a specific value should be initialized to zeroes. fields that typically need to be ini- tialized to a non-zero value are flagged with a # in the structure below. note: this is only one possible layout of the transmit portion of the lcd. some field locations vary and are further defined later in this section. care must be taken when updating fields in the lcd and then immediatly causing the updated fields to be accessed by other IBM2520L8767 entities. for example, it is possible, although not likely, under the right conditions, for a normal lcd update followed by a segbf cell enqueue operation to actually execute in reverse order. this is due to IBM2520L8767 internal priority levels and could result in segbf fetching the lcd data before it has been updated to the new value. for this reason, it is highly advisable to use the lcd update mechanism in raall ( raall lcd update data registers on page 295, raall lcd update mask registers on page 295, and raall lcd update op register on page 296) to guarantee that any lcd update operation completes before any subsequent ops can execute. the transmit portion of the lcd can be subdivided into three distinct parts based on which chip functions or entities access that particular part of the lcd. the first three 64-bit words are scheduling related and are accessed only by csked. the next two 64-bit words are related to both scheduling and segmentation and are accessed and shared by both csked and segbf. the words following these shared locations are related only to segmentation and are accessed only by segbf. the number of 64-bit words in this portion of the lcd can vary from zero to three. the actual number being used in an lcd is determined by the aal type bits. the three 64-bit words containing csked scheduling information can have four different formats depending upon whether scheduling is based on virtual path parameters or is configured for abr. these four formats are shown in scheduling portion of a transmit descriptor on page 40: IBM2520L8767 ibm processor for atm resources packet header page 40 of 553 atmrm.chapt03.01 08/27/99 scheduling portion of a transmit descriptor 32 time stamp timing data 32 32 32 32 32 virtual path descriptor reserved 32 32 32 32 next descriptor in chain 32 16 time stamp timing data 32 32 transmit packet 32 32 32 abr values and timing data 64 32 32 next descriptor in chain next descriptor in chain next descriptor in chain peak interval average interval 16 16 peak interval average interval 16 16 peak interval average interval 16 16 peak interval abr parameters 16 queue head pointer transmit packet queue tail pointer for a standard virtual circuit using abr for a virtual circuit on a virtual path for a virtual path transmit packet queue head pointer transmit packet queue tail pointer transmit packet queue head pointer tr a n s m i t p a ck e t queue tail pointer transmit lcd queueheadpointer tra ns m it lc d queue tail pointer address csked scheduling information (3) 64-bit words IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 41 of 553 transmit logical channel descriptor structure . typedef struct { bit32 next_lcd; bit16 #peak_interval; bit16 #average_interval; bit32 #timestamp; bit11 reserved; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit1 #max_resolution; bit3 #max_burst_mult; bit10 #max_burst_value; bit26 head_packet_pointer; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 dma_on_xmit; bit3 reserved; bit26 tail_packet_pointer; bit6 reserved; bit16 transmit_length; bit8 buffer_offset; bit1 #enable_blocking; bit1 #enable_statistics; bit1 flush_lcd; bit1 #generate_crc10; bit1 #oam_clp_source bit3 #aal_type; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit32 total_user_cells; bit32 total_user_cells_clp0; bit16 bip-16; bit8 monitor_sequence_number; bit1 oam_cell_transmitted bit2 previous_pcr_bits17_16 bit1 #oam_pti_bit0; bit1 previous_packet_contained_pcr bit1 #oam_clp_value; bit2 #oam_block_size; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr IBM2520L8767 ibm processor for atm resources packet header page 42 of 553 atmrm.chapt03.01 08/27/99 owing to the use of certain lcd fields, a connection running abr can not be set up for segmentation aal types 0x6 (fixed-sized blocking) or 0x7 (mpeg-2 assist) redefinition of shared and segmentation portion of transmit lcd for abr typedef struct { bit16 transmit_length; bit8 buffer_offset; bit1 #enable_blocking; bit1 #enable_statistics; bit1 flush_lcd; bit1 #generate_crc10; bit1 #oam clp source bit3 #aal_type; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit16 explicit_rate; bit16 current_rate; bit16 minimum_rate; bit16 reserved; bit16 bip-16; bit8 monitor_sequence_number; bit1 oam_cell_transmitted bit2 reserved bit1 #oam_pti_bit0; bit1 reserved bit1 #oam_clp_value; bit2 #oam_block_size; bit32 backward_ptr; bit32 total_user_cells; bit32 total_user_cells_clp0; } tx_lcd_struct, *tx_lcd_struct_ptr; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 43 of 553 redefinition of segmentation portion of transmit lcd for fixed size aal5 blocking (segmentation type 0x6) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit1 #enable_blocking; bit1 #enable_statistics; bit1 flush_lcd; bit1 #generate_crc10; bit1 #oam clp source bit3 #aal_type; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit16 bip-16; bit8 monitor_sequence_number; bit1 oam_cell_transmitted bit2 previous_pcr_bits17_16 bit1 #oam_pti_bit0; bit1 previous_packet_contained_pcr bit1 #oam_clp_value; bit2 #oam_block_size; bit8 current_blocking_count (4 bytes) bit8 #blocking_size (4 bytes x2f for mpeg-2) bit1 pid_field_valid bit2 pid_bits_12_11 bit5 current_transport_stream_packet bit1 check_pcr bit1 pcr_present bit1 pid_matches bit5 #packets_per_aal5_frame bit32 total_user_cells; bit32 total_user_cells_clp0; } tx_lcd_struct, *tx_lcd_struct_ptr; IBM2520L8767 ibm processor for atm resources packet header page 44 of 553 atmrm.chapt03.01 08/27/99 redefinition of segmentation portion of transmit lcd for mpeg2 (segmentation type 0x7) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit1 #enable_blocking; bit1 #enable_statistics; bit1 flush_lcd; bit1 #generate_crc10; bit1 #oam clp source bit3 #aal_type; bit32 #atm_header; bit32 segmentation_pointer; bit32 current_crc; bit16 previous_pcr_bits15_0 bit11 pid_bits_10_0 bit1 pcr_delta_valid bit36 pcr_delta bit16 bip-16; bit8 monitor_sequence_number; bit1 oam_cell_transmitted bit2 previous_pcr_bits17_16 bit1 #oam_pti_bit0; bit1 previous_packet_contained_pcr bit1 #oam_clp_value; bit2 #oam_block_size; bit8 current_blocking_count (4 bytes) bit8 #blocking_size (4 bytes x2f for mpeg-2) bit1 pid_field_valid bit2 pid_bits_12_11 bit5 current_transport_stream_packet bit1 check_pcr bit1 pcr_present bit1 pid_matches bit5 #packets_per_aal5_frame bit32 total_user_cells; bit32 total_user_cells_clp0; } tx_lcd_struct, *tx_lcd_struct_ptr; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 45 of 553 redefinition of scheduling portion of transmit lcd for abr typedef struct { bit32 next_lcd; bit16 #peak_interval; bit3 #nrm; bit3 #trm; bit10 #tadtf; bit8 #nc; bit8 #ncrm; bit16 reserved; bit11 tlrm1; bit1 remove_lcd; bit1 lc_on_timewheel; bit3 #alter_sched; bit2 #transmit_priority; bit1 #max_resolution; bit13 tlrm2; bit26 head_packet_pointer; bit1 free_on_xmit; bit1 queue_on_xmit; bit4 reserved; bit26 tail_packet_pointer; bit6 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; redefinition of scheduling portion of transmit lcd for timers typedef struct { bit32 next_lcd; bit32 #timer_period; bit32 #timestamp; bit12 reserved; bit1 lc_on_timewheel; bit1 reserved; bit2 #timer_type; bit2 #transmit_priority; bit1 #max_resolution; bit13 reserved; bit32 #dma_desc_addr; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; definition of lcd-based memory management of transmit lcd typedef struct { bit16 #threshold_1; bit16 #threshold_2; bit4 #pool_id1; bit4 #pool_id2; bit24 #bytes_queued; } tx_lcd_struct, *tx_lcd_struct_ptr; IBM2520L8767 ibm processor for atm resources packet header page 46 of 553 atmrm.chapt03.01 08/27/99 field definitions the following is a detailed description of the fields listed above. this data structure should be initialized at connection setup but not modified while transmission is occurring on the connection. only those fields marked with a # typically need to be initialized to something other than zero. definition of abr code variables typedef struct { bit8 #crm; bit8 #icdf; bit16 #imcr; bit16 #pcr; bit8 #irdf; bit8 #irif; bit16 #icr; } tx_lcd_struct, *tx_lcd_struct_ptr; abr code variables definitions (page1of7) field name field description next_lcd this field is used by the hardware to chain lcds together on queues. it contains the address of the next lcd if one exists. peak_interval # this field contains the minimum spacing allowed between consecutive cells on this connection. this spacing is expressed in cell times. a connection that can transmit every cell time would have a value of 1 for this field. average_interval # this field contains the minimum average spacing allowed between cells transmitted on this connection. it is the inverse of the sustainable cell rate. the value for this field is expressed in cell times. nrm # this field specifies the maximum number of cells a source may send for each forward rm-cell. number of cells = (2**nrm)+1. trm # this field provides an upper bound on the time between forward rm-cells for an active source. time = 100 ? (2**-trm) msec. tadtf # the acr decrease time factor is the time permitted between sending rm-cells before the rate is decreased to icr. time = tadtf ? 0.01 sec. nc # this field is used as a counter to determine when nrm cells have been sent. it should be initialized at connection setup time to 0. ncrm # this field is used as a counter to determine when crm rm-cells have been sent. it should be initialized at connection setup time to crm. timestamp # this field contains a timestamp used by the hardware to determine if transmit opportunity credits exist and if the burst tolerance has been exceeded. it should be initialized at connection setup time to the value in the current timeslot counter. tlrm1 & 2 these fields are used by the hardware to determine when the last rm cell was sent. they should be initialized to 0. lc_on_timewheel # this field indicates if the lcd is currently queued to the timewheel. it should be initialized ot 0. remove_lcd # if this bit is set the lcd will be removed from the time wheel at next transmission opportunity. it should be initialized to 0. lc_on_timewheel # this field indicates if the lcd is currently queued to the timewheel. it should be initialized to 0. IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 47 of 553 alter_sched # these encoding bits will alter the scheduling of cells on a virtual circuit (vc) 000 = normal scheduling scheduling is not altered. 001 = vc on vp this vc is contained on a virtual path and will share the vp band- width after one packet is sent. the scheduling parameters are con- tained in the descriptor for the virtual path that is pointed to by the virtual path discriptor address field in this lcd. 010 = mpeg-2 scheduling the cells being sent out on this connection are monitored for a peak cell rate (pcr). if a pcr is found, the aal5 packet is terminated at the end of the mpeg-2 frame and the last cell is scheduled to go out at the time specified in the pcr. 011 = packet-based scheduling packets will be scheduled at the average interval and cells within the packet will be scheduled at the peak interval. this is useful for send- ing information where variably-sized packets need to be sent at regu- lar intervals. 100 = abr scheduling this vc will send resource management cells and adjust its transmi- sin rate according to the behaviors specified in the atm forum traffic management specification, version 4.0. 101 = fair vc on vp this vc is contained on a virtual path and will share the vp band- width after one cell is sent. the scheduling parameters are contained in the descriptor for the virtual path which is pointed to by the virtual path descriptor address field in this lcd. 110 = reserved for mpeg-2 scheduling. 111 = reserved transmit_priority # this field specifies the priority of transmission on this connection. 0=high, 1=medium, 2=low. max_resolution # if this bit is set, the lower eight bits of the average interval and peak interval parameters contain a frac- tional component. this allows a finer resolution for scheduling. for example, for a peak interval of 1.5 time units, the value written to the peak_interval field should be hex 0180. if this bit is set, the initial value of timestamp should contain the current timeslot counter shifted 16 bits to the left. max_burst_mult # the values in this field and the next field are used to limit the number of cells that can be transferred at the peak rate. the max_burst_value will be multiplied by 4 to the power of the value in this field to yield the maximum credit time. this time is expressed in cell times and represents the time it would take to acquire the maximum number of cell credits. this maximum credit time should equal the maximum number of cells that can be transferred at the peak rate (mbs) times the difference between the aver- age and intervals. maximum credit time = mbs * (ai-pi) where mbs = maximum burst size, ai = aver- age interval, and pi = peak interval. mbs must be at least 1 to transmit at peak rate. if mbs is not at least 1 the peak interval should be set to the average interval. max_burst_value # the value in this field will be multiplied by 4 to the power of the value in the max_burst_mult field to yield the maximum credit time. head_packet_pointer this field is used to chain buffers to lcds. tail_packet_pointer this field is used to chain buffers to lcds. transmit_length this field contains the length of the currently transmitted packet. free_on_xmit this bit is set if the header of the currently transmitted packet has specified that the packet is to be freed after transmission. queue_on_xmit this bit is set if the header of the currently transmitted packet has specified that the packet is to be queued after transmission. dma_on_xmit this bit is set if the header of the currently transmitted packet has specified that a dma descriptor is to be queued after transmission. abr code variables definitions (page2of7) field name field description IBM2520L8767 ibm processor for atm resources packet header page 48 of 553 atmrm.chapt03.01 08/27/99 buffer_offset this field contains the offset into the buffer that the transmit data starts. enable_blocking # when set, this bit enables oam blocking cells to be sent on the associated vc by the segmentation logic. other fields in the lcd define the content and frequency of these frames. setting this bit also forces statistics to be kept for the associated lcd regardless of the state of the enable_statistics bit. this same function can be globally controlled in the segbf control register. enable_statistics # when set, this bit enables statistics keeping for the associated lcd. another eight bytes of the associ- ated lcd is used to maintain counts of the total number of user cells and the total number of user cells with clp=0 that have been sent over this vc. this same function can be globally controlled in the segbf control register. flush_lcd # when set, this bit causes the segmentation logic to flush all frames currently queued to the lcd without performing any segmentation on them. generate_crc10 # this bit is set if the header of the currently transmitted packet has specified that the cells in this packet should have crc-10 generated. when set, this bit overrides the other aal select bits in the lcd and forces the segmentation logic to generate a crc-10 terminated cell. in this mode, the segmentation logic fetches 52 bytes of data from memory. the hec is calculated over the first four bytes fetched, and appended following these four bytes. the next 48 bytes are used to calculate the crc-10 and the zero-padded two-byte result is appended after the 48 bytes of data. this function is intended to make it easier to send oam cells. oam_clp_source # when reset, the clp bit for all oam cells is retrieved from the atm header in the lcd. when set, the clp bit for all oam cells is retrieved from the oam_clp_value field in the lcd. this allows oam traf- fic to be sent with a different clp value than other traffic on the vc. abr code variables definitions (page3of7) field name field description IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 49 of 553 aal_type # this field specifies the aal type to be used with this connection. the following values are decoded by the hardware: ?0?x = raw 48-byte mode. when an lcd with this value is encountered, the segmentation logic assem- bles a cell from the four atm header bytes in the lcd, a calculated hec, and the 48 bytes pointed to by the transmit offset. ?1?x = raw 52-byte mode. when an lcd with this value is encountered, the segmentation logic assem- bles a cell from the four atm header bytes fetched using the transmit offset, a calculated hec, and the next 48 bytes following the atm header. ?2?x = raw 53-byte mode. when an lcd with this value is encountered, the segmentation logic assem- bles a cell directly from the 53 bytes pointed to by the transmit offset. ?3?x = reserved ?4?x = mpeg blocking with pcr termination. this mode is handled the same as fixed-size blocking mode with one additional feature. an mpeg transport stream packet that contains a pcr causes the current aal5 frame to be terminated even if the predefined number of packets has not been assembled into an aal5 frame. ?5?x = aal5 mode. when an lcd with this value is encountered, the segmentation logic assem- bles a cell in accordance with the aal5 specification. the four-byte atm header is retrieved from the lcd, then the hec is calculated and appended. the next 48 bytes of data are fetched from the current segmentation pointer and the crc-32 is calculated over all 48 bytes. if fewer than 48 bytes of data are available, the data is zero-padded to complete the cell. when all data in the buffer has been exhausted, the last cell will contain the aal5 trailer. the cpcs user to user field in the aal5 trailer depends on the state of the two bits defined in intst. ?6?x = fixed-size blocking. when an lcd with this value is encountered, the segmentation logic assem- bles a predefined number of packets of a predefined size into an aal5 packet. the number and size of the packets are defined in two other fields of the lcd. the length field of the lcd must be initialized with a value that is an integral multiple of the predefined size and the predefined number of packets. that is, if the predefined size is x?47? (188 bytes) and the pro- grammed number is 2, then the length must be initialized to n ? 188 ? 2, or 188, 376, 564 etc. ?7?x = mpeg blocking with pcr delay and termination. this mode is handled the same as mpeg blocking with termination but with one added feature. as well as terminating an aal5 frame, a transport stream packet that contains a pcr will be delayed by the segmentation logic until an internal time base indicates that the correct time has come for the packet to be delivered to the remote end. in this mode, the first pcr containing transport stream packet causes the segmentation logic to derive a pcr adjust value relative to an internal time- base. all pcr-containing packets processed in the future use this derived pcr adjust value to determine if the correct amount of time has passed indi- cating that the packet should be forwarded to it?s destination. if the correct amount of time has not passed, the last cell of the aal5 frame is delayed until the correct time. if the transport stream contains multiple pid values, a bit in the segbf control register can be used to globally enable only match- ing pid pcr recognition and delaying. atm_header # this field contains the first four bytes of the atm header. segmentation_pointer this field contains a pointer to the next data to be transmitted. in normal operation this field is initialized by the cell scheduler when a new frame is queued for segmentation. current_crc this field contains the crc as it is being built. bip-16 this 16-bit field contains the bit interleaved parity accumulated over the last block of data. after initial- ization, this field should only be accessed by the hardware. abr code variables definitions (page4of7) field name field description IBM2520L8767 ibm processor for atm resources packet header page 50 of 553 atmrm.chapt03.01 08/27/99 monitor_sequence_number this eight-bit field contains the monitor sequence number that is used to construct the hardware gen- erated oam cells. after initialization, this field should only be accessed by the hardware. oam_cell_transmitted this one-bit field contains a flag indicating that an oam cell has been sent. after initialization, this field should only be accessed by the hardware. previous_pcr_bits_17_16 this two-bit field contains bits 17 and 16 of the pcr in the most recently segmented mpeg transport stream packet. after initialization, this field should only be accessed by the hardware. oam_pti_bit0 # this one-bit field is copied directly to the low bit of the payload type field in the atm header as the seg- mentation logic is building an oam cell. previous packet contained pcr this one-bit field is used during mpeg processing by the hardware to indicate that a previous transport stream packet contained a pcr. after initialization, this field should only be accessed by the hardware. oam_clp_value # this one-bit field can be used to provide the value for the clp bit in the hardware generated oam cells. if the oam_clp_source bit elsewhere in the lcd is in the correct state, this bit will be copied directly to the clp bit in the atm header of the oam cell. oam_block_size # this two-bit field defines the number of user cells that are sent between oam cells. 00 = 128 cells 01 = 256 cells 10 = 512 cells 11 = 1024 cells current_blocking_count this eight-bit field contains the current count of four-byte values that have been assembled into cells and sent out on this lcd for all fix block or mpeg aal types. other than initialization, this field should only be accessed by the hardware. fixed_blocking_size # this eight-bit field should be initialized by the software to contain the number of four-byte values that constitute a packet. for mpeg2 this register should be set to x?47? (4 ? x?47? = 188 byte transport stream packet). pid_field_is_valid when set, this one-bit field indicates that the pid field in the lcd contains a valid pid. after initializa- tion, this field should only be accessed by the hardware. pid_bits_12_11 this two-bit field contains bits 12 and 11 of the previously saved pid. after initialization, this field should only be accessed by the hardware. current_transport_stream_pac ket this five-bit field contains the number of the current transport stream packet that is being segmented. after initialization, this field should only be accessed by the hardware. check_pcr this one-bit field is set when the segmentation hardware has determined that it is time to check and delay a cell if the pcr indicates. other than initialization, this field should only be accessed by the hardware. pcr_present this one-bit field is set by the hardware to indicate that the current transport stream packet contained a pcr. other than initialization, this field should only be accessed by the hardware. pid_matches this one-bit field is set by the hardware to indicate that the pid in the transport stream being seg- mented matches the pid which was previously locked on. packets_per_aal5_frame # this five-bit field should be initialized by the software to indicate how many packets should be concate- natedintoanaal5frame. previous_pcr_bits_15_0 this 16-bit field contains the least significant 16 bits of the last pcr that has been encountered. after initialization, this field should only be accessed by the hardware. pid_bits_10_0 this two-bit field contains bits 10 - 0 of the previously saved pid. after initialization, this field should only be accessed by the hardware. abr code variables definitions (page5of7) field name field description IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 51 of 553 pcr_delta_valid this one-bit field is set by the hardware to indicate that the 36-bit pcr delta field is valid. after initializa- tion, this field should only be accessed by the hardware. pcr_delta this 36-bit field is set by the hardware the first time a pcr-containing transport stream packet is encounteredbythesegmentationlogic.thehigh36bitsofthepcrinthepacket,alongwithaninter- nal time base, are used to determine a pcr delta for future use. after initialization, this field should only be accessed by the hardware. explicit_rate this 16-bit field contains the explicit cell rate as defined for abr traffic on this lcd. current_rate this 16-bit field contains the current cell rate as defined for abr traffic on this lcd. minimum_rate this 16-bit field contains the minimum cell rate as defined for abr traffic on this lcd. backward_ptr when software needs to send a backward rm cell, this 32-bit field should be updated with the address of a buffer that contains the desired backward rm cell. after the segmentation logic transmits the cell, this field will be cleared by the hardware. total_user_cells this 32-bit field contains a count of the total number of user cells that have been sent on this lcd, after either statistics or blocking are enabled either globally or locally for this lcd. this field should be set to zero when the connection is initialized. an event will be generated when this count wraps. total_user_cells_clp0 this 32-bit field will contain a count of the total number of user cells that have been sent on this lcd with clp = 0, if either statistics or blocking are enabled either globally or locally for this lcd. this field should be set to zero when the connection is initialized. an event will be generated when this count wraps. when configured, this field can also be total packets transmited. threshold_1&2 these fields are compared to the upper 24 bits of the bytes_queued field to determine when a thresh- old is crossed and the pool id for the received lcd should be changed. pool_id1&2 these fields are used to change the pool id when a threshold is crossed. bytes_queued this field is used to keep track of the number of bytes queued for transmission on this lcd. timer_type # these encoded bits determine the time of timer. 00 = relative non-periodic timer the expiration time will be in one timer period. the timer will not be scheduled again automatically. 01 = relative periodic timer the expiration time will be in 1 timer period. the timer will be auto- matically scheduled again . 10 = absolute non-periodic timer the timer will expire at the time specified by the timestamp field. the timer will not be automatically scheduled again . 11 = absolute periodic timer the timer will expire at the time specified by the timestamp field. the timer will be scheduled again, automatically, using the time specified in the timer_period field. timer_period # this field specifies the number of timeslots before the timer expires. dma_desc_addr # the dma descriptor pointed to by this field will be queued for execution when the timer expires. crm missing rm-cell count. crm limits the number of forward rm-cells which may be sent in the absence of received backward rm-cells. cdf is written to the ncrm field whenever a backward rm cell is detected. icdf cutoff decrease factor (cdf) controls the decrease in acr associated with crm. cdf is zero or a power of 2 value in the range of 1/64 to 1. icdf represents the power of 2 that is in the denominator of cdf. cdf = 1/(2**icdf) so icdf = log (base 2) of 1/cdf. range = 1 to 6. a zero value for cdf should be represented as 0xff for icdf. abr code variables definitions (page6of7) field name field description IBM2520L8767 ibm processor for atm resources packet header page 52 of 553 atmrm.chapt03.01 08/27/99 imcr this is the reciprocal of the minimum cell rate (mcr). mcr is represented in the abr rate format. imcr needs to be an integer representing the interval between cells, in units of timeslots per cell. the following formula illistrates the conversion from mcr to imcr. imcr = 1/(mcr) * 53 * 8 * (tsp/ci*(2**23)). the timeslot prescalar (tsp) is defined by the csked timeslot prescalar register. the clock interval (ci) is determined by the crset clock control regis- ter. with the tsp set to one timeslot per cell transmission time, imcr =1 for a full bandwidth, 2 for a half bandwidth, etc. pcr the peak cell rate (pcr) is the cell rate that the source may never exceed. pcr should be in the abr rate format. irdf rate decrease factor (rdf) controls the decrease in the cell transmission rate. rdf is a power of 2 value in the range of 1/32,728 to 1. irdf represents the power of 2 that is in the denominator of rdf. rdf = 1/(2**irdf) so irdf = log (base 2) of 1/rdf. range = 1 to 15. irif rate increase factor (rif) controls the increase in the cell transmission rate. rif is a power of 2 value in the range of 1/32,728 to 1. irif represents the power of 2 that is in the denominator of rif. rif = 1/(2**irif) so irif = log (base 2) of 1/rif. range = 1 to 15. icr the initial cell rate is the rate at which a source should send initially and after an idle period. icr shouldbeintheabrrateformat. abr code variables definitions (page7of7) field name field description IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 53 of 553 receive lcd data structure and modes the following are the major differences in this pass: the packed portion (first 32 bits) is almost completely different, but is now easier to set up and to follow. the host data and oam fields are swapped to improve performance. several options can no longer be set on an lcd basis; they are set on a chip basis instead. see raall for details. new modes and options. the format of the receive lcd structure depends on which aal is being configured and which options are used. the following sections detail the receive portion of the lcd for each major option: transmit data structure linkage lc cb next lcd@ head pointer tail pointer lc cb next lcd@ head pointer tail pointer lc cb next lcd@ head pointer tail poi nt e r lc cb next lcd@ head pointer tail pointer packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data packet buffer packet header packet data IBM2520L8767 ibm processor for atm resources packet header page 54 of 553 atmrm.chapt03.01 08/27/99 raw lcd a raw lcd allows raw atm cells to be received with no reassembly. the user can select to receive 53-, 52-, or 48-byte cells. the packet header contains the atm header regardless of the cell length selected. the cell data is then placed after the packet header at the configured receive offset. the 53-byte mode stores the entire cell including hec, the 52-byte mode stores the entire cell minus the hec, and the 48-byte mode stores only the atm cell payload. optional crc-10 checking is available in raw modes. raw lcd layout class rawlcd { // packet portion - bit32 bit2 aaltype; // 00 - raw bit2 mode; // 00 - none bit2 size; //00-53bytecell //01-52bytecell //10-48bytecell // 11 - res bit2 state; // 00 - down // 01 - idle/enabled bit1 res; bit1 res; bit1 res; bit1 storecrc10; bit1 res; bit3 res; bit1 res; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit32 res; bit32 res; bit32 res; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 55 of 553 raw routed lcd a raw routed lcd receives data in the same way that a raw lcd does. once received, the cell buffer is routed internally to the scheduler and rescheduled for transmission. normally when a cell is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a cell is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows cells to be routed out the transmit interface with the same or different vp/vc. when routing cells, the user can choose to surface non-user data (nud) cells to the user, or to route them in line with the user-data cells. this is controlled with the routenud bit in the lcd. a cell is considered nud if the most significant bit of the pti field in the atm header is turned on. if the routed cell stream is actually an aal5 packet stream, then earlydrop mode might be considered. in this mode, a cell being dropped due to resource causes the lcd to go into error mode until the cell that contains the user indicate (uind) bit is received. all cells received in error mode are dropped, except the final cell which is forwarded. this conserves bandwidth while maintaining the aal5 integrity. in raall, an additional pool can be specified to ensure that these final cells are always forwarded even when resources are low. the low order bits in the routedlcd field should be set correctly to free the buffer on transmission. these bits corespond to the flag bits in the packet header. raw routing is also called forwarded or fast forward mode. raw routed lcd layout class rawroutedlcd { // packet portion - bit32 bit2 aaltype; // 00 - raw bit2 mode; // 01 - routed bit2 size; //00-53bytecell //01-52bytecell //10-48bytecell // 11 - res bit2 state; // 00 - down // 01 - idle/enabled // 11 - error // only valid in early drop mode bit1 res; bit1 res; bit1 res; bit1 earlydrop; bit1 routenud; bit3 res; bit1 res; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit32 routedlcd; bit32 res; bit32 res; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 56 of 553 atmrm.chapt03.01 08/27/99 raw cut through lcd a raw cut-through lcd receives data in the same way that a raw lcd does. once received, the ctrxqnum field is used to get a dma descriptor address or a buffer address (direct cut-through enabled) from the core- sponding receive queue. the dma descriptor is then built using the cell buffer address, the data length, and the cut-through flags specified in raall. after being built, it is queued to the dma queue specified using dmaqsel and the configuration in dmaqs. if there is no dma descriptor available, then a no descriptor event is queued (see entity 14: receive queues (rxque) on page 300). raw cut through lcd layout class rawcutthrulcd { // packet portion - bit32 bit2 aaltype; // 00 - raw bit2 mode; // 10 - cut thru bit2 size; //00-53bytecell //01-52bytecell //10-48bytecell // 11 - res bit2 state; // 00 - down // 01 - idle/enabled bit1 res; bit1 res; bit1 res; bit1 storecrc10; bit1 res; bit3 ctrxqnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit32 res; bit32 res; bit32 res; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 57 of 553 rawfifolcd this mode is depreciated and should not be used. in the IBM2520L8767, a new fifo mode similar to the aal5 fifo mode will be implemented. there are four fifo modes supported, and the mode is specified in the protocol enable bits of the receive portion of the lcd. the four modes are: 53-byte cells 52-byte cells (no hec) 48-byte cells contiguous 48-byte cells the first three modes are logically the same and differ only in how much data is delivered to the user. in these modes, cells are received into each 64-byte area of the receive fifo. another way to think of it is the receive pointer increments by 64 bytes with the reception of each cell. when the end of the fifo is reached, it wraps back to the begining of the fifo buffer. raw fifo lcd layout class rawfifolcd { // packet portion - bit32 bit2 aaltype; // 00 - raw bit2 mode; // 11 - fifo mode bit2 size; //00-53bytecell //01-52bytecell //10-48bytecell // 11 - 48 byte cell contiguous bit2 state; // 00 - down // 01 - idle/enabled // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 res; bit1 res; bit1 res; bit3 res; bit1 res; bit3 rxqnum; bit4 res; bit8 res; bit6 res; bit10 fifothresh; bit10 fifosizemask; bit6 res; bit32 baseaddr; bit11 maxcellcnt; bit10 currrxcellcnt; bit11 totalrxcellcnt; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 58 of 553 atmrm.chapt03.01 08/27/99 the last mode is fundamentally different in that the 48-byte payload from each cell is copied into the fifo buffer in a contiguous fashion. every cell is contiguous in memory, so the tail portion of the fifo buffer is not used if it cannot hold a complete cell payload. again, if the end of the buffer is reached, then it wraps back to the begining of the buffer. the following figure shows the two fifo layouts: the receive fifo is maintained by raall using six number fields in the receive portion of the lcd: cell threshold count fifosizemask base addr and rx ptr maximum cell count current rx cell count total rx cell count once set up, cells are received into the fifo buffer. fifo threshold and/or fifo full events are posted as cells are received. the user can then process the cells that are surfaced with these events. if a threshold and full event coincide, then the threshold event is surfaced. the user informs raall that cells have processed by using the synchronization operation. the synchroniza- tion operation allows the user to specify either a specific number of cells to synchronize, or to use the thresh- old to synchronize cells. raall provides a status bit to indicate that a bad synchronization operation has been attempted (more cells synchronized than are in fifo). if status is enabled in the lc, then cell drop events are raised when a cell is dropped because the fifo was full. statistics and oam blocking support is supported in fifo mode. if enabled in the raall control register, then fifo lcs are included in the lcs reassembling counts. receive fifo buffer layouts non-contiguous contiguous base address - 0 base address - 64 base address + 0 base address + 48 cell data cell data cell data cell data cell data cell data unused area IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 59 of 553 aal5 lcd an aal5 lcd allows aal5 packets to be received with no special processing. the headerthresh can be used to allow packet header thresholding events to surface. aal5 lcd layout class aal5lcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 00 - none bit1 res; bit1 res; bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 descstate; bit3 res; bit1 res; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit16 headerthresh; bit16 maxlength; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 60 of 553 atmrm.chapt03.01 08/27/99 aal5 routed lcd an aal5 routed lcd allows aal5 packets to be received. once received, the packet buffer is then routed internally to the scheduler and rescheduled for transmission. normally when a packet is received, the receive lcd address is written into the packet header and the buffer is surfaced to the user. when a packet is routed, the routedlcd field is used to fill in the lcd address in the packet header. this allows packets to be routed out the transmit interface with the same or different vp/vc. the low order bits in the routedlcd field should be set correctly to free the buffer on transmission. these bits corespond to the flag bits in the packet header. aal5 routing is also called forwarded or fast forward mode. aal5 routed lcd layout class aal5routedlcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 01 - routed bit1 res; bit1 res; bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 routenud; bit3 res; bit1 res; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit32 routedlcd; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 61 of 553 aal5 cut-through mode 6 lcd an aal5 cut-through mode 6 lcd allows aal5 packets to be received with additional cut-through process- ing. once the entire packet is received, the ctrxqnum field is used to get a dma descriptor address or a buffer address (direct cut-through enabled) from the corresponding receive queue. the dma descriptor is then built using the buffer address, the data length, and the cut-through flags specified in raall. after being built, the descriptor is enqueued to the dma queue specified using dmaqsel and the configuration in dmaqs. if there is no dma descriptor available, then a no descriptor event is queued (see entity 14: receive queues (rxque) on page 300). the amount of data dma?d includes the packet header, any padding bytes specifed with the receive offset, and up to cutthruthresh bytes of data. aal5 cut-through mode 6 lcd layout class aal5ct6lcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 10 - cut thru bit1 ctmode; // 0 - mode 6 bit1 usefiforegs; // 0 - use normal cut thru desc bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 res; bit3 ctrxqnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit16 cutthruthresh; bit16 maxlength; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 62 of 553 atmrm.chapt03.01 08/27/99 aal5 cut-through mode 6 lcd using hardware fifo registers this is the same as aal5 cut-through mode 6, except for how dma descriptors are built. this mode is meant to be used with a hardware fifo device. two dma descriptors are built using the hardware fifo reg- isters in raall. the first descriptor is built to dma the data (same as mode 6) to the first fifo address. the second dma descriptor is built to write the buffer address to the second fifo address, thus forming a com- plete command. aal5 cut-through mode 6 using hardware fifo registers lcd layout class aal5ct6lcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 10 - cut thru bit1 ctmode; // 0 - mode 6 bit1 usefiforegs; // 1 - use hardware fifos regs to build cut thru desc bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit4 channelnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit16 cutthruthresh; bit16 maxlength; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 63 of 553 aal5 cut-through mode 7 lcd an aal5 cut-through mode 7 lcd allows aal5 packets to be received with additional cut-through process- ing. once cutthruthresh bytes of data are received the ctrxqnum field is used to get a dma descriptor address or a buffer address (direct cut-through enabled) from the coresponding receive queue. the dma descriptor is then built using the buffer address, the data length, and the cut-through flags specified in raall. after being built, the descriptor is enqueued to the dma queue specified using dmaqsel and the con- figuration in dmaqs. if there is no dma descriptor available, then it is retried on the next cell reception. if there is no dma descriptor available when the packet completes, then a no descriptor event is queued (see entity 14: receive queues (rxque) on page 300). the amount of data dma?d includes the packet header, any padding bytes specifed with the receive offset, and up to cutthruthresh bytes of data. aal5 cut-through mode 7 lcd layout class aal5ct7lcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 10 - cut thru bit1 ctmode; // 1 - mode 7 bit1 dmaedheader; bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 descstate; bit3 ctrxqnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit16 cutthruthresh; bit16 maxlength; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 64 of 553 atmrm.chapt03.01 08/27/99 aal 5 cut-through scatter mode lcd cut-through scatter mode allows received data to be "scatter dmaed" to host memory via a list of host pages. when enough data on a particular vc has arrived to fill a host page, a dma operation is automatically initi- ated to transfer that data from IBM2520L8767 memory to a page in host memory. as this occurs, subsequent receive data is accumulated until another host-page-sized page of data is collected, at which time a dma is initiated and the process continues. upon receiving the last data in a packet, the packet header along with all the dma descriptors used to trans- fer the 'scattered' data is passed up to the host. the host can now access the received data since it is already in host memory and it has the packet header and the list of dma descriptors describing where each page of the data packet resides in host memory. aal5 cut-through scatter mode lcd layout class aal5scatterlcd { bit2 aaltype; // 01 - aal 5 bit2 mode; // 11 - scatter mode bit1 res; bit1 res; bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 res; bit3 ctrxqnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit6 numdesc; bit10 numheadbytes; bit16 maxlength; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 65 of 553 aal5 fifo mode lcd an aal5 fifo mode lcd allows aal5 packets to be concatenated in a single receive buffer. the receive buffer is the fifo. this is useful with applications such as mpeg where small fixed-size packets are received, but the overhead of receiving a large number of packets per second is too high. this mode allows the packets to be gathered together into the fifo (or super packet) and then be processed with a single receive interrupt. the receive packet sizes do not need to be fixed-size, but the user needs to be able to parse the receive packets if they are not. the fifothresh is used to specify the largest packet that will be received. when the free space in the fifo falls to this threshold, the end of the current packet will terminate the fifo packet. subsequent cells are gathered into another packet. the encoded fifosize field specifies how large the fifo buffer can grow. this value should be less than or equal to the size of the receive buffers as configured in vimem. the fifoptr should be initialized to zero and used by the IBM2520L8767 to keep track of the current location in the fifo buffer between packets. when a fifo packet completes, there are two modes of operation. first, the default mode operates just like cut-through mode 6. when the packet completes, a cut-through dma descriptor is used to move the data to system storage. this can be disabled in the raall control register. when disabled, the packet is surfaced to software via a super-packet event (0xe) just like a normal aal5 packet. aal5 fifo mode lcd layout class aal5ct6lcd { bit2 aaltype; // 01 - aal 5 bit4 mode; // 1000 - same as cut thru mode 6 (see fifo mode bit below) bit2 state; // 00 - down // 01 - idle // 10 - reasm // 11 - error bit1 rtotest; bit1 rtoenable; bit1 tmpclp; bit1 tmpcongestion; bit1 fifomode; // must be set to 1 to use this mode bit3 ctrxqnum; bit1 dmaqsel; bit3 rxqnum; bit4 rxpoolid; bit8 rxoffset; bit3 fifosize; bit13 fifothresh; bit16 fifoptr; bit32 rxbuffaddr; bit32 rxcrc; bit32 tucclp0; bit32 tuc; bit32 hostdata; bit16 oamtuc; bit16 oambip; }; IBM2520L8767 ibm processor for atm resources packet header page 66 of 553 atmrm.chapt03.01 08/27/99 lcd field definitions the following are the definitions of the lcd fields grouped by major function: a * after the name specifies a field that software should set up. all reserved fields should be set to zero. common lcd field definitions field name field description note aaltype specifies the aal for this lcd. 00 = raw mode 01 = aal5 1 state specifies the reassembly state for this lcd. this field is used by the IBM2520L8767, but in order to receivecells,anlcdmustbeinitializedtoidlestate.thefollowingarethevalidvalues: 00 = down state 01 = idle state 10 = reassembling state 11 = error state 1 ctrxqnum specifies which rxque contains cut dma descriptors. this field is only valid in cut-through and scatter modes. 1 channelnum specifies which hardware channel is to be used. this field is only valid in cut-through mode h. 1 dmaqsel specifies which raal dma queue should be selected when the dma is sent to dmaqs. see dmaqs raall/csked queue number register. 1 rxqnum specifies which rxque normal events should be posted. note: some events may be routed to the error queue based on your rxque setup. 1 rxpoolid specifies which pool id whould be used when getting buffers for received packets. 1 rxoffset specifies the offset into the IBM2520L8767 buffer where the received packet should be placed. 1 tucclp0 lc statistic that counts the total users cells with clp=0 received on this lc. for accurate counts, this should initialized to zero. note: this field can be changed to count packets received. see raall control register. 1 tuc lc statistic that counts the total users cells received on this lc. for accurate counts, this should initial- ized to zero. 1 hostdata if enabled, the contents of this field are placed in packet of each received packet for this lcd. one use of this,istoplaceacorrelatortoahostspecificdatastructureforthislcd. 1 oamtuc oam blocking total user cells received on this lc. this is a rolling count that is updated when oam block- ing is enabled. a new value is set from each pm cell as it is received. oambip oam blocking 16-bit bit-interleaved-parity. this is the calculated bip over the current block of cells for this lc. it is reset to zero on each pm cell reception for this lc. 1. software should set up this field. IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 67 of 553 lcd raw mode field definitions field name field description note mode this field selects the major mode for this lcd. the other fields are based on this value. 00 = normal 01 = routed 10 = cut thru 11 = fifo mode 1 size this field specifes how many bytes are stored when cell is received. 00 = 53-byte cell 01 = byte cell (no hec) 10 = 48-byte cell 11 = 48-byte cells (contiguous mode in fifo mode only) 1 storecrc10 when set, the crc-10 state bit is written into the packet header. a one is written in the error status bit in word 0 if a bad crc-10 is detected. 1 earlydrop when set, the cells for this lcd are assumed to form an aal5 stream; early drop mode is enabled. 1 routenud when set, non-user data cells are routed just like other routed cells. when cleared, non-user data cells are terminated at this node. 1 routedlcd when routing cells, this field is used to fill in the lcd field of the packet header. this allows the user to dynamically route cells back out the interface using a different lcd. the user should be sure to set the free on transmit bit in this field as if it was in a packet header. 1 fifothresh specifies how many cells should be received in the receive fifo before a fifo threshold event should be surfaced. if this field is set to zero, no threshold events are surfaced. 1 fifosizemask used by raall to determine how large the fifo buffer is. sizefield (15-6) fifo size 64-byte cells 48-byte cells 0000000000 64 bytes 1 1 0000000001 128 bytes 2 2 0000000011 256 bytes 4 5 0000000111 512 bytes 8 10 0000001111 1k bytes 16 21 0000011111 2k bytes 32 42 0000111111 4k bytes 64 85 0001111111 8k bytes 128 170 0011111111 16k bytes 256 341 0111111111 32k bytes 512 682 1111111111 64k bytes 1k 1365 1 baseaddr specifies the base address of the fifo buffer at initialization. once enabled, raall uses this field to maintain a pointer to where the next cell is to be received. 1 maxcellcnt specifies the maximum number of cells that the fifo buffer should contain. this does not need to be the maximum specified by the buffer size. 1 currrxcellcnt specifies how many cells have been received into the fifo since the last threshold was crossed. this should be initialized to zero. after initialization, raall maintains this field. 1 totalrxcellcnt specifies how many active cells are contained in the fifo (cells not acknowledged by user). this should be initialized to zero. after initialization, raall maintains this field. 1 1. software should set up this field. IBM2520L8767 ibm processor for atm resources packet header page 68 of 553 atmrm.chapt03.01 08/27/99 aal5 field definitions (page 1 of 2) field name field description note mode this field selects the major mode for this lcd. the other fields are based on this value. 00 = normal mode 01 = routed mode 10 = cut thru mode 11 = scatter mode 1 rtotest this is the reassembly timeout processing test-and-set bit. it is used by the IBM2520L8767, but should be initialized to zero. 1 rtoenable if set, reassembly processing is enabled for this lc, if the lc is running aal5 or is in fifo mode. 1 tmpclp used by the IBM2520L8767 to track the current state of the or?d clp bit for the current aal5 packet. this field should be set to zero at initialization. after initialization, the IBM2520L8767 maintains this field. 1 tmpcongestion used by the IBM2520L8767 to track the current state of the or?d congestion bit for the current aal5 packet. this field should be set to zero at initialization time. 1 descstate this is used by the IBM2520L8767 for cut-through processing. this should be initialized to zero. 1 headerthresh specifies how much data should be received before poping a packet start event. if it is set to zero, only complete packet events will be popped. 1 maxlength specifies the maximum amount of data that can be received per packet on this lc. if set to zero, the value in raall max sdu length register is used. this allows the maximum packet size to be set on an lcd basis. 1 rxbuffaddr this field is used by the IBM2520L8767, but should be initialized to zero by software. this field is used to track the current packet under reassembly. 1 rxccrc this field is used by the IBM2520L8767 to maintain the crc residue as the current packet is reas- sembled. this field does not need to be initialized. routedlcd when routing cells, this field is used to fill in the lcd field of the packet header. this allows the user to dynamically route cells back out the interface using a different lcd. the user should be sure to set the free on transmit bit in this field as if it was in a packet header. 1 ctmode specifies cut-through mode 6 when cleared and mode 7 when set. mode 6 dmas the header when the packet is complete, while mode 7 dmas the headers when the threshold is met. 1 cutthruthresh used to determine how much cut-through data is dma?d. 1 dmaedheader this is used by the IBM2520L8767 for cut-through mode 7 processing. this should be initialized to zero. 1 numdesc this is used by the IBM2520L8767 for scatter processing, and sould be initialized to zero. 1 numheadbytes specifies how many bytes of data should kept with the packet header when dmaing the final dma list for a completed scatter packet. must be less than the page size. 1 1. software should set up this field. IBM2520L8767 ibm processor for atm resources atmrm.chapt03.01 08/27/99 packet header page 69 of 553 fifosize used to specify the size of aal5 fifo buffers. 000 = 512 bytes 001 = 1kb 010 = 2kb 011 = 4kb 100 = 8kb 101 = 16kb 110 = 32kb 111 = 64kb 1 fifothresh specifesmaximum-sizedpackettobereceivedintothereceivefifo. 1 fifoptr used by the IBM2520L8767. initialize to zero. 1 aal5 field definitions (page 2 of 2) field name field description note 1. software should set up this field. IBM2520L8767 ibm processor for atm resources packet header page 70 of 553 atmrm.chapt03.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 71 of 553 internal organization: entity descriptions this part contains detailed descriptions of the entities which, working together, make up the IBM2520L8767. the data flows through the chip have already been described; now the details of the registers and algorithms will be revealed. the entity descriptions are numbered for easy reference. note on set/clear/read type registers there are many registers in the IBM2520L8767 that operate as a set/clear type. these registers have two addresses. the base address is for clearing bits in the register, and base address +4 bytes is for setting bits in the register. the setting or clearing operations occur only for those bits that have the value of ?1? on the write of the register. either of the addresses can be used for reading the register. control processor bus interface entities entity 1: the iop bus specific interface controller (pcint) this entity provides pci specific interfacing between the external connection and the internal entities. it will support the following functions: pci memory target pcimaster address and data latching provide parity error detection and generation provide configuration space registers pci options taken medium address decode design point locking as a memory target supported interrupt a will be supported, with interrupt 2 as a the sideband signal registers will not burst, but cause retries when a burst is attempted bist defaults set at the pci 2 second maximum pci target response a target retry is issued if a burst crosses the end of the IBM2520L8767?s memory space. a target abort will be issued if ad and command bus have bad parity (address phase parity error). optionally, if serr# is enabled, it will also be returned. if enabled, the perr# signal will be driven on bad parity during data write cycles (data phase parity error) when the IBM2520L8767 is the target of the command. a target retry will be issued by the IBM2520L8767 if internal contention will cause a large bus access delay. pci master response a master abort will be issued if devsel# is not asserted after five clocks. if enabled, the perr# signal will be driven on bad parity during data read cycles (data phase parity error) when the IBM2520L8767 is the initiator of the command. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 72 of 553 atmrm.chapt04.01 08/27/99 pci master retry the IBM2520L8767 will retry when requested by the slave. 1.1:pcintconfigword0 identifies this device and vendor type, allocated by pci sig. length 32 bits type read only address xxxx 0000 restrictions can be read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?00a11014?, but alterable at power-up/reset time with crisco code. see entity 16: nodal processor bus interface (npbus) on page 340 for details. power on reset value (little endian) x?1410a100? device id vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-16 15-0 device id this is a unique two-byte device id assigned to this adapter. 15-0 15-0 vendor id this is a unique two-byte vendor id. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 73 of 553 1.2:pcintconfigword1 the status register is used to record status information for the pci bus related events. writing ?1? to a bit in this register will reset that bit. the command register provides coarse control over a device?s ability to gener- ate and respond to pci cycles. access type of the command register is read/write. see bit definitions. length 32 bits type read/write and read/reset address xxxx 0004 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?02800000? power on reset value (little endian) x?00008002? detected parity error signaled system error received master abort received target abort signaled target abort devsel timing data parity detected fast back-to-back capable udf supported 66 mhz capable reserved reserved fast back-to-back enable serr enable wait cycle control parity error response vga palette snoop memory write and invalidate enable special cycles bus master enable memory space enable i/o space enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31 15 detected parity error. this bit is set by the device whenever it detects a parity error, even if par- ity error handling is disabled (as controlled by bit 6 of pcint configuration word 1). 30 14 signaled system error. this bit is set whenever the device asserts serr . 29 13 received master abort. this bit is set by a master device whenever its transaction is terminated with master-abort, except for special cycle. 28 12 received target abort. this bit is set by a master device whenever its transaction is terminated with target-abort. 27 11 signaled target abort. this bit is set by a target device whenever its transaction is terminated with target-abort. 26-25 10-9 devsel timing. these bits are hard-wired to ?01?, assuming medium address decode. 24 8 data parity detected. this bit implemented by this bus master. it is set when this agent asserts perr or observed perr asserted, and this agent setting the bit acted as the bus master for the operation in which the error occurred, and bit 6 of pcint configuration word 1 is set. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 74 of 553 atmrm.chapt04.01 08/27/99 23 7 fast back-to-back capable. this bit is hard-wired to ?1?. 22 6 udf supported defaults to zero unless set by crisco. 21 6 66 mhz capable defaults to zero unless set by crisco. 20-16 6-0 reserved. reserved 15-10 15-10 reserved. reserved 9 9 fast back-to-back enable. this bit can be set to a value, but is ignored by internal logic. 88serr enable. if this bit is ?1?, the serr driver is enabled. 7 7 wait cycle control. this bit is hard-wired to zero because stepping is not supported by this master. 6 6 parity error response. when this bit is ?1?, normal action is taken when a parity error is detected. when it is ?0?, any parity errors detected are ignored and normal operation continued. 5 5 vga palette snoop. this bit is not implemented. 44 memory write and invalidate enable. this bit is not implemented. 3 3 special cycles. this bit is set to a ?0?, and will not monitor special cycle operations. 2 2 bus master enable. if this bit is ?1?, this device will be allowed to act as a bus master. 1 1 memory space enable. if this bit is ?1?, this device will respond to memory space accesses. 0 0 i/o space enable. if this bit is ?1?, this device will respond to i/o space accesses. bit(s) pci spec name description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 75 of 553 1.3:pcintconfigword2 the class code is used to identify the generic function for this device. the revision id is used to identify the level of function for this device. see bit definitions. length 32 bits type read only address xxxx 0008 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?02030004? power on reset value (little endian) x?04000302? upper byte middle byte lower byte revision id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-24 23-16 upper byte. the upper byte of the class code is a base code that broadly classifies the type of function this device performs. code chosen is: x?02? - network controller 23-16 15-8 middle byte. the middle byte of the class code is a sub-class code that identifies more specifically the function of this device. code chosen is: x?03? - atm con- troller 15-8 7-0 lower byte. the lower byte of the class code identifies a specific register-level pro- gramming interface so that device independent software can interact with this device. code chosen is: x?00? 7-0 7-0 revision id. this is the revision level of this chip. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 76 of 553 atmrm.chapt04.01 08/27/99 1.4:pcintconfigword3 this word specifies the system cache size in units of 32-bit words, the value of the latency timer for this pci bus master, the header type which identifies the layout of bytes in configuration space, and the register for the control and status of bist (built-in self-test). see bit definitions. length 32 bits type read/write address xxxx 000c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?00000000? power on reset value (little endian) x?00000000? bist capable start bist reserved completion code header type (read only) latency timer cache line size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31 7 bist capable. this bit is a ?1? because this device supports bist. 30 6 start bist. writing this bit ?1? will invoke bist. this bit is reset after bist is complete. this bit has two seconds to reset after a start bist action. 29-28 5-4 reserved. reserved 27-24 3-0 completion code. a value of ?0? means this device has passed bist. if bit 27 is on, the prpg value failed. if bit 26 is on, the misr value failed. bits 25 and 24 will always be zero. 23-16 7-0 header type (read only). the encoding chosen is x ?00?. 15-8 7-0 latency timer. this register specifies a value of latency in units of pci bus clocks. 7-0 7-0 cache line size. this register is used to best determine what read command should be used by this master. any cache line size is supported. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 77 of 553 1.5: pcint base address 1 (i/o for regs) this register specifies the base address of where in pci i/o space the IBM2520L8767 registers will be mapped. when written with ones and read back, the least significant bits read back as zero will indicate the amount of i/o space required for this device to operate. for example, when a value of ?ffffffff? is written, a value read of ?ffffff00? indicates that 256 bytes of address space this required. see bit definitions. length 32 bits type read/write address xxxx 0010 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. bit 17 in the pcint base address control register must be set to allow the IBM2520L8767 to decode addresses for this range. power on reset value (big endian) x?00000001? power on reset value (little endian) x?01000000? base address reserved i/o space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-2 31-2 base address. this register is used to hold the address where the target device will decode for i/o accesses. the size is 16k of addressing, naturally aligned. this means that only bits 31-14 are writable. the pci specification only allows 256 bytes of i/o base address, so this address is only for special applications. using the feature of non-postable writes for i/o cycles must accompany enough i/o space in the system memory map. 1 1 reserved. reserved and set to ?0?. 0 0 i/o space. this is i/o space, so this bit is set to a ?1?. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 78 of 553 atmrm.chapt04.01 08/27/99 1.6: pcint base address 2 (mem for regs) this register specifies the base address of where in pci memory space the IBM2520L8767 registers will be mapped. when written with ones and read back, the least significant bits read back as zero will indicate the amount of memory space required for this device to operate. for example, when a value of ?ffffffff? is written, a value read of ?ffffff00? indicates that 256 bytes of address space this required. see bit defini- tions. length 32 bits type read/write address xxxx 0014 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. bit 16 in the pcint base address control register must be set to allow the IBM2520L8767 to decode addresses for this range. power on reset value (big endian) x?00000000? power on reset value (little endian) x?00000000? base address prefetchable memory space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-4 31-4 base address this register is used to hold the address where the target device will decode for memory accesses. the size is 16k of addressing, naturally aligned. this means that only bits 31-14 are writable. 3 3 prefetchable. this memory space is non-prefetchable, so this bit is set to ?0?. this means that there are side effects on reads. 2-1 2-1 this base address can be mapped anywhere in 32 bit address space. the value of these bits is ?00?. 0 0 memory space. this is memory space, so this bit is set to ?0?. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 79 of 553 1.7: pcint base addresses 3-6 (memory) this register specifies the base address of where in pci memory space the IBM2520L8767 memory will be mapped. when written with ones and read back, the least significant bits read back as zero will indicate the amount of memory space required for this device to operate. for example, when a value of ?ffffffff? is written, a value read of ?ffffff00? indicates that 256 bytes of address space this required. see bit defini- tions. note: these registers power up to x?08000000? if accessed little endian. length 32 bits type read/write address reg 3 xxxx 0018 reg 4 xxxx 001c reg 5 xxxx 0020 reg 6 xxxx 0024 power on value x?00000008? restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. if one of these registers is not enabled (see pcint base address control regis- ter), then a read of that register will return all zeros. the power on value stated below assumes that the register is enabled. normally, configuration code will just read these registers to find out what is there. to enable more that the default of registers 3 and 4, the use of crisco code could be used. see entity 16: nodal pro- cessor bus interface (npbus) on page 340 for details. base address prefetchable type memory space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-4 31-4 base address this register is used to hold the address where the target device will decode for memory accesses. the size of addressing is naturally aligned and determined by what is set in the pcint base address control regis- ter. 3 3 prefetchable this memory space is prefetchable, so this bit is set to ?1?. this means that there are no side effects on reads, all bytes are returned on reads regard- less of byte enables, and host bridges can merge processor writes into this range without causing errors. 2-1 2-1 type this base address can be mapped anywhere in 32-bit address space. the value of these bits is 00b. 0 0 memory space this is memory space, so this bit is set to a ?0?. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 80 of 553 atmrm.chapt04.01 08/27/99 1.8: pcint cardbus cis pointer this register contains the an offset to where the card information structure (cis) is located. see bit defini- tions. length 32 bits type read/write address xxxx 0028 restrictions cannot be written unless by crisco, or the pci configuration space override write bit is on. power on reset value x?00000000? reserved address space indicator address space offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reserved reserved 30-27 address space indicator can be set by crisco code, likely to be in expansion rom space. 26-0 address space offset this field has the offset into expansion rom that is the location of the cis. see the pcmcia v2.10 specification for details of the cis. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 81 of 553 1.9: pcint subsystem id/vendor id this register contains the subsystem id and subsystem vendor id. see bit definitions. length 32 bits type read/write address xxxx 002c restrictions cannot be written unless by crisco, or the pci configuration space override write bit is on. power on reset value (big endian) x?xxxx1014? power on reset value (little endian) x?1410xxxx? reserved subsystem id subsystem vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reserved reserved 31-16 subsystem id generally will be set by crisco code. other possible codes that could be returned for the subsystem id are listed in the table below. the correctness of their value is superseded by higher (ioa card) levels of documentation. 15-0 subsystem vendor id default value is the ibm vendor id. alternate codes for subsytem id bits in pcint subsystem id/vendor id register subsystem id card name function control memory packet memory 00a2 caribou 25 mbs, 4/5 token ring, utp-3,4,5 0 meg 2 meg 00a3 reindeer-d 45 mbs, ds3, 75 ohm coax 0 meg 1 meg 00a4 reindeer-e 34 mbs, e3, 75 ohm coax 0 meg 1 meg 00a5 okapi 155 mbs, sonet oc3c, stp/utp05 0-16 meg 4-32 meg 00a6 gazelle 155 mbs, sonet oc3c, mm-fiber 16 meg 32 meg 00a8 moose 155 mbs, sonet oc3c, sm-fiber 16 meg 32 meg 00be sugarpine 622 mbs, sonet oc12c, fiber 4 meg 4 meg 0051 pioneer 622 mbs, sonet oc12c, fiber 8 meg 8 meg IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 82 of 553 atmrm.chapt04.01 08/27/99 1.10: pcint rom base address this register specifies the base address of where in pci memory space the IBM2520L8767 rom will be mapped. when written with ones and read back, the least significant bits read back as zero will indicate the amount of memory space required for this device to operate. for example, when a value of ?ffffffff? is written, a value read of ?ffffff00? indicates that 256 bytes of address space is required. see bit definitions. length 32 bits type read/write address xxxx 0030 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value x?00000000? base address reserved address decode enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-10 31-10 base address. this register is used to hold the address where the target device will decode for expansion rom. the size is fixed at 1k of addressing, natu- rally aligned. 9-1 9-1 reserved. reserved and set to a ?0?. 0 0 address decode enable. this bit set to ?1? will enable accesses to expansion rom only if memory spaceenablebit(bitoneinpcintconfigurationword1)isalsoset. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 83 of 553 1.11: pcint config word 15 this register is used to communicate interrupt line routing information, tells which interrupt pin this device uses, and specifies the desired setting for latency timer values. see bit definitions. length 32 bits type read/write address xxxx 003c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?00010100? power on reset value (little endian) x?00010100? max_lat (read only) min_gnt (read only) interrupt pin (read only) interrupt line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) pci spec name description 31-24 7-0 max_lat (read only). this value specifies a period of time in units of 1/4 microsecond. max_lat is used for specifying how often this device needs to gain access to the pci bus. 23-16 7-0 min_gnt(read only). this value specifies a period of time in units of 1/4 microsecond. min_gnt is used for specifying how long a burst period this device needs, assuming a33-mhzclockrate. 15-8 7-0 interrupt pin (read only). this device used inta for its pci bus interrupt. value of this field is 01h. 7-0 7-0 interrupt line. software will write the routing information into this register as it initializes and configures the system. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 84 of 553 atmrm.chapt04.01 08/27/99 1.12: pcint endian control register this register allows control and status to the big/little endian per address selection. see bit definitions. length 32 bits type read/write address xxxx 0058 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. power on reset value x?00000000? reserved see bits 4 - 0 reserved byte swap for expansion rom (on-card flash) reserved byte swap for configuration registers byte swap for register accesses (memory or i/o space) byte swap for memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-29 reserved. reserved 28-24 same as the definitions for bits 4-0. 23-5 reserved. reserved 4 byte swap for expansion rom (on-card flash). when this bit is set to ?1?, the bytes of an internal expansion rom access (big endian view) will be swapped to and from the pci interface. 3 reserved reserved 2 byte swap for configuration reg- isters. when this bit is set to ?1?, the bytes of an internal configuration register access (big endian view) will be swapped to and from the pci interface. 1 byte swap for register accesses (memory or i/o space). when this bit is set to ?1?, the bytes of an internal register access (big endian view) will be swapped to and from the pci interface. 0 byteswapformemory. when this bit is set to ?1?, the bytes of an internal packet memory access (big endian view) will be swapped to and from the pci interface. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 85 of 553 1.13: pcint base address control register this register controls all the base address registers that map to memory. see bit definitions. length 32 bits type read/write address xxxx 005c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?0001000f? power on reset value (little endian) x?0f000100? disable devto errors to gpdma disable master detected target abort errors to gpdma disable master detected perr errors to gpdma disable slave target abort errors from pcint disable master detected parity errors to gpdma disable slave memory incremental retry cycles encoded control for dma reads allow decoding for zero base address values enforce sequential pci register writes enforce sequential pci register reads disable retrying on the 1st cycle of a memory access enable writing to special config registers disable incremental latency timeout retries enable pcint base address 1 (i/o for regs) enable pcint base address 2 (mem for regs) encoded control for pcint base address 6 (memory) encoded control for pcint base address 5 (memory) encoded control for pcint base address 4 (memory) encoded control for pcint base address 3 (memory) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 disable devto errors to gpdma setting this bit to a ?1? will disable device time-out errors from stopping a gpdma transfer. 30 disable master detected target abort errors to gpdma setting this bit to a ?1? will disable master detected target abort errors from stopping a gpdma transfer. 29 disable master detected perr errors to gpdma setting this bit to a one will disable master detected parity errors from stopping a gpdma transfer. 28 disable slave target abort errors from pcint setting this bit to a ?1? will disable target abort errors to the requesting pci master. 27 disable master detected parity errors to gpdma setting this bit to a ?1? will disable master detected parity errors from stopping a gpdma transfer. 26 disable slave memory incremental retry cycles setting this bit to a ?1? will disable slave memory retry attempts and will wait until the data transfer has completed. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 86 of 553 atmrm.chapt04.01 08/27/99 25-24 encoded control for dma reads encoding of bits: x?0?: let the IBM2520L8767 pick the best memory read command based on the cachelinesizebitsandthedmacount. x?1?: fixthereaddmacommandtomemoryreadmultiple x?2?: fixthereaddmacommandtomemoryreadline x?3?: fixthereaddmacommandtomemoryread. 23 allow decoding for zero base address values. setting this bit to a ?1? will enable decoding of a bar address that is set to zero. nor- mally, the pci specification does not allow for a zero address to be a valid decode. 22 enforce sequential pci register writes. setting this bit to a ?1? will make sure that pci register writes will occur in sequential order of prior memory accesses or register reads. the cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete. 21 enforce sequential pci register reads. setting this bit to a ?1? will make sure that pci register reads will occur in sequential order of prior memory accesses or register writes. the cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete. 20 disable retrying on the 1st cycle of a memory access. setting this bit to a ?1? will disable the retrying of a memory access to the IBM2520L8767. this will cause a pci spec violation, but not a data integrity problem. it will solve the rare case where two masters are accessing control memory at the same time and retries happen to both endlessly. 19 enable writing to special config registers. setting this bit to a ?1? will enable writing to certain registers that are normally read-only. an example of this would be the vendor and function id register (pcint configuration word 0). 18 disable incremental latency time- out retries setting this bit to a ?1? will disable pci retries due to cycles taking more than eight cycles on burst accesses after the first access. 17 enable pcint base address 1 (i/o for regs). setting this bit to a ?1? will enable pcint base address 1 (i/o for registers). this does the same function as bit zero in the pcint configuration word 1 register, but also make the pcint base address 1 (i/o for regs) read back zeros even when written to with values. it guards against anything that bios code may do to pcint configuration word 1 register bit zero if i/o accesses are not desired. 16 enable pcint base address 2 (mem for regs). this bit set will enable pcint base address 2 (mem for regs) such that the IBM2520L8767 registers can be accessed by pci memory cycles. 15-12 encoded control for pcint base address 6 (memory). encoding of bits: x?0?: disable this base address. x?1?: configured to respond to a 2gb address size. x?2?: configured to respond to a 1gb address size. x?3?: configured to respond to a 512mb address size. x?4?: configured to respond to a 256mb address size. x?5?: configured to respond to a 128mb address size. x?6?: configured to respond to a 64mb address size. x?7?: configured to respond to a 32mb address size. x?8?: configured to respond to a 16mb address size. x?9?: configured to respond to a 8mb address size. x?a?: configured to respond to a 4mb address size. x?b?: configured to respond to a 2mb address size. x?c?: configured to respond to a 1mb address size. x?d?: configured to respond to a 64kb address size, and internal windowing of mem- ory is enabled. x?e?: configured to respond to a 32kb address size, and internal windowing of mem- ory is enabled. x?f?: configured to respond to a 16kb address size, and internal windowing of mem- ory is enabled. 11-8 encoded control for pcint base address 5 (memory). 7-4 encoded control for pcint base address 4 (memory). 3-0 encoded control for pcint base address 3 (memory). bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 87 of 553 1.14: pcint window offsets for base addresses 3-6 these registers specify the amount of memory space required for this device to operate. see bit definitions. length 32 bits type read/write address reg 3 xxxx 0060 reg 4 xxxx 0064 reg 5 xxxx 0068 reg 6 xxxx 006c power on value x?00000000? restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. windowing offset range reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-14 windowing offset range. this register is used to hold the address offset, which is added to the pci address (when windowing is enabled) to form the internal memory address. bits 15 and 14 may or may not be used, depending on how bits are set in the pcint base address control register. when bit 20 of pcint count time-out register is set, window offset register three can be updated with the address returned from a good get buffer from pools. this will save a write from code to this register. when bit 20 of pcint count timeout register is set, window offset register four can be updated with the address returned from a dequeue from the receive queue. this will save a write from code to this register. 13-0 reserved. reserved IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 88 of 553 atmrm.chapt04.01 08/27/99 1.15: pcint count timeout register this register holds the count limit of pci slave retry cycles. see bit definitions. length 32 bits type read/write address xxxx 0070 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register on page 85), or an i/o cycle. this register is documented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?0200ffff? power on reset value (little endian) x?ffff0002? reserved register read retry timeout value reserved enable dynamic window offset updates disable register retry accesses disable pci locking function disable slave machine crisco retry active slave transaction timeout retry timeout count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-27 reserved reserved 26-24 register read retry timeout value the bits can be set to determine how many pci cycles a register access will wait for aninternalcycletocompleteforareadaccess.itcanbeprogrammedtowaitforupto seven cycles. a value of zero will not timeout this access with a retry. 23-21 reserved reserved 20 enable dynamic window offset updates this bit will enable the values of pcint window offsets for base addresses 3-6 so that it updated with a good get primitive or certain receive queue dequeues. 19 disable register retry accesses this bit will disable pci retry signaling during a register or primitive access. 18 disable pci locking function this bit will disable this pci locking function when set to ?1? 17 disable slave machine this bit is for crisco code use. it will disable all responses to the pci bus in slave mode. in general, never turn this bit on. bit 19 of the pcint base address control register must be set before this bit can be changed. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 89 of 553 16 crisco retry active this bit is for crisco code use. it powers up to a ?1? at reset. when this bit is set, a retry will be signalled to all config accesses. it can be reset to a ?0? either by a register write by crisco, or by a reset pulse signalled from npbus when crisco execution is com- plete. a crisco write allows quicker access to configure space, even if crisco is not done writing to other parts of the chip. when this bit is on, the counter related to bits 7-0 of the register does not increment since the retry count could be excessive in this case. 15-8 slave transaction timeout these bits hold a value that is used to count the number of pci clocks times 256 when a pci slave cycle is in progress. if the count is reached, due to some internal chip hang condition, a target abort is issued. a value of ?0? will disable target aborts from this function 7-0 retry timeout count these bits hold a value that is used to count the number of pci retries. the max count is 256 times 16 retries. if the count is reached, a target abort is issued. a value of ?0? will disable target aborts from this function. bit(s) function description IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 90 of 553 atmrm.chapt04.01 08/27/99 1.16: pcint 64bit control register this register contains miscellaneous control bits. length 3bits type read/write address xxxx 0078 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?00000002? power on reset value (little endian) x?02000000? swap word mode disable 64bit data phase parity checking req64 indicates that a 64 bit pci bus is connected 210 bit(s) function description 2 swapwordmode this bit set to a ?1? will enable word swapping of the each of the four groups of data bytes in an 8-byte transfer. 1 disable 64bit data phase parity checking. this bit set to a ?1? will disable the data phase parity checking on bits 32 to 63 of the ad pci bus. 0 req64 indicates that a 64 bit pci bus is connected this bit will set when the req64 i/o pin was low bus when rst went inactive. when set to a ?0?, the enstate lines will actively be driving the pci pins ad(63 - 32). IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 91 of 553 1.17: pcint perf counters control register this register contains control bits for the pcint performance counter 1 and pcint performance counter 2. length 32 bits type read/write address xxxx 007c restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?00000000? power on reset value (little endian) x?00000000? reserved counter modes master/slave types - counter 2 cycles types - counter 2 master/slave types - counter 1 cycles types - counter 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-18 reserved reserved. 17-16 counter modes these bits will determine which kind of mode both counters will operate in. x?0? stop on overflow x?1? interrupt on wrap x?2? event on wrap x?3? reserved 15-12 master/slave types - counter 2 these bits will determine which kind of pci cycle owners to be counted for counter 2. the defines are the same as bits 7-4. 11-8 cycles types - counter 2 these bits will determine what kind of pci events are to be counted for counter 2. the defines are the same as bits 3-0. 7-4 master/slave types - counter 1 these bits will determine which kind of pci cycle owners to be counted for counter 1. x?0? all devices on the pci bus x?1? all devices but the IBM2520L8767 x?2? a only (master or slave) x?3? IBM2520L8767 master x?4? IBM2520L8767 slave (all types) x?5? IBM2520L8767 slave register accesses x?6? IBM2520L8767 slave memory accesses IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 92 of 553 atmrm.chapt04.01 08/27/99 3-0 cycles types - counter 1 these bits will determine what kind of pci events are to be counted for counter 1. x?0? off x?1? all pci clock cycles x?2? active pci bus cycles (frame + irdy + trdy) x?3? pci data xfer opportunities ((irdy + trdy) & devsel) x?4? pci data xfers (irdy & trdy) x?5? pci retries (irdy & no trdy & devsel & stop) x?6? pci target aborts (irdy & no trdy & no devsel & stop) x?7? pci disconnects (irdy & trdy & devsel & stop) bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the iop bus specific interface controller (pcint) page 93 of 553 1.18: pcint perf counter 1 this register contains pci performance counter 1. length 32 bits type read/write address xxxx 0080 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?xxxxxxxx? (indeterminate) power on reset value (little endian) x?xxxxxxxx? (indeterminate) counter 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 counter 1 see pcint performance counters control register on how this counter will increment. IBM2520L8767 ibm processor for atm resources the iop bus specific interface controller (pcint) page 94 of 553 atmrm.chapt04.01 08/27/99 1.19: pcint perf counter 2 this register contains pci performance counter 2. length 32 bits type read/write address xxxx 0084 restrictions can be written or read during configuration cycle, memory cycle when enabled (see pcint base address control register), or an i/o cycle. this register is docu- mented as big endian, but how data is presented on the pci bus depends on how the controls are set in the pcint endian control register. power on reset value (big endian) x?xxxxxxxx? (indeterminate) power on reset value (little endian) x?xxxxxxxx? (indeterminate) counter 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 counter 2 see pcint performance counters control register on how this counter will increment. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 95 of 553 entity 2: interrupt and status/control (intst) this entity contains the masking registers that choose which interrupt/status source will be gated onto one of the two available interrupt i/o pins. a new delayed interrupt function has been added. this function allows IBM2520L8767 status registers to be read and placed in system memory before the interrupt signal is raised. for details, see the dmaqs entity. a bus timer function is provided in this entity that times a single bus access to make sure that the cycle is ter- minated before the system timer times out. this allows the user code an opportunity to recover from the error as opposed to the subsystem common code. below is a summary of this entity?s functions: interrupt prioritized status registers interrupt source register interrupt enable registers bus timer function control processor error register with enable register 2.1: intst interrupt 1 prioritized status used to help quickly parse which interrupting entity of the IBM2520L8767 is active. length 32 bits type read only address xxxx 0400 restrictions none power on reset value x?00000000? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status. reading this register will give a prioritized value of this bits in the intst interrupt source and intst enable for interrupt 1 (minta) registers andd together, returning a value that will be a hex number equal to bit number n + 1. for example, if bit 31 is on, x?20? will be read back. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 96 of 553 atmrm.chapt04.01 08/27/99 2.2: intst interrupt 2 prioritized status used to help quickly parse which interrupting entity of the IBM2520L8767 is active. length 32 bits type read only address xxxx 0404 restrictions none power on reset value x?00000000? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status. reading this register will give a prioritized value of these bits in the intst interrupt source and intst enable for interrupt 2 (mint2) registers and?d together, returning a value that will be a hex number equal to bit number n + 1. for example, if bit 31 is on, x?20? will be read back. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 97 of 553 2.3: intst control register used to control various IBM2520L8767 functions. see note on set/clear/read type registers on page 71 for more details on addressing. reserved cpi bytes reserved disable the enstate output pins master chip enable for receiving. master chip enable for transmitting master chip enable zerosondataparity treat mint2 as push-pull enable the pll output (hardware test only) disable the enstate clocks output pins 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 length 32 bits type clear/set address xxxx 0408 and 0c restrictions none power on reset value x?0000202? bit(s) function description 31-11 reserved reserved 10-9 cpi bytes. these bits are encoded to tell how many bytes long the aal5 cpi field is. the following are the encodings: 00 cpi field is zero bytes long. in this case, the two bytes containing the cpi field and the aal5 user-to-user byte are copied into the packet header. see the definition of the packet header for the locations. 01 cpifieldisonebytelongandisalwayszero.inthiscase,theone-byteaal5 user-to-user byte is copied into the packet header. 10 cpi field is two bytes long and is always zero. 11 treated the same as ?00? 8 reserved reserved 7 disable the enstate output pins when this bit is set to ?0?, the chip i/o enstates will be driven with the output of the internally multiplexed debug states. when set to ?1?, these outputs will be quiet. 6 master chip enable forreceiv- ing. when this bit is set to ?1?, various state machines in the receive part of the chip will be enabled. 5 master chip enable for trans- mitting. when this bit is set to ?1?, various state machines in the transmit part of the chip will be enabled. 4 master chip enable. when this bit is set to ?1?, various state machines in the chip will be enabled. this must be set to ?1? to transmit or receive anything. 3 zeros on data parity. when this bit is set to ?1?, zeros will be forced on the data bus parity line(s) during a slave read data phase or a master address phase or a master write data phase. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 98 of 553 atmrm.chapt04.01 08/27/99 2 treat mint2 as push-pull whenthisbitissetto?1?,thechipi/omint2willbedrivenactivehighaswellaslow, like a push-pull driver. this is for use as a specific sideband application, not as a gen- eral shared open-drain interrupt line. 1 enable the pll output (hard- ware test only) when this bit is set to ?1?, the chip i/o ppllout will be driven with the output of the internal pll. when set to ?0?, this output will be quiet. this should be normally reset by crisco. 0 disable the enstate clocks output pins when this bit is set to ?0?, the chip i/o pintclk and pdblclk will be driven with the output of the internal clock tree. when set to ?1?, these outputs will be quiet. bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 99 of 553 2.4: intst interrupt source this register will indicate the source(s) of the interrupt(s) pending, or used as a status register when the bits are enabled. see note on set/clear/read type registers on page 71 for more details on addressing. it should be noted that bits in this register always reflect the state of the source register bit. writing a value will have no effect. reserved bits will not take on the written value. the delay of running through a latch has been removed. length 32 bits type read only address xxxx 0410 and 14 restrictions none power on reset value x?00000000? intst pcore comet or pakit intst gp timer bcach rxque 2 npbus rxque 4 gpdma dmaqs reasm reserved rxque 1 rxque 3 raall reserved pools pcore chksm external inta csked reserved segbf reserved linkc reserved intst gp timer reserved vimem reserved pbist spurious interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 intst a control processor related condition has occurred. a read of the intst cpb status and intst cpb status enable must be done for more information. see intst cpb status on page 102 and intst cpb status enable on page 104 . 30 pcore the pcore entity has hardware interrupts that need handling. 29 comet or pakit the comet or pakit entities have interrupts that need handling. 28 intst gp timer the intst general purpose timer counter has reach the intst general purpose timer compare value and caused an interrupt. 27 bcach the bcach entity has interrupts that need handling. 26 rxque 2 the rxque entity has interrupts that need handling. 25 npbus the npbus entity has interrupts that need handling. 24 rxque 4 the rxque entity has interrupts that need handling. 23 gpdma the gpdma entity has interrupts that need handling. 22 dmaqs the dmaqs entity has interrupts that need handling. 21 reasm the reasm entity has interrupts that need handling. 20 reserved reserved 19 rxque 1 the rxque entity has interrupts that need handling. 18 rxque 3 the rxque entity has interrupts that need handling. 17 raall the raall entity has interrupts that need handling. 16 reserved. reserved. 15 pools the pools entity has interrupts that need handling. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 100 of 553 atmrm.chapt04.01 08/27/99 2.5: intst enable for interrupt 1 (minta) this register serves as an enable for interrupt 1. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst interrupt source on page 99 register for the bitwise description that the corresponding bit in this register will enable. 14 pcore the pcore entity has user defined interrupts that need handling. 13 chksm the chksm entity has interrupts that need handling. 12 external inta this bit will be set when the IBM2520L8767 detects that minta is low and, conditionally, when the same bit in intst enable for pcore normal interrupt or intst enable for pcore critical interrupt is set. this bit is for use by the pcore entity, and recommended that interrupts directed out that drive this output (minta) are disabled. 11 csked the csked entity has interrupts that need handling. 10 reserved reserved 9 segbf the segbf entity has interrupts that need handling. 8 reserved reserved 7 linkc the linkc entity has interrupts that need handling. 6 reserved reserved 5intstgptimer the intst general purpose timer counter has reached the intst general purpose timer compare value and caused an interrupt. 4 reserved reserved 3 vimem the vimem entity has interrupts that need handling. 2 reserved reserved 1 pbist this bit is set when the pbist entity did not indicated that it was done. it also not clearable. 0 spurious interrupt under normal conditions, this bit should never be set. however, if one of the other bits in this register turn on, then off, a spurious interrupt condition would occur. the manual vec- tor passed to the processor would point to this bit being on. length 32 bits type clear/set address xxxx 0418 and 1c restrictions none power on reset value x?00000000? bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 101 of 553 2.6: intst enable for interrupt 2 (mint2) this register serves as a enable for interrupt 2. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst interrupt source on page 99 for the bitwise description that the corresponding bit in this register will enable. 2.7: intst interrupt source without enables used to help quickly parse which interrupting bit of intst interrupt source is active. it does not matter what state the enable registers are set to since the value returned does not depend on them. length 32 bits type clear/set address xxxx 0420 and 24 restrictions none power on reset value x?00000000? length 32 bits type: read only address xxxx 0428 restrictions none power on reset value x?00000000? prioritized status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-0 prioritized status reading this register will give a prioritized value of this bits in the intst interrupt source, returning a value that will be a hex number equal to bit number n + 1. for example, if bit 31 is on, x?20? will be read back. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 102 of 553 atmrm.chapt04.01 08/27/99 2.8: intst cpb status this register holds the status bits for errors on the control processor bus. these bits, when disabled, will set a bit in the intst interrupt source register. see note on set/clear/read type registers on page 71 for more details on addressing. length 19 bits type clear/set address xxxx 0430 and 34 restrictions none power on reset value x?00000? target abort: register access retry timeout target abort: slave access timeout pci timing changed arbit detected memory errors reserved reserved master pci parity error detected master detected perr active master termination: target abort received master termination: master-initiated abort target detected pci 64 bit data parity error target disconnect: memory addressing target detected pci data parity error target abort: memory access retry timeout target abort: address parity error target disconnect or retry: end of memory performance counter 2 performance counter 1 illegal register access 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 18 target abort: register access retry timeout this bit is set when this slave does more retry cycles than the specified amount in the pcint count timeout register during a register access. 17 target abort: slave access tim- eout this bit is set when this slave does not access the IBM2520L8767 in the specified amount in the pcint count timeout register. 16 pci timing changed the pci bus clock has changed operating range enough that the IBM2520L8767 must be adjusted to run with the new bus frequency. the IBM2520L8767 should be reset and re-ini- tialized. 15 arbit detected memory errors this bit is set when error conditions detected by arbit are enabled. note: this bit is a reflection of the arbitrator status bits and does not need to be reset if the arbitrator condi- tion has been reset. 14 reserved reserved 13 reserved reserved 12 master pci parity error detected this bit is set when a pci bus data parity error is detected in master mode. 11 master detected perr active this bit is set when a target has driven parity error. 10 master termination: target abort received this bit is set when in master mode and the transfer is aborted by the target. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 103 of 553 9 master termination: master-initi- ated abort this bit is set when in master mode and the transfer is aborted by this master. 8 target detected pci 64 bit data parity error this bit is set when a pci data parity error is detected in 64 bit target mode (the upper dword has the data parity error). 7 target disconnect: memory addressing this is set when a memory access is occurring and bits 0 and 1 of the address are not zero. 6 target detected pci data parity error this bit is set when a pci data parity error is detected in target mode. 5 target abort: memory access retry timeout this bit is set when this slave does more retry cycles than the specified amount in the pcint count timeout register during a memory access. 4 target abort: address parity error this bit is set when an address parity error is detected. 3 target disconnect or retry: end of memory this bit is set when a termination condition occurs due to reaching the end of the config- ured memory space. 2 performance counter 2 the pcint performance counter 2 has overflowed. 1 performance counter 1 the pcint performance counter 1 has overflowed. 0 illegal register access this bit is set when an IBM2520L8767 register is being accessed by fewer than four bytes at a time. this is not true for configuration registers during a configuration cycle. bit(s) function description IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 104 of 553 atmrm.chapt04.01 08/27/99 2.9: intst cpb status enable this register serves as a enable for the intst cpb status register. see note on set/clear/read type reg- isters on page 71 for more details on addressing. see the intst cpb status on page 102 for the bitwise description that the corresponding bit in this register will enable. this enable will initialize to the disabled state. 2.10: intst IBM2520L8767 halt enable this register serves as a enable for the intst cpb status register and will gate which errors will reset bit 4 (master chip enable), bit 5 (master chip enable for transmitting), and bit 6 (master chip enable for receiving), all in the intst control register register. this allows selected bits to disable the IBM2520L8767, especially in the case of severe hardware detected errors. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst cpb status on page 102 for the bitwise description that corresponding bit in this register will enable. this enable will initialize to the disabled state. length 19 bits type clear/set address xxxx 0438 and 3c restrictions none power on reset value x?00000? length 19 bits type clear/set address xxxx 0440 and 44 restrictions none power on reset value x?69f71? IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 105 of 553 2.11: intst cpb capture enable this register serves as a enable for the intst cpb status that will determine on which error type the intst cpb captured address register will be updated. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst cpb status on page 102 for the bitwise description that corre- sponding bit in this register will enable. 2.12: intst cpb captured address this information can be used to attempt a retry in the exception handling microcode. this register will hold the value of the IBM2520L8767 register address on the pci during a bus error condition. this will only latch val- ues from sources that are enabled in the intst cpb capture enable register. length 19 bits type clear/set address xxxx 0450 and 54 restrictions none power on reset value x?7ffff? length 32 bits type read/write address xxxx 0458 restrictions none power on reset value x?00000001? register address reserved invalid capture 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-2 register address captured IBM2520L8767 register address 1 reserved reserved 0 invalid capture when this bit is reset to ?0?, a valid capture has been made. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 106 of 553 atmrm.chapt04.01 08/27/99 2.13: intst general purpose timer pre-scaler this is the pre-scaler for the intst general purpose timer compare. owing to a physical design problem, the function of this register was lost. it should be set to a non-zero value, so that the intst general purpose timer counter can be used with a prescale of only the default clock (one tick every 30ns, assuming a 33-mhz system clock). 2.14: intst general purpose timer compare this is the compare value for the general purpose timer.this register will hold the value of the data that is compared to the count value in the intst general purpose timer counter, setting the intst general pur- pose timer status bits. see intst general purpose timer mode control on page 108 for details on opera- tion of this register. 2.15: intst general purpose timer counter this is the general purpose timer counter. this register will hold the value of the counter. it always counts up. see intst general purpose timer mode control on page 108 for details on operation of this register. length 32 bits type read/write address xxxx 0464 restrictions none power on reset value x?0000014c? length 32 bits type read/write address xxxx 0468 restrictions none power on reset value x?0800 0000? length 32 bits type read/write address xxxx 046c restrictions none power on reset value x?0000 0000? IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 107 of 553 2.16: intst general purpose timer status this is the status of the general purpose timer counter. see note on set/clear/read type registers on page 71 for more details on addressing. length 2bits type clear/set address xxxx 0470 and 74 restrictions none power on reset value x?0? timer wrapped timer interrupt 10 bit(s) function description 1 timer wrapped this bit is set when the intst general purpose timer counter wraps around to a zero count value. 0 timer interrupt see intst general purpose timer mode control on page 108 for details on how this bit is set. for mode 0: this bit is set when the intst general purpose timer counter matches the value in the intst general purpose timer compare register. the comparing condition must be changed (write intst general purpose timer counter or intst general pur- pose timer compare) before resetting this bit, or the bit will set again. IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 108 of 553 atmrm.chapt04.01 08/27/99 2.17: intst general purpose timer mode control this register controls the operating modes of the general purpose timer counter. see note on set/clear/read type registers on page 71 for more details on addressing. length 3bits type clear/set address xxxx 0478 and 7c restrictions none power on reset value x?4? timer modes 210 bit(s) function encodings description 2-0 timer modes these bits are encoded to provide eight different timer operation modes. mode 0 the intst general purpose timer counter is a free-running up-counter and sets bit zero of intst general purpose timer status when equal to intst general purpose timer compare mode 1 the intst general purpose timer counter is a free-running up-counter and sets bit 0 of intst general purpose timer status when equal to intst general purpose timer compare a write to intst general purpose timer compare will reset bit zero of intst general purpose timer status. mode 2 the intst general purpose timer counter is a free-running up-counter and sets bit 0 of intst general purpose timer status when equal to or greater than intst general pur- pose timer compare a write to intst general purpose timer compare will reset bit zero of intst general purpose timer status. mode 3 the intst general purpose timer counter is a up-counter and sets bit 0 of intst gen- eral purpose timer status when equal or greater than intst general purpose timer compare the intst general purpose timer counter is also reset when a comparison is made. a write to intst general purpose timer compare will reset bit zero of intst general purpose timer status and intst general purpose timer counter. mode 4 the intst general purpose timer counter is disabled and no status bits will be set. modes 5-7 reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 109 of 553 2.18: intst enable for pcore normal interrupt this register serves as a enable for the pcore normal interrupt input. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst interrupt source on page 99 for the bit- wise description that the corresponding bit in this register will enable. 2.19: intst enable for pcore critical interrupt this register serves as a enable for the pcore critical interrupt input. see note on set/clear/read type registers on page 71 for more details on addressing. see the intst interrupt source on page 99 for the bit- wise description that the corresponding bit in this register will enable. length 32 bits type clear/set address xxxx 0480 and 84 restrictions none power on reset value x?00000000? length 32 bits type clear/set address xxxx 0488 and 8c restrictions none power on reset value x?00000000? IBM2520L8767 ibm processor for atm resources interrupt and status/control (intst) page 110 of 553 atmrm.chapt04.01 08/27/99 2.20: intst debug states control this register serves as the control for external debug states. length 32 bits type read/write address xxxx 0490 restrictions none power on reset value x?04030201? entity state mux control 4 (hard- ware debug) entity state mux control 3 (hard- ware debug) entity state mux control 2 (hard- ware debug) entity state mux control 1 (hard- ware debug) 313029282726252423222120191817161514131211109876543210 bit(s) function description 31-24 entity state mux control 4 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (63-48). selection encoding is the same as multiplexer 1 control. 23-16 entity state mux control 3 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (4 -32). selection encoding is the same as multiplexer 1 control. 15-8 entity state mux control 2 (hardware debug) selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (31 -16) which are multiplexed over ad64 (31-16), also known as ad (63-48). selection encoding is the same as multiplexer 1 control. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 interrupt and status/control (intst) page 111 of 553 7-0 entity state mux control 1 (hardware debug) select of these bits allow internal state machines, counters, etc. to show up on chip out- puts enstate (15 - 0) which are multiplexed over ad64 (15 - 0), also known as ad (47 - 32). x?00? disabled (no transition on outputs). x?20? select pools 95-80 states. x?01? select crset 15-0 states. x?21? select pools 111-96 states. x?02? select npbus 15-0 states. x?22? select pools 127-112 states. x?03? select pcint 15-0 states. x?23? select vimem 15-0 states. x?04? select pcint 31-16 states. x?24? select vimem 31-16 states. x?05? select comet 15-0 states. x?25? select vimem 47-32 states. x?06? select comet 31-16 states. x?26? select arbit 15-0 states. x?07? select 15-0 states. x?27? select arbit 31-16 states. x?08? select 31-16 states. x?28? select arbit 47-32 states. x?09? select rxque 15-0 states. x?29? select arbit 63-48 states. x?0a? select rxque 31-16 states. x?2a? select pcore 15-0 states. x?0b? select raall 15-0 states. x?2b? select pcore 31-16 states. x?0c? select raall 31-16 states. x?2c? select pcore 47-32 states. x?0d? select raall 47-32 states. x?2d? select pcore 63-48 states. x?0e? select raall 63-48 states. x?2e? select pcore 79-64 states. x?0f? select reasm 15-0 states. x?2f? select pcore 95-80 states. x?10? select linkc 15-0 states. x?30? select pcore 111-96 states. x?11? select segbf 15-0 states. x?31? select pcore 127-112 states. x?12? select segbf 31-16 states. x?32? select dmaqs 15-0 states. x?13? select segbf 47-32 states. x?33? select dmaqs 31-16 states. x?14? select segbf 63-48 states. x?34? select dmaqs 47-32 states. x?15? select csked 15-0 states. x?35? select dmaqs 63-48 states. x?16? select chksm 15-0 states. x?36? select sclck 15-0 states. x?17? select chksm 31-16 states. x?37? select sclck 31-16 states. x?18? select gpdma 15-0 states. x?38? select sclck 39-32 states. x?19? select bcach 15-0 states. x?39?-x?ff? reserved (do not toggle as well) x?1a? select bcach 31-16 states. x?1b? select pools 15-0 states. x?1c? select pools 31-16 states. x?1d? select pools 47-32 states. x?1e? select pools 63-48 states. x?1f? select pools 79-64 states. bit(s) function description IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 112 of 553 atmrm.chapt04.01 08/27/99 entity 3: dma queues (dmaqs) dmaqs provides the interface to the IBM2520L8767?s dma master capability (described in general purpose dma (gpdma) on page 133 ). it provides three dma queues that hold dma descriptor chains that are exe- cuted in a multiplexed fashion. together with gpdma, a very powerful interface is provided to software to complete complex tasks including tcp/ip checksumming for transmit and receive packets. the following sections describe the features of dmaqs, how to set up dmaqs, and some trouble shooting tips. dmaqs also provides the delayed interrupt function. dma descriptors dma descriptors can reside in either pci/system memory space or the IBM2520L8767 memory space. cer- tain types of descriptors must be located in the IBM2520L8767 memory space. these are the cut-through dma descriptors. dma descriptors that are located in the IBM2520L8767 memory space are more efficient to process because they do not need to be moved across the pci bus. however, it is more costly for software to update across the bus. the best option is to mix descriptors in both locations. dma descriptors that are infre- quently changed, should reside in the IBM2520L8767 memory while dynamic descriptors should be placed in system memory. descriptors located in the IBM2520L8767 memory space must fall in a definable address range. see dmaqs local descriptor range registers. dma descriptor layout flags/byte count source address destination address ----------------- flags/byte count source address destination address blocks of up to 63 descriptors may be queued with one enqueue primitive one descriptor IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 113 of 553 dma types/options the dma descriptor is very versatile, and can perform many actions. the following list shows some examples and possible flags to use (other combos are possible, see ®dmcntn.): note: these are not the only options. some of the above can be or?d together also. using the above, you can efficiently do tcp checksumming, place user events in receive queues, do register reads/writes, free buffers, and get buffers. be creative. dma types and flags hex flags dma operation 3000 clear the current tcp checksum and include this dma in the tcp checksum. 1000 include this dma in the tcp checksum and use previous checksum as seed. 0800 this dma transfer is done in little endian mode. 0400 upon completion of this dma descriptor, the destination address from this descriptor is used as a packet address to be enqueued to transmit. 0100 queue a dma complete event when dma is complete. 0080 statusinthestatusregisterisinhibitedforthisdescriptor.thiscanbeusefulifints/pollingarebeingusedtotrack when a particular dma is complete. 0001 move system memory to the IBM2520L8767 memory. 0010 move the IBM2520L8767 memory to system memory. 0012 move a single IBM2520L8767 register to system memory. 0013 move IBM2520L8767 memory to system memory and free buffer. upon dma completion, the source address is used to free the IBM2520L8767 buffer as a get pool id. 0017 auto-increment source address and move IBM2520L8767 memory to system memory and free buffer. upon dma completion, the source address is used to free the IBM2520L8767 buffer as a get pool id. 0002 move single IBM2520L8767 register to IBM2520L8767 memory. 0020 move IBM2520L8767 memory to single IBM2520L8767 register. 0021 move system memory to single IBM2520L8767 register. 0031 move system memory to a new IBM2520L8767 buffer. a get buffer operation will be done to fill in the destination address using the low four bits of the destination address as a get pool id. 0050 move something to source address of next descriptor. allows indirection. 0062 move single IBM2520L8767 register to destination address of next descriptor. allows a get buffer operation in descriptor chain. (see get buff flag for a better option) 0008 use source address as immediate data. allows up to four bytes of immediate data in the dma descriptor. 0004 auto-increment the source address. the source address picks up right were it left off from the previous dma descriptor. 000c auto-increment the source address and use as immediate data. one use is to free a packet after dmaing data. (see free buff flags for better option) 0040 auto-increment the destination address. the destination address picks up right were it left off from the previous dma descriptor. one use is transmit scatter into an IBM2520L8767 virtual buffer. 2200 hold the destination address. useful for freeing a scatter dma list, or doing a repetitive write to an IBM2520L8767 register. 1200 hold the source address. useful for doing a repetitive read from an IBM2520L8767 register. IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 114 of 553 atmrm.chapt04.01 08/27/99 descriptor based dmas this is the recommended approach to processing dmas. a single descriptor or a descriptor chain is built that describes the actions to take. the descriptor is then enqueued to the proper dma queue. the number of the descriptor in the dma chain is placed in the lower six bits of the descriptor address as it is enqueued. register based dmas while register based dmas can be enabled and used, they are not recommended because they are not as efficient and they do not leave a debug trail as the descriptors do in the dma queue. these should not be used concurrently with descriptor-based dmas for a particular queue, but register-based and descrip- tor-based dmas can be used on different queues. one possible use for register-based dmas is doing dmas from the core. polling, interrupts, or events there are several choices for handling dma completion. first, the status register can be polled. while not very efficient, it is the easiest option. second, you can use interrupts to tell when a dma is done. again, not very efficient. however, interrupts should be used to tell when a dma error has happened. one way to deal with dma completes is the use the rxque event mechanism. by generating events, the user can dump in dma descriptor and clean up at a later time when it is convenient. the user can use the automatic dma events using the queue on dma complete flag, or the user can place a user event on an arbi- trary queue by writing a dma descriptor that does an explicit rxque enqueue with user data. error detection and recovery ideally, there should not be any errors. errors are usually user-errors in the dma descriptor which need to be fixed and are not recoverable. errors on the pci bus (i.e. parity) should not be happening in a normal working dma and must be recovered in gpdma. upon successful completion of the recovered dma, dmaqs will resume operation. dma/queue scheduling options there are three dma queues. queue zero is higher priority then the other two. this high priority queue is always scheduled to go if the current descriptor is ready. the other two queues (q1/q2) are of equal priority and are scheduled in a round robin fashion when the descriptor is ready. this was meant to provide a trans- mit dma queue, and receive dma queue, and a high priority dma queue. however, these queues can be used for any purpose by setting the routing registers properly. arbitration of queues: the queues can be arbitrated after each dma request length operation, after complete dma descriptor chains complete, after single dma descriptor in a chain completes. the queues can also be placed in true round robin mode, where all three queues have equal priority. no matter how the queues are arbitrated, the delayed interrupt transfer and dma descriptor transfer (from system to queue) are always highest priority and are arbitrated after every dma request length operation. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 115 of 553 initialization of dmaqs dmaqs is very simple to set up. the following steps should be followed to set up dmaqs: 1. set up each of the three dma queues. to do this, you need to know the size of each queue (see dmaqs upper bound registers on page 117 for choices). given this information, the dma queue is set up with two register writes in diagnostic mode (see dmaqs control register). dmaqs->lowerbound[q] = baseaddress // should be aligned with size of queue dmaqs->upperbound[q] = encodedsize; // set encoded size of dma queue the data structure for the dma queue is now set up. 2. set up the queue thresholds if they are being used: dmaqs->threshold[q] = threshold // set threshold size to be interrupted on // may also need to set int mask 3. set up the local dma descriptor range if local descriptors are being used: dmaqs->localdesclowerbound = localdescbase // set base addr of local desc in charm memory dmaqs->localdescupperbound = localdescend; // set endingaddr of local desc in charm memo ry 4. set up any options that are being used in the dmaqs control register: dmaqs->control[set] = enable_dma_queues ? clr_checksum_to_foxes // set options/modes 5. finally, clear the diagnostic bit: dmaqs->control[clr] = diag_mode // clear the diagmode bit 6. need to set up memory bank selection if necessary, but normally control memory is used. delayed interrupts when enabled, an IBM2520L8767 register can be moved to system memory before the interrupt is raised to the system. the register and destination address are specified in the dmaqs delayed interrupt source and destination registers. this allows the rxque status register or the intst status register to be read into sys- tem memory before the interrupt is raised, thus removing pci bus latency from your interrupt handler. another option is to use both sets of interrupt masks, but use only a single hardware interrupt. when this is done, both delayed interrupt sources are read for interrupt two before the interrupt is raised. this allows the user to setup mask 2 for errors only and mask 1 for normal mainline interrupts only. the rxque enabled status registers should also be considered as they show only the status that you are interested in. the dma transfer to move the registers is the highest priority in the dma scheduling mechanism. however, you still may need to tune your dma scheduling so these interrupts are not delayed behind a 64-k transfer. IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 116 of 553 atmrm.chapt04.01 08/27/99 3.1: dmaqs lower bound registers these registers specify the lower bound of the corresponding dma queue data structure. these registers specify the lower bound of the corresponding dma queue data structure. the head, tail, and length of the dma queue are initialized when this register is written. when the dma queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the dma queue as a circular buffer. when this register is written, the corresponding dma queue is essentially reset. this is because the head, tail, and length of the queue are all reset. length 32 bits type read/write address queue 0 xxxx 0600 queue 1 xxxx 0640 queue 2 xxxx 0680 power on value x?00000000? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the dmaqs control register. the alignment should correspond to the size specified in the upper bound register. for example, it should be 4-k aligned if the upper bound specifies 4-k size. the low order nine bits are not writable and read back zero. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 117 of 553 3.2: dmaqs upper bound registers these registers specify the encoded size/upper bound of the corresponding dma queue data structure. the actual upper bound is calculated by adding the decoded queue size to the lower bound. when the dma queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the dma queue as a circular buffer. length 3bits type read/write address queue 0 xxxx 0604 queue 1 xxxx 0644 queue 2 xxxx 0684 power on value x?00000000? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the dmaqs control register. bit(s) description 2-0 000 512 bytes of memory 001 1k of memory 010 2k of memory 011 4k of memory 100 8k of memory 101 16k of memory 110 32k of memory 111 64k of memory IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 118 of 553 atmrm.chapt04.01 08/27/99 3.3: dmaqs head pointer registers these registers point to the head element of the corresponding dma queue. during normal operations, these registers do not need to be read or written; they are used by the IBM2520L8767 to implement the dma queues. these registers are initialized when the dmaqs lower bound registers for the corresponding dma queue is written. the head pointer registers are 4-byte aligned. (low order two bits always zero). bits 31-17 are calculated internally 3.4: dmaqs tail pointer registers these registers point to the next free element of the corresponding dma queue. length 32 bits type read/write address queue 0 xxxx 0608 queue 1 xxxx 0648 queue 2 xxxx 0688 power on value x?00000000? restrictions during normal operations, these registers are read only. the registers can only be written when the diagnostic bit has been set in the dmaqs control register. length 32 bits type read/write address queue 0 xxxx 060c queue 1 xxxx 064c queue 2 xxxx 068c power on value x?00000000? restrictions during normal operations, these registers are read only. the registers can only be written when the diagnostic bit has been set in the dmaqs control register. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 119 of 553 3.5: dmaqs length registers these registers specify the length in bytes of the corresponding dma queue. these registers specify the length in bytes of the corresponding dma queue. this register is cleared when the corresponding dmaqs lower bound registers is written. 3.6: dmaqs threshold registers these registers specify a queue length threshold at which the corresponding status bit is generated. these registers should be set equal to the queue length that should cause status to be generated. for example, if the value was set to five, then no interrupt would be generated until the queue was length five or more for the corresponding dma queue. the threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. when this register is set to zero, no thresholding is done. length 17 bits type read address queue 0 xxxx 0610 queue 1 xxxx 0650 queue 2 xxxx 0690 power on value x?00000000? restrictions the lengths are calculated and cannot be written. length 17 bits type read/write address queue 0 xxxx 0614 queue 1 xxxx 0654 queue 2 xxxx 0694 power on value x?0000? restrictions must be a multiple of 4. IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 120 of 553 atmrm.chapt04.01 08/27/99 3.7: dmaqs interrupt status this register indicates the source(s) of the interrupt(s) pending. see note on set/clear/read type registers on page 71 for more details on addressing. length 25 bits type read/write address xxxx 0708 and 70c restrictions none power on value x?00009200? zero address in src/dst enqfifothreshexceeded error during delayed int transfer enqfifofull zero length dma loaded error enqueuing csked descriptor error enqueuing raall descriptor error enqueuing descriptor dma descriptor error dma descriptor queue 2 not full dma descriptor queue 2 threshold exceeded dma descriptor queue 2 full dma descriptor queue 1 not full dma descriptor queue 1 threshold exceeded dma descriptor queue 1 full dma descriptor queue 0 not full dma descriptor queue 0 threshold exceeded dma descriptor queue 0 full error occurred during descriptor transfer error occurred during dma transfer q2 error occurred during dma transfer q1 error occurred during dma transfer q0 dma transfer complete q2 dma transfer complete q1 dma transfer complete q0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 24 zero address in src/dst when set, a zero address was detected in the source or destination field of a dma descrip- tor. the remainder of the descriptor chain was skipped and an event was enqueued to the dma complete queue. this may or may not be an error condition. it is not an error if the get buffer mode is being used and no buffer was available. in this case, the descriptor can be retried or discarded by software. 23 enq fifo thresh exceeded when set, the dma enqueue fifo length threshold has been exceeded. 22 error during delayed int trans- fer when set, an error occurred while doing a delayed interrupt transfer. generally this is a user error in the delayed interrupt setup. when this happens, the delayed interrupt enables are reset so interrupts flow to the system. 21 enq fifo full when set, the dma enqueue fifo is full and further enqueues will be held off. this bit is hot and cannot be reset. 20 zero length dma loaded a descriptor was loaded that had a dma length equal to zero. this will not stop the dma engine, but it is technically a user error. 19 error enqueuing csked descriptor. a descriptor was enqueued from csked with a chain length of zero. 18 error enqueuing raall descriptor. a descriptor was enqueued from raall with a chain length of zero. 17 error enqueuing descriptor. a descriptor was enqueued with a chain length of zero. 16 dma descriptor error. an invalid transfer was described by the value loaded into the transfer count and flag reg- ister. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 121 of 553 15 dma descriptor queue 2 not full. the dma descriptor queue 2 is not full. this bit will always contain the status of the queue and is therefore is not writable. 14 dma descriptor queue 2 threshold exceeded. the threshold for dma descriptor queue 2 has been exceeded. 13 dma descriptor queue 2 full. the dma descriptor queue 2 is full. this bit will always contain the status of the queue and is therefore is not writable. 12 dma descriptor queue 1 not full. the dma descriptor queue 1 is not full. this bit will always contain the status of the queue and is therefore is not writable. 11 dma descriptor queue 1 threshold exceeded. the threshold for dma descriptor queue 1 has been exceeded. 10 dma descriptor queue 1 full. the dma descriptor queue 1 is full. this bit will always contain the status of the queue and is therefore is not writable. 9 dma descriptor queue 0 not full. the dma descriptor queue 0 is not full. this bit will always contain the status of the queue and is therefore is not writable. 8 dma descriptor queue 0 threshold exceeded. the threshold for dma descriptor queue 0 has been exceeded. 7 dma descriptor queue 0 full. the dma descriptor queue 0 is full. this bit will always contain the status of the queue and is therefore is not writable. 6 error occurred during descrip- tor transfer. hardware errors occurred transferring the dma descriptor. the transfer stopped after detecting the error. if the descriptor transfer is finished or is to be terminated, the byte count register must be written to clean up the failed descriptor transfer. before this bit is reset, the dma descriptor queue must contain the valid descriptor data or the ®dmt- dqcn. must be written to the value it contained prior to the descriptor enqueue. 5 error occurred during dma transfer q2. hardware errors occurred during the last transfer on queue 2. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 4 error occurred during dma transfer q1. hardware errors occurred during the last transfer on queue 1. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 3 error occurred during dma transfer q0. hardware errors occurred during the last transfer on queue 0. the transfer stopped after detecting the error. inspect gpdma registers for actual location of error. 2 dma transfer complete q2. the dma transfer has completed for queue 2. 1 dma transfer complete q1. the dma transfer has completed for queue 1. 0 dma transfer complete q0. the dma transfer has completed for queue 0. bit(s) function description IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 122 of 553 atmrm.chapt04.01 08/27/99 3.8: dmaqs interrupt enable this register serves as a mask for dmaqs interrupt status. the structure of this register is identical to the dmaqs interrupt status on page 120. see note on set/clear/read type registers on page 71 for more details on addressing. 3.9: dmaqs control register used to set options for dmaqs. see note on set/clear/read type registers on page 71 for more details on addressing. length 25 bits type read/write address xxxx 0700 and 704 restrictions none power on value x?006f0078? length 32 bits type read/write address xxxx 0710 and 714 restrictions see bit descriptions. power on value x?000c0001? reset fifo restart dma reserved disable desc snooping disable desc prefetch enable cache flushes of local desc fifo length threshold enable full round robin scheduling rearbitrate on desc completion rearbitrate on desc chain completion delayed int endian bit routeint2toint1 enable delayed int 1 enable delayed int 2 memory select for IBM2520L8767 dma desc memory select for dma queues enable register based dmas clear checksum to all ones queueonerror endian of dma descriptors enable queue 2 dmas enable queue 1 dmas enable queue 0 dmas diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s)0 function description 31 reset fifo when this bit is set, the internal dma enqueue fifo is flushed, and this bit is reset. the result is this bit will always be read as a zero. this bit can only be set in diagnostic mode. 30 restart dma when this bit is set, the internal dma state machine will restart the current dma that is stopped, and this bit is reset. the result is this bit will always be read as a zero. this bit should only be used if you really know what you are doing (translation: an IBM2520L8767 developer told you to use it!). IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 123 of 553 29-23 reserved reserved. 22 disable desc snooping when set, the dma descriptor snooping logic is disabled. when enabled, performance may be enhanced. 21 disable desc prefetch when set, the next descriptor prefetch logic is disabled. this must be disabled if the next_src or next_dest flags are going to be used, otherwise performance may be enhanced by enabling this function. 20 enable cache flushes of local desc when set, all local dma descriptors are flushed out of bcach before being used. this only needs to be used if local dma descriptors are in packet memory and are updated via the slave interface. cut-through descriptors do not fall in this category. 19-17 fifo length threshold this value * 2 is used to set the fifo length threshold. when this threshold is exceeded, moving descriptors across the pci bus becomes a higher priority until the length moves below the threshold. 16 enable full round robin scheduling when set, all three dma queues are of equal priority. when cleared, queue 0 is higher pri- ority then queues 1 & 2. 15 rearbitrate on desc completion when set, the dma queues are rearbitrated after each individual dma descriptor com- pletes. 14 rearbitrate on desc chain completion when set, the dma queues are rearbitrated after full dma descriptor chains complete. this bit takes precedence over bit 15. when both bits 14 and 15 are cleared, the queues are rearbitrated after each dma request length operation. note: no matter how the queues are arbitrated, delayed interrupts and descriptor moves are highest priority and are arbitrated after every dma request length operation completes. 13 delayed int endian bit this bit determines the endian of the status word dma transfer for delayed interrupts. 12 route int 2 to int 1 when set, the interrupt 2 signal is routed and raised as interrupt 1. this bit allows both sets of interrupt masks in the interrupt status register to be used, while still using only a single hardware interrupt. when set, both delayed interrupts should be enabled if they are being used. 11 enable delayed int 1 when set, the delayed interrupt mechanism for interrupt 1 is enabled. 10 enable delayed int 2 when set, the delayed interrupt mechanism for interrupt 2 is enabled. 9 memory select for IBM2520L8767 dma desc when this bit is set, the dma descriptors that are located in the IBM2520L8767 are located in packet memory, otherwise they are located in control memory. 8 memory select for dma queues when this bit is set, the dma queues are located in packet memory, otherwise they are located in control memory. 7 enable register based dmas when set, source, destination, count, and system descriptor address (sda) registers can be written to start a dma. 6 clear checksum to all ones. when this bit is set, the dmaqs checksum register is set to 0xffff when it is cleared. when this bit is cleared, the dmaqs checksum register is set to zero when it is cleared. this option should be used if the tcp/ip checksum should never be set to zero (0xffff is zero also). 5 queue on error. this bit on will cause any dma error to log an error event. 4 endian of dma descriptors. this bit on will indicate dma descriptors in system memory are in little endian format. the default is big endian. 3 enable queue 2 dmas. this bit enables dma queue 2. 2 enable queue 1 dmas. this bit enables dma queue 1. 1 enable queue 0 dmas. this bit enables dma queue 0. 0 diagnostic mode. when set dmaqs is in diagnostic mode. bit(s)0 function description IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 124 of 553 atmrm.chapt04.01 08/27/99 3.10: dmaqs enqueue dma descriptor primitive enqueues a dma descriptor chain to the corresponding dma queue. this register is used to enqueue a dma descriptor chain to the corresponding dma queue. the write data is the address of the descriptor chain that describes the dma transfers. the low six bits contain a count of the number of dma descriptors in this chain. after the dma descriptors are enqueued by writing to this register, the chain of descriptors are fetched from system memory and the dma transfers described by the chain of descriptors are performed 3.11: dmaqs source address register used to set and keep track of the source address during a dma transfer. this is the source for the current dma transfer. a bit in the transfer count and flag register will determine if the source address is internal to the IBM2520L8767 or is a system address. length 32 bits type write address queue 0 xxxx 0618 queue 1 xxxx 0658 queue 2 xxxx 0698 power on value x?00000000? restrictions none length 32 bits type read/write address queue 0 xxxx 0620 queue 1 xxxx 0660 queue 2 xxxx 06a0 power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 125 of 553 3.12: dmaqs destination address register used to set and keep track of the destination address during a dma transfer. this is the destination address for the current dma transfer. a bit in the transfer count and flag register will determine if the destination address is internal to the IBM2520L8767 or is a system address. 3.13: dmaqs transfer count and flag register specifies the type and number of bytes transferred during a dma transfer. the lower 16 bits are a counter of the number of bytes transferred during a dma transfer. the upper 16 bits specify the type of transfer as fol- lows. length 32 bits type read/write address queue 0 xxxx 061c queue 1 xxxx 065c queue 2 xxxx 069c power on value x?00000000? restrictions none length 32 bits type read/write address queue 0 xxxx 0624 queue 1 xxxx 0664 queue 2 xxxx 06a4 power on value x?00000000? restrictions none reserved clear checksum/hold dest compute checksum/hold src little endian mode tx on dma complete hold mode queue on dma complete inhibit status update when dma complete destination address specifier source address specifier byte transfer count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 126 of 553 atmrm.chapt04.01 08/27/99 bit(s) function description 31-30 reserved. these bits must be zero. 29 clear checksum/hold dest. when this bit is on the checksum and the alignment state are cleared. 28 compute checksum/hold src. when this bit is set a checksum will be computed over this dma segment. 27 little endian mode. when this bit is written to zero, this dma channel will operate in big endian mode. when one, will operate in little endian mode. when in little endian mode both the source and destination must be aligned on four-byte boundaries. 26 tx on dma complete when set, the destination address is used as the packet address that is to be enqueued to csked to be transmitted. the lower bits are zeroed so the buffer base is used for the csked enqueue operation. 25 hold mode when set, bit 28-29 are redefined to allow the source or destination address to be held instead of incremented. bit 29 becomes hold destination address and bit 28 becomes hold source address. this allows a single dma descriptor to do a n-to-1 or 1-to-n transfer. for example, an entire scatter dma list can be freed to a rxque enq regis- ter. the address being held must be a register address. when holding, the maximum length is 252 bytes. when holding, the source or destination is incremented by four when the dma completes (for auto-increment mode). 24 queue on dma complete. when this bit is set, the upper 26 bits of the dmaqs system descriptor address regis- ter will be queued to the dma event queue when the dma completes. if descriptors are not being used to set up the dma, the dmaqs system descriptor address register should be loaded before starting the dma with a value to identify this transfer. if descriptors are being used, the dmaqs system descriptor address register will be loaded automatically with the system address of the descriptor block at the time it is processed. 23 inhibit status update when dma complete. normally a bit will be set in the status register when the dma completes without error. if this bit is set, this update will not be done. this bit is useful when multiple dmas are to be done and an interrupt is only desired on the last transfer. the dma error status bits are unaffected by this bit. 22-20 destination address specifier. these bits specify how the destination address should be used for this dma descriptor. the following are the valid patterns: 000 IBM2520L8767 memory address ? the destination address specifies an IBM2520L8767 internal memory address. 001 pci bus address ? the destination address specifies a pci bus address. 010 IBM2520L8767 register address ? the destination address specifies an IBM2520L8767 register address. only the low 16 bits must be specified. 011 get IBM2520L8767 buffer ? the low four bits of the destination address spec- ifies a pool id from which to get a buffer. if a buffer is not available, a zero destination address event or appropriate status is raised, otherwise the buffer address is used as an IBM2520L8767 memory address. 100 auto increment destination address ? the destination address is sourced from the previous dma instead of the destination address specified in the descriptor. 101 next source address ? the destination address is the address of the source address field of the next descriptor in the current dma chain. using this fea- ture allows indirection. 110 next destination address ? the destination address is the address of the des- tination address field of the next descriptor in the current dma chain. using this feature allows operations like doing a get buffer in the dma descriptor chain. others reserved ? reserved, flagged as errors. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 127 of 553 19-16 source address specifier. these bits specify how the source address should be used for this dma descriptor. the following are the valid patterns: 0000 IBM2520L8767 memory address ? the source address specifies an IBM2520L8767 internal memory address. 0001 pci bus address ? the source address specifies a pci bus address. 0010 IBM2520L8767 register address ? the source address specifies an IBM2520L8767 register address. only the low 16 bits must be specified. 0011 IBM2520L8767 memory address and free buffer when dma complete ? the source address specifies an IBM2520L8767 internal memory address, and this address will be freed to pools when the dma is complete. -100 auto increment source address ? the source address is sourced from the previous dma instead of the source address specified in the descriptor. -111 auto increment source address and free buffer when dma complete ? the source address is sourced from the previous dma instead of the source address specified in the descriptor. the source address specifies an IBM2520L8767 internal memory address, and this address will be freed to pools when the dma is complete. 1-00 immediate data ? use the source address field as immediate data. length must be 4. 1-11 immediate data and free buffer when dma complete ? use the source address field as immediate data. length must be 4.thesourceaddress will be freed to pools when the dma is complete. others reserved ? reserved, flagged as errors. 15-0 byte transfer count. these bits indicate the number of bytes to transfer. a non-zero value in this field will start the dma transfer. bit(s) function description IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 128 of 553 atmrm.chapt04.01 08/27/99 3.14: dmaqs system descriptor address the upper 26 bits contain the address of the current descriptor block and the lower six bits contain the num- ber of descriptors in the chain that remain to be processed. if dma descriptors are used for dma transfers, this register will contain the system address of the current descriptor block and the number of descriptors that remain to be processed. this address may be queued on dma completion to correlate dma transfers with system control blocks. when doing register-based dmas, the low six bits are set to "000001" when the dmaqs transfer count and flag register is written. 3.15: dmaqs checksum register this register contains the accumulated checksum. this register contains the accumulated checksum value. it can also be used to initialize the checksum with a seed value. the most significant bit contains the alignment state (1 = odd, 0 = even alignment). the alignment state is significant between subsequent checksummed dmas. this register can be read at four different addresses. the base address will return the unmodified accumu- lated checksum. the base address +4 will return the inverted accumulated checksum. the base address + 8 will return the byte-swapped accumulated checksum. the base address + 12 will return the inverted byte-swapped accumulated checksum. length 32 bits type read/write address queue 0 xxxx 0628 queue 1 xxxx 0668 queue 2 xxxx 06a8 power on value x?00000000? restrictions this register should not be written if descriptors are going to be used to set up dma transfers. if it is used, it must be written to 0 before descriptors are enqueued. length 17 bits type read/write address q0 sum xxxx 0630 q0 inv sum xxxx 0634 q0 swapped sum xxxx 0638 q0 inv swapped xxxx 063c q1 sum xxxx 0670 q1 inv sum xxxx 0674 q1 swapped sum xxxx 0678 q1 inv swapped xxxx 067c q2 sum xxxx 06b0 q2 inv sum xxxx 06b4 IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 129 of 553 3.16: dmaqs delayed int src/dst registers these registers contain the source and destination operands for the delayed interrupt function. these regis- ters contain the source and destination operands for the delayed interrupt function. q2 swapped sum xxxx 06b8 q2 inv swapped xxxx 06bc power on value q0 sum x?00000000? q0 inv sum x?0000ffff? q0 swapped sum x?00000000? q0 inv swapped x?ffff0000? q1 sum x?00000000 q1 inv sum x?0000ffff? q1 swapped sum x?00000000? q1 inv swapped x?ffff0000? q2 sum x?00000000? q2 inv sum x?0000ffff? q2 swapped sum x?00000000? q2 inv swapped x?ffff0000? restrictions only the base address accepts write data. all four addresses return read data. length 16 bits type read/write address delayed int src 1 xxxx 0730 delayed int dst 1 xxxx 0734 delayed int src 2 xxxx 0738 delayed int dst 2 xxxx 073c power on value x?00000000? restrictions the low two bits of the source registers are not writable. IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 130 of 553 atmrm.chapt04.01 08/27/99 3.17: dmaqs local descriptor range registers these registers specify the lower and upper bounds of the memory range for local dma descriptors. these registers contain the address of the lower and upper bound of the memory range of descriptors that are in the IBM2520L8767. if a descriptor block is enqueued, it is compared to these registers. if it falls within this range, only the descriptor address is placed on the queue. when the descriptor is to be loaded into the dma regis- ters, and it falls within this range, it will not be taken from the queue but loaded directly from the descriptor address. these registers are 2-k aligned. 3.18: dmaqs raall/csked queue number register this register specifies which dmaqs queue should be used when dma descriptors are enqueued from raall (i.e. cut-through, scatter, etc.) or csked (dma on transmit comp). this register specifies which dmaqs queue should be used when dma descriptors are enqueued from raall (i.e. cut-through, scatter, etc.) or csked (dma on transmit comp). the low two bits specify raall queue 0, bits 3-2 specify csked queue, and bits 5-4 specify raall queue 1. the two raall queues are specified on an lcd basis using the queue selection bit. length 32 bits type read/write address lower bound xxxx 0720 upper bound xxxx 0724 power on value x?00000000? restrictions can be written in diagnostic mode only. length 6bits type read/write address xxxx 0728 restrictions can be written in diagnostic mode only. invalid values (i.e. 3), force queue number 2. power on value x?00000009? IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 dma queues (dmaqs) page 131 of 553 3.19: dmaqs dma request size register this register specifies the maximum request size for dma descriptor scheduling.this register specifies the maximum request size for dma descriptor scheduling. this is the amount of data that dmaqs will request gpdma to move in a single request. for example, if a descriptor wants to move 2k of data and the request size is set to 512 bytes, then dmaqs will request 512 bytes to be moved and then rearbitrate the dma queues. value of zero is the same as 0xffff. 3.20: dmaqs enq fifo head ptr register used to maintain the enqueue fifo. points to the head fifo entry in the fifo array. the msb bit, is used to determine if the head is chasing the tail, and is inverted each time the head pointer wraps 3.21: dmaqs enq fifo tail ptr register used to maintain the enqueue fifo. points to the next free fifo entry in the fifo array. the msb bit, is used to determine if the head is chasing the tail, and is inverted each time the tail pointer wraps length 16 bits type read/write address xxxx 06c0 power on value x?00000000? restrictions none length 5bits type read/write address xxxx 0778 power on value x?00000000? restrictions can only be written in diagnostic mode. length 5bits type read/write address xxxx 077c power on value x?00000000? restrictions can only be written in diagnostic mode. IBM2520L8767 ibm processor for atm resources dma queues (dmaqs) page 132 of 553 atmrm.chapt04.01 08/27/99 3.22: dmaqs enq fifo array holds dma descriptor waiting to be placed on a dma queue. holds dma descriptor waiting to be placed on a dma queue. array is organized as a 16x34 array. to access the upper two bits of each word (holds the dma queue number for descriptor), the array word number should be used as the address. to access the low-order 32 bits (the descriptor portion), the array word number times two plus four should be used. for example, address zero accesses the dma queue num- ber portion of array word zero and address four accesses the descriptor portion of array word zero. length 16 words x 34 bits type read/write address xxxx 0780-7fc power on value x?00000000? restrictions can only be read/written in diagnostic mode. when read in non-diagnostic mode, zero is returned. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 general purpose dma (gpdma) page 133 of 553 entity 4: general purpose dma (gpdma) this entity provides dma control between system memory and IBM2520L8767 packet memory. dma transfers must be enabled in the gpdma control registers for transmit and/or receive. there are two ways to initiate dma transfers. the first is by directly writing the source address, destination address, and transfer count and flag registers. the second is by using dma descriptors and enqueueing them using dmaqs. these two methods should not be used simultaneously. if using descriptors, refer to the dmaqs section beginning on page 112 for more information. dma transfers to system i/o space are not allowed. 4.1: gpdma interrupt status this register will indicate the source(s) of the interrupt(s) pending, or used as a status register when the bits are enabled. see note on set/clear/read type registers on page 71 for more details on addressing. length 9bits type read/write address xxxx 0108 and 0c power on reset value x?000? restrictions none dma transaction timeout dma command error reserved reserved zero length dma request from dmaqs error occurred during receive transfer error occurred during transmit transfer receive transfer complete transmit transfer complete 876543210 bit(s) function description 8 dma transaction timeout. the dma transaction timeout specified in the gpdma interrupt enable timed out. 7 dma command error. an invalid transfer was described by the value loaded into the transfer count and flag register. 6 reserved reserved 5 reserved reserved 4 zero length dma request from dmaqs. dmaqs has requested a dma with a length of zero. this bit is for information use only. this bit is not an error that will prevent gpdma from processing additional dma requests. 3 error occurred during receive transfer. hardware errors occurred during the last transfer. the transfer stopped after detecting the error. IBM2520L8767 ibm processor for atm resources general purpose dma (gpdma) page 134 of 553 atmrm.chapt04.01 08/27/99 4.2: gpdma interrupt enable this register serves as a mask for gpdma interrupt status. see note on set/clear/read type registers on page 71 for more details on addressing. see the gpdma interrupt status register for the bitwise description that the corresponding bit in this register will mask. 2 error occurred during transmit transfer. hardware errors occurred during the last transfer. the transfer stopped after detecting the error. 1 receive transfer complete. the receive transfer has completed. 0 transmit transfer complete. the transmit transfer has completed. length 9bits type read/write address xxxx 0110 and 14 power on reset value x?9c? restrictions none bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 general purpose dma (gpdma) page 135 of 553 4.3: gpdma control register used to set options for dma operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 24 bits type read/write address xxxx 0118 and 1c power on value x?880007? restrictions none pci transfer threshold memory transfer threshold dma transaction timeout reserved disable access to internal array enable limiting dma burst to cache line size pci target cache line size reserved enable receive dmas enable transmit dmas 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 23-20 pci transfer threshold the value of these bits multiplied by eight determines the number of bytes that must be ready to transfer before a dma transfer is initiated on the pci bus. this can be used to tune the performance of the pci bus. if the number of bytes left to transfer is less than the threshold, the transfer will start when all remaining bytes are ready to be transferred. 19-16 memory transfer threshold the value of these bits multiplied by eight determine the number of bytes that must be ready to transfer before a transfer is initiated on the internal memory bus. this can be used to tune the performance of the memory subsystem. 15-8 dma transaction timeout these bits hold a value that is used to count the number of cycles that an unacknowl- edged dma cycle is in progress. if the count is reached, due to an internal chip hang condition, the dma is terminated. a value of zero will disable this function. 7 reserved. was clear checksum to all ones. now handled in dmaqs. when this bit is set, the gpdma checksum register is set to 0xffff when it is cleared. when this bit is cleared, thegpdmachecksumregisterissettozero.thisoptionshouldbeusedifthetcp/ip checksum should never be set to zero (0xffff is zero also). 6 disable access to internal array. when this bit is set, the internal array cannot be read or written. this can be used to ensure that the array is not inadvertently read or written while dmas are in progress, causing unpredictable results. 5 enable limiting dma burst to cache line size. this bit on will cause a dma burst to terminate upon crossing a cache line boundary of the pci target. IBM2520L8767 ibm processor for atm resources general purpose dma (gpdma) page 136 of 553 atmrm.chapt04.01 08/27/99 4.4: gpdma source address register used to set and keep track of the source address during a dma transfer. this is the system address that will increment during a dma transfer. a bit in the transfer count and flag register will determine if the source address is internal to the IBM2520L8767 or is a system address. 4.5: gpdma destination address register used to set and keep track of the destination address during a dma transfer. this is the destination address that will increment during a dma transfer. a bit in the transfer count and flag register will determine if the destination address is internal to the IBM2520L8767 or is a system address. 4-3 pci target cache line size. this field will indicate the cache line size if aligning dmas to the cache line size of the pci target (see bit 5). 00 32 bytes 01 64 bytes 10 128 bytes 11 256 bytes 2 reserved. was enable descriptor dmas. now handled in dmaqs. this bit on will enable dma transfers to be initiated by dma descriptors. 1 enable receive dmas. this bit on will enable dma transfers out of the IBM2520L8767. 0 enable transmit dmas. this bit on will enable dma transfers into the IBM2520L8767. length 32 bits type read/write address xxxx 0128 power on value x?00000000? restrictions none length 32 bits type read/write address xxxx 0130 power on value x?00000000? restrictions none bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 general purpose dma (gpdma) page 137 of 553 4.6: gpdma transfer count and flag register specifies the type and number of bytes transferred during a dma transfer. the lower 16 bits are a counter of the number of bytes transferred during a dma transfer. it is a count down counter; when zero is reached, the transfer ends. writing a nonzero value to the lower 16 bits will start the dma transfer. the upper 16 bits specify the type of transfer as follows. length 32 bits type read/write address xxxx 0138 power on value x?000000? restrictions none reserved reserved. was clear checksum/hold dest reserved. was compute checksum/hold src little endian mode reserved hold mode reserved reserved reserved register/memory destination address system/IBM2520L8767 destination address data/address source address reserved register/memory source address system/IBM2520L8767 source address byte transfer count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-30 reserved. these bits must be zero. 29 reserved. was clear checksum/hold dest. when this bit is on, the checksum and the alignment state are cleared. 28 reserved. was compute checksum/hold src. when this bit is set, a checksum will be computed over this dma segment. 27 little endian mode. when this bit is written to zero, this dma channel will operate in big endian mode. when one, it will operate in little endian mode. when in little endian mode both the source and destination must be aligned on four-byte boundaries. 26 reserved. reserved for word swap mode. 25 hold mode when set, bits 28-29 are redefined to allow the source or destination address to be held instead of incremented. bit 29 becomes the hold destination address and bit 28 becomes theholdsourceaddress.anaddressbeingheldmustbearegisteraddress.whenhold- ing, the maximum length is 240 bytes. IBM2520L8767 ibm processor for atm resources general purpose dma (gpdma) page 138 of 553 atmrm.chapt04.01 08/27/99 4.7: gpdma dma max burst time used to limit the number of cycles a master can burst on the pci bus. when a dma burst is started a counter is loaded with the value in this register. when the counter expires and the current access completes, the pci bus will be released for use by another bus master. writing a non zero value to this register enables this func- tion 24 reserved. was queue on dma complete. now handled by dmaqs. when this bit is set, the upper 26 bits of the gpdma system descriptor address register will be queued to the dma event queue when the dma completes. if descriptors are not being used to set up the dma, the gpdma system descriptor address register should be loaded, before starting the dma, with a value to identify this transfer. if descriptors are being used, the gpdma system descriptor address register will be loaded automatically with the system address of the descriptor block at the time it is processed. 23 reserved. was inhibit status update when dma complete. normally a bit will be set in the status register when the dma completes without error. if this bit is set, this update will not be done. this bit is useful when multiple dmas are to be done and an interrupt is only desired on the last transfer. the dma error status bits are unaffected by this bit. 22 reserved. was auto increment destination address. this bit is only used when enqueuing descrip- tors. if this bit is set the destination address will be sourced from the previous dma instead of the destination address specified in the descriptor. 21 register/memory destination address. if this bit is set, the destination address is a register address. if this bit is not set, the des- tination address is a memory address. if the destination address is a system address this bit should cleared. i/o dma cycles on the pci bus are not implemented. 20 system/IBM2520L8767 destination address. if this bit is set, the destination address is a pci bus address. if this bit is not set, the des- tination address is internal to the chip. 19 data/address source address. if this bit is set, the source address register contains the source data. if this bit is not set, the source address register contains the source address. 18 reserved. was auto increment source address. this bit is only used when enqueuing descriptors. if this bit is set, the source address will be sourced from the previous dma instead of the source address specified in the descriptor. 17 register/memory source address. if this bit is set, the source address is a register address. if this bit is not set, the source address is a memory address. if the source address is a system address, this bit should cleared. i/o dma cycles on the pci bus are not implemented. 16 system/IBM2520L8767 source address. if this bit is set, the source address is a pci bus address. if this bit is not set, the source address is internal to the chip. 15-0 byte transfer count. these bits indicate the number of bytes to transfer. a non-zero value in this field will start the dma transfer. length 24 bits type read/write address xxxx 0158 power on value x?000? restrictions none bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 general purpose dma (gpdma) page 139 of 553 4.8: gpdma checksum register this register contains the accumulated checksum. this register will contain the accumulated checksum value. it can also be used to initialize the checksum with a seed value. the most significant bit contains the alignment state (1 = odd, 0 = even alignment). this register can be read at four different addresses. the base address will return the unmodified accumulated checksum. the base address +4 will return the inverted accu- mulated checksum. the base address + 8 will return the byte-swapped accumulated checksum. the base address + 12 will return the inverted byte-swapped accumulated checksum. 4.9: gpdma read dma byte count counts bytes dmaed into the IBM2520L8767. this register will count the bytes transferred into the IBM2520L8767 by the dma controller. descriptor bytes can optionally be included. (see gpdma control register for details). 4.10: gpdma write dma byte count counts bytes dmaed out of the IBM2520L8767 description. this register will count the bytes transferred out of the IBM2520L8767 by the dma controller. length 17 bits type read/write address xxxx 0160 power on value x?00000? restrictions none length 32 bits type read/write address xxxx 0178 power on value x?00000000? restrictions none length 32 bits type read/write address xxxx 017c power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources general purpose dma (gpdma) page 140 of 553 atmrm.chapt04.01 08/27/99 4.11: gpdma array reads the contents of the internal array. the internal array is used to hold data for the dma. length 32 words x 32 bits type read/write address xxxx 0180-ff power on value x?00000000? restrictions this address space is for diagnostic use only. it should not be read or written during normal operation. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 141 of 553 memory controlling entities entity 5: the dram controllers (comet/pakit) this section describes the function of the comet/pakit entities. comet is the memory controller for con- trol memory and pakit is the memory controller for packet memory. each controller can support the following types of memory: extended data out (edo) dram with a 60ns row access time and a 30ns page cycle. supports memory sizes of 1mb, 2mb, 4mb, 8mb, 16mb, 32mb, 64mb, 128mb. synchronous dram?s running at 66mhz (15ns cycle time) with a cas latency of 2 or 3, a burst length of 1 or 2. supports memory sizes of 1mb, 2mb, 4mb, 8mb, 16mb, 32mb, 64mb, 128mb. note that the cycle time of the sdram clock is a constant on the IBM2520L8767. any sdram part selected must be capable of running at 66mhz or faster at the desired cas latency. synchronous sram running at 66mhz (15ns cycle time) with a read latency of 1 or 2 and a write latency of 0 or 1 (late write). supports memory sizes of 1mb, 2mb, 4mb, or 8mb. for any memory configuration, modules must be selected such that the loading on any memory net (including card wiring) does not exceed 120pf. the number of column address lines is programmable, allowing both drams with symmetric address (same number of row and column address lines) and asymmetric (typically having more row than column address lines). the memory may be operated with one ras line or two. if the memory is configured to have two ras lines (arrays), the memory address range is split equally between the two ras lines (arrays). memory checking can be enabled/disabled and the method of checking selected can be either ecc or parity. if ecc is selected, seven data bits are used for ecc over the 32 data bits. if parity is selected, four data bits are used to provide parity over the 32 data bits. comet/pakit are designed so that memory contents will be preserved over a reset. if the IBM2520L8767 is reset while a memory write cycle is in progress, the cycle will be completed in an orderly fashion to ensure that valid ecc/parity is written. memory timings are not violated when reset goes active. refresh is main- tained during the reset. IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 142 of 553 atmrm.chapt04.01 08/27/99 5.1: memory reset sequence 1. after a reset, onboard rom or external firmware must properly configure the control registers for comet/pakit. 2. if using edo or sram, the reset sequence is complete. if using sdram, bit 0 of the memory controller?s sdram command and status register must be written to a ?1? to force the sdrams out of the self refresh state. 3. when the sdrams exit the self refresh state, bit 4 of the memory controller?s sdram command and status register will read as ?0? when this is detected, bit 2 of the same register must be written to ?1? to ini- tiate the sdram por sequence. 4. after the por sequence is complete, bit 5 will read ?0?. the sdram por sequence is now complete. note: memory configuration errors will occur if an attempt is made to use memory that is configured incor- rectly or if attempting to use sdram before the por sequence is completed. note: accesses to the first 0x20 bytes of memory (control or packet) are not allowed unless bit 26 of the cor- responding memory control register is set. with this restriction in place, accesses with zero-valued pointers will cause the zero address error bit in the memory controller?s status register to be set. the two entities have identical registers so they are only described once. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 143 of 553 5.2: comet/pakit control register this register contains the information which controls the functions of the entity. see note on set/clear/read type registers on page 71 for more details on addressing. before this register can be altered, writing it must be enabled in comet/pakit memory controller write e nable register (described on page 152). length 32 bits type read/write comet address xxxx 0900 and 04 pakit address xxxx 0980 and 84 restrictions: power on value: x?00000000? reserved memory data clock control sdram mode register programming control disable zero address error detection state information selection zbt sram sdram split ecc sdram burst length of 2 edo t sch freeze dram error registers latch dram error registers on single bit errors enable ecc or parity sram byte enables for writes only disable sdram overlapped bank accesses/shorten sram write duration parity or ecc sram late write mode sram module width sram or sdram latency memory type memory unpopulated dram column address size memory size number of dram arrays 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-29 reserved. reserved 28 memory data clock control. when set to ?1?, the returned memory output clock will be used to latch memory data. when a set to ?0?, an internal IBM2520L8767 c clock will be used. 27 sdram mode register programming control. when using sdram, this bit, set to ?0? will use the latency and the burst information available in this register to program the mode register. set to ?1?, bits 23-8 of the sdram command and status register will be used. 26 disable zero address error detection. when set to ?1?, this bit will disable the detection of zero address errors to memory. 25-24 state information selection. these bits control what will be visible on the enstate outputs if comet/pakit are selected for observation on the enstate pins. IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 144 of 553 atmrm.chapt04.01 08/27/99 23 zbt sram. if using zero bus turnaround (zbt) srams, this bit should be set to ?1?. otherwise, it should be set to ?0?. zbt is supported only for a latency of 2 and is mutually exclusive with sram late write mode. 22 sdram split ecc. when set to ?1?, this bit indicates that the ecc for multiple arrays of memory are in sep- arate modules. if this bit ?0?, the ecc is in a shared module. this bit applies only when sdram is being used. 21 sdram burst length of 2. when set to ?1?, this bit indicates that the sdram should be driven assuming a burst length of 2. this bit set to ?0? indicates a burst length of 1. 20 edo t sch . when set to ?1?, this bit will increase the dram timing parameter t csh to 60 nanosec- onds. otherwise, t csh is equal to 45ns. 19 freeze dram error registers. when set to ?1?, this bit will freeze the memory address register and the dram ecc syndrome register when a memory error occurs. when this bit is set to ?0?, the error registers are updated whenever an error is encountered. for this bit to have any mean- ing with single bit errors, bit 18 must also be ?1?. 18 latch dram error registers on single bit errors. when set to ?1?, this bit will allow error data to be latched into the memory error address register and the dram ecc syndrome register when a single bit error occurs. when this bit is set to ?0?, single bits errors do not latch data into the error registers. 17 enable ecc or parity. this bit set to ?1? will enable ecc detection/correction or parity error detection. 16 sram byte enables for writes only. this bit set to ?1.? will cause byte enables to only be driven on writes to sram. the enables will be driven inactive for reads. if the bit is set to ?0?, the byte enables are valid on both reads and writes. 15 disable sdram overlapped bank accesses/shorten sram write duration. when the memory controller is configured for sdram, setting this bit to ?1? will disable the overlapping of bank accesses. when configured for sram, setting this bit to ?1? will shorten the time the IBM2520L8767 drives data on writes. 14 parity or ecc this bit set to ?1? will cause parity to be generated. this bit set to ?0? causes ecc to be generated. ecc is supported for dram only. 13 sram late write mode when set to ?1?, this bit will allow sram write data to be driven one cycle after the con- trol signals. this bit set to ?0.? indicates write data must be driven simultaneously with the control signals. 12 sram module width this bit set to a ?1? indicates that sram modules are 36 bits wide. this bit set to ?0? indi- cates the sram modules are 18 bits wide. 11-10 sram or sdram latency these bits indicate the delay between performing a read and the memory returning data. the bits are encoded as follows: 00 1 cycle (sram only) 01 2 cycles 10 3 cycles (sdram only) 11 reserved 9-8 memory type these bits indicate the type of memory being used for memory. the bits are encoded as follows: 00 sram 01 t rac =60, cas= 15.0 on/15.0 off edo dram 10 66 mhz synchronous dram (sdram) 11 66 mhz enhanced synchronous dram (sdram) 7 memory unpopulated. if this bit is ?1?, there is no physical memory connected to this controller. bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 145 of 553 6-4 dram column address size these bits indicate the number of column address lines. the bits are encoded as fol- lows: 000 8 column address lines (256 words/row) 001 9 column address lines (512 words/row) 010 10 column address lines (1k words/row) 011 11 column address lines (2k words/row) - edo only 100 12 column address lines (4k words/row) - edo only 101 7 column address lines (128 words/row) 110 reserved 111 reserved 3-1 memory size these bits indicate the amount of memory present. the bits are encoded as follows: 000 1 mb - sram or edo dram 001 2 mb - sram or edo dram 010 4 mb - sram or dram 011 8 mb - sram or dram 100 16 mb - dram 101 32 mb - dram 110 64 mb - dram 111 128 mb - dram 0 number of dram arrays. this two bit indicates the number of arrays of dram present. this bit set to ?0? indicates 1 array and the bit set to ?1? indicates 2 arrays. bit(s) function description IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 146 of 553 atmrm.chapt04.01 08/27/99 5.3: comet/pakit status register this register contains status information for comet/pakit. see note on set/clear/read type registers on page 71 for more details on addressing. length 6bits type read/write comet address xxxx 0908 and 0c pakit address xxxx 0988 and 8c restrictions power on value: x?00000000? zero address error memory configuration error uncorrectable error detected single bit error memory address out of range error reserved 543210 bit(s) function description 31-6 reserved. reserved 5 zero address error this bit will be set if comet/pakit is presented an address of zero. 4 memory configuration error this bit will be set if comet/pakit is configured in an invalid combination. 3 uncorrectable error detected. this bit will be set if an uncorrectable error is detected. 2 single bit error this bit will be set if a single bit ecc error is detected. 1 memory address out of range error. this bit will be set if the address presented to the memory controller is out of the defined range. 0 reserved. reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 147 of 553 5.4: comet/pakit interrupt enable register this register contains bits corresponding to the bits in the comet/pakit status register. if a bit in this regis- ter is set and the corresponding bit is set in the comet/pakit status register, an interrupt is generated. see note on set/clear/read type registers on page 71 for more details on addressing. 5.5: comet/pakit lock enable register this register contains bits corresponding to the bits in the comet/pakit status register. if a bit in this regis- ter is set and the corresponding bit is set in the comet/pakit status register, a signal is sent to vimem indi- cating that memory should be locked. see note on set/clear/read type registers on page 71 for more details on addressing. 5.6: comet/pakit memory error address register this register holds the address at which the last memory error occurred. length 6bits type read/write comet address xxxx 0910 and 14 pakit address xxxx 0990 and 94 restrictions power on value: x?0000003a? length 6bits type read/write comet address xxxx 0918 and 1c pakit address xxxx 0998 and 9c restrictions power on value: x?0000003a? length 32 bits type read only comet address xxxx 0920 pakit address xxxx 09a0 restrictions power on value: x?00000000? reserved error address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-27 reserved. reserved 26-0 error address. the real address of the last memory error. IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 148 of 553 atmrm.chapt04.01 08/27/99 5.7: comet/pakit sdram command and status register this register is used to issue various commands to the synchronous drams when they are attached to the IBM2520L8767. if the IBM2520L8767 is not configured for sdrams, any writes to this register will be ignored (except for bits 23 - 8). this register is also used to reflect the status of the synchronous drams. when a command bit in this register is set (bits 2-0 only), the command will execute and reset the bit upon completion. only one bit (2-0 only) may be set during any write. software should poll this register to make sure the previous command has completed before issuing another write to this register. if more than one bit at a time is written to this register (2-0 only) the results may be unpredictable. length 32 bits type read/write comet address xxxx 0924 pakit address xxxx 09a4 restrictions power on value: x?00003030? reserved command register data reserved por self refresh reserved start power on reset sequence enter the self refresh state exit the self refresh state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-24 reserved. reserved 23-8 command register data. the value of these bits will be placed on synchronous dram address bits a15-a0 when the synchronous dram command register is written during the por sequence (see bit 2 of this register). these bits power up to x?0030?. 23-15 shouldbewrittentozero. 14-12 should be set to the desired cas latency. only latency 2 and 3 are supported. 11 should be set to ?0? for sequential addressing. 10-8 should be set to the burst length. only burst length 1 and 2 are supported. 7-6 reserved. reserved 5por when set to ?1?, this bit indicates the por sequence has not been performed on the sdrams. this bit will automatically reset to ?0? when the por sequence has been performed. 4selfrefresh this bit will read ?1? when the sdrams are in the self refresh state. this bit will read ?0? when the sdrams are not in the self refresh state. this bit will be a ?1? after a por or reset. the exit self refresh operation must be performed before the por sequence is initiated. 3 reserved. reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 149 of 553 5.8: comet/pakit dram refresh rate register this register holds the value of a counter used to control the rate of refresh for the dram. 2 start power on reset sequence. when set to ?1?, this bit will cause the dram controller to initiate the sdram power on sequence. this includes an all banks precharge, following by a command register write that will set the cas latency to 3, the wrap type to sequential, and the burst length to 1, followed by two refresh cycles. after this sequence is initiated, this bit will reset. when bit 5 has cleared, the sdrams are ready for normal use. 1 enter the self refresh state. when set to ?1?, this bit will cause the sdram controller to signal the sdrams to go into the self refresh state. all memory activity is suspended. this bit resets nearly instantly; bit 4 should be polled to determine if the sdrams have entered the self refresh state. 0 exit the self refresh state. when set to ?1?, this bit will cause the sdram controller to signal the sdrams to exit the self refresh state. this bit resets nearly instantly; bit 4 should be polled to deter- mine if the sdrams have exited the self refresh state. length 32 bits type read/write comet address xxxx 0928 pakit address xxxx 09a8 restrictions power on value: x?000009e6? reserved refresh rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-12 reserved. reserved 11-0 refresh rate. these bits are used to compare against the output of a polynomial counter. a polyno- mial counter is a shift register with an xor feedback. it does not count in the same order as a binary counter, but uses less logic to implement. when the comparison is a match, a refresh is required by the dram. this register powers up to a refresh interval of 15.6 microseconds. bit(s) function description IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 150 of 553 atmrm.chapt04.01 08/27/99 5.9: comet/pakit syndrome register this register holds the syndrome bits that can be used to isolate the data or check bit in error when ecc is used. when parity is used, this register will indicate which of the four bytes of the memory bus had a parity error. length 7bits type read/write comet address xxxx 092c pakit address xxxx 09ac restrictions power on value: x?00000000? syndrome bits 6543210 bit(s) function description bits 31-7 reserved reserved. 6-0 syndrome bits when using ecc, a single bit error can be identified by matching the contents of this regis- ter to the corresponding bit in the table below. when using parity, only bits 3-0 are valid and are interpreted as follows: 0000 no parity error 0001 parity error on bits 7-0 0010 parity error on bits 15-8 0100 parity error on bits 23-16 1000 parity error on bits 31-24 other reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the dram controllers (comet/pakit) page 151 of 553 ecc syndrome bits bit in error syndromes bit in error syndromes ecc(6) ?1000000? ecc(5) ?0100000? ecc(4) ?0010000? ecc(3) ?0001000? ecc(2) ?0000100? ecc(1) ?0000010? ecc(0) ?0000001? n/a n/a data(31) ?0111000? data(30) ?0110100? data(29) ?0110010? data(28) ?0101100? data(27) ?1110000? data(26) ?1101000? data(25) ?1100100? data(24) ?1100010? data(23) ?0100101? data(22) ?0010101? data(21) ?0001101? data(20) ?1100001? data(19) ?0110001? data(18) ?0101001? data(17) ?0011001? data(16) ?1000101? data(15) ?1010001? data(14) ?1001100? data(13) ?1001010? data(12) ?1000110? data(11) ?1000011? data(10) ?1011000? data(09) ?1010100? data(08) ?1010010? data(07) ?0100011? data(06) ?0010011? data(05) ?0001011? data(04) ?0000111? data(03) ?0011010? data(02) ?0100110? data(01) ?0010110? data(00) ?0001110? IBM2520L8767 ibm processor for atm resources the dram controllers (comet/pakit) page 152 of 553 atmrm.chapt04.01 08/27/99 5.10: comet/pakit checkbit inversion register this register can be used for diagnostic purposes to invert the ecc/parity check bits that are written to mem- ory. 5.11: comet/pakit memory controller write enable register this register must be written to a specific pattern before the memory control register can be written. length 32 bits type read/write comet address xxxx 0930 pakit address xxxx 09b0 restrictions power on value: x?00000000? reserved invert check bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-7 reserved reserved. 6-0 invert check bits setting any of these bits will invert the corresponding check bit that is written to memory. only bits 3-0 are valid when parity is used as a checking mechanism. length 32 bits type read/write comet address xxxx 0934 pakit address xxxx 09b4 restrictions power on value: x?000000b4? reserved lock bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-8 reserved reserved. 7-0 lock bits this register must be written to a x?b4? before the memory control register can be writ- ten. this register will por to x?b4?, but crisco code will set up the memory controller and clear this register back to x?0?. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 153 of 553 entity 6: atm virtual memory logic (vimem) this entity is responsible for adjustment of all addresses provided to the memory control entities. all addresses can be categorized into three distinct types, based entirely upon the location of the requested address with respect to the three base registers defined in this entity. the three types of addresses will be referred to as control, real packet, and virtual packet addresses. all memory requests arriving on the control memory bus are handled as control memory accesses, and simply have the contents of the control memory base register subtracted from them before being passed on to the control memory entity. when the processor accesses memory, the cache controller compares the requested address to the real packet memory base register and if the address is less than the base register, the request is routed to the control memory bus, else it is routed to the packet memory bus. all requests arriving on the packet memory bus are compared to the virtual memory base address register. if the address of the request is less than the base register, the contents of the real packet memory base register are subtracted from the address and this address is passed on to the packet memory control entity. if the requested address is greater than or equal to the base register, a more complex, but flexible scheme is used to determine the real address to provide to the packet memory control entity. for a detailed explanation of the virtual address generation scheme refer to virtual memory overview on page 197 and the accompanying figures. 6.1: vimem virtual memory base address this register defines the starting address of the virtual address space used to manage incoming and outgoing frames. any time an access is made to virtual memory, that falls within the defined bounds of virtual memory, the contents of this register are subtracted from the virtual address to derive the true offset into virtual mem- ory. this true offset, along with the known length of all virtual buffers, allows the index of the specific virtual buffer to be derived by the virtual memory access hardware. this index can then be used to access the real buffer map associated with this virtual buffer. length 32 bits type read/write address xxxx 0d10 power on value x?0040 0000? restrictions the start of virtual address space must begin on a 128-kb boundary. for this rea- son, the lowest 17 bits of this register are forced to zero and are not implemented. writes of any value to the low 17 bits of this register will be ignored, and a read will always return zero for the low 17 bits. base address of virtual memory 128kb boundary restriction - not implemented 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 these bits contain the upper 15 bits of the base address of virtual memory. 16-0 these bits will be forced to zero because the virtual memory base address must start on a 128k byte boundary. IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 154 of 553 atmrm.chapt04.01 08/27/99 6.2: vimem control memory base address this register defines the starting address of the control memory address space. any time an access is made to control memory, the contents of this register is subtracted from the address before an access to memory occurs. length 32 bits type read/write address xxxx 0d14 power on value x?0000 0000? restrictions the start of real control address space must begin on a 128-kb boundary. for this reason the lowest 17 bits of this register are forced to zero and are not imple- mented. writes of any value to the low 17 bits of this register will be ignored, and a read will always return zero for the low 17 bits. base address of real control memory 128kb boundary restriction - not implemented 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 these bits contain the upper 15 bits of the base address of real control memory. 16-0 these bits will be forced to zero because the real control memory base address must start on a 128k byte boundary. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 155 of 553 6.3: vimem packet memory base address this register defines the starting address of the packet memory address space. any time an access is made to packet memory, the contents of this register is subtracted from the address before an access to memory occurs. length 32 bits type read/write address xxxx 0d18 power on value x?0020 0000? restrictions the start of real packet address space must begin on a 128-kb boundary. for this reason the lowest 17 bits of this register are forced to zero and are not imple- mented. writes of any value to the low 17 bits of this register will be ignored, and a read will always return zero for the low 17 bits. this register must also be set up before any of the real buffer base registers, or the virtual buffer map registers are written. base address of real packet memory 128kb boundary restriction - not implemented 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 these bits contain the upper 15 bits of the base address of real packet memory. 16-0 these bits will be forced to zero because the real packet memory base address must start on a 128-kb boundary. IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 156 of 553 atmrm.chapt04.01 08/27/99 6.4: vimem virtual memory total bytes this register defines the total number of bytes in the address space being allocated for virtual memory. the contents of this register, divided by the configured size of virtual buffers, will yield the total number of virtual buffer indices that should be used to initialize pools. the value of the indices should range from this calcu- lated value minus 1, down to zero. if an address is determined to be above or equal to the virtual memory base register it is assumed to be a virtual access. if the virtual buffer index derived from the requested address indicates that the virtual buffer space being accessed is above the limit defined by this register an error will be generated. length 32 bits type read/write address xxxx 0d0c power on value x?0001 0000? restrictions the maximum value that should be set in this register is (65535 * virtual buffer size). for example, if 64-byte virtual buffers are configured, the maximum value that should be loaded into this register is x?3fffc0?. virtual memory address space not implemented 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 these bits contain the upper 26 bits of the total number of bytes of address space being reserved for virtual memory. 5-0 these bits are not implemented and will be forced to zero because the virtual memory block can only be allocated in incrementsofthecurrentvirtualbuffersize(minimumsizeis64bytes). IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 157 of 553 6.5: vimem virtual/real memory buffer size this register defines the total number of bytes to be occupied by each of the virtual or real buffers as well as the spacing from one buffer to the next. length 4bits type read/write address xxxx 0d04 power on value x?2? restrictions care must be taken to set this register to a large enough value to contain the entire frame being sent as well as certain control information that the hardware stores in the buffer header. for example if the maximum frame being sent or received is 1024 bytes long, then this register should be set to indicate 2048-byte frames to allow sufficient room for the buffer header information added by the hardware. virtual/real buffer size 3210 bit(s) description 3-0 these bits contain the encoded 4-bit value that defines the virtual/real buffer size. the encoding is as follows: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 reserved IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 158 of 553 atmrm.chapt04.01 08/27/99 6.6: vimem packet memory offset this register contains the number that will be added by the vimem access logic to all accesses of real packet memory that occur. in a high performance configuration (separate control and packet store), this register should be written to all zeros to indicate that all accesses of real packet memory do not require any additional offset to be added. in a medium performance configuration (combined control and packet store), this register should be loaded with a value that indicates the logical partitioning between control and packet storage. if for instance, a single bank of 2 meg was configured and this register was loaded with x?00100000? (1 meg), then all accesses to real packet memory would be forced into the 1-meg to 2-meg range. 6.7: vimem maximum buffer size this register is used by the virtual memory logic to determine if an access to a virtual buffer falls into the region of the buffer that can be accessed. if a virtual buffer read or write accesses an offset in a virtual buffer that is greater than the contents of this register, the virtual memory logic can be configured to halt and gener- ate an interrupt. the power up value of all ?1?s will cause this check to be disabled. this register is intended to provide the user with a means of providing additional protection to accesses of the virtual buffers. for exam- ple, if this register is loaded with x?ff8?, all memory access up to and including the byte at address x?fff? will be allowed. any access of offset x?1000? or above will cause an exception. length 32 bits type read/write address xxxx 0d3c power on value: x?0000 0000? restrictions this register should only be loaded with a non-zero value if a medium performance configuration (combined control and packet store) exists. the value loaded must be between zero and the maximum of the total amount of memory in the single bank, and it must be on a 128-kb boundary. any time the value in this register is changed, the related base registers must be reloaded because the value loaded into them is affected by the contents of this register during the load operation. the related registers are the virtual buffer map base address register and all five real buffer base registers. length 17 bits type read/write address xxxx 0d34 power on value x?1 fff8? restrictions all address logic based on this register only recognizes eight-byte words in mem- ory. for this reason, the low three bits of this register are not implemented and will always be forced to zeros. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 159 of 553 6.8: vimem access control register the bits in this register control the configurable features of the virtual memory logic. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type read/write address xxxx 0d80 and 84 power on value x?0? restrictions none reserved ignore virtual buffer map fetch required map serialize packet memory control access priority reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 reserved. 15 when set, this bit will force the virtual memory logic to ignore the virtual buffer map validity indication, and force all maps to appear valid. 14 when set, this bit will force the virtual memory logic to fetch the required map entry from storage on every new virtual access. if a virtual memory map is updated by the software for any reason, this bit should be toggled on and off after the map is updated and before any virtual access happens to ensure that the virtual memory logic is not using stale cached map segments. there is no hardware provided to make sure that the map entry required by the virtual memory logic is not contained in one of the bcach lines. if is the responsibility of the software to ensure that all modified lines are flushed from the cache before the virtual memory logic needs them. 13 when set, this bit will force all accesses to packet memory to be serialized. 12 when set, this bit will cause control accesses to always have priority over packet accesses in a single memory bank con- figuration. when reset, priority will toggle every time an access is initiated. 11-0 reserved. IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 160 of 553 atmrm.chapt04.01 08/27/99 6.9: vimem access status register this register contains information regarding the current status of the virtual memory logic mainly with respect to detected error access conditions. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type read/write address xxxx 0d60 and 64 power on value x?0000? restrictions none reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 reserved. 16 when set, this bit indicates that the required conditions for the control, packet, and virtual base registers has not been satis- fied. the required conditions are: control base < packet base < virtual base 15 when set, this bit indicates that the virtual memory logic has detected a page fault error when attempting to read memory. this indicates that no real buffer was available to map into the virtual address space when required. all virtual reads that fail during a page fault regardless of the requesting entity will cause this bit to be set. if the corresponding bit is reset in the lock register, the read operation will complete, but with invalid data. 14 when set, this bit indicates that a control memory access was detected that was above the value contained in the packet memory offset register for single bank configurations, or in a multiple bank configuration that the high address bits 31 - 27 were not zero. 13 when set, this bit indicates that a packet memory access of address zero was detected in single bank mode, or that a packet address was detected that contained an address out of range (high five bits non-zero). 12 when set, this bit indicates that the virtual memory logic has detected a virtual memory operation that attempted to access a map that was not marked as valid. a virtual buffer map is marked valid by the pools entity when the buffer is originally acquired, and is marked as invalid when the buffer is freed back to pools. receiving this error indication, typically means that the software is trying to use a buffer that has not been acquired through the normal means, or trying to use a buffer that has already be freed, or that memory has been corrupted. the valid indication that is checked by the hardware is the value x??656? in the first 16 bits of the eight-byte map entry being accessed. to determine the failing address, the memory control entity can be locked on this type of failure, and the information saved by the memory controller, along with the base registers in this entity can be used to determine which map was being accessed at the time of failure. 11 when set, this bit indicates that the virtual memory logic has detected a non-recoverable page fault error when attempting to write memory. this indicates that no real buffer was available to map into the virtual address space when required. all virtual writes that fail during a page fault with the exception of bcach and raall operations will cause this bit to be set. 10 when set, this bit indicates that the virtual memory logic has detected a recoverable page fault error when attempting to write memory. this indicates that no real buffer was available to map into the virtual address space when required. operations from bcach and raall will cause this bit to be set instead of the non-recoverable bit because the software can recover from these failures. if a bcach write to virtual memory fails in this manner, the packet header of the frame being updated will be updated to indicate the failure. software can check the field in the packet header to ensure that the dma operation completed successfully. if such a packet is enqueued to csked, the packet header is checked and will prevent the frame from being passed on to the segmentation logic. the frame will generate a bad transmit event in rxque instead. if a failure is indicated, the software must perform any required recovery actions. if a raall write to virtual memory fails in this manner, the packet currently being received is dropped, it is up to the software to perform any recovery operations that are required. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 161 of 553 09 when set, this bit indicates that the virtual memory logic has detected a read operation that caused a page fault. this is an invalid condition because the data required for a read operation should have been previously initialized by a write operation, so no page fault should ever occur on a read operation. if the corresponding bit in the lock register is reset, a page will be mapped into the current virtual buffer segment and the data that previously was written in that page will be returned. this bit can come on in several situations that are not really errors. in these cases, the associated interrupt and lock bits can be reset so that this error does not cause the adapter to halt normal operation. several of these conditions are: when predictive fill is enabled, a read from the end of a buffer may cause a predictive read that crosses a virtual segment boundary and causes this bit to be set. if a small buffer (fits entirely in the cache) is copied from one IBM2520L8767 buffer to another IBM2520L8767 buffer, a subsequent read of the last bytes written will cause this bit to be set if the cache hasn?t been flushed between the write and the read, and the last write cycle did not write all 4 bytes, and the address that is being written/read is within the first 0x20 bytes of a virtual segment. 08 when set, this bit indicates that the virtual memory logic has detected an access of a virtual buffer that falls above the limit set by the buffer maximum size register. 07 when set, this bit indicates that the virtual memory logic has detected an access that does not fall in one of the currently mapped buffer segments based upon the currently-configured virtual buffer map size. 06 when set, this bit indicates that a virtual access has been detected that used a base register that had an invalid associated buffer size configured in the low order bits. 05 when set, this bit indicates that a virtual access has been detected that used a base register that was not on the correct memory boundary. for example, if a base register is set up to use 2-kb buffers, then the base register must be set up on a 2-kb boundary. 04 when set, this bit indicates that a virtual access has been detected that used a base register that contained a value of 0. 03 reserved. 02 when set, this bit indicates that the virtual memory logic has detected a memory access that resulted in the generation of a buffer index that was greater than the currently configured maximum derived from the vimem virtual memory total bytes reg- ister. 01 when set, this bit indicates that the currently configured size of buffers is invalid. 00 when set, this bit indicates that the map base register contains an invalid value. two possible causes are that bits 5-2 are not zero or bits 31-6 are zero. bit(s) description IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 162 of 553 atmrm.chapt04.01 08/27/99 6.10: vimem access status interrupt enable register this register allows the user to enable interrupts for each of the conditions reported in the vimem access status register. each bit corresponds to the same bit in the status register and when set to a ?1? will generate an interrupt to the processor if the condition is detected. see note on set/clear/read type registers on page 71 for more details on addressing. 6.11: vimem memory lock enable register this register allows the user to selectively allow each of the conditions reported in the vimem access status register to force a memory lock condition in the memory controller. each bit corresponds to the same bit in the status register and when set to a ?1? will cause a memory lock if the condition is detected. see note on set/clear/read type registers on page 71 for more details on addressing. length 17 bits type read/write address xxxx 0d68 and 6c power on value x?1ffff? restrictions none length 17 bits type read/write address xxxx 0d70 and 74 power on value x?1ffff? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 163 of 553 6.12: vimem state machine current state this register provides feedback to the user regarding the current status of the state machines in vimem. one use of this register is to make sure that the required initialization time has expired after loading the segment size register. this is accomplished by reading this register repeatedly until the initialization state machine is in theidlestate. length 9bits type read only address xxxx 0d78 power on value x?1?0? restrictions none state of initialization state machine current state 876543210 bit(s) description 8-4 these bits contain the current state of the initialization state machine. a value of "1----" indicates that the state machine is in the idle state. 3-0 these bits contain the current state of the vimem main state machine. a value of "0000" indicates that the state machine is intheidlestate. IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 164 of 553 atmrm.chapt04.01 08/27/99 6.13: vimem last processor read real address this register provides information to the user about the last read access of virtual packet memory by the pro- cessor. if a virtual address was accessed, this register will contain the real address generated by the virtual memory logic that can be used to access the same location. this register is intended mainly as an aid in debugging to make virtual address translation easier. to perform the translation, the processor must read from the desired virtual address, after the read is complete, this register will contain the real address that was accessed. the address contained in this register is an offset from the beginning of physical packet memory. length 32 bits type read only address xxxx 0d7c power on value x?0000 0000? restrictions none zero bits real address accessed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-27 these bits will always read as zero. 26-0 after any read operation from the processor to packet memory, these bits will contain the real address that was accessed. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 165 of 553 6.14: vimem virtual buffer segment size register this register, along with the lower four bits of the real buffer base registers, defines the size of the second through 16th real buffers that are concatenated to make up a virtual buffer. two bits of this register are asso- ciated with each real buffer segment and indicate one out of four possible associations. the associative pos- sibilities are shown in the bit table below. every two bit defines the connection between a particular buffer segment and the real buffer base registers. length 32 bits type read/write address xxxx 0d00 power on value x?0000 0000? restrictions care must be used when setting up this register to ensure that only values that cor- respond to real buffer sizes that pools has also been set up to provide are loaded. a write to this register causes the virtual memory logic to calculate the dif- ferent real buffer boundaries within a virtual buffer. this calculation requires infor- mation from the real buffer base registers to determine the size of the different segments making up the virtual buffer. for this reason it is required that this register be written after the real buffer base registers have been initialized. after writing this register, the software must wait at least 2 microseconds before accessing virtual memory. 16th buffer segment 15th buffer segment 14th buffer segment 13th buffer segment 12th buffer segment 11th buffer segment 10th buffer segment 9th buffer segment 8th buffer segment 7th buffer segment 6th buffer segment 5th buffer segment 4th buffer segment 3th buffer segment 2th buffer segment reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 166 of 553 atmrm.chapt04.01 08/27/99 bit(s) description bit association 31-30 defines the 16th buffer segment?s connection. 00 associates this real buffer segment with real buffer base register 0 01 associates this real buffer segment with real buffer base register 1 10 associates this real buffer segment with real buffer base register 2 11 associates this real buffer segment with real buffer base register 3 29-28 defines the 15th buffer segment?s connection. 27-26 defines the 14th buffer segment?s connection. 25-24 defines the 13th buffer segment?s connection. 23-22 defines the 12th buffer segment?s connection. 21-20 defines the 11th buffer segment?s connection. 19-18 defines the 10th buffer segment?s connection. 17-16 defines the 9th buffer segment?s connection. 15-14 defines the 8th buffer segment?s connection. 13-12 defines the 7th buffer segment?s connection. 11-10 defines the 6th buffer segment?s connection. 09-08 defines the 5th buffer segment?s connection. 07-06 defines the 4th buffer segment?s connection. 05-04 defines the 3rd buffer segment?s connection. 03-02 defines the 2nd buffer segment?s connection. 01-00 reserved. the first real buffer is implicitly associated with the virtual buffer, these bits will always be read as zero. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm virtual memory logic (vimem) page 167 of 553 6.15: vimem buffer map base address this register contains the address in packet memory at which the buffer map table starts. the buffer map table consists of a variable number of 8 byte entries for each buffer that will be allocated in the system. the first 16 bits of each 8 byte entry contains the pool id and various status flags associated with this buffer, thus this base register is used in both real and virtual memory modes. in virtual memory mode, each of the three subsequent 16 bits contains an index which is associated with a buffer size base register using the buffer segment limit register. the index and buffer size base register are used to determine a real buffer address. if the map size is set to 8 bytes, only one 8 byte entry is used for each buffer. if the map size is set to 16 bytes, two 8 byte entries are used for each buffer. if the map size is set to 32 bytes, four 8 byte entries are used for each buffer. if the map size is set to 64 bytes, five 8 byte entries are used for each buffer, the remaining 24 bytes of the map are unused by the hardware. length 32 bits type read/write address xxxx 0d08 power on value x?0020 0000? this value is actually the power up contents of the packet memory real base register added to the power up contents of this register (x?00000000?) due to the automatic address adjustment explained below. restrictions the base address for the buffer map must begin on a 64-byte boundary. when a base register is written, the hardware performs an automatic adjustment to the address using the contents of the packet memory real base register, and the packet memory offset register. this results in the actual value being stored, not being the value that is written by the program. this is done to make the virtual accesses that use the base register execute quicker. the reverse adjustment is made when the read operation is performed, so that it appears to the program no different than a normal operation. care must be taken however to ensure that both the packet memory real base register and the packet memory offset register are set-up before any of the base registers are written. if the packet memory base register or the packet memory offset register are changed, packet memory should not be accessed until all the base registers have been written again. starting address reserved map entry size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-06 defines the starting address of the buffer map 05-02 reserved, should be written with 0 01-00 defines the size of each map entry 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes IBM2520L8767 ibm processor for atm resources atm virtual memory logic (vimem) page 168 of 553 atmrm.chapt04.01 08/27/99 6.16: vimem real buffer base addresses these registers contain the address in packet memory at which a block of memory begins that is used to pro- vide a given size buffer. in general, the block allocated must be large enough to contain as many buffers as will be freed to pools on initialization, however for real buffer base 4, the size of the block reserved must be large enough so that one buffer is available for each of the virtual buffers freed to pools. these buffers must not be freed to pools because they are implicitly used as the first real buffer segment for each of the virtual buffers. if a given base register and associated buffer size is not used, the low four bits of the register should be set to x?f? to ensure that accesses of this buffer size will be detected and flagged as an error. when using real memory mode (controlled in pools), all of these base registers are unused with the excep- tion of base register zero, which contains the base address for all real memory buffers. in real mode, the low four bits of base register zero are of no significance. the size of the real buffers is controlled through the buffer size register. buffer size 01234(implicit) length 32 bits 32 bits 32 bits 32 bits 32 bits type read/write read/write read/write read/write read/write address xxxx 0d20 xxxx 0d24 xxxx 0d28 xxxx 0d2c xxxx 0d30 power on value x?0020 000f? x?0020 000f? x?0020 000f? x?0020 000f? x?0020 000f? restrictions the base address for any given buffer size must begin on a boundary that is equal to the buffer size. for example the base address for 128-byte buffers must be on a 128-byte boundary and the base address for 4096-byte buffers must be on a 4096-byte boundary. starting address reserved real buffersize 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 defines the starting address in packet memory of the memory block used to provide real buffers of defined size 5-4 reserved (user should write zeros and ignore read value) 3-0 defines the size of the real buffers in this block of memory with the following encoding: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 169 of 553 entity 7: atm packet/control memory arbitration logic (arbit) this section contains descriptions of the registers used by the arbiter logic. 7.1: arbit control priority resolution register high this register, which consists of five 4-bit fields, defines the priority of requesting entities to packet memory. length 20 bits type read/write address xxxx 0e00 restrictions none power on value x?c ba98? priority level c priority level b priority level a priority level 9 priority level 8 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 19-16 the value loaded into these bits define which entity will be requesting at priority level c (lowest priority) value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi 15-12 the value loaded into these bits define which entity will be requesting at priority level b. see description of bits 19-16 for entity values. 11-08 the value loaded into these bits define which entity will be requesting at priority level a. see description of bits 19-16 for entity values. 07-04 the value loaded into these bits define which entity will be requesting at priority level 9. see description of bits 19-16 for entity values. 03-00 the value loaded into these bits define which entity will be requesting at priority level 8. see description of bits 19-16 for entity values. IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 170 of 553 atmrm.chapt04.01 08/27/99 7.2: arbit control priority resolution register low this register, which consists of eight 4-bit fields, defines the priority of requesting entities to packet memory. length 32 bits type read/write address xxxx 0e04 restrictions none power on value x?7654 3201? priority level 7 priority level 6 priority level 5 priority level 4 priority level 3 priority level 2 priority level 1 priority level 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 the value loaded into these bits define which entity will be requesting at priority level 7. value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi 27-24 the value loaded into these bits define which entity will be requesting at priority level 6. see description of bits 31-28 for entity values. 23-20 the value loaded into these bits define which entity will be requesting at priority level 5. see description of bits 31-28 for entity values. see description of bits 31-28 for entity values. 19-16 the value loaded into these bits define which entity will be requesting at priority level 4. see description of bits 31-28 for entity values. 15-12 the value loaded into these bits define which entity will be requesting at priority level 3. see description of bits 31-28 for entity values. 11-08 the value loaded into these bits define which entity will be requesting at priority level 2. see description of bits 31-28 for entity values. 07-04 the value loaded into these bits define which entity will be requesting at priority level 1. see description of bits 31-28 for entity values. 03-00 the value loaded into these bits define which entity will be requesting at priority level 0 (highest priority). see description of bits 31-28 for entity values. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 171 of 553 7.3: arbit control error mask register the bits in this register control if arbit detected error conditions on an entities interface will lock the control memory subsystem. bits in this register also control the locking of the control memory subsystem based on control memory, packet memory, virtual memory, and bcach detected error conditions. resetting the appro- priate bit will force errors from that source to be ignored. length 18 bits type clear/set address xxxx 0e08 and 0c power on value x?3ffff? restrictions none bit(s) bit name/function 17 arbit detected packet errors 16 pools errors 15 reserved 14 bcach collision 13 virtual errors 12 packet errors 11 control errors 10 chksm 09 csked 08 reasm 07 rxque 06 pcore 05 segbf 04 raall 03 gpdma 02 dmaqs 01 pools 00 bcach IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 172 of 553 atmrm.chapt04.01 08/27/99 7.4: arbit control error source register the bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. length 18 bits type clear/set address xxxx 0e18 and 1c power on value x?00000? restrictions bits 16, 17, and 11 through 14 are driven from external entities and can not be set/reset in this register. they must be set/reset in the entity of origin. bit(s) bit name/function 17 arbit detected packet errors 16 pools errors 15 reserved 14 bcach collision 13 virtual errors 12 packet errors 11 control errors 10 chksm 09 csked 08 reasm 07 rxque 06 pcore 05 segbf 04 raall 03 gpdma 02 dmaqs 01 pools 00 bcach IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 173 of 553 7.5: arbit control winner register the bits in this register indicate which entity currently owns control memory. length 32 bits type read address xxxx 0e2c power on value x?f? restrictions none lock set/reset reserved reserved control winner b control winner a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 for performance reasons, two sets of operational latches (bank a and bank b) exist in the arbiter for control memory. when set, this bit indicates that the b latches are active, and when reset it indicates that the a latches are active. when this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. if this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that most recently was accessing memory 30 reserved. 29-8 reserved. will read zero. 7-4 control winner b 3-0 control winner a value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 174 of 553 atmrm.chapt04.01 08/27/99 7.6: arbit control address register a if latch bank a is active, the bits in this register indicate the last address that was used to access control memory. 7.7: arbit control address register b if latch bank b is active, the bits in this register indicate the last address that was used to access control memory. length 32 bits type read address xxxx 0e10 power on value x?0000 0000? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the control memory controller. length 32 bits type read address xxxx 0e20 power on value x?0000 0000? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the control memory controller. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 175 of 553 7.8: arbit control length register the bits in this register indicate the last length that was used to access control memory. length 16 bits type read address xxxx 0e14 power on value x?0000 0000? restrictions none latch bank b length latch bank a length 1514131211109876543210 bit(s) description 15-8 these bits contain the length used to access control memory through latch bank b. 7-0 these bits contain the length used to access control memory through latch bank a. IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 176 of 553 atmrm.chapt04.01 08/27/99 7.9: arbit control lock entity enable register the value programmed in this register controls what entity, if any, has access to packet memory immediately after memory has locked. this register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. length 4bits type read/write address xxxx 0e28 power on value x?f? restrictions none bit map value 3210 bit(s) description 3-0 the value in these bits map to the following entities: value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 177 of 553 7.10: arbit control config register the bits in this register control the operation of the control memory arbiter. length 2bits type clear/set address xxxx 0e38 and 3c power on value x?0? restrictions none reserved set/reset 1 0 bit(s) description 1 reserved 0 when set, this bit forces all operations to control memory to be serialized. an operation from one entity must be entirely com- plete before an operation from another entity will be started. when reset, if the memory operation in process can be over- lapped, a second operation will be started before the first operation is complete. IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 178 of 553 atmrm.chapt04.01 08/27/99 7.11: arbit packet priority resolution register high this register, which consists of five 4-bit fields, defines the priority of requesting entities to packet memory. length 20 bits type read/write address xxxx 0e80 power on value x?c ba98? restrictions none priority level c priority level b priority level a priority level 9 priority level 8 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 19-16 the value loaded into these bits defines which entity will be requesting at priority level c (lowest priority). value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi 15-12 the value loaded into these bits define which entity will be requesting at priority level b. see description of bits 19-16 for entity values. 11-08 the value loaded into these bits define which entity will be requesting at priority level a. see description of bits 19-16 for entity values. 07-04 the value loaded into these bits define which entity will be requesting at priority level 9. see description of bits 19-16 for entity values. 03-00 the value loaded into these bits define which entity will be requesting at priority level 8. see description of bits 19-16 for entity values. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 179 of 553 7.12: arbit packet priority resolution register low this register, which consists of eight 4-bit fields, defines the priority of requesting entities to packet memory. length 32 bits type read/write address xxxx 0e84 restrictions none power on value x?7654 3201? priority level 7 priority level 6 priority level 5 priority level 4 priority level 3 priority level 2 priority level 1 priority level 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 the value loaded into these bits defines which entity will be requesting at priority level 7. value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi 27-24 the value loaded into these bits define which entity will be requesting at priority level 6. see description of bits 31-28 for entity values. 23-20 the value loaded into these bits define which entity will be requesting at priority level 5. see description of bits 31-28 for entity values. 19-16 the value loaded into these bits define which entity will be requesting at priority level 4. see description of bits 31-28 for entity values. 15-12 the value loaded into these bits define which entity will be requesting at priority level 3. see description of bits 31-28 for value definitions. 11-08 the value loaded into these bits define which entity will be requesting at priority level 2. see description of bits 31-28 for entity values. 07-04 the value loaded into these bits define which entity will be requesting at priority level 1. see description of bits 31-28 for entity values. 03-00 the value loaded into these bits define which entity will be requesting at priority level 0 (highest priority). see description of bits 31-28 for entity values. IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 180 of 553 atmrm.chapt04.01 08/27/99 7.13: arbit packet entity error mask register the bits in this register control if arbit detected error conditions on an entities interface will lock the packet memory subsystem. bits in this register also control the locking of the packet memory subsystem based on control memory, packet memory, virtual memory, and bcache detected error conditions. resetting the appropriate bit will force errors from that source to be ignored. length 18 bits type clear/set address xxxx 0e88 and 8c power on value x?3ffff? restrictions none bit(s) bit name/function 17 arbit detected control errors 16 pools errors 15 re-arbitration failure 14 bcach collision 13 virtual errors 12 packet errors 11 control errors 10 chksm 09 csked 08 reasm 07 rxque 06 pcore 05 segbf 04 raall 03 gpdma 02 dmaqs 01 pool 00 bcach IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 181 of 553 7.14: arbit packet error source register the bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. length 18 bits type clear/set address xxxx 0e98 and 9c power on value x?00000? restrictions bits 17, 16, and 11 through 14 are driven from external entities and can not be set/reset in this register. they must be set/reset in the entity of origin. control errors pools errors rearbitration detected bcach collision virtual errors packet errors control errors chksm csked reasm rxque pcore segbf raall gpdma dmaqs pools bcach 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) bit name/function 17 arbit detected control errors 16 pools errors 15 rearbitration detected while already handling a rearbitration condition. this condition would indicate that the priorities pro- grammed in the priority resolution logic were incorrectly programmed and pools high was not given the highest priority. 14 bcach collision 13 virtual errors 12 packet errors 11 control errors 10 chksm 09 csked 08 reasm 07 rxque 06 pcore 05 segbf 04 raall 03 gpdma 02 dmaqs 01 pools 00 bcach IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 182 of 553 atmrm.chapt04.01 08/27/99 7.15: arbit packet winner register the bits in this register indicate which entity currently owns packet memory. length 32 bits type read address xxxx 0eac power on value x?f? restrictions none active set/reset reserved reserved packet winner b packet winner a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31 for performance reasons, two sets of operational latches (bank a and bank b) exist in the arbiter for packet memory. when set, this bit indicates that the b latches are active, and when reset indicates that the a latches are active. when this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. if this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that most recently was accessing memory 30 reserved 29-8 reserved, will read zero. 7-4 packet winner b 3-0 packet winner a value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 183 of 553 7.16: arbit packet address register a if latch bank a is active, the bits in this register indicate the last address that was used to access packet memory. 7.17: arbit packet address register b if latch bank b is active, the bits in this register indicate the last address that was used to access packet memory. length 32 bits type read address xxxx 0e90 power on value x?0000 0000? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the packet memory controller. length 32 bits type read address xxxx 0ea0 power on value x?0000 0000? restrictions none last address provided by arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the last address provided by the arbiter to the packet memory controller. IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 184 of 553 atmrm.chapt04.01 08/27/99 7.18: arbit packet length register the bits in this register indicate the last length that was used to access packet memory. length 16 bits type read address xxxx 0e94 power on value x?0000 0000? restrictions none latch bank b length latch bank a length 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15-8 these bits contain the length used to access packet memory through latch bank b 7-0 these bits contain the length used to access packet memory through latch bank a IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 atm packet/control memory arbitration logic (arbit) page 185 of 553 7.19: arbit packet lock entity enable register the value programmed in this register controls what entity, if any, has access to packet memory immediately after memory has locked. this register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. length 4bits type read/write address xxxx 0ea8 power on value x?f? restrictions none bit map value 3210 bit(s) description 3-0 the value in these bits map to the following entities: value c chksm value b bcach lo value a pools lo value 9 csked value 8 reasm value 7 rxque value 6 pcore value 5 segbf value 4 raall value 3 gpdma value 2 dmaqs value 1 pools hi value 0 bcach hi IBM2520L8767 ibm processor for atm resources atm packet/control memory arbitration logic (arbit) page 186 of 553 atmrm.chapt04.01 08/27/99 7.20: arbit packet config register the bits in this register control the operation of the packet memory arbiter. length 2bits type clear/set address xxxx 0eb8 and bc power on value x?0? restrictions none reserved set/reset 10 bit(s) description 1 reserved 0 when set, this bit forces all operations to packet memory to be serialized. an operation from one entity must be entirely com- plete before an operation from another entity will be started. when reset, if the memory operation in process can be over- lapped, a second operation will be started before the first operation is complete. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the bus dram cache controller (bcach) page 187 of 553 entity 8: the bus dram cache controller (bcach) this entity provides the caching function for data transfers on the control processor bus. the array is orga- nized in four logically separate cache lines, any of which can be used for processor accesses or master/slave dma accesses. the cache is accessible on byte boundaries on the control processor side; access of this entity to comet is performed on 64-bit (word) boundaries. the address tags of each of the four 32-byte cache lines are used to compare on the requesting address to select the bank to be used to satisfy the con- trol processor bus operation. streaming accesses of the cache use a predictive look-ahead scheme to fill the cache for read operations from packet memory. under normal conditions, a single cache miss will be expected at the start of each dma read operation. this cache miss will initiate a read operation from packet memory to fetch the requested data and enough additional data to fill the remainder of the cache line. if the requested data is in the last n bytes ( n is programmable via the bcach control register) of the cache line, the read operation to comet will be extended to fill the next cache line with sequential data as well. this same programmable value is used to determine when to initiate the next sequential cache line fill operation during a dma read operation. during non-aligned write operations to packet memory, bcach will perform read/modify/write cycles to pakit. processor accesses operate without predictive caching. when a cache miss occurs, a comet read opera- tion will be initiated to fetch the 32-byte block of data that contains the requested data. the data read from comet will be loaded into the ?least recently used? cache line. this section contains descriptions of the registers used by the bus cache logic. IBM2520L8767 ibm processor for atm resources the bus dram cache controller (bcach) page 188 of 553 atmrm.chapt04.01 08/27/99 8.1: bcach control register the bits in this register control the various functions provided by the cache logic. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 1000 and 004 power on value x?2000 0000? restrictions none enable caching packet memory reads enable caching packet memory writes retry delayed accesses bcach diagnostic mode flush cache line 3 flush cache line 2 flush cache line 1 flush cache line 0 use rxque advice ack rxque immediately enable ping pong buffer support disable locking on collisions enable automatic flush force predictive fill/flush for non-streaming accesses reserved predictive fill threshold timed flush time out value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 enable caching packet memory reads when set, reads of packet memory will be cached. 30 enable caching packet memory writes when set, writes to packet memory will be cached. 29 retry delayed accesses when set, and the cache is enabled, any access of packet memory that cannot be satis- fied within one cycle will be terminated by the cache with a retry indication. the access- ingdeviceisexpectedtoallowothercompetingdevicesachancetogainaccesstothe bus and then retry the same operation again. 28 bcach diagnostic mode when set, diagnostic mode is enabled and reads and writes of the bcach array from the processor are enabled. when reset, reads from the processor will return x?badd- badd? and writes will have no affect. care must be taken when performing writes from the processor, if a cache line fill operation is in process and a write is performed from the processor that writes to the same address in the array as is being written from the fill operation, results are indeterminate. 27 flush cache line 3 setting this bit will force a flush of cache line 3 if it is dirty. this bit will be reset by the hardware when the flush completes. 26 flush cache line 2 setting this bit will force a flush of cache line 2 if it is dirty. this bit will be reset by the hardware when the flush completes. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the bus dram cache controller (bcach) page 189 of 553 25 flush cache line 1 setting this bit will force a flush of cache line 1 if it is dirty. this bit will be reset by the hardware when the flush completes. 24 flush cache line 0 setting this bit will force a flush of cache line 0 if it is dirty. this bit will be reset by the hardware when the flush completes. 23 use rxque advice when set, advice from the receive queue entity will cause the cache logic to fill a line with the data from the start of the buffer that was just dequeued by the software. this should improve performance by having the receive data available when the processor accesses the buffer after the dequeue. to make best use of this feature, the code should access the receive data shortly after the dequeue to avoid the data in the cache line from becom- ing stale and being invalidated due to other cache functions. when reset, advice from the receive queue entity will be ignored. 22 ack rxque immediately when reset, advice from the receive queue entity will be acknowledged immediately even if the cache is not able to perform the requested data fetch. in this case, the advice will be lost, and the cache will not fetch the data until the processor requests it again. when set, the advice from the receive queue entity will not be acknowledged until the cache has actually latched the advice information. this guarantees that the advice will be used, but may cause delays in the receive queue entities processing. 21 enable ping pong buffer support when reset, this bit will disable the two-line ping pong feature associated with consistent sequential cache accesses. when set, a series of sequential accesses to packet memory that would normally require more than two cache lines to be satisfied will be limited to only two cache lines, regardless of the length of the transfer. this feature is intended to improve cache performance by preventing cache lines that contain the most recently used processor data from being flushed due to a long streaming access. 20 disable locking on collisions when set, this bit will prevent detected collisions from locking up the memory control entity. 19 enable automatic flush when set, this bit will enable the automatic flush feature of the cache. the auto flush fea- ture will force a flush of a cache line to be performed if a sequential write of the last 2 locations in the cache line is detected. 18 force predictive fill/flush for non-streaming accesses when set, this bit will force the predictive fill/flush logic to operate on all accesses of the cache and not just streaming accesses. when reset, the predictive fill logic will only be activated for streaming accesses in the cache. 17-16 reserved reserved 15-8 predictive fill threshold these bits set the threshold at which a predictive fill will be initiated. if all of these bits are set to ?1?, a predictive fill will be initiated on the first streaming access of a cache line, regardless of which byte in the line is accessed. if this field is set to x?3f? a predictive fill will be initiated on any streaming access of bytes at offset x?2? through x?7? in the cache line. if this field is set to x?03? a predictive fill will be initiated on any streaming access of bytes at offset x?6? or x?7? in the cache line. setting the field to all zeros will disable pre- dictive fills. 7-0 timed flush time out value these bits control the time-out value used to monitor dirty cache lines for inactivity. the value loaded into these eight bits is the number of 240ns ticks that can occur without any activityinadirtycachelinebeforethecachelogicwillforceaflushofthelinetomain memory. setting these bits to all zeros disables the timed flush feature. bit(s) function description IBM2520L8767 ibm processor for atm resources the bus dram cache controller (bcach) page 190 of 553 atmrm.chapt04.01 08/27/99 8.2: bcach status register the bits in this register reflect the current status of the cache. see note on set/clear/read type registers on page 71 for more details on addressing. length 8bits type clear/set address xxxx 1008 and 00c power on value x?00? restrictions none pools invalidation of dirty lines write hit on multiple lines read hit on multiple lines negative ack from vimem collision on cache line 3 collision on cache line 2 collision on cache line 1 collision on cache line 0 76543210 bit(s) function description 7 pools invalidation of dirty lines when set, this bit indicates that pools requested that the cache logic invalidate a line that was dirty. this is usually an indication that a buffer was freed by the software before data written out to the buffer had been flushed to memory. this may or may not be an error condition 6 write hit on multiple lines when set, the cache logic has detected a write hit to multiple lines. this indicates an internal logic error in the cache. 5 read hit on multiple lines when set, the cache logic has detected a read hit to multiple lines. this indicates an internal logic error in the cache. 4 negative ack from vimem when set, the cache logic has detected a negative acknowledgment from the virtual memory logic entity. this indicates that a virtual buffer boundary was crossed and a new real buffer was needed to map the requested address space into, but no real buffer was available. in addition to setting this status bit, the cache logic will write the pattern x?zzzzzbad? into the header of the packet at offset x?c? where zzzzz is the offset of the failing write into the packet. 3 collision on cache line 3 when set, the cache logic has detected a collision in cache line 3. this is a situation where another entity in the chip was accessing an area of memory that was contained in one of the cache lines that was dirty. further information for problem diagnosis is latched in the memory controller logic when this condition is detected. 2 collision on cache line 2 when set, the cache logic has detected a collision in cache line 2 1 collision on cache line 1 when set, the cache logic has detected a collision in cache line 1 0 collision on cache line 0 when set, the cache logic has detected a collision in cache line 0 IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the bus dram cache controller (bcach) page 191 of 553 8.3: bcach interrupt enable register the low eight bits in this register allow the user to selectively determine which bits in the bcach status regis- ter will cause processor interrupts. a zero in a bit position masks interrupts from the corresponding bit loca- tion in the bcach status register. a one in a bit position allows interrupts for the corresponding bit in the bcach status register. the high eight bits in this register allow the user to selectively determine which bits in the bcach status register will lock the cache. a one in any bit position will force the cache to lock if the cor- responding bit is set in the bcach status register. if the cache locks, all status regarding the cache lines is maintained until the cache enable bits in the control register are turned off. see note on set/clear/read type registers on page 71 for more details on addressing. 8.4: bcach high priority timer value the contents of this register define the number of 30ns cycles that will pass from the time that a valid pci bus request is raised to bcach until bcach will raise it?s high priority request to the memory controllers. a value of zero in this register will disable this function completely. length 16 bits type clear/set address xxxx 1010 and 014 power on value x?ffff? restrictions none length 8bits type read/write address xxxx 1040 power on value x?40? restrictions none number of 30ns cycles 76543210 bit(s) description 7-0 determines the number of 30ns cycles before a high priority request IBM2520L8767 ibm processor for atm resources the bus dram cache controller (bcach) page 192 of 553 atmrm.chapt04.01 08/27/99 8.5: bcach line tag registers these registers are useful only in diagnostic testing of the cache logic. each register will contain the tag value for the data contained in that particular cache line. length 32 bits type read only address tag number 0 xxxx 1080 tag number 1 xxxx 10a0 tag number 2 xxxx 10c0 tag number 3 xxxx 10c0 power on value x?0000 0000? restrictions none 32-bit memory line address modulo read fill op. reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-05 these bits contain the address of the 32-byte line of memory contained in the cache line. 04-03 in an attempt to provide the fastest possible access to data in memory, the 8 byte word in memory that contains the requested read data is accessed first and all other entries in the cache line are filled by wrapping back to the beginning of the cache line if required. these two bits contain the starting address for the modulo read fill operation. they will also contain the least significant address bits when a cache line is initially written to. 02-00 will always be returned as zeros. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the bus dram cache controller (bcach) page 193 of 553 8.6: bcach line valid bytes register these registers are useful only in diagnostic testing of the cache logic. each register will contain a bit signifi- cant flag indicating which bytes in the 32-byte cache line are valid. all of these bits will be active after a cache line fill operation has happened, but any combination of these bits can be valid after the processor has per- formed a write operation to memory. length 32 bits type read only address tag number 0 xxxx 1084 tag number 1 xxxx 10a4 tag number 2 xxxx 10c4 tag number 3 xxxx 10e4 power on value x?0000 0000? restrictions none cache line fill operation set/reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-00 each bit indicates if the associated byte in the cache line contains valid data or not. if the bit is set, the cache line contains valid data and a fetch from main storage is not required to fulfill a request for a read from this location. if the bit is reset, a read of the associated location will require a cache line fill operation before the request can complete. IBM2520L8767 ibm processor for atm resources the bus dram cache controller (bcach) page 194 of 553 atmrm.chapt04.01 08/27/99 8.7: bcach line status register these registers are useful only in diagnostic testing of the cache logic. each register will contain a bit signifi- cant flag indicating the current status of the associated cache line. length 32 bits type read only address tag number 0 xxxx 1088 tag number 1 xxxx 10a8 tag number 2 xxxx 10c8 tag number 3 xxxx 10e8 power on value x?0000 0000? restrictions none valid tag reserved loaded by pci read loaded by predictive fill loaded by rxque advice loaded by pci write reserved lru bits dirty bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 valid tag when set, this indicates that the associated tag register contains a valid tag. 30-12 reserved reserved 11 loaded by pci read when set, this bit indicates that the associated tag register was loaded due to a read request from the pci bus 10 loaded by predictive fill when set, this bit indicates that the associated tag register was loaded due to a predictive fill request 09 loaded by rxque advice when set, this bit indicates that the associated tag register was loaded due to advice from the receive queue entity 08 loaded by pci write when set, this bit indicates that the associated tag register was loaded due to a write request from the pci bus 07-06 reserved reserved 05-04 lru bits these bits indicate the cache lines current position with respect to the least recently used algorithm. a value of 0 indicates it is the most recently used while a value of 3 indicates the least recently used. 03-00 dirty bits these bits, when set, indicate that the associated 8 byte word of the cache line is dirty. this information is used on cache line flushes, to lower memory utilization, by eliminating non-dirty word flushes from the cache line flush operation. for example if these bits contain a x?1?, only the 8 byte word at offset zero in the cache line is dirty, so the flush operation will only write this one word to memory, saving 3 memory access cycles. if these bits contain a x?c?, only the two 8 byte words starting at offset x?10? in the cache line are dirty. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 the bus dram cache controller (bcach) page 195 of 553 8.8: bcach cache line array this array is divided into four 32-byte buffers used as cache lines 0,1,2 and 3. the four cache lines start at the following offsets into the array: line 0 offset x?00? line 1 offset x?20? line 2 offset x?40? line 3 offset x?60? length 16 words x 64 bits type read/write address xxxx 1100 - 17f restrictions this array can only be accessed when the diagnostic mode bit in the control regis- ter is set. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 196 of 553 atmrm.chapt04.01 08/27/99 entity 9: buffer pool management (pools) pools acts as a memory manager for the IBM2520L8767. memory buffers are checked out and checked in via two operations (primitives) supported by pools: the get pointer primitive and the free pointer primitive. these primitives can be performed explicitly by accessing specified addresses within the pools entity, and they may also be done by hardware. csked can free a buffer upon transmission if specified by the corre- sponding packet header (see ecc syndrome bits on page 151), and raall gets buffers to store received data. in addition pools contains mechanisms to control resource utilization and supports a real memory mode and a virtual memory mode. basic operation in real memory mode if memory is viewed as a series of buffers, pools maintains a circular list of available buffers. there are pointers (the head and tail) to the start and the end of the list. when a get pointer primitive is executed, the buffer at the head of the list is checked out, the head pointer is advanced and the correct resource group(s) is debited. when a free pointer primitive is executed, the freed buffer is checked in at the end of the list, the tail pointer is advanced and the correct resource group credited. basic operation in virtual memory mode with the addition of virtual memory, pools must maintain five sets of head and tail pointers, thresholds, and active counts; one for the virtual buffers themselves and the rest for the four regions of real buffers that con- stitute the virtual buffers. in this case the base virtual address is the item returned from a get pointer operation and returned during a free pointer operation. when the get buffer primitive is executed pools creates an active buffer map (page table) for the virtual address. as the virtual address is used and buffer(page) bound- aries are crossed vimem will request buffers from pools when a buffer(page) fault occurs. vimem will then place the buffer index in the buffer map. when the virtual buffer is no longer needed and a free pointer primi- tive is issued with the starting virtual address, pools takes the contents of the buffer map and frees the resources that were assigned to the buffer map. resource controls pools adds another layer of service by creating "pools" of buffers (currently a maximum of 16 pools). for each pool, a maximum number of allowable buffers may be specified. the intent is to make it possible for several applications to use the IBM2520L8767 at once without one or more applications starving the remaining applications for memory buffers. a particular pool?s buffers are divided into "guaranteed" and "common" buffers. all the guaranteed buffers are considered to be dedicated to their respective pool and are therefore not available for general use. the common buffers are all the memory buffers remaining after the guaranteed buffers are subtracted from the total buffers. to maintain the buffer limits on each pool, every pool has a guaranteed threshold, total threshold, and an active count. when a request is made for a buffer from a particular pool, the guaranteed threshold is first checked. if the active count of the pool is less than the guaranteed threshold, the buffer is provided. if the guaranteed threshold has been reached, then the total threshold is checked. if the active count is equal to the total threshold, no buffer is provided. if the active count is less than the total threshold, and a common buffer is available, a buffer is provided. if there are no common buffers available, a buffer cannot be provided and a null index is returned. to determine if a common buffer is available a count is maintained for each size of buffer. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 197 of 553 virtual memory overview each virtual buffer consists of a number of real buffers. for each virtual buffer there is a buffer map that defines the size and number of real buffers that may be allocated to the virtual buffer. each map is built from a common template (the vimem virtual buffer segment size register) that associates 1 to n buffer indexes in the map to a real buffer in one of the four real buffer regions defined in vimem. in vimem, the buffer map base address register defines the size of the map and therefore also the number of buffer indexes in the vir- tual buffer map. each eight-byte entry of the map contains the pool id of the pool to which the buffer is allocated plus space for three real buffer segment indexes. this implies the smallest map yields a virtual buffer of one to four real buffer segments (three real buffer segments plus the implicit real buffer that all virtual buffers are allocated). the biggest map defines a virtual buffer of 1-16 real buffer segments (15 plus the implicit). the intention of this structure is to allow the user to customize the value in the virtual buffer segment size register to utilize memory in an efficient manner relative to network data traffic. for example, if network traffic contained 50% packets of < 512 bytes, 35 % packets of < 1k bytes, and the rest was < 5k bytes, the user could set up virtual memory to use three real segments of 512 bytes, 512 bytes, and 4k bytes. the incoming data would neatly fit into the segments and minimize wasted memory. pools and vimem maintain the maps for the virtual buffers. on a write that crosses a real buffer boundary into an as yet an unresolved region of a virtual buffer, a page fault occurs. when a page fault occurs, pools determines whether or not a real buffer can be assigned. if it can be assigned, the index of the real buffer rel- ative to the base address of the particular buffer size is placed by vimem into the buffer map. the first buffer is implicitly associated with the virtual memory address for a particular virtual buffer and enough real memory must be available to support the first real buffer of each virtual buffer at initialization time. there is not neces- sarily enough real storage for all the possible real buffers associated with a virtual buffer. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 198 of 553 atmrm.chapt04.01 08/27/99 all real buffers of a particular size are stored in a contiguous region of memory. the buffer index, in conjunc- tion with the base address for this real buffer size, will point to a particular real buffer. the implicit buffers are also stored in a data structure of this type. virtual address buffer map packet size (17 bits max) 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit note: the buffer index of the first buffer and buffer limit segment register (32 bits) buffer index of the first buffer in the virtual address (16 bits max) number of bits for largest 32 bit virtual address the virtual address index are the same. also note that they are right justified. virtual address buffer map IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 199 of 553 the following example illustrates these concepts. buffer/virtual memory allocation structure in memory buffer size one base index zero buffer size one index one buffer size one index two ...... buffer size one index n skip to next buffer size bound buffer size two base index zero buffer size two index one buffer size two index two ...... buffer size two index n skip to next buffer size bound buffer size three base index zero buffer size three index one buffer size three index two ...... buffer size three index h skip to next buffer size bound buffer size four base index zero buffer size four index one buffer size four index two ...... buffer size four index n skip to implicit buffer base address implicit buffer index zero implicit buffer index one implicit buffer index two ...... implicit buffer index n the single box represents the storage for the whole buffer, whatever its size. these indexes are determined by the virtual buffer?s virtual address IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 200 of 553 atmrm.chapt04.01 08/27/99 virtual address buffer map buffer,size(4) 256 base index zero buffer, size(4) 256 index one buffer, size(4) 256 index two ... buffer, size(4) 256 index n skip to next buffer size base address buffer, size(0) 256 base index zero buffer, size(0) 256 index one buffer, size (0) 256 index two ... buffer, size(0) 256 index n skip to next buffer size base address buffer, size(1) 1024 base index zero buffer, size(1) 1024 index one buffer, size (1) 1024 index two ... buffer, size(1) 1024 index n skip to next buffer size base address buffer, size(2) 4096 base index zero buffer, size(0) 4096 index one buffer, size (0) 4096 index two ... buffer, size(2) 4096 index n skip to next buffer size base address buffer, size(3) 16384 base index zero buffer, size(3) 16384 index one buffer, size (3) 16384 index two ... buffer, size(3) 16384 index n skip to virtual address base address v.m. address index zero v.m. address index one v.m. address index two v.m. address index n ... brb4 + shifted buffer index 0 + offset into pkt pool id 0000 buffer index implicit 256 byte buffer index size(0) 256 byte buffer index size (0) 256 byte buffer index size (1) 1024 byte buffer index size(3) 16384 unused buffer index 1 buffer index 2 buffer index 0 pool id 0000 buffer index 4 buffer index last segment decode one yes? segment decode two yes? segment decode three yes? segment decode four yes? segment decode fourteen yes? segment decoder brb0 + shifted buffer index 0 + offset into pkt brb0 + shifted buffer index 2 offset into pkt brb2 + shifted buffer index 0 + offset into pkt bbr2 + shifted buffer index 4 offset into pkt bbr3 + shifted buf. index last + offset into pkt virtual address. index implicit buffer index size(4) 0 no.ofbitsfor largest packet size(17 max) packet address region brbm + shifted buffer index 0 + offset into map 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 2 bits 2 bits 2 bits 2 bits 2 bits 2 bits base address registers base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer size(0) brb0 base address register buffer map brbm packet storage area byte buffer index size(2) 4096 byte segment decode zero yes? IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 201 of 553 the lower seventeen bits of the virtual address are used in conjunction with the segment template in the vimem virtual buffer segment size register to determine from which portion of the buffer map the buffer index is retrieved. once the buffer index is retrieved, it is combined with the appropriate base address for that particular buffer size. the offset into the buffer is then added to get the real 32-bit address that is used in physical memory. pools uses the data structures above to manage packet memory resources. each lcd is associated with a particular pool and multiple different lcd?s may be associated with that same pool. within a pool, there are five different resource categories and two variables to go with each resource. resources and variables example 9.1: pools get pointer primitive the pools get pointer primitive returns a pointer to the requester. the request to the virtual packet/buffer size 4 address will always return a memory address. if in virtual mode, the address will be virtual. requests made for buffer sizes 0 to 3 will not return an address but rather a buffer index in bits 15-0. the real address associated with this index can be generated by shifting the index by the buffer size (e.g. six bit positions for a 64-byte buffer) and adding the result to the base address for this size buffer. access to buffer sizes 0 - 3 is not permitted in operational mode. the address of the primitive also selects the pool id. the pool id is con- tained in address bits 5-2; the pool id selects which pool will be charged for the pointer. the buffer size is selected with address bits 8-6. if there are no more pointers available in the specified pool, a null pointer is returned. the active pointer count for that pool is incremented if a non-null pointer is returned. if the guaranteed threshold has been exceeded and a buffer from the common pool is returned, the common pools count for that size is decre- mented by 1. resource type pool 0000 virtual memory addresses buffer type one buffer type two buffer type threebuffer type four guaranteed no. 100 200 50 10 0 total no. 150 300 100 5 10 length 32 bits type read only address buffer size 0 xxxx 3200 buffer size 1 xxxx 3240 buffer size 2 xxxx 3280 buffer size 3 xxxx 32c0 virtual packets / buffer size 4 xxxx 3300 power on value x?00000000? restrictions during normal operations this register is to be used as a read only register. writes to this address will be ignored. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 202 of 553 atmrm.chapt04.01 08/27/99 9.2: pools free pointer primitive the pools free pointer primitive returns the pointer to the proper free list. if it is a virtual memory address, the virtual memory buffer map is traversed to free the indexes associated with the virtual memory address. in the case where it is a real memory buffer, the single index is freed. this primitive uses address mapping to select the size of the object to be freed. the size is contained in address bits 4-2. during normal operation only frees to buffer size four are relevant. during initialization mode, buffer sizes 0 - 3 can be used to load indexes. the indexes are loaded into bits 31-16. in normal operations it is not necessary to read this "register". length 32 bits type write only address buffer size 0 xxxx 3350 buffer size 1 xxxx 3354 buffer size 2 xxxx 3358 buffer size 3 xxxx 335c virtual packets / buffer size 4 xxxx 3360 power on value x?00000000? restrictions during normal operations this register is to be used as a write only register. reads from this address will return zeros. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 203 of 553 9.3: pools common pools count registers the pools common pools count registers indicates the number of pointers in the particular common pool. the bits are a 16-bit count. the gtptrs that exceed the guaranteed allocation decrement this count by one assuming that the count is non-zero. when the count is zero, the gtbuf will fail. the frptrs that operate beyond the guaranteed threshold for a particular client and free the pointer(s) increment this count by one. the microcode should initialize these registers to the value of the respective common pool that it desires to have. length 16 bits type read/write address buffer size 0 xxxx 3000 buffer size 1 xxxx 3004 buffer size 2 xxxx 3008 buffer size 3 xxxx 300c virtual packets / buffer size 4 xxxx 3010 power on value x?0000? restrictions during normal operations these registers are to be used as a read only. writing to these registers during operation could create a data loss situation. this register should be set up by the microcode at initialization time. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 204 of 553 atmrm.chapt04.01 08/27/99 9.4: pools client thresholds array the pools client thresholds array holds the guaranteed and total threshold values for the 16 pools and the four(five) pointer sizes. when a gtptr primitive is processed, the values in this array are used to deter- mine if a primitive can return a pointer. the active count from the active packet count array is used with these registers to determine if a threshold has been exceeded. if the guaranteed threshold has been exceeded and the total not exceeded and there is a common pointer available, then the common count will be incremented. if there are no common buffers available or the request will cause the total threshold to be exceeded, the request will be rejected. during a frptr primitive processing, the pointer is returned to the free list and these thresholds are used to determine if a common count should be credited. this array con- tains the guaranteed and total thresholds for the managed pools. length 32 bits x 16 words type read/write address buffer size 0 xxxx 3400 buffer size 1 xxxx 3440 buffer size 2 xxxx 3480 buffer size 3 xxxx 34c0 virtual packets / buffer size 4 xxxx 3500 power on value x?00000000? restrictions none guaranteed threshold total threshold 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 guaranteed threshold 15-0 total threshold. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 205 of 553 9.5: pools user threshold and client active packet count array the pools user threshold and client active packet count array holds the user thresholds and active pointer counts for each of the 16 managed pools and four (five) pointer sizes. this array contains the user thresholds and active buffer counts for the managed pools and pointer sizes. when a gtptr primitive is processed, the active count is retrieved and compared with the threshold counts. if it falls within bounds and a pointer is available, the active count will be incremented by one reflecting the additional buffer charged to that queue. when a frptr primitive is processed, the active count is retrieved, and, when the pointer is returned to the free list, the active buffer count is decremented by one. the user threshold may be used to check on resource utilization as opposed to resource allocation. the guaranteed and total thresholds are used when allocating resources to make decisions. the user thresh- old is not used to govern resource allocation directly. one such use is for high water mark indication. when a frptr primitive is processed or a gtptr is processed the active packet count is compared to the user threshold. if the event interface is enabled and a boundary condition is crossed an event is issued to the event interface. length 32 bits x 16 words type read/write address buffer size 0 xxxx 3600 buffer size 1 xxxx 3640 buffer size 2 xxxx 3680 buffer size 3 xxxx 36c0 virtual packets / buffer size 4 xxxx 3700 power on value x?00000000? restrictions none user threshold active packet count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 user threshold 15-0 active packet count IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 206 of 553 atmrm.chapt04.01 08/27/99 9.6: pools pointer queues dram head pointer offset address register the pools pointer queues dram head pointer offset address register indicates the address in dram where the head of the queue starts. note however, that this address is only relative to the dram portion of the queue. unless the head of the queue portion of the cache is locked out and needs two frames, the actual head of the queue is in the cache. these 19 bits on write represent the offset to the address in dram of the head of the queue relative to the dram base address. on a read the address in dram of the pointer is returned. this pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. since each memory reference contains four indices, this allows for 128k index locations possible in the queue. length 32 bits read/19 bits write type read/write address buffer size 0 xxxx 3014 buffer size 1 xxxx 3018 buffer size 2 xxxx 301c buffer size 3 xxxx 3020 virtual packets / buffer size 4 xxxx 3024 power on value buffer size 0 x?00 01 00 00? buffer size 1 x?00 02 00 00? buffer size 2 x?00 02 40 00? buffer size 3 x?00 02 60 00? virtual packets / buffer size 4 x?00 02 70 00? restrictions during normal operations this register is to be used as a read only register. this regis- ter defaults to zero at initialization. it is assumed that the queues start on a maximum size queue boundary. these registers should be setup at initialization time. this regis- ter is cleared when the pools pointer queues dram lower bound address register is written to. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 207 of 553 9.7: pools pointer queues dram tail pointer offset address register the pools pointer queues dram tail pointer offset address register indicates the offset address in dram where the tail of the queue starts. note however that this address is only relative to the dram por- tion of the queue. unless a ?no cache frames to be written through? state is in effect the actual tail of the queue is in the cache. these 19 bits on write represent the offset to the address in dram of the tail of the queue relative to the dram base address. on a read the address in dram of the pointer is returned. this pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. since each memory reference contains four indices this allows for 128k index locations possible in the queue. length 16 bits type read/write address buffer size 0 xxxx 3028 buffer size 1 xxxx 302c buffer size 2 xxxx 3030 buffer size 3 xxxx 3034 virtual packets / buffer size 4 xxxx 3038 power on value buffer size 0 x?00 01 c0 00? buffer size 1 x?00 02 00 00? buffer size 2 x?00 02 40 00? buffer size 3 x?00 02 60 00? virtual packets / buffer size 4 x?00 02 70 00? restrictions during normal operations this register is to be used as a read only register. this regis- ter defaults to zero at initialization. it is assumed that the queues start on the maximum size queue boundary. these registers should be setup at initialization time. this regis- ter is cleared when the pools pointer queues dram lower bound address register is written to. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 208 of 553 atmrm.chapt04.01 08/27/99 9.8: pools pointer queues dram lower bound address register the pools pointer queues dram lower bound address register indicates the address in dram where the queue data structure is initially started. when the queue reaches the maximum address allowed for in the upper bound register it will wrap back around to the address specified in this register. this implements the queue in a circular buffer. these thirty-two bits represent the address in dram where the queue will begin at and eventually wrap to. at initialization this register and the pools pointer queues dram tail pointer offset address register and pools pointer queues dram head pointer offset address register must be equal. . length 32 bits type read/write address buffer size 0 xxxx 303c buffer size 1 xxxx 3040 buffer size 2 xxxx 3044 buffer size 3 xxxx 3048 virtual packets / buffer size 4 xxxx 304c power on value buffer size 0 x?00 01 c0 00? buffer size 1 x?00 02 00 00? buffer size 2 x?00 02 40 00? buffer size 3 x?00 02 60 00? virtual packets / buffer size 4 x?00 02 70 00? restrictions during normal operations this register is to be used as a read only register. this regis- ter should be setup at initialization time. the size of the dram queue storage which is formed with the lower and upper bounds is constrained in its size. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. note if the maximum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 209 of 553 9.9: pools pointer queues dram upper bound register the pools pointer queues dram upper bound register indicates the max queue length in dram of the queue data structure. when the queue reaches this address, it wraps back to the address specified by the lower bound register. this implements the queue in a circular buffer. this upper bound is to be provided as an encoded field. the encoded field represents the number of 8-byte addresses that can be contained by the queue. these four bits represent the encoded maximum queue length in dram where, when matched, trig- ger the queue to wrap back to the address contained in the dram lower bound address register. length 4bits type read/write address buffer size 0 xxxx 3050 buffer size 1 xxxx 3054 buffer size 2 xxxx 3058 buffer size 3 xxxx 305c virtual packets / buffer size 4 xxxx 3060 power on value buffer size 0 x?b? buffer size 1 x?a? buffer size 2 x?9? buffer size 3 x?9? virtual packets / buffer size 4 x?b? restrictions during normal operations this register is to be used as a read only register. this regis- ter should be setup at initialization time. the size of the dram queue storage which is formed with the lower and upper bounds is constrained in its size. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. note if the maximum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available. pointer queues dram upper bound address (page 1 of 2) encoded value number of 32 bit words number of indexes x?0? 8 16 x?1? 16 32 x?2? 32 64 x?3? 64 128 x?4? 128 256 x?5? 256 512 x?6? 512 1024 x?7? 1024 2048 x?8? 2048 4096 x?9? 4096 8192 x?a? 8192 16384 IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 210 of 553 atmrm.chapt04.01 08/27/99 x?b? 16384 32768 x?c? 32768 65536 x?d? 65536 131072 x?e? 65536 131072 x?f? 65536 131072 pointer queues dram upper bound address (page 2 of 2) encoded value number of 32 bit words number of indexes IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 211 of 553 9.10: pools pointer queues length registers the pools pointer queues length registers indicates the length of the queue. the bits are a 16-bit count. a primitive that adds to the queue increments this counter and primitives that remove items from the queue decrement this counter. restrictions: during normal operations this register is to be used as a read only register. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. this register is cleared when the pools pointer queues dram lower bound address register is written to. 9.11: pools interrupt enable register this register is used to enable bits from the pools status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit(s) in the pools status register are set, the pools interrupt to pcint will be enabled. see note on set/clear/read type registers on page 71 for more details on addressing. see pools status register on page 215 for the bit descriptions. length 16 bits type read/write address buffer size 0 xxxx 3064 buffer size 1 xxxx 3068 buffer size 2 xxxx 306c buffer size 3 xxxx 3070 virtual packets / buffer size 4 xxxx 3074 power on value x?00 00? restrictions during normal operations this register is to be used as a read only register. this register should be setup at initialization time. the size of the dram queue storage which is formed with the lower and upper bounds is constrained in its size. it can be written when the diagnostic mode bit is set, otherwise the write is ignored. note if the maximum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available. length 32 bits type clear/set address xxxx 3078 and 07c power on value x?00 03 f8 00? restrictions none IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 212 of 553 atmrm.chapt04.01 08/27/99 9.12: pools event enables this register is used to enable an event based on bits from the corresponding primitive transaction. if the bits are set in the enable and a transaction occurs that matches the event, an event will be sent to the rxque. see note on set/clear/read type registers on page 71 for more details on addressing. 9.13: pools event hysteresis register the pools event hysteresis register provide the capability for hysteresis on threshold checking. length 16 bits type clear/set address gtd event enables xxxx 3a00 and a04 total event enables xxxx 3a08 and a0c user event enables xxxx 3a10 and a14 power on value x?0000? restrictions none length 8bits type read/write address xxxx 3a18 power on reset value x?0000? restrictions none hysteresis value 76543210 bit(s) function description 7-0 hysteresis value whenafreeoccursthevalueinthisregisterwillbeaddedtothenextactivepacket count. this value will be then tested against the threshold value. if it is equal to the threshold an event if events are enabled and the event associated with this transaction is enabled will be issued. IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 213 of 553 9.14: pools event data register the pools event data register provides the data that was sent on the last event. length 32 bits type read address xxxx 3a1c power on reset value x?0000003e? restrictions none free processed gtd threshold match with hysteresis free processed total threshold match with hysteresis free processed user threshold match with hysteresis get processed gtd threshold match get processed total threshold match get processed user threshold match reserved pool id of the event reserved buffer size of the event reserved event source id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31 free processed gtd threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 30 free processed total threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 29 free processed user threshold match with hysteresis this event occurs when a free is processed and the threshold is matched. the threshold is modified by the value in the hysteresis register. the event is issued when the actual value of the active packet count plus the hysteresis equals the threshold. 28 get processed gtd threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 27 get processed total threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 26 get processed user threshold match this event occurs when a get is processed and the threshold is matched. the event is issued when the new active packet count equals the threshold. 25-20 reserved reserved IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 214 of 553 atmrm.chapt04.01 08/27/99 19-16 pool id of the event this indicates which pool is associated with this event. 15-11 reserved reserved 10-8 buffer size of the event this indicates which size is associated with this event. 7-6 reserved reserved 5-0 event source id this indicates that pools is associated with this event. bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 215 of 553 9.15: pools status register the pools status register provides status information about pools operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 3080 and 084 power on reset value x?00 00 00 00? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved pools event issued packet memory access timer expired control memory access timer expired pools locked initialization error detected unused buffer freed error bad map detected active count error detected bad index detected pointer common buffers size 4 exhausted common buffers size 3 exhausted common buffers size 2 exhausted common buffers size 1 exhausted common buffers size 0 exhausted buffer size 4 threshold crossed buffer size 3 threshold crossed buffer size 2 threshold crossed buffer size 1 threshold crossed buffer size 0 threshold crossed get pointer primitive failed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-21 reserved reserved 20 pools event issued this bit is set when a pools event is issued. 19 packet memory access timer expired this bit is set when the packet memory access timer hits the packet memory access threshold and the control bit in the control register is set to enable this func- tion. 18 control memory access timer expired this bit is set when the control memory access timer hits the control memory access threshold and the control bit in the control register is set to enable this func- tion. 17 pools locked this bit is set when a lock enable bit is set and the corresponding status bit is set. this causes all state machines to be held in idle once this bit is set. it is the func- tional equivalent to pools control register bit 0. 16 initialization error detected this bit is set when too many indexes are freed to a queue. 15 unused buffer freed error this bit is set when a previously freed buffer is detected during a free operation. this typically would occur when the buffer was freed two or more times. 14 bad map detected this bit is set when a bad map is detected during a free operation. 13 active count error detected this bit is set when an active packet count is decremented from zero to x?ffff?. this is most likely the result of a subtle map corruption where a pool id has been changed. 12 bad index detected this bit is set when an index threshold is crossed. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 216 of 553 atmrm.chapt04.01 08/27/99 11 free pointer primitive null detected/max pointer queue length exceeded. this bit is set as a result of one of two detectable errors: null index detected within free address. total allowed storage for a particular queue has been exceeded. 10 common buffers size 4 exhausted common buffer count for size 4 is zero. 9 common buffers size 3 exhausted common buffer count for size 3 is zero. 8 common buffers size 2 exhausted common buffer count for size 2 is zero. 7 common buffers size 1 exhausted common buffer count for size 1 is zero. 6 common buffers size 0 exhausted common buffer count for size 0 is zero. 5 buffer size 4 threshold crossed the number of size 4 buffers is equal to or less than the threshold that was set for size 4 buffers. 4 buffer size 3 threshold crossed the number of size 3 buffers is equal to or less than the threshold that was set for size 3 buffers. 3 buffer size 2 threshold crossed the number of size 2 buffers is equal to or less than the threshold that was set for size 2 buffers. 2 buffer size 1 threshold crossed the number of size 1 buffers is equal to or less than the threshold that was set for size 1 buffers. 1 buffer size 0 threshold crossed the number of size 0 buffers is equal to or less than the threshold that was set for size 0 buffers. 0 get pointer primitive failed this bit is set when a null address is returned on a get. bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 217 of 553 9.16: pools control register the pools control register provide status information about pools operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 30c8 and 0cc power on reset value x?00 00 20 01? restrictions caution must be used when asserting some of the bits during operation. reserved primitive trap source selector lock pools on error packet high priority on get or free fifos full packet high priority always control high priority always packet high priority with request timer control high priority with request timer fast free mode initialization mode virtual memory mode limit event generation enable event interface enable out of range index checking force all queue transactions to memory diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) function description 31-18 reserved reserved 17-14 primitive trap source selector these bits will select the source of the last primitive trapped register. 0000 free from the pci bus 0001 free from raall 0010 free from rxque 0011 free from csked 0100 free from segbf 0101 free from dmaqs 0110 get from pci bus 0111 get from raall 1000 get from dmaqs 1001 get from vimem (pool id(4 bits), size(2 bits),blank(10 bits),index(16 bits)) 13 lock pools on error when set, this bit in conjunction with the lock mask will hold pools state machines in an idle state until cleared. 12 packet high priority on get or free fifos full when set, this bit will cause pools to turn on its high priority request to packet mem- ory when either the free or get fifo is full. 11 packet high priority always whenset,thisbitwillcausepoolstoalwaysuseitshighpriorityrequesttopacket memory. 10 control high priority always whenset,thisbitwillcausepoolstoalwaysuseitshighpriorityrequesttocontrol memory. IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 218 of 553 atmrm.chapt04.01 08/27/99 9 packet high priority with request timer when set, this bit will cause pools to time the wait for packet memory service and when the timer expires move to high priority. 8 control high priority with request timer when set, this bit will cause pools to time the wait for control memory service and when the timer expires move to high priority. 7fastfreemode when this bit is set, fast free mode is enabled. when pools is in fast free mode it does not write out the buffer map with the modified control information that indicates that the map is unused. when in this mode unused buffer free error checking is dis- abled. 6 initialization mode when the value of the bit is ?0?, initialization mode is set. when the value is 1, opera- tional mode is set. during initialization mode indexes are in the upper 16 bits of the data word. it is assumed that when initialization mode is on other normal operations are not active such as transmit or receive. during operational mode packet addresses assumedtobeonthedatabus. 5 virtual memory mode when set to ?0?, virtual memory mode is enabled. when set to ?1?, real memory mode is enabled. 4 limit event generation when set, this bit will cause pools to limit the issuance of events to rxque when a gtd threshold, total threshold or pool threshold is reached. it will issue the first event and disable the related event enable bit. software must then reset the bit if it wishes to see another such event. however, it is possible that events may be lost when this bit is set on. 3 enable event interface when set, this bit will cause pools to issue resource events to rxque when a gtd threshold, total threshold or pool threshold is reached. 2 enable out of range index checking when set, this bit will cause pools to check the indexes that are streaming by to be checked against a maximum value for that size index. if the normal initialization sequence is used, these maximum values will auto set. 1 force all queue transactions to memory when set, this will disable the internal tail to head transfer path within the queue. all indexes will proceed into memory before being brought to the head of the queue. this effectively preserves the operational history in memory. however, some caution is warranted since four full entries are required for a write to memory. this could cause indexes to get "stuck" at the back of the queue. when this residue occurs, a zero pointer will be returned even though the operation might have otherwise returned a valid pointer. 0 diagnostic mode when set, pools is in diagnostic mode. when cleared, pools is in normal mode. when in diagnostic mode, state machines are held in idle. if they are already active, when they next go to idle they will hold there. bit(s) function description IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 219 of 553 9.17: pools buffer threshold registers 0-4 the pools buffer threshold registers 0-4 is the threshold set by the software to set the threshold crossed bit in the pools status register. this register is used to compare with the queue length register. this regis- ter consists of a 16-bit count match. the threshold count is compared to the queue length count. if the queue length is less than the value in this register, the appropriate bit is set in the status register respective to this queue. 9.18: pools index threshold registers 0-4 the pools index threshold registers 0-4 provide error checking. the pools index threshold registers 0-4 are the thresholds set by the software or hardware to set the index threshold crossed bit in the pools status register. this register is used to check indexes during free operations to look for an out of bounds index. each register consists of a 16-bit compare value. the threshold count is compared to the index while being processed. if an index is greater than the value in this register, the appropriate bit is set in the status register. length 16 bits type read/write address virtual packets/ buffer size 0 xxxx 3088 buffer size 1 xxxx 308c buffer size 2 xxxx 3090 buffer size 3 xxxx 3094 buffer size 4 xxxx 3098 power on value x?0000? restrictions none length 16 bits type read/write address virtual packets/ buffer size 0 xxxx 30f0 buffer size 1 xxxx 30f4 buffer size 2 xxxx 30f8 buffer size 3 xxxx 30fc buffer size 4 xxxx 3100 power on value x?0000? restrictions none IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 220 of 553 atmrm.chapt04.01 08/27/99 9.19: pools last primitive trap register the pools last primitive trap register provide debug assistance. this register contains the 32 bit last primitive address. 9.20: pools last buffer map read on free register the pools last buffer map read on free register provide debug assistance. this register contains the 32 bit address of the buffer map used in the last free operation. 9.21: pools error lock enable register the pools error lock enable register provides the ability to halt pools when the corresponding status bit in the status register are set. when a bit in this register that corresponds to a bit that is set in the status regis- ter, the state machines in pools will be held in idle state until the lock is disabled. see note on set/clear/read type registers on page 71 for more details on addressing. 9.22: pools packet and control memory access threshold the pools packet and control memory access threshold timers are used to help limit the amount of time that pools can be held off from its respective memory. the bits are a 12-bit count. when the proper bit in length 32 bits type read address xxxx 30e8 use the pools last primitive trap register is the last primitive address to pools, as selected in the pools control register, while in operational mode. power on reset values x?00 00 00 00? restrictions none length 32 bits type read address xxxx 30ec use the pools last buffer map read on free register is the address of the last buffer map read on a free. power on reset values x?00 00 00 00? restrictions none length 21 bits type clear/set address xxxx 30d8 and dc power on reset value x?00 f8 00? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt04.01 08/27/99 buffer pool management (pools) page 221 of 553 the pools control register is set and a request is made to the requisite memory, a counter is loaded with this value. the counter will then count down to zero in 30ns ticks. when it hits zero, it will force the request to high priority. 9.23: pools buffer map group the pools buffer map group holds the buffer map of the packet that is in the process of being freed. from this map the pool id and the indexes that have been used will be returned to their correct queue. this reg- ister consists of a 16-bit flag fields and 16-bit indices. the flag field contains the pool id and the valid bit. when a packet is freed the valid bit is set to zero. when a get operation occurs the valid bit is then set. this helps to find address duplicates and other address related problems that software can generate but are hard to find. length 12 bits type read/write address packet memory timer threshold xxxx 30e4 control memory timer threshold xxxx 30e0 power on value x?080? restrictions none length 32 bits type read/write address upper 16 bits lower 16 bits flag field 0 index 0 xxxx 309c index 1 index 2 xxxx 30a0 flag field 1 index 3 xxxx 30a4 index 4 index 5 xxxx 30a8 flag field 2 index 6 xxxx 30ac index 7 index 8 xxxx 30b0 flag field 3 index 9 xxxx 30b4 index 10 index 11 xxxx 30b8 flag field 4 index 12 xxxx 30bc index 13 index 14 xxxx 30c0 power on value x?ffffffff? restrictions none IBM2520L8767 ibm processor for atm resources buffer pool management (pools) page 222 of 553 atmrm.chapt04.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 transmit cell scheduler (csked) page 223 of 553 transmit data path entities entity 10: transmit cell scheduler (csked) the transmit cell scheduler entity is responsible for receiving a packet from the processor, determining when cells from the packets need to be transmitted, and passing this information to the segmentation buffer entity. the logic consists of timers and counters for determining transmit opportunities, a register for determining where the timing data is located, a status register, and interfaces to arbit (for accessing the timing data and descriptors), pcint (for register accesses), rxque (for queuing events), pools (for returning buffers when finished transmitting), and segbf (which gets the cells from memory to transmit). operational description a logical channel descriptor (lcd), and optionally a logical path descriptor (lpd), containing scheduling parameters for the circuit must be initialized before segmentation can be started. the parameters that are important to the operation of this entity are the average interval, peak interval, transmission priority, and maximum credits that can be accumulated. see transmit descriptor data structures on page 39 for further information on these descriptors. packets to be segmented are written to packet memory that has been allocated by pools. the address of the lcd describing the channel that this packet is to be transmitted on, must be written to the header of the packet. packet segmentation is started by issuing the transmit enqueue primitive to this entity. this entity will schedule segmentation of the packet according to the parameters set up in the lcd or vpd. scheduling options csked has logic to assist in the processing of abr connections. if the connection is abr, the lcd will have a different configuration as specified in transmit descriptor data structures on page 39. the following fields need to be initialized before the packets are sent on the connection. scheduling parameters this field must be set to the value specifying an abr connection. nrm this field should specify the maximum number of cells a source may send for each forward rm-cell. number of cells = (2 ?? nrm)+1. trm this field provides an upper bound on the time between forward rm-cells for an active source. time = 100 ? (2 ?? -trm) msec. adtf the acr decrease time factor is the time permitted between sending rm-cells before the rate is decreased to icr. time = adtf ? .01msec. all other abr fields should be initialized to zero. this section contains descriptions of the registers used by the cell scheduler. . IBM2520L8767 ibm processor for atm resources transmit cell scheduler (csked) page 224 of 553 atmrm.chapt05.01 08/27/99 10.1: transmit enqueue primitive enqueues a buffer for transmission. 10.2: resume transmission primitive resumes transmission on a connection specified by an lcd address. on an abr connection, certain events can cause the transmission to be suspended until a rate conversion is completed. this primitive will resume transmission on those connections. this is normally done by the internal processor. length 32 bits type write only address xxxx 1200 power on value x?0000 0000? restrictions none transmitted buffer address ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 this must contain the address of the buffer to be transmitted. buffers must be aligned on at least 64-byte boundaries. the lower six bits are ignored. length 32 bits type read/write address xxxx 1204 power on value x?0000 0000? restrictions this address should be written with care. this primitive should only be used on connections that have been suspended. resume lcd address ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 this must contain the address of the lcd that is to resume transmission. the lower seven bits are ignored. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 transmit cell scheduler (csked) page 225 of 553 10.3: close connection primitive transmission is complete on a connection specified by an lcd address. when no more traffic is to be sent on a connection, this primitive can be executed to cause an event to be generated when segmentation has stopped on this connection. segmentation will be stopped immediately, or stopped after all packets on this connection have been transmitted as specified in the c sked control register. 10.4: start/stop timer primitive start or stop a timer with the parameters in the specified lcd address. when this primitive is executed, a timer, with parameters contained in the specified lcd, is started or stopped. bit 0 specifies whether to start (0) or stop(1) the timer. when the timer pops, a dma descriptor specified in the lcd will be executed. length 32 bits type read/write address xxxx 120c power on value x?0000 0000? restrictions none close lcd address ignored 313029282726252423222120191817161514131211109876543210 bit(s) description 31-7 this must contain the address of the lcd that is to be closed. the lower seven bits are ignored. length 32 bits type read/write address xxxx 125c power on value x?0000 0000? restrictions none timer parameter lcd address ignored start - stop 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-7 this must contain the address of the lcd that contains the timer parameters. the lower seven bits are ignored. 6-1 these bit are not used. 0 this bit specifies whether the timer is to be started(0) or stopped(1). IBM2520L8767 ibm processor for atm resources transmit cell scheduler (csked) page 226 of 553 atmrm.chapt05.01 08/27/99 10.5: timeslot prescaler register this register determines the length of time for 1 timeslot. this controls the rate that the cell scheduling counters are incremented. each clock cycle the value in this register is added to a 24-bit counter. when the upper bit of the counter changes state the current timeslot counter is incremented. this should normally be set to the time it takes to transmit one cell. it will be initialized to the cell time for a 155 mb/s sonet connec- tion (149.76 mb/s payload). the following formula should be used to determine the value to load in this regis- ter: timeslot prescaler = (clock interval/timeslot interval) x 2 ?? 23. 10.6: current timeslot counter this counter contains a count of how many prescaled intervals have elapsed. it is used to determine if sched- uling needs to be done or credits exist. length 24 bits type read/write address xxxx 1210 power on value x?015b3e? restrictions this register should be written only at initialization time. timeslot counter rate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 23-0 this value will determine the rate at which the current timeslot counter is advanced. length 32 bits type read/write address xxxx 1218 power on value x?0000 0000? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. elapsed interval count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents how many expirations have occurred since the counter rolled over. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 transmit cell scheduler (csked) page 227 of 553 10.7: timing data base address 32kb of control memory must be reserved for timing data. this register contains the base address for the timing data. the lower 15 bits will be taken from the appropriate counter. 10.8: csked control register this register is used to control the actions of csked. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type read/write address xxxx 121c power on value x?0001 0000? restrictions the timing data base address must be on 32-kb boundary. timing data base address from counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-16 this value represents the upper 17 bits of the timing data base address. 15-0 taken from the appropriate counter. length 22 bits type read/write address xxxx 1220 and 024 power on value x?0759? restrictions none disable csked overlap close connection immediately queue lcd memory management lcd memory management bandwidth scheduling group a gfc reset group b gfc reset queue lcd address disable virtual buffer error detection disable queuing virtual buffer errors reserved segbf queue length threshold disable segbf queue length buffer request priority enable timers reschedule packets enable high priority traffic enable medium priority traffic enable low priority traffic enable cell scheduling 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBM2520L8767 ibm processor for atm resources transmit cell scheduler (csked) page 228 of 553 atmrm.chapt05.01 08/27/99 bit(s) name description 21 disable overlapping transmit requests this bit is meant for debug purposes only. it will disable the ability of csked to overlap requests to segbf. 20 close connection immediately setting this bit will cause segmentation to stop immediately on any connection that has been issued a close connection primitive. if this bit is not set an event will be generated after all traffic queued to this connection has been sent. 19 queue lcd based memory management events setting this bit will cause lcd based memory management events to be queued to the transmit complete queue, if enabled by bit 18 of this control register. if lcd based memory management is enabled and this bit is off, the receive pool id associated with this connection will be updated when a thresh- old is crossed. 18 lcd based memory management setting this bit will enable lcd based memory management for received packets. see logical channel data structure on page 38 and definition of lcd-based memory management of transmit lcd on page 45 for further informationonthisfunction. 17 use bandwidth scheduling for low priority setting this bit will cause low priority traffic to be bandwidth scheduled. the peak interval in the lcd is used to provide a relative weight in determining the amount of bandwidth the connection will use. for example a peak interval of one will use twice the bandwidth as a connection with a peak interval of two. the average interval specifies the maximum rate that the connection can use. for example if the average interval is set to ?2?, the maximum rate at which it can send a cell is every two timeslot times (as defined in the timeslot pres- caler register). 16 control scheduling of medium priority traf- fic with gfc reset for group a setting this bit will cause medium priority traffic to be controlled by the group a gfc bits in the atm header of received cells. 15 control scheduling of low priority traffic with gfc reset for group b setting this bit will cause low priority traffic to be controlled by the group b gfc bits in the atm header of received cells. 14 queue the lcd address if freeing and queueing setting this bit will cause the lcd address, instead of the packet address, to be queued if both freeing and queueing on transmit complete. 13 disable virtual buffer error detection setting this bit will cause the buffer enqueue logic to ignore virtual buffer errors. 12 disable queuing virtual buffer errors if virtual buffer error detection is not disabled, detected errors will be queued. if this bit is set, this queuing is disabled and the buffer will be freed. 11 reserved reserved. 10-8 segbf queue length threshold cells can be queued in segbf up to the number specified in this register. the default is seven which is above the limit for pass two. writing these bits to zero will also disable this function. 7 disable segbf queue length in schedul- ing csked will normally include segbfs queue length in the calculations when rescheduling a cell. if this bit is on it will disable this function and the cell will be scheduled as if the cells were transferred when segbf accepted the cells. 6 priority of buffer requests if this bit is not set, scheduling requests have a higher priority than buffer requests. if this bit is set this priority is reversed. it should be set if a significant percentage of packets are only a few cells in length. 5 enable timers timer descriptors can be enqueued to this entity that will cause a dma descriptor to be executed on expiration. if these timers are used, this bit must be set. if they are not used, this bit should be reset. 4 reschedule packets in the slow queue to the fast queue this function is not implemented in pass one. it is implemented in pass two. if the average or peak interval is greater than 255, the cells will be scheduled in the slow queue. the slow queues will be serviced every 64 prescaler time units. this means that a jitter of up to 64 prescaler time units should be expected for slow traffic. if this bit is set, packets in the slow queue will be rescheduled at the appropriate time to the fast queue. this will decrease the variation in the scheduling but may cause some performance degradation if traffic is heavy. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 transmit cell scheduler (csked) page 229 of 553 10.9: transmit segmentation throttle register this register contains the number of cycles to wait between successive requests to transmit a cell. its purpose is to slow segmentation on all vcis if software determines that the network cannot handle the gener- ated load. the value in this register will be loaded into the transmit segmentation counter each time a cell is accepted for transmission. for normal operation the value in this register should be zero. 3 enable high priority traffic for each priority enabled 16kb of control memory must be reserved for timing data. if only one or two priorities are to be used, bits corresponding to unused priorities should be cleared to improve performance. 2 enable medium priority traffic enable medium priority traffic. 1 enable low priority traffic enable low priority traffic. 0 enable cell scheduling if this bit is off no primitives will be handled or cells scheduled. length 16 bits type read/write address xxxx 1230 power on value x?0000 ? restrictions none queue length 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15-0 when the transmit complete queue length reaches this value an interrupt will be generated. bit(s) name description IBM2520L8767 ibm processor for atm resources transmit cell scheduler (csked) page 230 of 553 atmrm.chapt05.01 08/27/99 10.10: transmit segmentation throttle counter this register is loaded with the value in the transmit segmentation throttle register after each cell is accepted for transmission and counts down until it reaches zero. a new cell transmission will not be requested until this counter reaches zero. 10.11: mpeg conversion register this register is used to convert mpeg time units into timeslot time units. if mpeg traffic is configured in the lcd, the data stream will be monitored for pcrs. if a pcr is detected, it will be scheduled at the time speci- fied in the pcr. a conversion factor needs to be written into this register to convert the mpeg time units into timeslot units. it will be initialized to a value that converts the mpeg time units (90 khz) into the timeslot units (353.2 khz, assuming one timeslot is the time it takes to send one cell over a sonet connection). the lower 12 bits of this register contain the fractional portion of this conversion factor. example: 353.2076 khz / 90 khz = 3.924528 = 3.ecb hex length 16 bits type read only address xxxx 1234 power on value x?0000? restrictions read only transmit segmentation throttle counter 1514131211109876543210 bit(s) description 15-0 when this counter reaches zero a new cell can be transmitted. length 15 bits type read/write address xxxx 1208 power on value x?3ecb? restrictions none mpeg time conversion factor 14131211109876543210 bit(s) description 14-0 contains the conversion factor. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 transmit cell scheduler (csked) page 231 of 553 10.12: gfc reset values this register is used to load values into the gfc counters upon receiving a cell with the gfc reset bit on in the received atm header. the lower eight bits will be the value loaded into the group a counter, and the upper eight bits will be the value loaded into the group b counter. length 16 bits type read/write address xxxx 1214 power on value x?0101? restrictions none group b counter group a counter 1514131211109876543210 bit(s) description 15-8 value loaded into the group b counter. 7-0 value loaded into the group a counter. IBM2520L8767 ibm processor for atm resources transmit cell scheduler (csked) page 232 of 553 atmrm.chapt05.01 08/27/99 10.13: abr timer prescaler register this register determines the length of time for a tick of the rm cell timer. this controls the rate that the cell scheduling counters are incremented. each clock cycle the value in this register is added to a 24-bit counter. when the upper bit of the counter changes state, the rm cell timer is incremented. this should be set to a value of .78 ms. it will be initialized to .78 ms assuming a 30-ns clock (as set up in sclock). the following formula should be used to determine the value to load in this register: abr timer prescaler = (clock inter- val/.78 ms) x 2 ?? 23. 10.14: rm cell timer this register is used to keep track of the last time that an abr rm cell was sent. its period should be .78 ms. length 24 bits type read/write address xxxx 127c power on value x?000143? restrictions this register should be written only at initialization time. abr counter rate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 23-0 this value will determine the rate at which the abr counter is advanced. length 24 bits type read/write address xxxx 126c power on value x?000000? restrictions none rm timer value 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 23-0 timer value. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 performance registers page 233 of 553 performance registers this section contains registers that are for performance purposes. 10.15: high priority bandwidth limit register this register can be used to limit the bandwidth used by high priority connections. the upper eight bits of this register specifies the number of high priority cells that can be sent in a window specified by the lower eight bits of this register. length 16 bits type read/write address xxxx 1270 power on value x?00000000? restrictions none cells transmitted cell times in window 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from high priority connections in one time window. 7-0 this value specifies the number of cell times in the window. IBM2520L8767 ibm processor for atm resources performance registers page 234 of 553 atmrm.chapt05.01 08/27/99 10.16: medium priority bandwidth limit register this register can be used to limit the bandwidth used by medium priority connections. the upper eight bits of this register specifies the number of medium priority cells that can be sent in a window specified by the lower eight bits of this register. 10.17: low priority bandwidth limit register this register can be used to limit the bandwidth used by low priority connections. the upper eight bits of this register specifies the number of low priority cells that can be sent in a window specified by the lower eight bits of this register. length 16 bits type read/write address xxxx 1274 power on value x?00000000? restrictions none cells transmitted cell times in window 1514131211109876543210 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from medium priority connections in one time window. 7-0 this value specifies the number of cell times in the window. length 16 bits type read/write address xxxx 1278 power on value x?00000000? restrictions none cells transmitted cell times in window 1514131211109876543210 bit(s) description 15-8 this value specifies the number of cells that can be transmitted from low priority connections in one time window. 7-0 this value specifies the number of cell times in the window. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 performance registers page 235 of 553 10.18: high priority cells transmitted counter this register contains the number of cells transmitted from high priority connections. 10.19: medium priority cells transmitted counter this register contains the number of cells transmitted from high priority connections. length 32 bits type read/write address xxxx 1260 power on value x?00000000? restrictions none number of high-priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from high priority connections. length 32 bits type read/write address xxxx 1264 power on value x?00000000? restrictions none number of medium-priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from high priority connections. IBM2520L8767 ibm processor for atm resources performance registers page 236 of 553 atmrm.chapt05.01 08/27/99 10.20: low priority cells transmitted counter this register contains the number of cells transmitted from high priority connections. length 32 bits type read/write address xxxx 1268 power on value x?00000000? restrictions none number of low-priority cells transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 this value represents the number of cells transmitted from high priority connections. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 debugging register access page 237 of 553 debugging register access this section contains registers that are for debug purposes only. these registers need not be written or read during normal operations. 10.21: high priority serviced counter this register contains the value of the last high priority slot that has been serviced. when this count differs from the current timeslot count, at least one high priority slot needs servicing. each time the high priority slot is serviced, this counter will increment. 10.22: medium priority serviced counter this register contains the value of the last medium priority slot that has been serviced. when this count differs from the current timeslot count, at least one medium priority slot needs servicing. each time the medium priority slot is serviced, this counter will increment. length 16 bits type read/write address xxxx 1240 power on value x?0000? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. high-priority service counter 1514131211109876543210 bit(s) description 15-0 this value represents how many times this time wheel has been serviced since the counter rolled over. length 16 bits type read/write address xxxx 1244 power on value x?0000? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. not used medium-priority service counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15-0 this value represents how many times this time wheel has been serviced since the counter rolled over. IBM2520L8767 ibm processor for atm resources debugging register access page 238 of 553 atmrm.chapt05.01 08/27/99 10.23: low priority serviced counter this register contains the value of the last low priority slot that has been serviced. when this count differs from the current timeslot count, at least one low priority slot needs servicing. each time the low priority slot is serviced, this counter will increment. 10.24: slow serviced counters there are three slow serviced counters, one for each transmit priority. these registers contain the value of the last slow time slot that has been serviced. when this count differs from the current timeslot count, at least one slow slot needs servicing. each time the slow slot is serviced, this counter will increment. length 16 bits type read/write address xxxx 1248 power on value x?0000? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. low-priority service counter 1514131211109876543210 bit(s) description 15-0 this value represents how many times this time wheel has been serviced since the counter rolled over. length 10 bits type read/write address xxxx 124c xxxx 1250 xxxx 1254 power on value x?000? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. slow service counter 9876543210 bit(s) description 9-0 this value represents how many times this slow wheel has been serviced since the counter rolled over. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 debugging register access page 239 of 553 10.25: timer serviced counters in addition to the counters above, there is an additional counter for processing timer requests. this register contains the value of the last timer slot that has been serviced. when this count differs from the current timeslot count (bits 22-15), at least one slow slot needs servicing. each time a timer slot is serviced, this counter will increment. length 16 bits type read/write address xxxx 1280 power on value x?00? restrictions this register is meant to be read only. it is writable for diagnostic purposes only. not used timer service counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15-0 this value represents how many times this timer wheel has been serviced since the counter rolled over. IBM2520L8767 ibm processor for atm resources debugging register access page 240 of 553 atmrm.chapt05.01 08/27/99 10.26: csked status register this register is used to control the actions of csked. see note on set/clear/read type registers on page 71 for more details on addressing. length 5bits type clear/set address xxxx 1228 and 22c restrictions none power on value x?0? virtual memory error detected high-priority serviced counter medium-priority serviced counter low-priority serviced counter current timeslot counter 43210 bit(s) name description 4 virtual memory error detected if a virtual memory write operation could not complete because a real buffer was not available, a signature is written to the packet header. if this signature is detected when the buffer is enqueued for transmission, this bit will be set and an event will be posted to rxque. 3 high priority serviced counter high priority serviced counter has overrun. 2 medium priority serviced counter medium priority serviced counter has overrun. 1 low priority serviced counter low priority serviced counter has overrun. 0 current timeslot counter current timeslot counter has wrapped if this bit is on the timeslot counter has wrapped. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 debugging register access page 241 of 553 10.27: csked interrupt enable register this register is used to enable interrupts from csked. if a bit is on in the status register and the correspond- ing enable bit is on in this register, an interrupt will be generated, if enabled in intst.see note on set/clear/read type registers on page 71 for more details on addressing. 10.28: timing data array this array contains data relevant to scheduling cells. it should only be written for diagnostic purposes to test the array. it will power up to all zeros and should be rewritten to zeros after the array has been tested. length 5bits type clear/set address xxxx 1238 and 23c power on value x?0? restrictions none length 24 words x 32 bits type read/write address xxxx 1300 power on value x?000000? restrictions should be written for diagnostic use only. initialize back to zeros when through testing. scheduling data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 scheduling data. IBM2520L8767 ibm processor for atm resources debugging register access page 242 of 553 atmrm.chapt05.01 08/27/99 10.29: state machine variables this register contains the current state of the three main state machines in this entity. length 14 bits type read address xxxx 1258 power on value x?0000? restrictions none state machine variables 131211109876543210 bit(s) description 13-0 value of state machine variables. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 243 of 553 entity 11: atm transmit buffer segmentation (segbf) the segmentation buffer entity (segbf) accepts frames from the cell scheduler (csked) or software, and then generates atm cells to send out over the external physical interface. this entity knows or cares nothing about scheduling cells over time, it will simply construct a cell when it is provided an address of a logical channel descriptor on which to operate. all rate and scheduling concerns must be addressed by the logic or software prior to queueing a frame to segbf. the segbf logic consists of a four-deep input fifo for 24-bit lcd addresses, a general purpose crc generator to handle data from one to eight bytes wide, a special purpose crc generator to calculate the hec, a four-deep output fifo for cells waiting to be transmitted, and various pieces of control logic. a simplified block diagram is shown in the ?segbf block diagram.? segbf block diagram software lcd enqueue register cell scheduler lcd enqueue 2deeplcdfifo 64 64 control 64 packet 64 miscellaneous control logic crc calculation 4deep53bytecellfifo 64 memory (lcds) memory (data) IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 244 of 553 atmrm.chapt05.01 08/27/99 the sequence of events that happens when an aal5 frame is enqueued to segbf is as follows: 1. the required information associated with the enqueued frame is fetched form the logical circuit descriptor (lcd). this data consists of but is not limited to: current data pointer, current crc, aal type, four bytes of atm header, data length and various flag bits. 2. the atm header fetched above, is used to calculate the single byte hec. these five bytes are the first bytes of the cell buffer. alternatively, mainly for diagnostic purposes, the capability exists to force the fifth byte of the cell to be any value the user wishes. an eight-bit register and a control bit are provided to implement this function. 3. the current data pointer and data length from step 1 are used to determine how many data bytes to fetch from data storage. as many as 48 bytes can be fetched or if the previous cell from this frame contained the last byte of data but did not have space left over for the aal5 trailer, 0 bytes can be fetched. 4. if the internal logic determines that the current cell being assembled will be the last cell of this frame, the aal5 trailer is appended to the cell buffer, with any unused bytes being padded with zeros. if the frame was provided by csked, then an indication is returned to csked to allow the appropriate data structures to be updated. 5. the updated currregisters this section contains descriptions of the registers used by the buffer segmentation logic. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 245 of 553 11.1: segbf software lcd enqueue this register provides a mechanism for software to transmit a single cell or a group of cells making up a buffer that can contain any user defined data at any time. to cause a cell/buffer to be transmitted, the software must write the address of a valid vci control block to this register. the segmentation hardware will then construct a cell to match the aal type defined in the lcd control block, using the segmentation pointer contained in the lcd to fetch data and present this cell to the next lower level of hardware to transmit. this method of cell transmission bypasses the cell scheduler completely so it is the responsibility of the software to ensure that peak and average rates are not violated. when the segmentation logic has completed building the cell and queued it for transmission, the lcd address will be loaded into the software lcd complete register. this method of cell transmission is not designed for high performance and as such, there is only a single level of queueing underneath the complete register. it is recommended that only a single software lcd be queued to the segmentation logic at any one time to prevent hanging the segmentation logic as it attempts to queue a complete software lcd to the complete queue. length 32 bits type read/write address xxxx 1400 power on value x?0000 0000? restrictions before enqueuing a vci, software must ensure that the previous software enqueue has been handled by the hardware. this is accomplished by reading this register before an enqueue is attempted. if a value of zero is returned, the segmentation hardware is ready to accept an enqueue operation. if a non-zero value is returned, it will be the address of the previous vci that was enqueued and this indicates that the segmentation hardware has not been able to enqueue the vci to it?s internal vci buffer segmentation queue. if this mechanism shows that this interface is busy and unable to accept new vci addresses for any appreciable amount of time (tens of s), it is likely that a condition exists which is preventing the hardware below the segmentation logic from accepting cells for transmission, and the segmentation logics input buffer is full. this mechanism also adds the restriction that a vci control block should never exist at address zero. vci control block address cell type 313029282726252423222120191817161514131211109876543210 bit(s) description 31-7 these bits contain the upper 25 bits of the address of the vci control block. 6-0 these bits control what type of cell will be built by the segmentation logic. there are currently only two valid values for these bits. if these bits are all zero, a normal cell as defined by the lcd will be built. if these bits have a value of 0x7f, an abr cell will be built using fields defined in the lcd. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 246 of 553 atmrm.chapt05.01 08/27/99 11.2: segbf force hec value this register provides a mechanism for software to force the fifth byte of a cell to contain any value when it is provided to the externally connected physical interface chip. this value will only be used if the segbf control register indicates that the hec should be loaded and not calculated. length 8bits type read/write address xxxx 1404 power on value x?00? restrictions none 5thbyteinsert 76543210 bit(s) description 7-0 these bits contain the eight bits that will be inserted in the fifth byte of the cell being assembled IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 247 of 553 11.3: segbf control register this register provides a mechanism to control the various programmable features of segbf. see note on set/clear/read type registers on page 71 for more details on addressing. ?u length 22 bits type clear/set address xxxx 1408 and 40c power on value x?00000? restrictions none pti field 111 pti field 110 pti field 101 pti field 100 lcd address shift lcd fetch hec replacement function pre-pended lcd data idle state pause cell delay frame counter frame termination prevention no pcr packet end mpeg-2 pid enable reset control logic lcd statistics prevent lcd statistics oam blocking prevent oam blocking ignore cell scheduler req?s 5thbytevalue enter diagnostic mode 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 21 when set, this bit will force all nud cells with the pti field of 111 to be excluded from the nud cell counter. 20 when set, this bit will force all nud cells with the pti field of 110 to be excluded from the nud cell counter. 19 when set, this bit will force all nud cells with the pti field of 101 to be excluded from the nud cell counter. 18 when set, this bit will force all nud cells with the pti field of 100 to be excluded from the nud cell counter. 17 when set, this bit will force all lcd address to be shifted by eight bytes when accessed by the segmentation logic. it is meant to be used for diagnostic testing of the segmentation hardware. 16 when set, this bit will force all lcds to be fetched from memory and not buffered in segbf. 15 when set, this bit will enable a function in the segmentation logic that replaces the hec in the cell with a fourth byte of user data from the lcd. the byte that replaces the hec will be retrieved from a location in the lcd that is specified by the pre-pended header steering register. 14 this bit when set will enable the segmentation function which allows user data from the lcd to be pre-pended on the cells as they are built. when enabled, the segmentation logic will always place three bytes of user-defined data from a location in the lcd that is specified in the pre-pended header steering register, into the cell buffer preceding the atm header before passing the cell to the next lower level. 13 this bit when set will cause the segmentation logic to pause when it reaches the idle state. segmentation will not be con- tinued until this bit has been reset. care must be taken to leave this bit set for a very short duration so that segmentation throughput will not be adversely affected. 12 when set, this bit will cause the segmentation logic to delay the cell immediately following the cell that contained the pcr until the correct time. if reset, the last cell of the aal5 frame that contained a pcr will be delayed. 11 when set, this bit will cause the segmentation logic to count the number of frames that have been sent instead of the num- ber of cells that have been sent with clp = 0. both the register that counts these events across all lcds as well as the vci specific field in a particular lcd are affected by this bit. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 248 of 553 atmrm.chapt05.01 08/27/99 10 when set, this bit will prevent pcr containing packets from terminating an aal5 frame only when the pcr containing packet is the first transport stream packet in the aal5 frame. the aal5 frame will be terminated on the second transport stream packet even if that packet does not contain a pcr. 9 when set, this bit will prevent pcr containing packets from terminating an aal5 frame. 8 when set, this bit will enable the mpeg-2 pid screening logic. in this mode, all mpeg-2 pcr related logic will only be active if the 188-byte transport stream packet being processed has the correct pid value. the correct value is determined as the transport stream packets are being segmented. the first 188-byte packet that contains a pid that satisfies the pid limit register, and has a pcr, will cause the segmentation logic to "lock" onto that pid value. once locked, the pcr rate matching logic will only be active on packets that contain that pid. any other packets that have a different pid will be sent out at the normal scheduled rate regardless of whether the packet contains a pcr or not. the pid logic will "unlock" from a given pid if a packet with that pid is not processed by the segmentation logic in a programmable amount of time defined in the ®sgpidd. when reset, the pid field in all transport stream packets will be ignored. 7 when set, this bit will reset all control logic in the entity. after being set, this bit must be reset before the segmentation logic will function properly. this bit must remain set for at least 1 s to reset the segmentation logic properly. 6 when set, this bit will force statistics to be kept on all lcds processed by the segmentation logic. 5 when set, this bit will prevent statistics from being kept on any lcds processed by the segmentation logic. this bit will have precedence over the force statistics bit. 4 when set, this bit will force oam blocking to occur an all lcds processed by the segmentation logic. the oam blocking logic requires that statistics are being kept for the lcd being monitored, so if this bit is set, statistics will be forced on all lcds. 3 when set, this bit will prevent oam blocking for happening on any lcds processed by the segmentation logic. this bit will have precedence over the force blocking bit. 2 when set, this bit will cause all requests from the cell scheduler to be ignored. this allows complete program control of all cells being sent out on the external interface 1 when set, this bit causes the fifth byte of all cells being assembled by segbf to contain the value that is contained in the force hec register. when reset, the fifth byte will contain a value calculated over the first four atm header bytes retrieved from the lcd. 0 this bit when set causes the segbf entity to enter diagnostic mode. this bit must be set in order to access the internal array. when accessing the array, care must be taken that normal entity reads and writes of the array are not happening at thesametimeortheresultswillbeindeterminant. bit(s) description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 249 of 553 11.4: segbf status register this register provides feedback to the user on the current status of segbf. see note on set/clear/read type registers on page 71 for more details on addressing. length 8bits type clear/set address xxxx 1410 and 414 power on value x?00? restrictions none reserved oam cells wrapped user cells with clp=l0 wrapped user cells wrapped cell generation completed invalid condition detected 76543210 bit(s) description 7-5 reserved 4 when set, this bit indicates that the total oam cells transmitted register has wrapped. 3 when set, this bit indicates that the total user cells transmitted with clp=0 register has wrapped. 2 when set, this bit indicates that the total user cells transmitted register has wrapped. 1 when set, this bit indicates that the segmentation logic has completed cell generation for a lcd that was enqueued by the software to the software lcd enqueue register. 0 when set, this bit indicates that the segmentation logic has detected an invalid condition in one of the lcds that it was pro- cessing. the address of the lcd in error is contained in the invalid lcd register. any invalid lcds detected, are not pro- cessed further by the segmentation logic, so the program must do something to clear this condition. the following are detected sources of the invalid lcd condition: 1 128-byte lcds are configured and an lcd on a 64-byte bound is detected 2 an invalid aal was specified in the lcd 3 the packet length plus the buffer offset is greater than the configured buffer size. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 250 of 553 atmrm.chapt05.01 08/27/99 11.5: segbf invalid lcd register this register provides feedback to the program when the segmentation logic detects an invalid lcd. if multi- ple invalid lcds are being processed, this register will contain the address of the last one that was processed by the segmentation logic. to clear this condition for lcds being processed by the cell scheduler it is suggested that the program write x?ffffffff? to the segmentation pointer in the indicated lcd. this will cause the segmentation logic to terminate cell transmission on the next opportunity and cause the cell sched- uler to clean up and go on to the next buffer indicated in the lcd. there are several invalid lcd situations that the segmentation logic checks for: the first is the lcd address not being on the correct boundary. for example, if the chip is configured to have all lcds on 128-byte boundaries and a lcd is encountered that is not on a 128-byte boundary. another invalid condition is when the transmit length configured in the lcd plus the offset in the lcd when added together exceed the maximum overall packet size configured in the chip. it is up to the program to determine which of the possible conditions caused the error to be reported. length 32 bits type read/write address xxxx 1418 power on value x?00000000? restrictions none detected lcd error address always read as zeros size exceeded invalid aal-type field detected transmit length error bad synch byte detected 313029282726252423222120191817161514131211109876543210 bit(s) description 31-7 these bits contain the 32-bit address of the lcd detected to be in error. 6-4 always read as zeros. 3 when set, this bit indicates that an lcd has been encountered that requires a larger number of eight-byte words from the vci than the current value configured in the segbf maximum lcd size register. 2 when set, this bit indicates an lcd containing an invalid aal-type field was detected. 1 when set, this bit indicates a transmit length error was detected. 0 when set, this bit indicates that a bad sync byte was detected in an mpeg-2 transport stream packet. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 251 of 553 11.6: segbf software lcd complete this register provides feedback to the program when the segmentation logic completes cell generation for a lcd that was enqueued by the software. after the segmentation logic has updated the lcd, the address of the lcd is copied into this register providing any previous lcd addresses written to this register have been read by the software. if multiple software queued lcds are outstanding to the segmentation logic at any time, the segmentation process can be delayed when multiple software enqueued lcds complete without the software getting a chance to read the lcd addresses from this register. to guarantee that the segmentation logic never has to wait for the software to read this register, it is recommended that only one software lcd be enqueued at any one time. 11.7: segbf interrupt enable register this register allows the user to selectively determine which bits in the segbf status register will cause processor interrupts. a zero in a bit position masks interrupts from the corresponding bit location in the segbf status register. a one in a bit position allows interrupts for the corresponding bit in the segbf status register. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type read/write address xxxx 141c power on value x?00000000? restrictions bits 5 - 0 are not implemented and will always return zero. to maintain future compatibility, zeros should be written to these bits. lcd address always zero 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 these bits contain the upper 26 bits of the lcd address that the segmentation logic has finished processing. 5-0 these bits will always be read as zero. length 8bits type clear/set address xxxx 1420 and 424 power on value x?01? restrictions none IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 252 of 553 atmrm.chapt05.01 08/27/99 11.8: segbf total user cells transmitted this register provides a count of the total number of user cells that have been sent out regardless of vci or vpi. any cell assembled and sent with the most significant bit of the payload-type field reset, will cause this counter to be incremented. when the counter wraps, a status bit will be set, and an interrupt can be gener- ated if desired. 11.9: segbf total user cells transmitted with clp=0 this register provides a count of the total number of user cells that have been sent out regardless of vci or vpi with the cell loss priority bit reset. any cell assembled and sent with the most significant bit of the payload type field reset and the cell loss priority bit reset will be cause this counter to be incremented. when the counter wraps a status bit will be set, and an interrupt can be generated if desired. alternatively, if bit 11 of the control register is set, this register will count the total number of operations that have been enqueued to csked that have been completely processed by segbf. by counting each operation enqueued to csked and monitoring this register, the software can determine how many operations are still queued for segmenta- tion. length 32 bits type read/write address xxxx 1430 power on value x?00000000? restrictions none user cells transmitted count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain a count of the total number of user cells sent by this station. length 32 bits type read/write address xxxx 1434 power on value x?00000000? restrictions none user cells with clp=0 transmitted count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain a count of the total number of user cells sent by this station with clp=0, or the total number of csked enqueue operations that have been completed by the segmentation logic. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 253 of 553 11.10: segbf total nud cells transmitted this register provides a count of the total number of nud cells that have been sent out regardless of vci or vpi. the segbf control register can be used to exclude any of the four possible pti values from this count. when the counter wraps, a status bit will be set, and an interrupt can be generated if desired. length 32 bits type read/write address xxxx 1438 power on value x?00000000? restrictions none nud cells transmitted count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain a count of the total number of nud cells sent by this station. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 254 of 553 atmrm.chapt05.01 08/27/99 11.11: segbf cell queue status this register provides status about the number of cells queued up for transmission over the media. segbf can have a maximum of six cells queued up for transmission. when an lcd is scheduled for transmission, either by csked or software, the address of the lcd is stored in a two deep queue. as space becomes available in the four-deep cell buffer, addresses are removed from the address queue and cells are built in the cell buffers. this register provides status about the lcd address input queue as well as the cell buffers. length 11 type read address xxxx 143c power on value x?00000000? restrictions none encoded cells queued reserved 2nd lcd address latch 1st lcd address latch 4th cell buffer valid 3rd cell buffer valid 2nd cell buffer valid 1st cell buffer valid 109876543210 bit(s) description 10-8 these three bits contain the encoded number of cells queued up for transmission in segbf. this number should normally correspond directly to the status defined in the low six bits of this register, with the possibility of a one cycle lag when segbf either passes a cell to linkc or eliminates one based on some detected error condition. 7-6 reserved, will always read zeros. 5 when set, this bit indicates that the second lcd address latch contains an lcd address for segmentation. 4 when set, this bit indicates that the first lcd address latch contains an lcd address for segmentation. 3 when set, this bit indicates that the fourth cell buffer contains a valid cell for transmission on the media. 2 when set, this bit indicates that the third cell buffer contains a valid cell for transmission on the media. 1 when set, this bit indicates that the second cell buffer contains a valid cell for transmission on the media. 0 when set, this bit indicates that the first cell buffer contains a valid cell for transmission on the media. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 255 of 553 11.12: segbf last active lcd data registers these registers are useful in determining the contents of the last lcd that the segmentation logic has accessed. length 32 bits type read only address word number 0 xxxx 1440 word number 1 xxxx 1444 word number 2 xxxx 1448 word number 3 xxxx 144c word number 4 xxxx 1450 word number 5 xxxx 1454 word number 6 xxxx 1458 word number 7 xxxx 145c word number 8 xxxx 1474 word number 9 xxxx 1478 power on value x?0000 0000? restrictions none lcd fetched memory value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-00 these bits contain the value that was fetched from memory the last time an lcd was fetched. the 32 bytes contained in these eight registers contain the lcd data significant to the segmentation logic. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 256 of 553 atmrm.chapt05.01 08/27/99 11.13: segbf pid high and low limit register this register provides a mechanism for software to specify what pid values in an mpeg-2 transport stream should be considered significant during pcr rate matching. length 29 bits type read/write address xxxx 147c power on value x?1fff0000? restrictions none high-limit pid values reserved low-limit pid values 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 28-16 thesebitscontainthehighlimitforpidvaluesduringmpeg-2pcrratematching.ifthepidina188-bytetransport packet is greater than this value, it will not be checked for a pcr, and it will be segmented at the normal scheduled rate. 15-13 reserved, should be written with zero. zeros will always be read. 12-0 these bits contain the low limit for pid values during mpeg-2 pcr rate matching. if the pid in a 188-byte transport packet is less than this value, it will not be checked for a pcr, and it will be segmented at the normal scheduled rate. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 257 of 553 11.14: segbf last active lcd address 0 this register provides feedback to the user that can be useful during initial program debug. this register and the register following this one contain the address of either the next two lcds that segbf will operate on or the last two lcds that segbf did operate on. length 32 type read address xxxx 1460 power on value x?00000000? restrictions none lcd address reserved lcd queued 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-6 these bits contain an lcd address. 5-1 reserved, will always read zeros. 0 when set, this bit indicates that the lcd was queued to segbf by software else it was queued by csked. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 258 of 553 atmrm.chapt05.01 08/27/99 11.15: segbf last active lcd address 1 this register provides feedback to the user that can be useful during initial program debug. this register and the register following this one contain the address of either the next two lcds that segbf will operate on or the last two lcds that segbf did operate on. length 32 type read address xxxx 1464 power on value x?00000000? restrictions none lcd address reserved lcd queued 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 these bits contain an lcd address. 5-1 reserved, will always read zeros. 0 when set, this bit indicates that the lcd was queued to segbf by software else it was queued by csked. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 259 of 553 11.16: mpeg-2 pcr increment register each tick of the time base will add the contents of this register to the mpeg pcr reference register. this register contains a fixed point number with 27 bits of fraction and five bits of units. this means that the exter- nal reference clock can range in speed from 22.5khz to the maximum speed of this entity which is tbd. assuming that the entity will run with a 50-mhz clock, the conversion to 720khz can be done with an accuracy of 1.1 parts in 2 million. (a clock of 19.4mhz will give a conversion accuracy of 1 part in 4.9 million). if the input clock is 19.4mhz, then the value to put in the increment register is (720,000 / 19,400,000) ? 2 ?? 27 or 4,981,277. if the input clock is 33mhz, then the value to put in the increment register is (720,000 / 16,666,666) ? 2 ?? 27 or 5,798,206. length 32 bits type read/write address xxxx 1468 power on value x?002c3c9f? (33mhz) restrictions none increment value whole increment value fractional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-27 these bits contain the whole part of the increment value. 26-0 these bits contain the fractional part of the increment value. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 260 of 553 atmrm.chapt05.01 08/27/99 11.17: mpeg-2 local pcr high this register contains the high 32 bits of the locally maintained pcr. accessing this register will provide the high 32 bits of the free running local timebase used by the segmentation logic to deliver mpeg-2 traffic in a timely fashion. although the pcr field in an mpeg-2 transport stream packet is really 42 bits, only 36 bits are significant and used by the segmentation logic. for correct operation in mpeg-2 mode, the mpeg-2 pcr increment register must be set up with the correct value so that the local pcr counts up at a rate of 720khz. owing to the free running nature of this value, when this register is read, the low four bits of the value are latched and can be read at a later time. length 32 bits type read address xxxx 146c power on value free running restrictions none local mpeg-2 timebase 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-0 these bits contain the high 32 bits of the local mpeg-2 timebase. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 261 of 553 11.18: mpeg-2 local pcr low this register contains the low four bits of the locally maintained pcr. accessing this register will provide the previously latched low four bits of the free running local timebase used by the segmentation logic to deliver mpeg-2 traffic in a timely fashion. the value is latched when the high 32 bits of the timebase are read. although the pcr field in an mpeg-2 transport stream packet is really 42 bits, only 36 bits are significant to, and used by the segmentation logic. for correct operation in mpeg-2 mode, the mpeg-2 pcr increment register must be set up with the correct value so that the local pcr counts up at a rate of 720khz. 11.19: mpeg-2 pid invalidation time this register should be loaded with a value that indicates how long the segmentation hardware should allow a pid that has been locked on, to be absent from a data stream before forcing the hardware to unlock from that pid and begin searching for the next available pid that contains a pcr to lock on. the time base for this register is 720khz. length 32 bits type read address xxxx 1470 power on value x?0? restrictions none low 4 bits mpeg-2 timebase 3210 bit(s) description 31-4 these bits will always return zero. 3-0 these bits contain the low four bits of the local mpeg-2 timebase. length 18 bits type write/read address xxxx 1480 power on value x?9ab0?(55ms) restrictions none unlock inactive pids 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 17-0 these bits contain the value used by the segmentation logic to unlock inactive pids from a stream. IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 262 of 553 atmrm.chapt05.01 08/27/99 11.20: pre-pended header byte steering register this register is used to specify the location in the lcd of the bytes that are to be used in the pre-pended cell header. four bits are used for each of the eight possible segmentation modes that can be set in the transmit portion of the lcd. the most significant two bits specify which of the words in the lcd following the csked/segbf shared region contain the bytes to prepend to the cell header. the least significant two bits specify the specific location in the eight-byte word that should be used. 720khz. length 32 bits type write/read address xxxx 1428 power on value x?00000000? restrictions none segment type 7 segment type 6 segment type 5 segment type 4 segment type 3 segment type 2 segment type 1 segment type 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-28 these bits contain the steering bits for segmentation type 7. 27-24 these bits contain the steering bits for segmentation type 6. 23-20 these bits contain the steering bits for segmentation type 5. 19-16 these bits contain the steering bits for segmentation type 4. 15-12 these bits contain the steering bits for segmentation type 3. 11-8 these bits contain the steering bits for segmentation type 2. 7-4 these bits contain the steering bits for segmentation type 1. 3-0 these bits contain the steering bits for segmentation type 0. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 atm transmit buffer segmentation (segbf) page 263 of 553 11.21: segbf maximum lcd size this register should be loaded with a value that indicates the maximum number of eight-byte words that are being used by the segmentation logic. the minimum value is two. this would be the correct value if running only aal5 with no statistics being kept on each lcd. the maximum value is seven. setting this register to a value that is too small, will likely cause the chip to function improperly. setting this register to a value that is too large, will adversely affect performance. length 3bits type write/read address xxxx 1488 power on value x?3?(this is the correct value when running aal5 with statistics) restrictions none number of 8-byte words 210 bit(s) description 2-0 these bits contain the number of eight-byte words in the lcd to be used by segbf during segmentation IBM2520L8767 ibm processor for atm resources atm transmit buffer segmentation (segbf) page 264 of 553 atmrm.chapt05.01 08/27/99 11.22: segbf internal status this register provides status regarding the current state of the internal segbf state machines and various other status bits. it is intended for to assist in debug. 11.23: segbf cell staging array this array is divided into four 64-byte buffers used to assemble cells that are ready for transmission on the line. length 16 bits type read address xxxx 1484 power on value x?0000? restrictions none 1st word indicator current state - main state machine current state - control memory access state machine reserved current state - packet memory access state machine reserved mpeg-2 frame early current state - internal multiply state machine 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 15 when set, this bit indicates that the first word of an lcd is being latched 14-12 these bits provide the current state of the main state machine 11-8 these bits provide the current state of the control memory access state machine 7 reserved 6-5 these bits provide the current state of the packet memory access state machine. 4 reserved 3 when set, this bit indicates that the current mpeg-2 frame is early and will not be sent. 2-0 these bits provide the current state of the internal multiply state machine used to generate packet length for fixed-size block mode. length 32 words x 64 bits type read/write address xxxx 1500 - 5ff restrictions this array can only be accessed when the diagnostic mode bit in the control regis- ter is set. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 cell re-assembly (reasm) page 265 of 553 receive data path entities entity 12: cell re-assembly (reasm) reasm is the entity which: collects the bytes from linkc into cells. discards null cells and idle symbols. looks up the vpi/vci control block in control store. provides the barrel shifter data interface to packet memory. check and correct the hec. reasm does these tasks with a 256-byte fifo receive buffer which can buffer up to four cells worth of data. the figure below is a block diagram of the reasm entity. reasm buffers the incoming cells and looks up the proper logical channel descriptor (lcd) address for the cell. it then passes the lcd pointer to raall and the cell data to packet memory. the lookup of the lcd from the cell data has just one level of indirection. the logical channel descriptor translate table is a data structure stored in control memory and maintained by software. reasm block diagram pm barrel shift oam processing seed residue crc logic fifo buffer vci data lcd entry address linkc interface 4-entry cache hec logic IBM2520L8767 ibm processor for atm resources cell re-assembly (reasm) page 266 of 553 atmrm.chapt05.01 08/27/99 vpi/vci -? lct entry mapping function gfc vpi bits vci bits flags hec cell data... offset range checking index from base lctt base base of logic channel translate table lookup with extended bit off first resulting offset added to lct base register hec mask and shift mask IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 cell re-assembly (reasm) page 267 of 553 12.1: reasm control register used to control reasm options. used to determine which bits of the vpi, vcp and mid will be used. also used to determine the acceptability of cells with fixable and non-fixable hec errors. see note on set/clear/read type registers on page 71 for more details on addressing. length 22 bits type clear/set address xxxx 1600 and 604 power on value x? 0010? restrictions none out-of-range receive cells zero index receive cells vci-vpi out-of-range bits disable reassembly vci flush reassembly vci reset control logic non-user cell count diagnostic bit receive cells w/ vpi/vci out-of range ignore hec errors receive cells w/ invalid hec disable hec correction number of vpi bits number of vci bits 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 21 receive cells that have bits in the vpi-vci that are out of range into the lcd specified in the reasm out of range lcd register. raall will generate an event that contains the cell address on a queue specified in raall. 20 receive cells that have an index of zero in the vci to lcd translation table. no index for the lcd is generated. raall will generate an event that contains the cell address on a queue specified in raall. 19 receive cells that have bits in the vpi-vci that are out of range. no index for the lcd is generated. raall will generate an event that contains the cell address on a queue specified in raall. 18 this bit will disable the reassembly vci to lcd translate cache when set. 17 this bit will flush the reassembly vci to lcd translate cache when set. it will reset when the flush is complete. 16 when set, this bit will reset all control logic in the entity. after being set, this bit must be reset before the logic will function properly. this bit must remain set for at least. 1 s to reset the reassembly logic properly. 15 count non-user cells instead of hec errors. 14 diagnostic bit. must be set to enable pci bus access to the array or write to the internal state machine register. setting this bit will prevent cells from being processed. 13 receive cells with vpi/vci out of range using the valid bits for generating the index for the lcd. 12 ignore hec errors. hec errors will not be reported if this bit is set. 11 receive cells with invalid hec. cells with hec errors will be received on a queue specified in raall. 10 disable hec correction. 9-5 number of bits of the vpi (0-12) that make up the table lookup address. 4-0 number of bits of the vci (0-16) that make up the table lookup address. IBM2520L8767 ibm processor for atm resources cell re-assembly (reasm) page 268 of 553 atmrm.chapt05.01 08/27/99 12.2: reasm status register used to relay reasm status information. this register contains status for the following conditions. length 11 bits type read/write address xxxx 1608 and 60c power on value x?00? restrictions none out-of-range counter overflow correctable error counter overflow uncorrectable error counter overflow received counter overflow received w/ clp=0 counter overflow non-null cell received reserved cell vpi/vci out of range correctable hec error detected uncorrectable hec error detected overrun detected 109876543210 bit(s) description 10 cell address out of range counter overflow. 9 cell hec correctable error counter overflow. 8 cell hec uncorrectable error counter overflow. 7 total user cells received counter overflow. 6 total user cells received with clp=0 counter overflow. 5 non-null cell received. 4 reserved. 3 cell vpi/vci out of range or index of zero in vpi/vci to lcd translate table detected. 2 correctable hec error detected. 1 uncorrectable hec error detected. 0 overrun detected. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 cell re-assembly (reasm) page 269 of 553 12.3: reasm interrupt enable register used to enable interrupts for reasm status conditions. if set, the specified condition will generate an inter- rupt from reasm. length 11 bits type read/write address xxxx 1610 and 614 power on value x?08? restrictions none out-of-range counter overflow correctable error counter overflow uncorrectable error counter overflow received counter overflow received w/ clp=0 counter overflow non-null cell received reserved cell vpi/vci out of range correctable hec error detected uncorrectable hec error detected overrun detected 109876543210 bit(s) description 10 cell address out of range counter overflow. 9 cell hec correctable error counter overflow. 8 cell hec uncorrectable error counter overflow. 7 total user cells received counter overflow. 6 total user cells received with clp=0 counter overflow. 5 non-null cell received. 4 reserved. 3 cell vpi/vci out of range or index of zero in vpi/vci to lcd translate table detected. 2 correctable hec error detected. 1 uncorrectable hec error detected. 0 overrun detected. IBM2520L8767 ibm processor for atm resources cell re-assembly (reasm) page 270 of 553 atmrm.chapt05.01 08/27/99 12.4: reasm logical channel table base register the reasm logical cha nnel table base register indicates the starting address of the logical channel table. this register defines where the logical channel descriptors are located. 12.5: reasm logical channel translate table base register this register defines where the vci to lcd translate table is located. when a cell is received, the vpi/vci fields are used to generate an index into this table. each entry of the translate table contains a 16-bit index which specifies which lcd in the logical channel table corresponds to the received vpi/vci. all unused entries should be initialized to zero, or to the index of an lcd that is intended to receive all unexpected vpi/vci combinations. 12.6: reasm cell address out of range counter counts cells with invalid vpi/vci fields. the counter will increment if the vpi/vci received is not in the range specified in the reasm control register bits (9-0), or the lcd i ndex corresponding to the received vci in the reasm logical channel table table base register is zero. length 32 bits type read/write address xxxx 1618 power on value x?0000 8000? restrictions the value must be in the range of the physical memory allocated for control memory. length 32 bits type read/write address xxxx 161c power on value x?0000 0000? restrictions none length 32 bits type read/write address xxxx 1628 power on value x?0000 0000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 cell re-assembly (reasm) page 271 of 553 12.7: reasm cell hec correctable error counter/non-user cell counter counts cells with correctable hec errors or non-user cells selectable by bit 15 in the reasm control regis- ter. the counter will increment when a cell with a correctable hec is received. 12.8: reasm cell hec uncorrectable error counter/rm cell counter counts cells with uncorrectable hec errors or rm cells selectable by bit 15 in the reasm control register. the counter will increment when a cell with an uncorrectable hec is received. 12.9: reasm total user cells received counter counts total user cells received. this counter will increment each time a user cell is processed. this count includes cells with hec errors and cells with vpi/vcis that are not valid. . length 32 bits type read/write address xxxx 162c power on value x?0000 0000? restrictions none length 32 bits type read/write address xxxx 1630 power on value x?0000 0000? restrictions none length 32 bits type read/write address xxxx 1634 power on value x?0000 0000? restrictions none IBM2520L8767 ibm processor for atm resources cell re-assembly (reasm) page 272 of 553 atmrm.chapt05.01 08/27/99 12.10: reasm total user cells received with clp=0 counter counts total user cells received with clp bit equal to zero. the counter will increment whenever a user cell is received with the cell loss priority bit equal to zero. 12.11: reasm out of range lcd register defines the lcd that all out of range vpi-vcis will be received on. this register will be used to determine the lcd that cells that have vpi-vci values that are out of range. the high 26 bits are used to select the lcd, the low six bits are ignored. length 32 bits type read/write address xxxx 1638 power on value x?0000 0000? restrictions none length 32 bits type read/write address xxxx 164c power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 cell re-assembly (reasm) page 273 of 553 12.12: reasm state machine register returns the state of reasms internal state machines. this register contains the current state of reasms state machine variables. it is to be used for debug purposes only. it should not be written during normal operation. 12.13: reasm cell staging array provides access to receive buffer. this array is divided into four 64-byte buffers used to assemble cells received from the line. length 10 bits type read/write address xxxx 1648 power on value x?000? restrictions diagnostic mode must be set to write this register. length 64 words x 32 bits type read/write address xxxx 1700-7ff power on value x?00000000? restrictions this array can only be accessed when the diagnostic mode bit in the control regis- ter is set. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 274 of 553 atmrm.chapt05.01 08/27/99 entity 13: receive aal processing (raal) functional description raall implements the receive functions of the atm adaptation layers (aal). the following functions are supported: raw cell mode - routed/spliced - cut-through - fifo mode aal5 - high speed data transfer w/ variable bit rate - routed/spliced - mode 6/7 cut-through - scatter mode the aal functions include: protocol verification cell reassembly into packets cell crc verification packet reassembly timeouts and errors raall also performs: lc based statistics oam f5 blocking support packet thresholding for cut-through support IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 275 of 553 reassembly timeout (rto) processing reassembly timeout processing is supported for aal 5/6/7 lcs. it can be enabled on an lc basis by turning on the rto enable bit in the lc. the following registers also need to be properly set up to run rto process- ing: raall lc table bound registers raall reassembly timeout value register raall reassembly timeout pre-scaler register see the register descriptions for more register details. the lc table registers define the lc table that the rto processor examines. the value register is used as a compare value against a counter that counts based on a pre-scaler. each time the registers compare, rto processing is started for a single lc and the time base is reset. rto processing checks the rto bit. if it is reset, it sets it and continues. if it is set, then a timeout occurs and the lc is placed in error state and the current packet is either freed or surfaced to the user via an event. the rto bit is reset with each inbound cell received or when a packet either completes or goes into error state. note: if the rto bit is set when rto processing is disabled, it will remain set unless the lc goes into error state. an lc needs to be touched twice to cause a timeout (once to set it and once to detect that it is already set). the time base starts running as soon as the rto processing is complete. currently, the rto processing takes the back seat if there are cells to be processed. so, rto processing can be held off indefinitely. note: for aal0 fifo rto, it is assumed that the software will reset all counts and/or remove all cells from the fifo before resetting the state to idle. this needs to be done in order to maintain the reassembly count! lc statistics if enabled, raall maintains lc level statistics. the following statistics are kept: total user cells received total user cells received with clp=0 using these numbers, the total user cells received with clp=1 can be calculated. both are 32-bit counters that wrap on overflow. using the raall lc statistics overflow register, the overflow behavior of the counters can be changed to overflow on a value other than 0xffffffff. if enabled in the mode reg, software is notified of overflow events via the counter overflow event queue specified in rxque. statistics can be enabled on a lc basis by turning on the statistics enable bit in the lc. statistics can be globally enabled/disabled across all lcs by setting the appropriate bit in the raall mode register. the global enable/disable overrides all lc enables, and the global disable overrides the global enable. if oam blocking is enabled, then you might as well turn on statistics because you get them for free. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 276 of 553 atmrm.chapt05.01 08/27/99 oam f5 blocking support if enabled, raall maintains oam f5 blocking statistics on an lc basis. the following statistics are kept: total user cells received - tuc 16-bit interleaved parity - bip-16 both are 16-bit values. blocking can be enabled on a lc basis by turning on the blocking enable bit in the lc. blocking can be globally enabled/disabled across all lc?s by setting the appropriate bit in the raall mode register. the global enable/disable overrides all lc enables, and the global disable overrides the global enable. when an oam f5 flow cell is received, the current receive tuc and bip-16 are appended in the first full eight-byte word after the cell data (depends on what offset is set to in the lc). this information can then be used along with the values in the cell to complete the reporting/monitoring process. the bip-16 is reset to zero and the tuc takes the value from each pm cell. by doing this, the software does not need to maintain any temporary copies of these fields. the pm processing does not affect the lc statistics fields. note: if oam blocking is enabled, you might as well turn on statistics because you get them for free. bad cell support (bad hec, vp/vc out of range, and vc index equal zero) if reception of bad cells is enabled in reasm, then bad cells are received as 53-byte cells using the non-user data registers to select the receive queue, offset, and pool id. the lc pointer in the packet header is zeroed. these cells are only received if receive bad frame mode has been turned on in rxque. this function may be desirable for network tracing tools. raw cell routing support raw cells (53, 52, or 48 bytes) can be routed back out the transmit interface. normally, when a cell is received, the receive lcd is written into the packet header and the buffer is surfaced to the user. when routing is enabled, by turning on the msb of the lcd state field, the second word or the receive lcd is used as the data to fill in the packet header lcd field. the buffer is then sent to the scheduler and rescheduled for transmission. this allows cells to be routed out the transmit interface with the same or different vp/vc. when routing cells, the default is to surface non-user data cells to the user. by turning on bit two of the lcd state field, all non-user data cells will be routed the same way as user data cells for that lcd. the user should be sure to turn on the free on transmit bit in the second word of the lcd so the cell buffers are freed when they are re-transmitted. the original clp bit from the inbound cell is always written to the lsb of lcd field in the packet header. general packet/cell buffer layout when not using fifos, all cells and packets are assembled in packet buffers. these buffers have a packet header followed by the data section. the following figure shows the general layout of aal5 packets and aal0 cells: IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 277 of 553 the first pad is determined by the receive offset field in the lc or the nud receive offset register. in the case of a blocking cell, the second pad is generated to align the current statistics on an eight-byte boundary. in the aal5 packet, the aal5 trailer is received into the packet buffer as it was received. so, all pad bytes are also received. it would be a good idea to have a minimum buffer size of 128 bytes. 64-byte buffers will work only if receiving raw cells in 48-byte mode with zero offset. also, no oam cells would be able to be received. packet/cell layout in packet buffer aal 0 and nud cell oam blocking cell aal5packets packet header (16 bytes) packet header (16 bytes) packet header (16 bytes) pad (0-7 fbytes) pad (0-7 fbytes) pad (0-7 fbytes) cell data (48 - 53 bytes) cell data (48 - 53 bytes) packet data (0 - 64 bytes) pad aal 5 trailer (8 -48 bytes) oam data (8 bytes) (0 - 7 bytes) IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 278 of 553 atmrm.chapt05.01 08/27/99 shutting down an lcd to shut down an lcd for receive, the following steps should be followed: 1. clear the entry for this lcd in the lcd table table (to stop receiving cells for this lcd). 2. do an lcd update operation that sets lcd state to down. 3. read the lcd reassembly pointer. 4. if the reassembly pointer is non-zero and lcd is set up to do cut-through, be sure to free any dma descriptor that was added with the cut-through operation. 5. if reassembly pointer is non-zero, free it to pools. 6. if reassembly pointer is non-zero, decrease the reassembly count by writing the reassembly count regis- ter. if reassembly timeout is being used, the following sequence can be used: 1. clear the entry for this lcd in the lcd table table (to stop receiving cells for this lcd). 2. wait for reassembly timeout event. 3. if set up for cut-through, a dma canceled event will also flow. 4. at this point, do an lcd update operation that sets lcd state to down. 5. if set up to receive the packet address in the event, free it to pools. performing an lcd shutdown of a cut-through lcd there are two possibilities here. the first uses the timeout feature and is immeasurably preferable since it makes the best use of the on-chip mechanisms for resource allocation and control. to shut down the cut-through lcd, use the following procedures. using the timeout feature the key here is to use the reassembly timeout feature. one can shut down 100s or 1000s of lcds and then wait for a short time (approximately 100 microseconds) and everything will return to normal. you may use the second set of reassembly timeout registers allowing you to leave the first set alone and use the second set for the shutdown mechanism. 1. clear the lcds entry in the lcd table table (the vci to lcd translate table in reasm, offset 0x 161c). this halts cell reception for this lcd. 2. flush the reasm cache. 3. wait for the reassembly timeout event (see note below). IBM2520L8767 now cleans up resources used for this lcd. 4. if the lcd is set for cut-through and it has a dma descriptor enqueued to the packet, awaiting packet completion, a dma cancelled event will follow the reassembly timeout. 5. now the state of the lcd can be checked to determine if it is ?error? or ?idle?. either way, the lcd is now shut down and any other administrative processing may be done. 6. using the lcd update operation register (raall), set the state of the lcd to ?down?. this is the ?state? field of the receive lcd and it is set to 0x00. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 279 of 553 note: the reassembly timeout process can be considerably sped up by temporarily changing the lc table lower bound register and the lc table upper bound register in raall. because it is known which lcd(s) is (are) being shut down, the lower and upper bounds can both be set to the lcd entry you are shutting down. that way, only one lcd is examined at the timeout rather than an entire range of lcds (as defined by the lower/upper bound registers). once this is completed, the bounds can be reset to their original values and everything is back to normal. manual shutdown this is much more complicated since resources must be checked and freed as required while shutting down an lcd. there are three specific mechanisms depending on whether the lcd is mode 6, mode 7, or (dma) scatter mode. you will have to adapt the mechanism to your specific system. this explanation is intended to give a general understanding as to which issues must be considered. because the lcds are being shut down manually, you must be particularly aware of which resources are in use and free those that will not be used. resources to keep in mind are packet buffers, dma descriptors, and caches. remember also to free the packet (if needed) at the finish of a shutdown. 1. clear the lcds entry in the lcd table (the vci to lcd translate table in reasm, base address is offset 0x161c). this halts cell reception for this lcd. (same as in i.) 2. flush the reasm cache. this guarantees that the previous step is utterly complete. 3. read the state of the lcd state variable in the lcd and perform the following steps: step if ... then ... 1 state == down done. 2 state == idle using lcd update op, set state to down. done. 3 state == reasm decrement the reasm counter. this is very important! 4 mode == mode 6 read the reasm pointer and free the pointer. set lcd state to down. done. 5 mode == mode 7 (not using scatter/gather) read the lcd descriptor state variable. descriptor state var == false set lcd state to down. free the packet. done. descriptor state var == true free the descriptor. set lcd state to down. free the packet. done. 6 scatter/gather mode check the lcd numdesc field. numdesc == 0 (no descriptors) set lcd state to down. free the packet. done. numdesc != 0) (free descriptors) either step through descriptor list in packet and free each one, or use dma engine to do this. note: freeing the descriptor will put the associated host page back on the available list so the host pages do not need special treatment. set lcd state to down. free the packet. done. 7 state == error set lcd state to down. done. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 280 of 553 atmrm.chapt05.01 08/27/99 aal5 packet thresholding for cut-through support raall supports packet header thresholding for aal5. the threshold is set in the lcd. once a number of bytes the threshold value has been received, a packet threshold event is raised to the user. at this point, the packet header contains valid offset and length values, and the atm header field in the packet header is from the first cell received for the current packet. this allows the user to inspect the packet header and initial packet data before the entire packet has been reassembled. the user has two options for determining when the packet has been reassembled. the two options are controlled by the appropriate bit in the control register. first, the user can choose to have a packet complete event raised when the packet completes. second, the user can poll the packet header to watch for the packet to complete. the polling method utilizes the done and error bits in the packet header. the method used depends on how the user is doing the cut-through processing. for example, if correlating two events is a problem, the polling method should be used. note: in both methods error events are always raised. when using the single event mode, it is required that the receive queues are not allowed to reach a full condition or that there is enough receive queue room for all threshold events. if this is not the case, buffers can be lost if threshold events are flushed due to queue full conditions. rx aal 5/6/7 cut-through support cut-through support allows software to be written that minimizes latency and the number of interrupts (events) that occur. cut-through support uses two mechanisms to accomplish this, automatic header dmas and software-assisted dmas upon packet completion. automatic header dmas automatic header dmas occur as the cells arrive for a packet. as the amount of receive data exceeds the configurable threshold, a dma is scheduled that dmas the packet header and data into a system buffer specified by a software provided system dma descriptor. an event can be placed on a receive queue after the dma is complete. at this point, software has all of the header data in system memory and can operate on it in an efficient manner. the threshold should be set to a value that is large enough so that software can process the entire header and set up a subsequent dma to move the protocol payload data into a system buffer when it arrives. for example, given enough of the protocol headers, the length of a tcp/ip packet can be derived, and the session info can be derived. given this info, a dma can be setup to do the tcp/ip check- sum and move the data into a system/user buffer upon packet completion. this is referred to as software assisted dmas on packet completion. setting up an lcd for rx cut-through support to set up an lcd for receive cut-through support, the all type must be set to 0x7. by doing this, the most significant three protocol enable flags are redefined to be the receive queue number from which header the dma descriptors are obtained. this receive queue should be set up to run in reverse direction, and should be filled by software with system dma descriptor addresses. this queue should not be allowed to go to an empty state or headers will be delayed and eventually packets will be thrown away if the packet completes before the header was scheduled to be dmaed. in addition, the header threshold value in the lcd needs to be set up. the value in this field determines when the header is dmaed. once the number of bytes of receive data exceed the value in this field, the header is eligible to be dmaed. if a dma descriptor is available from the specified receive queue, the dma is sched- uled. if no dma descriptors available, then an attempt to schedule the dma will be made when the next cell is IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 281 of 553 received. if the packet is completed and no dma descriptors are available and the header has not been dmaed, the packet is discarded. if the packet is completed before the threshold is met, the entire packet is dmaed using a header dma descriptor. dma descriptors used for header dmas the dma descriptor placed in the dma descriptor receive queue, must be valid descriptor. the source address and length do not need to be filled in the first descriptor, as these are filled in by the IBM2520L8767 when the header dma is scheduled. either a single descriptor or a compound descriptor can be used (make sure the number of descriptors is filled in least significant bits when they are placed in receive queue just as if they were being enqueued to gpdma). the user can be notified when the dma is complete in several ways. either the notify on completion flag can be set, or the second descriptor can be used to enqueue an event to a receive queue. doing software assisted dmas on packet completion after processing the packet header, an arbitrary system dma descriptor can be built for the packet. the packet address can be found in the sixth word of the packet header. note: this implies that the receive offset is at least 24 bytes. the address of the dma descriptor (and the number of descriptors in low order bits) is then written into the raall cut-through descriptor address registers. once the descriptor address is written, a raall cut-through operation is performed by writing the raall cut-through operation (ctop) registers with the base address of the packet. raall then looks at the current state of the packet. if the packet is complete and has no errors, dma is immediately scheduled. if the packet is complete, but there were errors, a dma canceled event is placed on the appropriate receive queue, and the event data contains the system dma descriptor address of the descriptor that would have been used (the packet is not freed). if the packet is still being reassembled, then the lcd is marked for processing when the packet completes or an error occurs. if the lcd was marked for later processing, when a packet completes, the dma descriptor is scheduled or a dma canceled event is posted, depending if errors occurred. alternate header dma method normally the header data dma is scheduled as soon as the threshold is crossed and a descriptor is available. alternatively, the aal type can be set to six instead of seven. when set to six, the header dma is not sched- uled until the packet is complete. receive aal0 and non-user data cut-through support cut-through can also be used in non-fifo aal0 modes and can be set up for non-user data cells. for aal0 lcds, the rto enable bit in the lcd can be set to enable cut-through processing. when this bit is set, the rxq_num field is used to get dma descriptor instead of specifying which queue to place events on. in this mode, for each cell that is received, a dma descriptor is obtained from the specified receive queue. the dma descriptor is then scheduled with gpdma. if there is no dma descriptor avail, then a no descriptor event is enqueued. cut-through for non-user data cells is similar. the receive queue from which dma descriptors are obtained, is specified in the raall non-user data config register. cut-through for non-user data cells is enabled by setting bit 15 in the raall control register. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 282 of 553 atmrm.chapt05.01 08/27/99 aal5 scatter support scatter (as in scatter/gather) is now supported for aal5. the following parameters need to be specified: systempagesize(see raall scatter page size and queue register on page 286) rxque queue number that pages are stored in (see raall scatter page size and queue register) first/single page size if used (see raall scatter page size and queue register) number of header data bytes (in lcd) rxque queue number that holds the header dma descriptors (in lcd) the following figure shows the format of a packet and how it is divided for dmas: IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 283 of 553 the packet header is 0x18 bytes long when doing scatter mode. the last four bytes of the packet header contains the buffer address in the upper bits, and the lower bits contain how many real buffers are in the dma list that follows. scatter packet buffer layout 0x18 var off 0x18 var off packet header packet header dma list dma list pad pad num head bytes page 1 page 2 single page mode page n page n + 1 pad&aal5trailer single page size IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 284 of 553 atmrm.chapt05.01 08/27/99 the dma list follows immediately after the packet header and is variable length based on how many pages were needed to dma the packet into the system. the receive offset specified in the lcd, must be large enough to hold the packet header and the maximum dma list that will be used. there may be some pad bytes based on the value of the receive offset specified in the receive lcd. this can be used to align the packet data on some boundary (eight-byte boundary is optimal for IBM2520L8767). next is the actual packet received from the network. it is divided into a header area, followed by 0-n fully populated pages, possibly followed by a partial page, followed by the aal5 pad and trailer bytes. all of these areas are contiguous in the IBM2520L8767. the header area is 0-255 bytes as specified in the lcd. this area is kept with the packet header and dma list when dmaed to the system. this allows the device driver to split protocol information and user pages before moving to the system. complete pages are dmaed to the system as the packet is received. when a complete page has been received, a real system page address is obtained from the specified receive queue number. using this address, the IBM2520L8767 address, and the page size, a dma descriptor is built and enqueued to dmaqs, and the address is written to the dma list in the packet header. when the packet completes (uind=1 in last cell), the final page is dmaed to the system, and the dma list is updated. the lower bits of this final dma list entry contains how many bytes were in page n+1 (zero if page was complete). once the dma list is updated, a dma descriptor is obtained from the receive queue number specified in the ctrxqnum in the lcd. this final descriptor is used to dma the data in packet header through the header bytes into a system specified address. this mechanism is similar to normal cut-through modes, so the IBM2520L8767 buffer can be freed using subsequent dma descriptors. single page mode for short packets, a single page size can be specified in raall scatter page size and queue register. if all of the packet data and the packet header fit in this space, then all of the data is dmaed with the packet header when the packet completes. scatter error recovery during reception, it is ok to not have a real page address available. as more cells are received, raall will attempt to catch up. if a packet completes and there is a lack of pages, then a no page event is posted. if running in receive bad frame mode then the user needs to query and free up any entries in the dma list. this can be done easily with the new n-to-1 dma descriptor. alternately, the user can move the rest of the data and surface the packet because the packet is actually a good packet. if not running in receive bad frame mode, the dma list and packet are automatically freed for the user and the event contains the lcd address instead of the packet address. if an error occurs in the packet (eg. crc), then the corresponding event (eg. bad crc) is posted. again, the cleanup depends on bad frames being received. if a packet is received, and all pages were dmaed, but there was a lack of dma descriptor to dma the header, then a no descriptor event is posted. again, cleanup depends on bad frames being received. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 285 of 553 13.1: raall max sdu length register used to verify aal5 packet lengths will not exceed the size set in this register. this register contains the maximum sdu size that is allowed to be received. if the packet size exceeds this value, a "too big" event is surfaced. this register is only used if maximum sdu size in the lc is set to zero. 13.2: raall lc reassembling count register used to count the number of lcs that are currently reassembling packets. this register contains the count of lcs that are currently reassembling packets. this count is incremented each time a new reassembly is started and decremented each time a reassembly completes. this is a free running counter that can be thresholded using the raall lc reassembling threshold register. an interrupt can also be generated when this counter is in zero and non-zero. normally, only aal5 packets count in this calculation by default. if the proper bit in the control register is set, then aal0 fifo lcs also count. fifo lcs are added when any cell is received in the fifo, and removed when all cells are removed from the fifo. they are also removed when they timeout. if this register is written in non-diagnostic mode, the value is ignored, and the value of this register is decre- mented by one. this function is intended to be used when shutting down an lcd. length 16 bits type read/write address xxxx 0c5c power on value x?0000ffff? restrictions none length 20 bits type read/write address xxxx 0c38 power on value x?00000000? restrictions can only be written with a value in diagnostic mode. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 286 of 553 atmrm.chapt05.01 08/27/99 13.3: raall lc reassembling threshold register used to threshold the number of lcs reassembling. this register contains the threshold count of lcs reassembling. when the value in the raall lc reassembling count register is greater or equal to this register, the appropriate status bit is turned on. when this register is written with a value of zero, no threshold- ing is done. 13.4: raall scatter page size and queue register used to specify the system physical page size. this register specifies the encoded system page size and the receive queue number that holds the real buffers for scatter mode. the following are the bit descriptions: length 20 bits type read/write address xxxx 0c3c power on value x?00000000? restrictions none length 11 bits type read/write address xxxx 0c20 power on value x?00000000? restrictions none single page size reserved buffer queues reserved page size 109876543210 bit(s) name description 10-8 single page size specifies the buffer size used for single page packets. the following encodings are used: 0 disable single page mode 1128bytes 2256bytes 3512bytes 41kbytes 52kbytes 64kbytes 78kbytes 7 reserved reserved. 6-4 buffer queues specifies which receive queue holds the real buffer addresses. 3 reserved reserved. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 287 of 553 13.5: raall scatter dma list free destination register used to specify the destination that is used to free dma lists for bad packets. this register specifies the desti- nation address that is used to free dma lists for bad packets. this is only used when receive bad frame mode is set to not receive bad frames. in this mode, this destination should be set the receive queue enqueue address for the queue number that is used to store scatter page addresses. a dma descriptor is built that frees the dma list back to the appropriate receive queue by using this destination address. 13.6: raall non-user data config register used to specify how non-user data (nud) should be processed. this register contains the information on how to process non-user data cells. the information in this register is specified using the same format as the receive lcd for consistency. the nud config register has the same format as the packed information in word zero of the receive lcd, and bits 27-26,20,18-16,14-0 are valid. if nud cells are to be routed for a particular lcd, the routed lcd for that lcd is used. 2-0 page size specifies the real buffer size. the following encodings are used: 0512bytes 11kbytes 22kbytes 34kbytes 48kbytes 5 16k bytes 6 reserved 7 reserved length 32 bits type read/write address xxxx 0c24 power on value x?00000000? restrictions none length 32 bits type read/write address xxxx 0c40 power on value x?00000010? restrictions none bit(s) name description IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 288 of 553 atmrm.chapt05.01 08/27/99 13.7: raall raw mode early drop pool-id register used to specify the pools pool id to use for error state end of packet (eop) cells when routing raw cells. this register contains the pools pool id to use for error state eop cells when routing raw cells. eop cells have uind=1. 13.8: raall interrupt enable register used to specify which status register bits should be used to generate interrupts. see note on set/clear/read type registers on page 71 for more details on addressing. see raall status register on page 289 for the bit descriptions. length 4bits type read/write address xxxx 0c18 power on value x?00000000? restrictions none length 6bits type clear/set address xxxx 0c00 and 04 power on value x?00000039? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 289 of 553 13.9: raall status register used to set raall modes and relay raall status information. this register contains the mode bits and the status bits. see note on set/clear/read type registers on page 71 for more details on addressing. the following are the bit descriptions: length 6bits type clear/set address xxxx 0c08 and 0c power on value x?00000002? restrictions status bits are driven by raall, so even if the software writes these, the value will most likely change. bad offset in lcd sync op failed threshold exceeded count /= 0 count = 0 reserved 543210 bit(s) name description 5 bad offset in lcd when this bit is set, a bad offset was detected in the lcd. 4 sync op failed when this bit is set, a sync operation has failed because more cells were synchronized than were in the receive fifo. 3 lc reassembling threshold exceeded when this bit is set, the raall lc reassembling count register has exceeded the threshold set in the raall lc reassembling threshold register. 2 lc reassembling count /= 0. when this bit is set, the raall lc reassembling count register is not equal to zero. 1 lc reassembling count = 0. when this bit is set, the raall lc reassembling count register is equal to zero. 0 reserved reserved IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 290 of 553 atmrm.chapt05.01 08/27/99 13.10: raall control register used to set raall modes. this register contains the mode bits that specify how raall is to operate. see note on set/clear/read type registers on page 71 for more details on addressing. the following are the bit descriptions: length 29 bits type clear/set address xxxx 0c10 and 14 power on value x?00000000? restrictions none disable cut-through for mpeg fifo mode enable packet header timestamp enable direct cutthrough disable lcd caching include aal5 trailer in cutthrough dma disable aal5 length checking disable aal5 crc checking disable aal5 cpi checking use clp from cell when cell routing use clp from packet when packet routing enable packet counts enable host data word in lcd/packet header enable new aal5 error checking enable non-user data cut through enable aal 5 packet trailer debug word aal 5 threshold mode enable reassembly timeout processing for raw fifo mode enable reassembly counting for raw fifo mode enable crc-10 for cells with pti=7 enable crc-10 for cells with pti=6 enable crc-10 for cells with pti=5 enable crc-10 for cells with pti=4 rx bad crc-10 cells enable counter overflow events enable statistics reserved enable blocking diagnostic mode graceful reset 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 28 disable cut-through for mpeg fifo mode when set, all lcds that use the aal5 mpeg fifo mode, will surface packet events instead of doing an aal5 mode 6 cut-through operation. 27 enable packet header timestamp when set, a timestamp is generated by the rxque timestamp logic and is placed in the packet header at offset 0x0c when the last cell is processed. it is also generated when the first cell is generated. so if using cut-through mode 7, you can potentially get both timestamps. by using this option, you lose the atm header field in the packet header. this has some consequences. for example, you should use 52- or 53-byte raw modes for raw mode cells if the atm header needs to be examined. this function is intended for use by sniffer-like functions. 26 enable direct cutthrough when set, cut assumes that the cut-through receive queue holds buffer addresses instead of dma descriptors. the dma descriptor is built by raall and has a length of one. this mode has the advantage of being more efficient, but only a single descriptor is allowed. 25 disable lcd caching ?when set, the receive lcd information is not cached in raall. 24 include aal5 trailer in cutthrough dma when set, the aal5 trailer is dmaed as part of a mode 6 cut-through dma. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 291 of 553 23 disable aal5 length checking when set, the aal5 trailer length field is not checked. 22 disable aal5 crc checking when set, the aal5 trailer crc is not checked. 21 disable aal5 cpi checking when set, the aal5 trailer cpi bytes are not checked against zero. 20 use clp from cell when cell routing when set, the clp bit from the received cell is used to fill in the clp bit in the lcd of the packet header when routing cells. when cleared, the lsb of the second word of the lcd is used to fill in the clp bit of the lcd of the packet header when routing cells. 19 use clp from packet when packet routing whenset,theordedclpbitacrossanaal5packetisusedtofillintheclpbitin the lcd of the packet header when routing packets. when cleared, the lsb of the second word of the lcd is used to fill in the clp bit of the lcd of the packet header when routing packets. 18 enable packet counts when set, the total user cells rx with clp=0 field in the lcd is used as a total packets rx count. the same event is generated when the counter overflows regard- less of how this bit is set. this count is a total of the good and bad packets received. 17 enable host data word in lcd/packet header when set, the eighth word in the receive lcd is used as host data. this word is written into the fifth word of the packet header. the low order eight bits of the host data are ignored and should be set to zero. 16 enable new aal5 error checking when set, the new proposed aal5 error checking is enabled. this is useful for mpeg-2 processing, and allows the new aal5 event to flow. this new event specifies that an aal5 packet was received, and the crc was bad, but the length was good. 15 enable non-user data cut through when set, non-user data cells are automatically dmaed into system storage using dma descriptor from the receive queue specified in the raall non-user data config register. when cleared, non-user data events are surfaced as normal. if no descrip- tors are avail, then a no dma descriptor event is surfaced. 14 enable aal 5 packet trailer debug word when set, 0xbadddeadbeffcafe is written in the word following the word that contains the aal5 packet trailer (or last data in too big case). when cleared, the word is not written. 13 aal 5 threshold mode when set, packet complete events are not generated if a packet threshold event was generated. when cleared, packet complete events are always generated. error events are always generated regardless of the state of this bit. 12 enable reassembly timeout pro- cessing for raw fifo mode when set, the reassembly timeout processing is performed on raw fifo lcs. 11 enable reassembly counting for raw fifo mode when set, the count of lcs reassembly includes aal0 fifo lcs. 10 enable crc-10 for cells with pti=7 when set, crc-10 checking is done on cells with a pti=7. 9 enable crc-10 for cells with pti=6 when set, crc-10 checking is done on cells with a pti=6. 8 enable crc-10 for cells with pti=5 when set, crc-10 checking is done on cells with a pti=5. 7 enable crc-10 for cells with pti=4 when set, crc-10 checking is done on cells with a pti=4. 6 rx bad crc-10 cells when set, non-user data cells with bad crc-10 fields are received as events. the event will be the actual cell buffer if in receive bad frame mode, otherwise only the lc is surfaced in the event. when reset, these cells are flushed. this is only valid for pti field types that have crc-10 checking enabled. 5 enable counter overflow events when set, counter overflow events are generated when an lc statistics counter over- flows. when reset, the counter will roll over with no notification. 4 enable statistics when set receive statistics are kept on all lcs. bit(s) name description IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 292 of 553 atmrm.chapt05.01 08/27/99 13.11: raall lc table bound registers used to specify the lower/upper bounds of the lc table. the lower bound should be initialized to the address of the first lc in the lc table if reassembly timeout processing is to be done. the upper bound should be initialized to the address of the last lc in the lc table if reassembly timeout processing is to be done. the second set of rto related registers is meant to be used with mpeg fifo mode lcds, but can be used for whatever. 3 reserved reserved. 2 enable blocking when set enables oam blocking on all lcs. note: the lc enable went away. 1 diagnostic mode when set, raall is placed in diagnostic mode. 0 graceful reset when set, no new buffers are requested. this has the affect of allowing all currently reassembling buffers to complete, while all new reassembly requests are rejected. reassembly timeout processing continues while set. during graceful reset, all non-user data cells and aal0 cells (raw) are discarded. the aal0 fifos are treated like reassembly buffers. if there are cells in the fifo, new cells are accepted. if no cells are in the fifo or the fifo is in error state, then new cells are not accepted. reg lower bound 1 upper bound 1 lower bound 2 upper bound 2 length 32 bits 32 bits 32 bits 32 bits type read/write read/write read/write read/write address xxxx 0c2c xxxx 0c30 xxxx 0c44 xxxx 0c48 power on value x?00000000? x?00000000? x?00000000? x?00000000? restrictions must be 128-byte aligned (low order seven bits not writable). bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 293 of 553 13.12: raall reassembly timeout value register used to specify the time interval used for reassembly timeout processing. this register is the number of pre-scaler intervals between reassembly processing. the pre-scaler interval is determined by raall reassembly timeout pre-scaler register a single lc is checked for reassembly timeout during each reassembly processing interval. when this register is set to zero, reassembly timeout processing is disabled. for more information on how reassembly timeout conditions are processed see reassembly timeout (rto) processing on page 275 . the second set of rto related registers is meant to be used with mpeg fifo mode lcds, but can be used for whatever. 13.13: raall reassembly timeout pre-scaler register used to specify the time interval of each rto timer tick. this register determines the number of 30-ns inter- vals between rto timer ticks. the value in the register plus one is the number of 30-ns intervals between rto timer ticks. so, the default value of zero means that the rto timer ticks every 30ns. if a value of four is placed in this register, the rto timer ticks every 150ns (5 ? 30 ns). for more info on how reassembly timeout conditions are processed see reassembly timeout (rto) processing on page 275 . the second set of rto related registers is meant to be used with mpeg fifo mode lcds, but can be used for whatever. reg timeout 1 timeout 2 length 32 bits 32 bits type read/write read/write address xxxx 0c34 xxxx 0c4c power on value x?00000000? x?00000000? restrictions none reg prescale 1 prescale 2 length 16 bits 16 bits type read/write read/write address xxxx 0c54 xxxx 0c1c power on value x?00000000? x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 294 of 553 atmrm.chapt05.01 08/27/99 13.14: raall lc statistics overflow register used to specify the overflow value of the lc statistics. this register specifies at what value the lc statistics roll over. by default, this register is set to zero and specifies that the counters roll over at 0xffffffff. if this regis- ter was set to 0x00010000, the lc statistic counters would count up to 0x0000ffff and then roll over to zero. 13.15: raall fifo sync operation register used to synchronize raall and the software fifo counts. this register is written to update the fifo cell counts. raall maintains the total cell count for each fifo. as software processes these cells, the synchro- nizing operation needs to be performed to decrement the cell count to make room for incoming cells. it is obviously important to keep the software and raall in synchronization. when this register is written, the most significant bits specify what the lc the operation is for. the low order six bits specify a cell count. the value of zero in the cell count field means use the threshold value. this cell count is subtracted from the raall total cell count when the operation is completed. for example, if the cell threshold is set to 128, and the low order bits are zero, then 128 is subtracted from the total cell count. if they are set to five, then five is subtracted from the total cell count. a read to this register returns the current/last lcd address in the upper 26 bits. bit zero is zero if a synchroni- zation operation is not running, and one if a synchronization operation is running. length 32 bits type read/write address xxxx 0c58 power on value x?00000000? restrictions none length 32 bits type read/write address xxxx 0c50 power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 295 of 553 13.16: raall lcd update data registers used to specify data to write into the lcd on the update lc operation. these registers contain the data used in the lc update operation. for more information on its use, see the raall lcd update op registers. this register changes to contain the updated data written to the lc word while the operation is completing. the second set of lcd update registers is meant for the core to use, but is available for general use. 13.17: raall lcd update mask registers used to specify which data to write into the lcd on the update lc operation. this register contains the mask used in the lc update operation. for more information on its use, see the raall lcd update op registers. the second set of lcd update registers is meant for the core to use, but is available for general use. register update 1 update 2 length 32 bits 32 bits type read/write read/write address xxxx 0c6c xxxx 0c80 power on value x?00000000? x?00000000? restrictions none register update 1 update 2 length 32 bits 32 bits type read/write read/write address xxxx 0c70 xxxx 0c84 power on value x?00000000? x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 296 of 553 atmrm.chapt05.01 08/27/99 13.18: raall lcd update op register used to specify what lcd word to update. this operation is used to update a portion of an lcd. if this opera- tion is not used, then software or the IBM2520L8767 updates of the lcd may be lost because the lcd is cached in the IBM2520L8767 while cells are being processed. this register is written with the address of the lcd word to update. once this register is written the update operation starts. all subsequent reads or writes to the data, mask, or update registers are held off until the operation completes. a read-modify-write will occur to update the portion specified by the mask with the masked value in the data register. normally this register would not be read. however, if it is read, the low order bit is read as zero and the next lowest order bit (bit 1) is read as the busy bit. this signifies whether an operation is still going on. if an opera- tion is still going on, a new write to any of the data, mask, or update operation registers is held off until the original operation is complete. the second set of lcd update registers is meant for the core to use, but is available for general use. 13.19: raall cut through desc address registers used to hold the dma descriptor address for cut-through operations. this register is used to hold the dma descriptor address for cut-through operations. for more information, see the cut-through discussion. a second set of ctop registers was added this pass. register update 1 update 2 length 32 bits 32 bits type read/write read/write address xxxx 0c74 xxxx 0c88 power on value x?00000000? x?00000000? restrictions the low order two bits are not writable. register set ctop 1 ctop 2 length 32 bits 32 bits type read/write read/write address xxxx 0c78 xxxx 0c90 power on value x?00000000? x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 297 of 553 13.20: raall cut through op (ctop) registers used to notify raall that a packet has a dma descriptor address to be scheduled on packet completion. this register is used to notify raall that a packet has a dma descriptor address to be scheduled on packet completion. for more information, see the cut-through discussion. a second set of ctop registers was added this pass. register set ctop 1 ctop 1 length 32 bits 32 bits type read/write read/write address xxxx 0c7c xxxx 0c94 power on value x?00000000? x?00000000? restrictions reads last value used for previous cut-through operation. low order bit indicates ctop ongoing if set. low order six bits are not writable. IBM2520L8767 ibm processor for atm resources receive aal processing (raal) page 298 of 553 atmrm.chapt05.01 08/27/99 13.21: raall cut through hardware fifo registers used to specify addresses of hardware fifo and hardware complete registers. these registers specify addresses of hardware fifo and hardware complete registers. the base registers specify where fifo and complete register set zero are located. the fifo and complete registers for each additional channel are calculated using the channel number ? the corresponding size register. the maximum size (distance between registers) is 128k. the size registers have the following encoding: register fifo base fifo size complete base complete size length 32 bits 32 bits 32 bits 32 bits type read/write read/write read/write read/write address xxxx 0cb0 xxxx 0cb4 xxxx 0cb8 xxxx 0cbc power on value x?00000000? x?00000000? x?00000000? x?00000000? restrictions none bit(s) description 31-4 reserved. 0-3 0000 4byte offsets 0001 8byte offsets 0010 16 byte offsets 0011 32 byte offsets 0100 64 byte offsets 0101 128 byte offsets 0110 256 byte offsets 0111 512 byte offsets 1000 1k byte offsets 1001 2k byte offsets 1010 4k byte offsets 1011 8k byte offsets 1100 16k byte offsets 1101 32k byte offsets 1110 64k byte offsets 1111 128k byte offsets IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive aal processing (raal) page 299 of 553 13.22: raall - dma flag registers used to specify the flags field of dma descriptors that are built by raall. used for: cut-through descriptor, scatter page descriptor, free dma list descriptor, hardware fifo descriptor 1, and hardware fifo descriptor 2. these registers specify the flags field of dma descriptors that are built by raall. flags can be set for normal cut-through descriptor (includes mode 6 & 7 cut-through and descriptor for scatter header), scatter mode page descriptor, free dma list descriptor, hardware fifo dm descriptor, and hardware complete descriptor. length 18 bits type read/write address xxxx 0cc0 xxxx 0cc4 xxxx 0cc8 xxxx 0ccc xxxx 0cd0 power on value x?00000010? x?00000010? x?00002220? x?00000010? x?00000000? restrictions none bit(s) description 17-16 specify how the event data (if any) is formed. normally, the dma descriptor is used for dma events, but when the entire dma descriptor is built there is no descriptor address to use. 00 use dma descriptor address 01 use source address 10 use destination address 15-0 dma flags. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 300 of 553 atmrm.chapt05.01 08/27/99 entity 14: receive queues (rxque) functional description rxque has a single function: to manage the receive queues for software by providing an easy to use primi- tive interface. when talking about the receive queues, the term rxq is used to talk about a receive queue, and the term deq is used to refer to a dequeue operation and enq is used to refer to a enqueue operation. receive queue interface a group of eight receive queues are available for software use. the receive queues hold events or user speci- fied data. each queue entry (event) is 32 bits, and contains both a event type field as well as some event information. the event information typically contains a pointer (when low order bits are zeroed) to a packet buffer, a cell buffer, or an lcd. it can also contain a dma descriptor address or user specified data. raall rxque event structure 6 event info event type 26 IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 301 of 553 the following are the different event types that are defined: event summary and routing info (page 1 of 2) event number description event information error count tx comp tx dma rx dma abr pool 000000 = 00 aal5 packet event (packet complete) packet/lcd 000001 = 01 aal5 packet header event (packet start) packet 000010 = 02 aal5 packet with bad crc packet/lcd x 000011 = 03 aal5 packet with bad length field packet/lcd x 000100 = 04 aal5 packet that exceeds maximum length in lc packet/lcd x 000101 = 05 aal5 packet timeout packet/lcd x 000110 = 06 aal5 packet forward abort packet/lcd x 000111 = 07 aal5 packet cpi field not equal to zero packet/lcd x 001110 = 0e aal5 fifo packet packet 001111 = 0f aal5 packet with bad crc and good length packet/lcd x 001000 = 08 cell event (user data) packet/lcd 001001 = 09 nud cell event (non-user data) packet/lcd 001010 = 0a nud cell with bad crc-10 packet/lcd x 001011 = 0b bad cell - bad hec packet x 001100 = 0c bad cell - out of range packet x 001101 = 0d bad cell - index equal zero packet x 010000 = 10 aal0 cell dropped - lack of pools buffers lcd x 010001 = 11 aal5 cell dropped - lack of pools buffers lcd x 010010 = 12 nud cell dropped - lack of pools buffers lcd x 010011 = 13 fifo cell dropped - fifo full lcd x 010100 = 14 fifo threshold event lcd 010101 = 15 fifo full event lcd 010110 = 16 fifo rto event lcd x 011000 = 18 total user cells receive counter overflow lcd x 011001 = 19 total user cells rx clp=0 counter overflow lcd x 011010 = 1a total user cells tx counter overflow lcd x 011011 = 1b total user cells tx clp=0 counter overflow lcd x 011110 = 1e threshold 1 crossed lcd & dir x 011111 = 1f threshold 2 crossed lcd & dir x 100000 = 20 transmit complete packet x 100001 = 21 transmit complete buffer freed packet/lcd x 100010 = 22 "bad" found in first word of packet packet x 100011 = 23 connection closed lcd x 100100 = 24 transmit dma complete descriptor x IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 302 of 553 atmrm.chapt05.01 08/27/99 100101 = 25 receive dma complete descriptor x 100110 = 26 transmit dma complete with error descriptor x 100111 = 27 receive dma complete with error descriptor x 101000 = 28 transmit dma complete with virtual error descriptor x 101001 = 29 zero address in dma descriptor src/dst address descriptor x x 101100 = 2c adtf event lcd x 101101 = 2d crm event lcd x 101110 = 2e ccr=0 event lcd x 101111 = 2f rm cell event packet x 110000 = 30 user event 110001 = 31 user event 110010 = 32 user event 110011 = 33 user event 110100 = 34 user event 110101 = 35 user event 110110 = 36 user event 110111 = 37 user event 111000 = 38 virtual memory resource event packet/lcd x 111001 = 39 buffer overflow event packet/lcd x 111010 = 3a no dma descriptor for aal7 packet packet/lcd x 111011 = 3b dma canceled for aal7 packet due to error descriptor x 111100 = 3c no scatter pages available and packet com- plete packet/lcd x 111101 = 3d entity counter overflow event counter x 111110 = 3e pools status event status x 111111 = 3f timestamp event timestamp event summary and routing info (page 2 of 2) event number description event information error count tx comp tx dma rx dma abr pool IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 303 of 553 aal5 packet events for aal5 packet events, the event specifies the packet buffer address, and the event type field specifies the type of packet event. the following event types are defined bit(s) name description 0x00=000000 normal aal 5 packet event (packet com- plete) this event specifies that an aal5 packet was received and has passed all aal5 protocol checks (crc, length). the event information contains a pointer to the packet. 0x0e=001110 normal aal5 fifo packet event this event specifies that an aal5 fifo packet was received and has passed all aal5 protocol checks (crc, length, ...). the event informa- tion contains a pointer to the packet. 0x01=000001 normal aal5 packet header threshold event (packet start) this event specifes that the aal5 packet header threshold was exceeded as set in the lcd. the event information contains a pointer to the packet header, and the user can access up to the packet header threshold bytes of data. 0x02=000010 aal5 packet with bad crc was rx on lc this event specifies that a aal5 packet was received and the aal5 crc is bad. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x0f=001111 aal5 packet with bad crc and good length was rx on lc this event specifies that a aal5 packet was received and the aal5 crc is bad, but the aal5 length was good. this event is useful for mpeg-2 operation. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x03=000011 aal5 packet with bad length field was rx on lc this event specifies that a aal5 packet was received and the aal5 length field is bad. for example, there is too much data or not enough, but typically the bad crc is detected first. the event information con- tains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x04=000100 aal5 packet that exceeds max len in lc was rx this event specifies that a aal5 packet was received but the amount of data has exceeded the maximum length as specified in the lcd or in the msdu register. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x05=000101 aal5 packet timeout on this lc this event specifies that a reassembly timeout has occurred for a aal5 packet that was being reassembled. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x06=000110 aal5 packet forward abort this event specifies that a aal5 packet was terminated with a forward abort. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x07=000111 aal5 packet cpi field not equal to zero this event specifies that a aal5 packet was received and the aal5 cpi field was not set to zero which is an aal5 protocol violation. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 304 of 553 atmrm.chapt05.01 08/27/99 cell events for aal0 events, the event specifies a cell buffer address, and the event type field specifes type of aal0 event. the following event types are defined: bit(s) name description 0x08=001000 aal0 cell event this event specifies that a aal0 (non-fifo mode) cell was received. the event information contains a pointer to the cell. 0x09=001001 non-user data cell event this event specifies that a non-user data cell was received and the crc-10 was good if checking was enabled. the event information con- tains a pointer to the cell. 0x0a=001010 non-user data cell with bad crc-10 event this event specifies that a non-user data cell was received and the crc-10 was bad. the event information contains either a pointer to the cell if receiving bad frames, or a pointer to the lcd on which this cell was received. 0x0b=001011 cell with bad hec event this event specifies that a cell was received with a bad hec. the event information contains a pointer to the cell. 0x0c=001100 cell with vp/vc out of range event this event specifies that a cell was received with a vp/vc that was out of range. the event information contains a pointer to the cell. 0x0d=001101 cell with vc index equal zero this event specifies that a cell was received with a vc index equal zero. the event information contains a pointer to the cell. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 305 of 553 lc events for lc events, the event specifies a lc, and the event type field specifes what happened on the lc. the following event types are defined: abr events the following events are used for abr processing, and are routed to the receive queue specified in the abr event routing register. bit(s) name description 0x10=010000 aal0 cell was dropped due to lack of pools buffers this event specifies that a aal0 (non-fifo mode) cell was received, but was discarded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x11=010001 aal5 cell was dropped due to lack of pools buffers this event specifies that the first aal5 cell for a packet was received, but was discarded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x12=010010 non-user data cell was dropped due to lack of pools buffers this event specifies that a non-user data cell was received, but was dis- carded because no pool buffers were available. the event information contains a pointer to the lcd on which this cell was received. 0x13=010011 fifo cell was dropped because fifo full this event specifies that a aal0 (fifo mode) cell was received, but was discarded because the fifo was full. the event information con- tains a pointer to the lcd on which this cell was received. 0x14=010100 fifo threshold occurred this event specifies that the fifo threshold has been crossed. the event information contains a pointer to the lcd on which this threshold occured. 0x15=010101 fifo is full this event specifies that a fifo has become full. the event information contains a pointer to the lcd on which this timeout occured. 0x16=010110 fifo has timed out this event specifies that a reassembly timeout has occurred for a fifo. the event information contains a pointer to the lcd on which this time- out occured. 0x17=010111 reserved reserved 0x18=011000 lc total user cells rx counter overflow this event specifies that the tuc rx counter in the lcd has over- flowed. the event information contains a pointer to the lcd. 0x19=011001 lc total user cells clp=0 rx counter overflow this event specifies that the tuc w/clp=0 rx counter in the lcd has overflowed. the event information contains a pointer to the lcd. 0x1a=011010 lc total user cells tx counter overflow this event specifies that the tuc tx counter in the lcd has over- flowed. the event information contains a pointer to the lcd. 0x1b=011011 lc total user cells clp=0 tx counter overflow this event specifies that the tuc w/clp=0 tx counter in the lcd has overflowed. the event information contains a pointer to the lcd. bit(s) name description 0x2c=101100 adtf event this event occurs when the tadtf timer (as set in the lcd) has expired. the event information contains a pointer to the lcd. 0x2d=101101 crm event this event occurs when crm or more rm cells are sent without receiv- ing a backward rm cell. the event information contains a pointer to the lcd. 0x2e=101110 ccr = 0 event this event specifies that the current cell rate has been set to 0. the event information contains a pointer to the lcd. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 306 of 553 atmrm.chapt05.01 08/27/99 miscellaneous 0x2f=101111 rm cell rx-ed this event specifies that a rm cell was received. the event information contains a pointer to the receive buffer. bit(s) name description 0x1e=011110 thresh 1 event this event specifies that a memory management threshold was crossed. the event information contains the lcd address, and bit six contains the direction (1 if up, 0 if down). 0x1f=011111 thresh 2 event this event specifies that a memory management threshold was crossed. the event information contains the lcd address, and bit six contains the direction (1 if up, 0 if down). 0x20=100000 transmit complete this event specifies that a packet/cell was successfully transmitted. the event information contains a pointer to the buffer transmitted. 0x21=100001 transmit complete buffer freed this event specifies that a packet/cell was successfully transmitted and the buffer was freed back to pools. the event information contains a pointer to the buffer transmitted. 0x22=100010 transmit bad this event specifies that a packet was to be transmitted, but the buffer was marked as bad, so was canceled. this is casued by getting a page fault when dmaing into the transmit packet buffer. the event informa- tion contains a pointer to the bad buffer. 0x23=100011 connection closed this event specifies that all packets for the given lcd have been trans- mitted. the event information contains the lcd address. 0x24=100100 tx dma complete (into IBM2520L8767) this event specifies that a tx dma completed successfully. the event information depends on how the dma was set up. 0x25=100101 rx dma complete (out of IBM2520L8767) this event specifies that a rx dma completed successfully. the event information depends on how the dma was set up. 0x26=100110 tx dma complete with error (into IBM2520L8767) this event specifies that a tx dma had errors. the event information depends on how the dma was set up. 0x27=100111 rx dma complete with error (out of IBM2520L8767) this event specifies that a rx dma had errors. the event information depends on how the dma was set up. 0x28=101000 tx dma complete with virtual error this event specifies that a tx dma had a virtual error. the reminder of the dma descriptor was cancelled. the event information contains the dma descriptor address. 0x29=101001 dma desc has zero address this event specifies that a dma descriptor source destination address was zero. the remainder of the dma descriptor was cancelled. the event information contains the dma descriptor address. 0x30=110000 user defined 0x31=110001 user defined 0x32=110010 user defined 0x33=110011 user defined 0x34=110100 user defined 0x35=110101 user defined 0x36=110110 user defined 0x37=110111 user defined bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 307 of 553 the receive queues are maintained by rxque with the following operations being avail to software: dequeue remove the entry at the head of the queue enqueue add arbitrary entry at the tail of the queue the following figure shows how events, in a receive queue, link to other data structures including lc control blocks, packet buffers, and cell buffers. 0x38=111000 virtual memory resource event this event specifies that an aal5 cell was received, but could not be written into the buffer because a virtual memory boundary was crossed and a buffer was not available to fill in the next segment. this can also happen if the cell crosses a boundary that would make the buffer larger than the virtual buffer size. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd that on which this packet was received. 0x39=111001 buffer overflow event this event specifies that an aal5 cell was received, but could not be written into the buffer because it would exceed the real buffer size. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x3a=111010 no dma desc for aal7 packet event this event specifies that an aal7 (aal5 with cut-through) packet was completed, but no dma descriptors were available to dma the packet header. the event information contains either a pointer to the packet if receiving bad frames, or a pointer to the lcd on which this packet was received. 0x3b=111011 dma cancelled for aal7 packet due to error event this event specifies that a dma desc enqueued with a cut-through operation was cancelled because an error condition was detected with the packet (crc, length, ...). the event information contains the system descriptor address that was cancelled. 0x3c=111100 no pages available for aal5 scatter packet this event specifies that a aal5 packet completed with no errors, but there was a lack of scatter buffers to complete the scatter dma. the user must interrogate the partial dma list in the packet header to recover the system pages. once this is done, the packet should be freed. the user can alternately treat this as a good packet and complete the packet processing by setting up additional dmas to move the remaining data to system pages. the event information contains the IBM2520L8767 buffer address. 0x3d=111101 IBM2520L8767 counter overflow event this event specifies that a counter overflow event has been raised. the event info specifies which counter overflowed. multiple counter over- flows can be specified with a single event. the following is the definition of the event information: bit 31 segbf total user cells tx overflow bit 30 segbf total user cells with clp=0 tx overflow bit 29 reasm total user cells rx overflow bit 28 reasm total user cells with clp=0 rx overflow bit27gpdmawritedmabytecountoverflow bit 26 gpdma read dma byte count overflow bit 25 rxque timestamp counter overflow bit 24 pcint performance counter 1 overflow bit 23 pcint performance counter 2 overflow 0x3e=111110 pools status event this event specifies that a pools status event has been raised. the event info contains the status. see pools for the definition. 0x3f=111111 timestamp event this event specifies that a timestamp event has been placed ahead of next event. the event info contains the timestamp. bit(s) name description IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 308 of 553 atmrm.chapt05.01 08/27/99 general queue, event, and data structure linkage head status lc cb lc info raw cell data packet lc raw packet event event event event event event header data tai l header event raw lc IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 309 of 553 rxque structure each queue is implemented as a wrap around buffer with the head chasing the tail. each queue entry is a 32-bit event. each queue has a number of registers that define the queue and its behavior: the following figure shows the structure of the queue in memory. the entire queue is stored in either the control or packet portion of the IBM2520L8767 memory. the head/tail of each queue is cached to allow fast dequeue operations by software. lower bound pointer to beginning of wrap around buffer upper bound encoded maximum length of wrap around buffer head pointer pointer to head of queue tail pointer pointer to the next free entry in queue. points to head if queue is full or empty. queue length current length of the queue maximum queue length encoded maximum length of the queue (can be different from upper bound) threshold length threshold used to generate interrupts high water threshold length threshold used to generate interrupts general rxque queue structure lower bound head event event event event tai l lower bound IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 310 of 553 atmrm.chapt05.01 08/27/99 rxque initialization the receive queues power on enabled and ready to run. if different addresses or options are to be used, the receive queues need to be initialized. to set up a receive queue, at least two pieces of information are needed. first, the base address of the receive queue. second, the length of the receive queue is needed. the following general pseudo code illus- trates how to set up a receive queue for operation: the example above applies to any of the receive queues. the routine could also take the receive queue number, if the includes for the registers are properly defined. the following restrictions should be taken into account when setting up a queue: the lower bound and upper bound must be at least 512-byte aligned. the low order bits of these registers are not writable. so the minimum physical size of a receive queue is 128 entries (512 bytes). the align- ment should correspond to the size specified in the upper bound register (i.e. 4-kb aligned if upper bound is 4kb). the head and tail pointers are initialized when the lower bound register is written. these registers are only writable for diagnostic purposes. the threshold is level-sensitive. as long as the queue length is greater than or equal to the threshold, the appropriate status bit is driven. all registers, except the threshold registers, can only be written in diagnostic mode and are intended to be written only once when they are set up. rxque initialization code void initrxq(bit32* baseaddr, bit8 physize, bit16 thresh) { // rxque should be in diagmode for this routine to succeed rxque->lowerbound = baseaddr; rxque->upperbound = physize; // physize is encoded rxque->threshhold = thresh; } IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 311 of 553 rxque event routing events are routed to a receive queue based the current event type and mode of the chip. events fall into these categories: normal events errorevents counter events transmit complete events dma events (transmit/receive) abr events pools status events refer to the table at the beginning of this chapter to see how the different events are categorized. all events other than normal and error events are routed using the corresponding rxque event routing registers. normal events are always routed to the receive queue specified in the receive portion of the lcd. error events are special; they are routed based on the values of the "receive bad frame" mode bit and the "always route error events" mode bit in rxque control register. if the always route error events bit is on, then the error events are always routed to the error queue. otherwise, if the receive bad frame mode is on, the error events are routed to the receive queue specified in the receive portion of the lcd just as a normal event. when receive bad frames is off, the error events are routed to the error queue. rxque normal operation this section is meant to help describe how to use the receive queues (rxq) and the receive queue operations. the receive queue contains events for the end user to process. these events are obtained by the user by executing the reasm dequeue operation. the user can be notified of new events by setting up the threshold and interrupt enable registers appropriately. otherwise, the receive queues length register can be polled to check for events. the dequeue operation is executed by reading the dequeue register address for the appropriate receive queue. the event at the head of the queue is returned and the event is removed from the queue. some events have a packet/cell buffer associated with it. this buffer is owned by the user and it is the users respon- sibility to free this buffer. the following pseudo code illustrates how a receive queue could be processed: IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 312 of 553 atmrm.chapt05.01 08/27/99 rxque queue full operation when a receive queue is full (length is equal to maximum length), the appropriate status bit is set. when a queue is full, all subsequent events are flushed until room is available in the receive queue. if a buffer was associated with the event, it is freed back to pools. when an event is dropped, the event dropped status bit is set and the event data that was dropped can be found in rxque last event dropped register. rxque last event dropped register will not change until the event dropped status bit is cleared. it is obviously not good to let a receive queue become full! rxque event timestamping when timestamp mode is set in the rxque control register, events are timestamped. when timestamping is enabled, a timestamp event is placed in the corresponding receive queue followed by the actual event. the event info of the timestamp event carries the timestamp. the timestamp is determined from the rxque timestamp register, rxque timestamp pre-scaler register, and the rxque timestamp shift register. if the corresponding receive queue is full, both events are dropped. it is possible to lose only the timestamp event or lose the actual event, depending on the length of the queue and the timing of the dequeue opera- tions. rxque dequeue event loop // rxq was polled or int ocurred to get here event = rxque->deq; // read an event from rxq if (event neq 0) { // need to check for null event eventtype = event & 0x3f; // calc event type event = event & 0xffffffc0; // calc lc or buffer ptr switch (eventtype) { case(event1): processsimpleevent1(event); break; case(event2): processsimpleevent2(event); break; case(eventx): processsimpleeventx(event); break; } } IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 313 of 553 14.1: rxque lower bound registers these registers specify the lower bound of the corresponding receive queue data structure. these registers specify the lower bound of the corresponding receive queue data structure. the head and tail of the receive queue are initialized when this register is written. when the receive queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the receive queue as a circular buffer. when this register is written, the corresponding receive queue is essentially reset. this is because the head, tail, and length of the queue are all reset. length 32 bits type read/write address queue 0 xxxx 1800 queue 1 xxxx 1840 queue 2 xxxx 1880 queue 3 xxxx 18c0 queue 4 xxxx 1900 queue 5 xxxx 1940 queue 6 xxxx 1980 queue 7 xxxx 19c0 power on value queue 0 x?0000e000? queue 1 x?0000e400? queue 2 x?0000e800? queue 3 x?0000ec00? queue 4 x?0000f000? queue 5 x?0000f400? queue 6 x?0000f800? queue 7 x?0000fc00? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. the lower bound registers must be at least 512-byte aligned (low order nine bits not writable). the alignment should also correspond to the size specified in the upper bound register. for example, it should be 4-kb aligned if the upper bound specifies 4-kb size. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 314 of 553 atmrm.chapt05.01 08/27/99 14.2: rxque upper bound registers these registers specify the encoded upper bound of the corresponding receive queue data structure. the actual upper bound is calculated by adding the decoded queue size to the lower bound. when the receive queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the receive queue as a circular buffer. length 3bits type read/write address queue 0 xxxx 1804 queue 1 xxxx 1844 queue 2 xxxx 1884 queue 3 xxxx 18c4 queue 4 xxxx 1904 queue 5 xxxx 1944 queue 6 xxxx 1984 queue 7 xxxx 19c4 power on value x?00000001? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. reserved encoded upper bound 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-3 reserved. 2-0 000 128 entries -> 512 bytes of memory 001 256 entries -> 1kb of memory 010 512 entries -> 2kb of memory 011 1k entries -> 4kb of memory 100 2k entries -> 8kb of memory 101 4k entries -> 16kb of memory 110 8k entries -> 32kb of memory 111 16k entries -> 64kb of memory IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 315 of 553 14.3: rxque head pointer registers these registers point to the head element of the corresponding receive queue. the head pointer registers are four-byte aligned. (low order two bits not writable) bits 31-16 are calculated internally, and are not writable. during normal operations, these registers do not need to be read or written, as they are used by the IBM2520L8767 to implement the receive queues. these registers are initialized when the lower bound regis- ter for the corresponding receive queue is written. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 316 of 553 atmrm.chapt05.01 08/27/99 14.4: e rxque tail pointer registers these registers point to the next free element of the corresponding receive queue. during normal operations, these registers do not need to be read or written, as they are used by the IBM2520L8767 to implement the receive queues. these registers are initialized when the lower bound register for the corresponding receive queue is written. length 32 bits type read/write address queue 0 xxxx 180c queue 1 xxxx 184c queue 2 xxxx 188c queue 3 xxxx 18cc queue 4 xxxx 190c queue 5 xxxx 194c queue 6 xxxx 198c queue 7 xxxx 19cc power on value queue 0 x?0000e000? queue 1 x?0000e400? queue 2 x?0000e800? queue 3 x?0000ec00? queue 4 x?0000f000? queue 5 x?0000f400? queue 6 x?0000f800? queue 7 x?0000fc00? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. bits 31-16 are calculated internally, and are not writable. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 317 of 553 14.5: rxque length registers these registers specify the length (number of valid entries) of the corresponding receive queue and are cleared when the corresponding lower bound is written. these registers can be used to query the status of a receive queue. length 15 bits type read address queue 0 xxxx 1810 queue 1 xxxx 1850 queue 2 xxxx 1890 queue 3 xxxx 18d0 queue 4 xxxx 1910 queue 5 xxxx 1950 queue 6 xxxx 1990 queue 7 xxxx 19d0 power on value x?0000? restrictions these registers can only be written in diagnostic mode. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 318 of 553 atmrm.chapt05.01 08/27/99 14.6: rxque threshold registers these registers specify a queue length threshold at which the corresponding status bit is generated. these registers should be set equal to the number of queue entries that should cause status to be generated. for example, if the value was set to five, then no interrupt would be generated until five or more events were queued on the corresponding receive queue. the threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. when this register is set to zero, no thresholding is done. when the direction bit is set for a receive queue, the threshold has the opposite polarity. for example, as long as there are more events in the queue than specified in the threshold register no status would be raised. length 32 bits type read address queue 0 xxxx 1818 queue 1 xxxx 1858 queue 2 xxxx 1898 queue 3 xxxx 18d8 queue 4 xxxx 1918 queue 5 xxxx 1958 queue 6 xxxx 1998 queue 7 xxxx 19d8 power on value x?0000? restrictions during normal operations, these registers are read only. these registers can only be written when the diagnostic bit has been set in the control register. bits 31-16 are calculated internally, and are not writable. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 319 of 553 14.7: rxque dequeue registers these registers are used to retrieve the event at the head of the corresponding receive queue. 14.8: rxque enqueue registers these registers are used to enqueue user events at the tail of the corresponding receive queue. length 32 bits type read address queue 0 xxxx 181c queue 1 xxxx 185c queue 2 xxxx 189c queue 3 xxxx 18dc queue 4 xxxx 191c queue 5 xxxx 195c queue 6 xxxx 199c queue 7 xxxx 19dc power on value x?00000000? restrictions this is a read only register, and all writes will be ignored. events are only returned when the diagnostic bit is reset in the control register, otherwise zero will be returned. length 32 bits type read/write queue 0 xxxx 1820 queue 1 xxxx 1860 queue 2 xxxx 18a0 queue 3 xxxx 18e0 queue 4 xxxx 1920 queue 5 xxxx 1960 power on value x?00000000? restrictions all reads result in zero. rxque should be enabled to do this. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 320 of 553 atmrm.chapt05.01 08/27/99 14.9: rxque last event dropped register contains the event that was last dropped. this register contains the last event that was dropped. it holds its value until the event dropped status bit is cleared. 14.10: rxque timestamp register used to specify the current timestamp measured using the timestamp pre-scaler ticks. this register keeps the current timestamp. it counts based on the value in the rxque time-stamp pre-scaler register. it can be read or written at any time. it is cleared when the pre-scaler register is written. 14.11: rxque timestamp pre-scaler register used to specify the time interval of each timestamp timer tick. this register determines the number of 30-ns intervals between timestamp timer ticks. the value in the register plus one is the number of 30-ns intervals between timestamp timer ticks. so, the default value of zero means that the timestamp timer ticks every 30ns. if a value of four is placed in this register, the timestamp timer ticks every 150ns (5 ? 30 ns). length 32 bits type read/write address xxxx 1ac0 power on value x?00000000? restrictions none length 32 bits type read/write address xxxx 1ac0 power on value x?00000000? restrictions none length 16 bits type read/write address xxxx 1a10 power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 321 of 553 14.12: rxque timestamp shift register used to specify the number of bits to shift the timestamps. this register determines the number of bits that the timestamps are shifted. for example, if a value of zero is placed in this register, then the timestamp is not shifted, and the low order six bits are lost. if a value of two is placed in this register, then the timestamps are shifted two places and only the low order four bits of the timestamp are lost. this allows the user to control what portion of the timestamp is lost due to the low order event bits. 14.13: rxque event routing registers used to specify to which receive queue different types of events should be routed. these registers contain the receive queue that different types of events should be routed to. see event summary and routing info on page 301 for event type mappings. length 3bits type read/write address xxxx 1a14 power on value x?00000002? restrictions none length 3bits type read/write address tx complete xxxx 1a3c counter overflow xxxx 1a40 error xxxx 1a44 tx dma comp xxxx 1a48 rx dma comp xxxx 1a6c pools status xxxx 1a88 abr xxxx 1a8c power on value x?00000000? restrictions for code compatibility, the rx dma comp routing register is written when the tx dma comp routing register is written. if both registers need to be written, tx dma comp routing register should be written first and then the rx dma comp routing register. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 322 of 553 atmrm.chapt05.01 08/27/99 14.14: rxque event latency timer register used to specify the event latency time interval. this register is specified in 30-ns intervals. when a new event is placed on a receive queue, the event latency timer is started (if not already started). when this timer expires, the event latency timer expired status bit is set, and the timer is stopped. the status bit must be reset before the timer is started again. every time the status register (or prioritized status) is accessed, the timer is stopped. if this register is written while the timer is running, the new value takes effect immediately. if this register is set to zero, the latency timer does not run. 14.15: rxque interrupt enable registers used to specify which status register bits should be used to generate interrupts. used to specify which status register bits should be used to generate interrupts. each mask register is used to drive a different rxque status bit in intst as specified below. the different masks and status bits allow a high and low priority rxque interrupt on both the interrupt a and b pins. see note on set/clear/read type registers on page 71 for more details on addressing. see rxque status and enabled status registers on page 323 for the bit descriptions. length 32 bits type read/write address xxxx 1a18 power on value x?00000000? restrictions none length 27 bits type clear/set address enable 1 xxxx 1a20 and a24 enable 3 xxxx 1a90 and a94 enable 5 xxxx 1aa0 and aa4 enable 7 xxxx 1aa0 and aa4 power on value enable 1 x?07ffff00? enable 3 x?07ffff00? enable 5 x?00000000? enable 7 x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 323 of 553 14.16: rxque status and enabled status registers this register contains the status bits. the enabled version of these regs provide a version of the status regis- ter that is masked with the corresponding interrupt enable register. see note on set/clear/read type regis- ters on page 71 for more details on addressing. the following are the bit descriptions:used to relay rxque status information. length masked with none 27 bits masked with enable 1, 3, 5, or 7 32 bits type masked with none clear/set masked with enable 1, 3, 5, or 7 read only address masked with none xxxx 1a28 and a2c address masked with enable 1 xxxx 1ab0 masked with enable 3 xxxx 1ab4 masked with enable 5 xxxx 1ab8 masked with enable 7 xxxx 1abc power on value x?00000000? restrictions only the event latenenable 1cy timer expired bit is writable. the enabled status registers are read only. general purpose timer status int 1 status or pcore normal int status int 2 status or pcore critical int status reserved event latency timer expired event dropped head valid threshold exceeded queue full/empty 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 general purpose timer status this is a mirror of the general purpose timer status bit in interrupt status. 30 int 1 status or pcore normal int status when read from the pci bus, this bit indicates if there is status other than receive queue status and general purpose timer status in the interrupt source register using interrupt mask register 1 as a mask. when read from the pcore polling interface, the mask used is the interrupt status 1. 29 int 2 status or pcore critical int status when read from the pci bus, this bit indicates if there is status other than receive queue status and general purpose timer status in the interrupt source register using interrupt mask register 2 as a mask. when read from the pcore polling interface, the mask used is the pcore normal interrupt status in the interrupt status register. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 324 of 553 atmrm.chapt05.01 08/27/99 28 reserved reserved 27 reserved reserved 26 reserved reserved 25 event latency timer expired when this bit is set, the event latency timer has expired. this indicates that new events are waiting to be processed on some queue(s) and the queue has not been processed for a period equal to the latency timer. this bit must be reset to re-enable the event latency timer. 24 event dropped when this bit is set, at least one event has been dropped. rxque last event dropped register contains the event that was dropped. 23-16 head valid these bits are set when the head is valid for queue 7-0 respectively. if these bits are set, then a dequeue operation should complete successfully. 15-8 threshold exceeded these bits are set when the queue length register equals or exceeds the value in the queue threshold register for queue 7-0 respectively. 7-0 queue full/empty bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 325 of 553 14.17: rxque control register see note on set/clear/read type registers on page 71 for more details on addressing. this register contains the mode bits that specify how rxque is to operate. it is used to set rxque modes. length 32 bits type clear/set address xxxx 1a30 and a34 power on value x?00000000? restrictions none reset fifo reserved queue direction always route error events enable chip overflow events memory select inhibit enqueues timestamp mode receive bad frames bcach advice diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 reset fifo when this bit is set, the internal fifo is flushed, and this bit is reset. the result is this bit will always be read as a zero. this bit can only be set in diagnostic mode. 30-16 reserved reserved. 15-8 queue direction when set, the direction of the corresponding queue is assumed to be reversed. this only affects the full condition, the threshold exceeded condition, and the high water threshold exceeded condition. when this bit is set, the polarity of these status signals changes. so, the full condition becomes an empty condition, and the two threshold conditions trigger when the length of the queue is less than the corresponding thresh- old instead of greater than or equal. this mode is mainly used for queues that relay information from the system to the IBM2520L8767. also, event enqueues to a queue that is reversed do not start the event latency timer (since no new event for system has arrived). 7 always route error events when this bit is set, all error events are routed to the error queue even if receive bad frames (bit 2) is turned on. when cleared, error events are only routed to the error queue if receive bad frames is turned off. this bit allows the user to keep bad frames in time sequence with good frames or to route them to the error queue. the clear state of this bit is code compatible with previous passes. 6 enable chip overflow events when set, the chip level counter overflow events are surfaced. 5 memory select when this bit is set, rxque will use packet memory instead of control memory to store the event queues. 4 inhibit enqueues when this bit is set, the enqueue state machine will not accept any new enqueue requests. this should be used in extreme cases as it holds off all enqueues indefi- nitely. 3timestampmode when this bit is set, timestamp events are inserted before each real event. the times- tamps correspond to when the event happened on chip. when this bit is off, times- tamps can still be read from the timestamp register. the timestamps would correspond to when the event was dequeued in this scenario. IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 326 of 553 atmrm.chapt05.01 08/27/99 14.18: rxque control 2 register this register contains the mode bits that specify how rxque is to operate. it is used to set rxque queue modes. see note on set/clear/read type registers on page 71 for more details on addressing. the follow- ing are the bit descriptions: 2 receive bad frames when this bit is set, bad frame events (all error events), will be received in the normal receive queue defined in the lcd. all buffers are not freed, and the packet address is raised in the event data. when this bit is reset, bad frame events are routed to the receive queue specified by the error event receive queue register. all packet based events will carry the lc address in the event data instead of the packet address. all buffers are freed back to pools. this bit should only be changed sparingly, because it changes the way packets are freed and what is surfaced in an event (lcd vs frame pointer). it should really only be changed when the receive side is inactive. 1 bcach advice this bit when set allows rxque to give bcach cache fill advice based on events that are dequeued. 0 diagnostic mode when this bit is set or when the chip is disabled, the rxque entity is in diagnostic mode and primitive execution is disabled. length 16 bits type clear/set address xxxx 1a80 and a84 power on value x?00000000? restrictions none disable bcach advice for queue 7-0 disable timestamps for queue 7-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 15-8 disable bcach advice for queue 7-0 when set, the bcach advice is disabled for queue 7-0. this is necessary in order to use a queue as a general purpose container for user data. 7-0 disable timestamps for queue 7-0 when set, timestamps are disabled for queue 7-0. this is necessary in order to run cut-through modes. bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 receive queues (rxque) page 327 of 553 debugging register access this section is a very brief documentation of access that has been put in for the internal registers of rxque. these addresses need not be written or read during normal operations. 14.19: rxque rxq state machine variable register main state variable for rxq processing state machine. 14.20: rxque rxq enq state machine variable register main state variable for rxq processing state machine. length 4bits type read/write address xxxx 1a38 power on value x?00000000? restrictions none length 3bits type read/write address xxxx 1a4c power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources receive queues (rxque) page 328 of 553 atmrm.chapt05.01 08/27/99 14.21: rxque enq fifo head ptr register points to the head fifo entry in the fifo array. the msb bit, is used to determine if the head is chasing the tail, and is inverted each time the head pointer wraps. it is used to maintain the enqueue fifo. 14.22: rxque enq fifo tail ptr register points to the next free fifo entry in the fifo array. it is used to maintain the enqueue fifo. the msb bit, is used to determine if the head is chasing the tail, and is inverted each time the tail pointer wraps. . 14.23: rxque enq fifo array holds events waiting to be placed on a receive queue. array is organized as a 16x36 array. to access the upper four bits of each word (holds the receive queue number for event), the array word number should be used as the address. to access the low order 32 bits (the event portion), the array word number times two plus four should be used. for example, address zero accesses the receive queue portion of array word zero and address four accesses the event portion of the array word zero. note: the most significant bit is not used. only the three bits are needed for the receive queue number. length 5bits type read/write address xxxx 1b78 power on value x?00000000? restrictions can only be written in diag mode. length 5bits type read/write address xxxx 1b7c power on value x?00000000? restrictions can only be written in diagnostic mode. length 16 words x 36 bits type read/write address xxxx 1b80-bfc power on value x?00000000? restrictions can only be read/written in diagnostic mode. when read in non-diagnostic mode, zero is returned. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 329 of 553 phy level interfaces entity 15: the phy interface (linkc) functional description linkc provides the interface between the IBM2520L8767 and either an atm phy device or, when the inter- nal framer is selected, a serializer/deserializer device. linkc is composed of three pieces. linkx, which contains all the registers described below, is clocked with the same clock as other parts of the chip. linkt, the transmit logic, is clocked on the transmit clock, which is selected via the clock control register (described on page 388). linkr, the receive logic, is clocked on the receive clock, which is also selectable via the clock control register. transmit and receive transfers are synchronized via their respective interface transfer clock. the data path size is 8 or 16 bits wide and is selectable through bit three of the control register. the phy devices that the IBM2520L8767 interfaces to are: pmc sierra pm5346 suni lite for sonet sts-3c 155.52 mb/s utopia 8 or 16 bit interface. ibm25mb/soverutp. IBM2520L8767 ibm processor for atm resources the phy interface (linkc) page 330 of 553 atmrm.chapt05.01 08/27/99 15.1: linkc control register this register contains the information which controls the operation of linkc. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 0b30 and 34 power on value x?00006d? restrictions none additional header bytes for router function disable limited hec checking on received idle/unassigned cells disable hec generation on transmitted idle cells transmit phy sampling latch override enable transmit phy sampling latch override ignore gfc in null/idle cell determination enable xon/xoff transmit phy device enable transmit phy interface override receive phy device enable receive phy interface override enable output latches use sampling latches on phy inputs disable phy bus drivers reserved enable parity checking unassigned/idle cell reception modify byte alignment in 16-bit phy mode phy device support null cell generation phy data path size loop back mode 52 byte cell even/odd parity selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-30 additional header bytes for router function the value of bits 31-30 indicate the number of additional header bytes that will be read from segbuf and added to the beginning of each cell as each is transmitted to the phy. the bytes are meant to be used for additional routing information. these control bits have no effect in ibm 25 mb/s phy mode, and should be set to zeros when in internal sonet/sdh framer mode. if used in conjunction with 52-byte mode, the byte normally containing the cell hec will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. if 16-bit phy mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. as a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (lsb is normally padded with zeros so msb gets truncated). bit three of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 331 of 553 29 disable limited hec checking on received idle/unassigned cells if bit 29 is set to ?1?, the receive logic will ignore the hec byte of the header of idle and unassigned cells. idle is defined as a header of x?00000001? and unassigned is defined as a header of x?0000000n? where n is ?xxx0?. if bit nine is set to enable unas- signed/idle cell reception, all cells will be passed to reasm regardless of how this bit is set. if bit nine is set to disable unassigned/idle cell reception and this bit is set to ?0?, the hec byte of cells with an apparent idle header will be completely checked before deciding whether or not to pass the cell to reasm. if a cell appears to have an unas- signed header, hec bits 7,6, and 0 will be checked because they are a constant regardless of the value of bits 3-1 of the header. if other hec bits are bad, reasm will detect the hec error and discard the cell. if there is a correctable hec error and the cell is indeed unassigned, an out of range error will occur in reasm. 28 disable hec generation on transmittedidlecells ifbit28issetto?1?,x?00?willbeplacedinthehecbyteofidlecells(assumingbitfour is set to enable idle cell generation). this bit set to ?0? allows hec to be generated on idle cells. 27 transmit phy sampling latch override if bit 26 is set, this bit determines whether the transmit phy interface uses sampling latches on its inputs or not. set to ?1?, this bit enables the use of sampling latches. 26 enable transmit phy sampling latch override when set, bit 26 will allow bit 27 to determine whether the transmit phy interface uses sampling latches on its inputs or not regardless of the setting of bit 14. 25 ignore gfc in null/idle cell determination when set, bit 25 causes the receive logic to ignore the first four bits of the atm header in determining whether a cell being received is a null or idle cell. 24 enable xon/xoff when set, bit 24 allows the xon/xoff bit of the header of a received cell to sus- pend/continue transmission from the IBM2520L8767?s transmit logic. 23-21 transmit phy device 23-21 override the settings in bits 7-5 when bit 20 is set to ?1?. these bits only effect the phy transmit interface. they select the transmit phy interface with the same encoding as bits 7-5. 20 enable transmit phy interface override this bit, when set to ?1? allows bits 23-21 to override the phy interface setting in bits 7-5. this only alters the transmit phy interface. 19-17 receive phy device 19-17 override the settings in bits 7-5 when bit 16 is set to ?1?. these bits only effect the phy receive interface. they select the receive phy interface with the same encoding as bits 7-5. 16 enable receive phy interface override whensetto?1?,thisbitallowsbits19-17tooverridethephyinterfacesettinginbits 7-5. this only alters the receive phy interface. 15 enable output latches when set to ?1?, this bit causes linkt and linkr to use sampling latches on phy out- puts in utopia mode. this should be set to ?0? in normal operation and is only pro- vided for a possible backward compatibility situation with the 1.5 release. 14 use sampling latches on phy inputs when set to ?1?, this bit causes linkt and linkr to use sampling latches on phy inputs. when set to ?0?, the inputs are used raw. this should be set to ?0? when using the internal sonet framer. 13 disable phy bus drivers when set to ?1?, this bit tri-states the drivers of the phy bus. when set to ?0?, the drivers are enabled. 12-11 reserved reserved. 10 enable parity checking when set, this bit enables checking of parity on data from the receive path. the default is parity checking is disabled. the upper bit of the transmit parity is not valid when the the internal sonet/sdh framer has been selected as the receive phy device. the upper bit of the receive parity is also not valid when the internal sonet/sdh framer has been selected as the transmit phy device. this is only a concern if a combination of the internal framer and an external phy is being used and that external phy has a 16-bit data interface. in this case, parity cannot be checked/generated on the upper byte. 9 unassigned/idle cell reception when set to ?1? , this bit enables unassigned/idle cell reception. this should be set to ?0? when using the internal sonet framer. bit(s) name description IBM2520L8767 ibm processor for atm resources the phy interface (linkc) page 332 of 553 atmrm.chapt05.01 08/27/99 8 modify byte alignment in 16-bit phy mode when set to ?1?, this bit changes the default byte alignment in 16-bit phy mode if this register also contains a non-zero value in bits 31-30. see the description of those bits for further details. 7-5 phy device 7, 6 and 5 indicate which phy the IBM2520L8767 will be interfacing. ?000? reserved ?001? reserved ?010? ibm 25 mb/s ?011? pmc pm5346 suni lite/utopia interface (sts-3c/stm-1 or sts-1) ?100? internal sonet(sts-3c)/sdh(stm-1) framer with external serdes (parallel interface) ?101? internal sonet(sts-3c)/sdh(stm-1) framer with internal serdes (serial interface). 4 support null cell generation when set, this bit enables the IBM2520L8767 to send unassigned cells to the assigned cell stream. this bit needs to be set when interfacing with a phy that doesn?t support null cell generation and has synchronous cell time slots(e.g.sonet, ds3). this should be set to ?0? when using the internal sonet framer. 3 phy data path size this bit, when set to ?0?, selects a 16-bit wide data path to the phy device. when set to ?1?, the data path width to the phy will be eight bits. this bit has no affect on the inter- nal sonet/sdh framer except if the internal framer has been selected as the rx phy device but not as the transmit phy device. in this case, ?1? on this bit will allow fyt- dat(15 - 13) to be used for the 16-bit external transmit phy device, while ?0? will allow fytdat(15-13)tobeusedforthereceivehdlccontroller.thisimpliesthatitisnot possible to use the internal receive framer, the receive hdlc interface, and an exter- nal 16-bit transmit framer at the same time. 2 loop back mode this bit set to ?1? places the IBM2520L8767 in an internal loop back mode. the phy interface will be disabled. the clocks to linkt and linkr should be set to the same source in clock control register (nibble aligned) (described on page 388). this bit is flushed to ?1? after por. 1 52bytecell when set, the cell sent to the phy will be 52 bytes. no hec byte will be sent or received. this bit does not affect the internal sonet framer. 0 even/odd parity selection even parity is selected when this bit is cleared. the default value is for odd parity. bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 333 of 553 15.2: linkc transmitted hec control byte the transmitted control byte (hkcs) is an error mask that allows the insertion of one or more errors into the hec byte (byte five of the atm cell header). a logic one in a given position causes the inversion of the corre- sponding hec bit position. length 8bits type read/write address xxxx 0b04 power on value x?00? initiate inversion 76543210 bit(s) description 7-0 when set to ?1?, any of these bits will cause the inversion of the corresponding bit in the generated hec byte. IBM2520L8767 ibm processor for atm resources the phy interface (linkc) page 334 of 553 atmrm.chapt05.01 08/27/99 15.3: linkc interrupt/status register this register reports the status of linkc. length 8bits type clear/set address xxxx 0b10 and 14 power on value x?00? reserved null cell received parity error - upper byte parity error - lower byte reserved no carrier detect 76543210 bit(s) description 7 reserved. 6 indicates that the IBM2520L8767 has received a null cell. 5 indicates a parity error on the upper byte of receive data from the phy. 4 indicates a parity error on the lower byte of receive data from the phy. 3-1 reserved. 0 no carrier detect from the phy. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 335 of 553 15.4: linkc interrupt enable register this register enables the linkc interrupt to intst. when a bit is set in this register and the corresponding bit is set in the interrupt status register, the linkc interrupt will be driven. see note on set/clear/read type registers on page 71 for more details on addressing. 15.5: linkc prioritized interrupts used to access the prioritized encoding of linkc interrupts. reading this location will give a decimal number that is the prioritized encoding of bits 7 - 0 in comet/pakit status register (seven being the most signifi- cant bit) assuming the corresponding enable bit is on. length 8bits type clear/set address xxxx 0b18 and 1c power on value x?00? restrictions none length 8bits type read address xxxx 0b2c power on value x?00? restrictions none IBM2520L8767 ibm processor for atm resources the phy interface (linkc) page 336 of 553 atmrm.chapt05.01 08/27/99 15.6: linkc transmit state machine register this register indicates the state of the transmit sequencer. 15.7: linkc receive state machine register this register indicates the state of the receive sequencer. length 3bits type read/write address xxxx 0b24 power on value x?0? restrictions none transmit state machine 210 bit(s) description 2-0 transmit state machine. length 2bits type read/write address xxxx 0b28 power on value x?0? restrictions none receive state machine 10 bit(s) description 1-0 receive state machine. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 337 of 553 15.8: linkc unassigned cell payload data this register contains the data within the payload of an unassigned cell. the lower address selects bits 63 - 32 and the higher address selects bits 31 - 0. 15.9: linkc unassigned cell payload data -- bit reversed this register contains the same data as the linkc unassigned cell payload data register except each byte is bit-reversed. 31 - 0. length 64 bits type write/read address xxxx 0b38 and 3c power on value x?aaaa55555555aaaa? restrictions none length 64 bits type read address xxxx 0b08 and 0c power on value x?5555 aaaaaaaa5 555? restrictions none IBM2520L8767 ibm processor for atm resources the phy interface (linkc) page 338 of 553 atmrm.chapt05.01 08/27/99 15.10: linkc passed tx data register the bits in this register are passed over the phy transmit data i/o pins 15-8 when using an eight-bit wide phy data bus. length 8bits type read/write address xxxx 0b40 power on value x?00? restrictions none passed to IBM2520L8767 fytdat(15) passed to IBM2520L8767 fytdat(14) passed to IBM2520L8767 fytdat(13) passed to IBM2520L8767 fytdat(12) passed to IBM2520L8767 fytdat(11) passed to IBM2520L8767 fytdat(10) passed to IBM2520L8767 fytdat(9) passed to IBM2520L8767 fytdat(8) 76543210 bit(s) description 7 passedtoIBM2520L8767fytdat(15) 6 passedtoIBM2520L8767fytdat(14) 5 passedtoIBM2520L8767fytdat(13) 4 passedtoIBM2520L8767fytdat(12) 3 passedtoIBM2520L8767fytdat(11) 2 passedtoIBM2520L8767fytdat(10) 1 passedtoIBM2520L8767fytdat(9) 0 passedtoIBM2520L8767fytdat(8). IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 the phy interface (linkc) page 339 of 553 15.11: linkc pdh interface register the bits in this register are used to make adjustments to the utopia interface for compatibility with the suni-pdh phy. length 8bits type read/write address xxxx 0b44 power on value x?00? restrictions none reserved drive renb inactive when not receiving gate rsoc with rca receive extra header byte 76543210 bit(s) name description 7-3 reserved. 2 drive renb inactive when not receiving when set to ?1?, this bit forces the receive logic to deactivate renb when in the idle state. 1 gatersocwithrca when set to ?1?, this bit forces the receive logic to see both rsoc and rca before considering rsoc valid. 0 receive extra header byte when set to ?1?, this bit allow an extra header byte to be accepted at the start of a cell by the receive logic. the extra byte is discarded. IBM2520L8767 ibm processor for atm resources nodal processor bus interface (npbus) page 340 of 553 atmrm.chapt05.01 08/27/99 entity 16: nodal processor bus interface (npbus) this entity controls the signals of the np bus. the phy registers are accessible to the processor by way of the address space of the IBM2520L8767. in addition, the operation of the front end is effected by the npbus status register. see note on set/clear/read type registers on page 71 for more details on addressing. 16.1: npbus control register this register is used to report phy level hardware errors and interrupts. length 28 bits type clear/set address xxxx 2000 and 004 power on value x?0002010? restrictions none status led 4 toggle status led 3 toggle status led 2 toggle status led 1 toggle status led 4 flashing status led 3 flashing status led 2 flashing status led 1 flashing status led 4 on status led 3 on status led 2 on status led 1 on +utp/-stp interface select disable driving the np address over the enstate(47 - 32) pins enable carrier detect led enable phy data bus parity detection invert interrupt inputs and phy reset access internal sonet framer register space phy bus interface type enable hardware error to disable phy reboot serial/parallel eprom remove internal sonet framer from reset state force a phy logic reset enable the front end pb0phy2 control external eprom type reserved 2726252423222120191817161514131211109876543210 bit(s) name description 27 status led 4 toggle when this bit is set, the state of bit 19 of this register will be toggled by repeatedly set- ting bit 19. 26 status led 3 toggle when this bit is set, the state of bit 18 of this register will be toggled by repeatedly set- ting bit 18. 25 status led 2 toggle when this bit is set, the state of bit 17 of this register will be toggled by repeatedly set- ting bit 17. 24 status led 1 toggle when this bit is set, the state of bit 16 of this register will be toggled by repeatedly set- ting bit 16. 23 status led 4 flashing when set to ?1?, this bit will flash status indicator led 4. bit 19 of the register will over- ride this bit. 22 status led 3 flashing when set to ?1?, this bit will flash status indicator led 3. bit 18 of the register will over- ride this bit. 21 status led 2 flashing when set to ?1?, this bit will flash status indicator led 2. bit 17 of the register will over- ride this bit. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 nodal processor bus interface (npbus) page 341 of 553 20 status led 1 flashing when set to ?1?, this bit will flash status indicator led 1. bit 16 of the register will over- ride this bit. 19 status led 4 on when set to ?1?, this bit will turn on status indicator led 4. 18 status led 3 on when set to ?1?, this bit will turn on status indicator led 3. 17 status led 2 on when set to ?1?, this bit will turn on status indicator led 2. 16 status led 1 on when set to ?1?, this bit will turn on status indicator led 1. 15 +utp/-stp interface select thisbitcontrolsachipoutputpintoswitchhighorlow,andcanbeusedtoselectdif- ferent phy interfaces, etc. where this bit is off, or a logical ?0?, the chip output is high, or a logical ?1?. 14 disable driving the np address over the enstate(47 - 32) pins for debug reasons, the driven of the address for eprom and phy fetches can be turned off with this bit. 13 enable carrier detect led when set to ?1?, this bit allow indicator led 1 to reflect the status of carrier detect. this isachipinput. 12 enable phy data bus parity detection when set to ?1?, if a parity error occurs on the phy data bus during a phy register access, bit one of the npbus status register will be set. 11 invert interrupt inputs and phy reset when set to ?0?, the phy interrupt chip inputs will set bits two or three of the npbus status register when active low. when set to ?1?, the interrupt inputs will be inverted such that a positive input on the phy interrupt lines will set bits two or three of the npbus status register, and the phy reset out line will be inverted so that a high level will be a reset. this would be used for an ibm trac or compatible chip. 10 access internal sonet framer register space when this bit is zero, the external phy register space can be accessed through phy 1 registers or phy 2 registers. when this bit is set to ?1?, the internal sonet framer registers can be accessed (see sonet framer core on page 397). the full offset range for this access is x?2100? to x?2fff?. 9 phy bus interface type when this bit is ?0?, phy access speed is 200ns (suni-like interface). when ?1?, access requires an acknowledge input response. this is to support a utopia-like micro-processor interface. 8 enable hardware error to disable phy allows bit four (master enable) of the intst control register register to reset bit four of this register. (disables front end logic). this function assumes that bit four of the intst control register register has already been enabled and that either a hardware or software event has turned the bit off. 7 reboot serial/parallel eprom this bit will restart the external serial or parallel eprom initialization code. the access time expected for the serial eprom is the number of crisco instructions x the instruc- tion length in bytes (typically seven bytes) + three overhead bytes to address the serial eprom plus one ending instruction. this will give the total number of bytes. there are nine clocks per byte. multiply the total number of clocks times the serial eprom clock period (either 10 sor20 s depending on the ffcfg bit settings and assuming a pci 33-mhz clock). example: 13 intrs x 7 + 3 + 1 = 95 bytes. 95 ? 9clocks ? 20 s= 17.1ms. 6 remove internal sonet framer from reset state this bit powers up to a zero and keeps the internal sonet framer in reset mode. set- ting this bit to a ?1? will enable normal operation. 5 force a phy logic reset before any software reset, turn this bit on and off for the phy specified amount of time. if the ibm atm-tc (25 mb/s endec) is used, this bit will power-up to an active reset (since the input to the endec is positive reset). this bit must then be turned off for normal operation. 4 enable the front end when this bit is ?0?, no data will be transmitted to or received from the phys or IBM2520L8767. see bit eight for more information on control of this bit. bit(s) name description IBM2520L8767 ibm processor for atm resources nodal processor bus interface (npbus) page 342 of 553 atmrm.chapt05.01 08/27/99 3-2 pb0phy2 control encoded control for the pb0phy2 output pin. the enabled of pibselo overrides these bits and is controlled by pcint cascade control register. x?0? enable pb0phy2 pin x?1? enable pbdatap pin and its detection of valid parity. x?2? enable mpmdsel pin x?3? reserved 1 external eprom type thisbitwillsetatresettimeastowhattypeofepromisdetected.whenset,aserial eprom has been detected. when ?0?, parallel eprom is assumed (or none at all). this will also indicate from what type of device a pci rom access will retrieve vpd data. 0 reserved reserved bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 nodal processor bus interface (npbus) page 343 of 553 16.2: npbus status register this register is used to report phy level hardware errors and interrupts. see note on set/clear/read type registers on page 71 for more details on addressing. length 7bits type clear/set address xxxx 2028 and 02c power on value x?x1?, where x is determined by which type of crisco ipl eprom is used restrictions none parallel eprom access complete serial eprom access failed serial eprom access complete internal sonet framer interrupt interrupt phy1 phy data bus parity error crisco execution complete 6543210 bit(s) name description 6 parallel eprom access complete the requested action to the parallel eprom has been completed. see npbus eprom address/command register. 5 serial eprom access failed the requested action to the serial eprom has missed an acknowledge sequence while trying to complete the action. see npbus eprom address/command register. 4 serial eprom access complete the requested action to the serial eprom has been completed. see npbus eprom address/command register. 3 internal sonet framer interrupt the internal framer has signaled an interrupt. 2 interrupt phy1 this bit indicates that an interrupt occurred on phy 1. 1 phy data bus parity error when set to ?1?, a data parity was detected over the phy data eight-bit bus. parity checked is odd. 0 crisco execution complete external serial/parallel eprom initialization has run and is completed. IBM2520L8767 ibm processor for atm resources nodal processor bus interface (npbus) page 344 of 553 atmrm.chapt05.01 08/27/99 16.3: npbus interrupt enable register this register is used to mask bits from the npbus status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit in the npbus status register are set, the npbus status bit will be set in npbus status register. see note on set/clear/read type regis- ters on page 71 for more details on addressing. see npbus status register for the bit descriptions. length 6bits type clear/set address xxxx 2008 and 00c power on value x?00? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 nodal processor bus interface (npbus) page 345 of 553 16.4: npbus eprom address/command register used to accessed a maximum of 2k external serial eprom or 16mg of parallel eprom. length 32 bits type read/write address xxxx 2010 power on value x?00000100? restrictions none reserved execute parallel eprom access more bytes to read/write serial eprom ot read/write execute serial eprom access eprom/extended phy address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-28 reserved reserved 27 execute parallel eprom access this bit will start a read or write function to the parallel eprom. this bit will auto reset after the command is issued. 26 more bytes to read/write serial eprom this bit set to ?1? will help speed up sequential acesses to the serial eprom. if writing, there is a limit as to how many bytes can be written before the serial eprom write buffer is full. typical range is from two to eight bytes, depending on the device. 25: not read/write this bit set to ?1? will cause a write function to the serial/parallel eprom. this bit set to ?0? will cause a read function to the serial/parallel eprom. 24 execute serial eprom access this bit will start a read or write function to the serial eprom. this bit will auto reset after the command is issued. 23-0 eprom/extended phy address this holds the address field that will be used address the serial/parallel eprom. it is also where the 15 - 8 address bits will be held if addressing a phy with more address ability than eight bits. IBM2520L8767 ibm processor for atm resources nodal processor bus interface (npbus) page 346 of 553 atmrm.chapt05.01 08/27/99 16.5: npbus eprom data register used to accessed a maximum of 2k external serial eprom or 16 meg of parallel eprom. 16.6: phy 1 registers this address range provides access to the phy 1 hardware. the details of the registers can be found in the specific publication for the phy hardware. phy 2 registers this address range provides access to the phy 2 hardware. it should be noted that not all applications of IBM2520L8767 will use this access port. the details of the registers can be found in the specific publication for the phy hardware. length 32 bits type read/write address xxxx 2018 power on value x?00000000? restrictions none reserved read data reserved write data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-24 reserved 23-16 read data the holds the data that was read back from the serial/parallel eprom. 15-8 reserved 7-0 write data the holds the data that is destined to be written to the serial/parallel eprom. length 256 doublewords (only lowest eight bits valid) type read/write address xxxx 2400 - 7ff power on value reference the phy-specific publication. restrictions reference the phy-specific publication. length 256 doublewords (only lowest 8 bits valid) type read/write address xxxx 2800 - bff power on value reference the phy-specific publication. restrictions reference the phy-specific publication. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 on-chip checksum and dram test support (chksm) page 347 of 553 hardware protocol assist entities entity 17: on-chip checksum and dram test support (chksm) functional description the chksm entity has two functions. first, it is capable of initializing and/or testing packet and control mem- ory. second, it can perform tcp checksums (2s complement, 16-bit sum with "end-around-carry"). 17.1: chksm base address register the chksm base address register indicates the starting address of a test operation or checksum calcula- tion. the base address can be set up with any alignment and valid address. this register increments with each read or write to memory. on a test mode error, the register holds the address of the 64 bit word which was read in error. length 32 bits type read/write address xxxx 0a00 power on value x?00000000? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register). IBM2520L8767 ibm processor for atm resources on-chip checksum and dram test support (chksm) page 348 of 553 atmrm.chapt05.01 08/27/99 17.2: chksm read/write count register the chksm read/write count register indicates the count of remaining bytes of a checksum operation. this register keeps track of how many bytes remain in the current checksum operation and is decremented with each read or write operation. any length can be set in the 30 lower significant bits. the upper two bits of this register can be written when starting a checksum operation instead of writing the control register. the following are the meanings of the upper two bits: length 32 bits type read/write address xxxx 0a04 power on value x?00000000? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register). st-ck cl-ip current checksum operation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 st-ck start a checksum operation. when this bit is written, bits 0 and 1 in the control register are set, and a check- sum operation is started. this should only be done when the rest of the control register bits are already set up. (i.e. memory select, invert checksum, ...) 30 cl-ip when this bit is written it will clear the chksm tcp/ip checksum data register. this is the same as writing ?1? to bit six of the chksm control register. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 on-chip checksum and dram test support (chksm) page 349 of 553 17.3: chksm tcp/ip checksum data register the chksm tcp/ip checksum data register collects the 16-bit, 2s complement, end-around-carry sum of the bytes. the source data is zero padded if it starts/ends on an odd byte boundary. the chksm tcp/ip checksum data register collects the 16-bit, 2s complement, end-around-carry sum of the bytes. it can be seeded with an initial value. if it is not cleared before running a checksum, the previous value will act as a seed. this register can be cleared when starting a checksum operation by writing the clip bit in the chksm control register or by writing upper bits of chksm read/write count register. see description of chksm control register for description of how to get/set current checksum alignment. 17.4: chksm ripple base register this register is used as base of a ripple pattern when in test mode. this register forms the base for a ripple pattern. each consecutive byte will be incremented by 1 or 8 in the pattern. the ripple mode must be set in the control register to use this feature. the value of this register will change during the test operation. so if a write and compare operation are being performed, this register needs to be setup again for the second opera- tion. length 16 bits type read/write address normal sum xxxx 0a08 inverted sum xxxx 0a0c swapped sum xxxx 0a34 inverted swapped sum xxxx 0a38 power on value x?0000? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register) length 8bits type read/write address xxxx 0a14 power on value x?00? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register). IBM2520L8767 ibm processor for atm resources on-chip checksum and dram test support (chksm) page 350 of 553 atmrm.chapt05.01 08/27/99 17.5: chksm ripple limit register this register is used to determine when the ripple base register overflows to zero. this register forms the compare value for the ripple base register. when the value of the ripple base reg is greater than or equal to this register, the base register will overflow to zero. for example, when this register is set to four, the ripple base register would count from zero through four if counting by one. when set to 0x00, no overflows to zero occur. for example, when the ripple value is 0xff, and you are count- ing by eight, the next value would still be seven. if counting by one, then the next value would be zero. this register should be written before the ripple base. 17.6: chksm interrupt enable register used to specify which status register bits should be used to generate interrupts. see note on set/clear/read type registers on page 71 for more details on addressing. see ?chksm status register? for the bit descrip- tions. length 8bits type read/write address xxxx 0a10 power on value x?ff? restrictions can only be written when chksm is not enabled (see ee bit in chksm control register). length 12 bits type clear/set address xxxx 0a20 and 24 power on value x?ffe? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 on-chip checksum and dram test support (chksm) page 351 of 553 17.7: chksm status register used to relay chksm status information. see note on set/clear/read type registers on page 71 for more details on addressing. the following are the bit descriptions: length 12 bits type clear/set address xxxx 0a18 and 1c power on value x?01? restrictions the count zero bit is not writable. tex -- test error in byte 7-0 lck -- comet lock te1--testerrormsw te0--testerrorlsw cz -- count zero 11109876543210 bit(s) name description 11-4 tex -- test error in byte 7-0 when these bits are set, the checksum has determined that a read comparison error was encountered in the corresponding byte. byte zero is bits 63 - 56 in a 64-bit long word. 3 lck -- comet lock when this bit is set, the checksum has determined that comit has ceased operation for some reason. 2te1--testerrormsw when this bit is set, checksum has determined that a read comparison error was encountered in the most significant 32-bit word. 1 te0 -- test error lsw when this bit is set, the checksum has determined that a read comparison error was encountered in the least significant 32-bit word. 0 cz -- count zero this bit is set when the terminal count of an operation is reached IBM2520L8767 ibm processor for atm resources on-chip checksum and dram test support (chksm) page 352 of 553 atmrm.chapt05.01 08/27/99 17.8: chksm control register the various bits in this register control the mode in which the checksum entity operates. see note on set/clear/read type registers on page 71 for more details on addressing. the various bits are described below: length 13 bits type clear/set address xxxx 0a28 and 2c power on value x?00? restrictions none cl-ff -- clear to all ones ex-al -- expose alignment hi-lo -- hi lo word sw-sum -- swap checksum in-sum -- invert checksum rp-add -- ripple addend cl-ip -- clear ip rp -- ripple ms -- memory select rw -- r/-w test mode tm -- test mode et -- enable tcp checksum updates ee -- enable entity chksm 1211109876543210 bit(s) name description 12 cl-ff -- clear to all ones when this bit is set, the chksm tcp/ip checksum data register is set to 0xffff when it is cleared. when this bit is cleared, it is the chksm tcp/ip checksum data register is set to zero when it is cleared. this option should be used if the tcp/ip checksum should never be set to zero (0xffff is zero also). 11 ex-al -- expose alignment when this bit is set, the internal checksum alignment is exposed for reading/writing. for writes, bit 16 of the write data is used to set the internal alignment. for reads, the alignment is exposed in bit 16 or bit zero depending on the value of the hi-lo bit in this register. this can be useful if doing non-consecutive multiple part check sums (need to preserve alignment between chunks). when this bit is cleared, the internal checksum alignment is not exposed. it is always cleared when the cl-ip bit in this register is set. normally the internal alignment is calculated and maintained across consecutive check sums. 10 hi-lo -- hi lo word when this bit is set, the checksum data register data is placed in the most sig 16 bits of the 32 bit value read. when this bit is cleared, the checksum data register data is placed in the least significant 16 bits of the 32 bit value read. this bit does not affect how writes to the checksum data register occur, the data from the least significant 16 bits is always used. 9 sw-sum -- swap checksum when this bit is set, the checksum data register data is byte-swapped when read. when this bit is cleared, the checksum data register data is read normally. 8 in-sum--invertchecksum when this bit is set, the checksum data register data is inverted when read. when this bit is cleared, the checksum data register data is read normally. there are also new checksum data register addresses that can be read that do the same thing as this control bit. this bit is depreciated. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 on-chip checksum and dram test support (chksm) page 353 of 553 17.9: chksm internal state internal state of checksum. note: this register should not be written unless you know what you are doing! 7 rp-add -- ripple addend when this bit is set, the ripple base register counts up by 1. when this bit is cleared, the ripple base register counts up by eight. 6 cl-ip -- clear ip when this bit is written it will clear the chksm tcp/ip checksum data register and itself. the result of this will be that this bit will never be read as a ?1?. the internal align- ment is also cleared. 5rp--ripple when this bit is set, a ripple pattern will be used in both the read and write test modes. the ripple pattern is used instead of the constant test pattern. when this bit is reset, the constant test pattern is used for the test mode data. 4 ms -- memory select when this bit is set, all chksm memory accesses are to the control memory. when this bit is cleared, all chksm memory accesses are to the packet memory. 3rw--r/-wtestmode when this bit is set, the entity will take the data that is read, and compare it to the test/ripple pattern. when this bit is reset, the checksum entity will write data using the test/ripple pattern to the dram. 2tm--testmode when this bit is set, the entity will take the data that is read, and compare it to the test/ripple pattern, or will write data using the test/ripple pattern to the dram depend- ing on the setting of the rw bit. in both cases, the reading or writing will continue until either an error is encountered, or the chksm read/write count register counts down to zero. when this bit is reset, the checksum entity will operate as described by the other bits. test and chksm modes are mutually exclusive, and test mode takes pre- cedence. 1 et -- enable tcp checksum updates when this bit is set, the entity will collect the tcp checksum in the chksm tcp/ip checksum data register. when this bit is reset, the chksm tcp/ip checksum data register will not be changed by data that is read from the dram. test and chksm modes are mutually exclusive, and test mode takes precedence. 0 ee -- enable entity chksm when this bit is set, the entity will run as specified. when this bit is reset, the entity will not run. length 3bits type read/write address xxxx 0a3c power on value x?00000000? restrictions none bit(s) name description IBM2520L8767 ibm processor for atm resources on-chip checksum and dram test support (chksm) page 354 of 553 atmrm.chapt05.01 08/27/99 software use of chksm this section outlines some ways chksm can be set up and used. test mode possible patterns in test mode, a 64-bit pattern is written/compared to/with memory. there are several different patterns that canbeused: constant test pattern when in test mode, and the rp bit is cleared, the chksm ripple base register is replicated eight times to form a 64-bit pattern. ripple pattern w/ increment of 1 when in test mode and the rp bit is set and rp-add is set and chksm ripple limit register is set to zero, a 64-bit pattern is generated using the chksm ripple base register as a base. for example, if the chksm ripple base register is set to one, the following pattern is generated: 0102030405060708 0203040506070809 030405060708090a 0405060708090a0b ripple pattern w/ increment of 8 when in test mode and the rp bit is set and rp-add is cleared and chksm ripple limit register is set to zero, a 64-bit pattern is generated using the chksm rip- ple base register as a base. for example, if the chksm ripple base register is set to one, the following pattern is generated: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 191a1b1c1d1e1f20 ripple pattern with ripple limit each of the above ripple patterns can also make use of the chksm rip- ple limit register. by setting this register, the user can control when the ripple pattern rolls over to zero. for example, when the chksm ripple limit register is set to three in increment by one mode the ripple pattern looks like: 0102030405060708 0203040506070809 030405060708090a 0001020304050607 0102030405060708 0203040506070809 030405060708090a similarly, when the chksm ripple limit register is set to ten, in increment-by-8 mode, the ripple pattern looks like: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 0001020304050607 IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 on-chip checksum and dram test support (chksm) page 355 of 553 initializing packet/control memory the following list shows the steps to use chksm to initialize packet or control memory: make sure chksm is in diagnostic mode, and other mode bits are reset set the start address by writing the base addr set up the read/write count with number of bytes to initialize set up the test pattern register (ripple pattern register) with pattern to use set up the control register to enable test mode, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized now busy wait until operation is done (or set up interrupt enable register and wait for interrupt) testing packet/control memory the following list shows the steps to use chksm to test packet or control memory: first initialize memory with a pattern using above sequence make sure chksm is in diagnostic mode, and other mode bits are reset set the start address by writing the base addr set up the read/write count with number of bytes to test (same as initialization value) the test pattern register (ripple pattern register) already contains the pattern set up the control register to enable test mode, turn on rw bit, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized now busy wait until operation is done (or set up interrupt enable register and wait for interrupt) when done, check the status register for any errors using ripple pattern generation/checking in packet/control memory the procedures to use the ripple pattern generation and checking, are the same as using test write/read modes. the only difference is that the use ripple pattern mode bit must be set and the ripple pattern base register must be set up. running a tcp/ip checksum in packet/control memory the following list shows the steps to use chksm to generate/verify a tcp/ip checksum: make sure chksm is in diagnostic mode (not enabled) set the start address by writing the base address set up the read/write count with number of bytes to run checksum over, and set the upper two bits of the read/write count register. writing these upper two bits assumes other mode bits are set correctly (i.e. memory bank select). now busy wait until operation is done (or set up interrupt enable register and wait for interrupt) IBM2520L8767 ibm processor for atm resources processor core (pcore) page 356 of 553 atmrm.chapt05.01 08/27/99 entity 18: processor core (pcore) pcore contains the on-board processor and its local subsystems. the primary intent is to run available bit rate (abr) control software. the reason that this is done in a processor is that the standards for this function are in a state of flux at the time of this design. in addition a number of customers have expressed a desire to run additional code specific to their applications such as protocol termination code. below is a diagram of the pcore entity: dcr interface the device control register(dcr) interface is a special processor bus to access local registers. these include registers in the processor local bus(plb) logic, serial port and various IBM2520L8767 registers. pcore block diagram sram control memory int pci master int pci slave int packet memory int bridge control control data sl sl sl sl plb mst 0 mst 1 401 core tmm dcr interrupt clock & power mgmt interface controller IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 357 of 553 interrupt controller this logic manages the interrupts that are passed on to the 401 core. there are two levels of interrupt for the core, critical interrupts and normal interrupts. interrupts can be taken from both on-chip and off-chip sources. pcore has a variety of interrupt source and enable registers. clock & power management this logic controls the various sleep and wakeup options for the 401 core. processor local bus(plb) the plb is used as an interface between the 401 core and its variety of slave devices. the 401 core instruc- tion bus and the 401 core data bus are each connected as masters to this bus. the instruction bus is connected as master 0. the data bus is connected as master 1. bridge the bridge translates processor space addresses to slave subsystem addresses. when a plb read or write transaction is issued from the plb, the bridge function translates the address from the processor address to the slave subsystem address and starts a slave system access. sram there is an on-chip sram for the use of the processor. this sram is typically used only by the processor, therefore, it has a generally predictable access time. this sram would typically be mapped into the proces- sor?s address space. there are a number of different ways that this can be done. control memory control memory can be accessed by the processor. this memory may be mapped into the processor space in a number of different ways. packet memory packet memory can be accessed by the processor. this memory may be mapped into the processor space in a number of different ways. packet memory space also includes the virtual memory space of the IBM2520L8767. pci master interface-external the processor can access the pci bus through this interface. parts of pci space are mapped into processor space. there are a number of different ways that this can be mapped into processor space. IBM2520L8767 register space this access mode of the pci master interface allows access to the internal IBM2520L8767 registers. this access is handled internally and does not affect the external pci bus. IBM2520L8767 ibm processor for atm resources processor core (pcore) page 358 of 553 atmrm.chapt05.01 08/27/99 pci slave interface the pcore registers are accessible via this interface. address translation examples 18.1: pcore control register the pcore control register provides control information about pcore operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 3c00 and c04 power on reset value x?00 00 00 87? restrictions caution must be used when asserting some of the bits during operation. reserved state mux select disable plb 16 cycle timer memory lock normal/critical interrupt little endian mode slave access dead man timer enabled serial port receive interrupt priority serial port transmit interrupt priority 401 timer sleep mode allowed 401 sleep mode allowed lock pcore on error 401 core reset diagnostic mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-11 reserved reserved 12-11 state mux select this selects what data is sent to the state multiplexor. ?00? icu conections ?01? dcu connections ?10? dcr connections/pcore state ?11? plb slave side connections 10 disable plb 16 cycle timer when this bit is set the plb 16-cycle timer will be disabled. 9 memory lock normal/critical interrupt when this bit is written to zero, pcore will treat memory locked as a critical interrupt. when it is one this condition will be treated as a normal interrupt. 8 littleendianmode when this bit is written to zero, pcore master pci access will operate in big endian mode. when one, will operate in little endian mode. when in little endian mode, both the source and destination must be aligned on four-byte boundaries. 7 slave access dead man timer enabled when set, this bit enables the slave-access, dead-man timer to operate. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 359 of 553 6 serial port receive interrupt prior- ity when set, this bit causes the receive interrupt to be a critical interrupt. when not set, it is a regular interrupt. 5 serial port transmit interrupt pri- ority when set, this bit causes the transmit interrupt to be a critical interrupt. when not set, it is a regular interrupt. 4 401 timer sleep mode allowed when set, this bit allows the core timer logic to be put to sleep by the core. 3 401 sleep mode allowed when set, this bit allows the core to put itself into sleep mode. 2 lock pcore on error when this bit is set, an error occurs, and the corresponding lock enable bit is set, pcore will lock. this state is equivalent to being in diagnostic mode. 1 401 core reset when set, this bit places the 401 core in reset state. the output of this register is used in addition to the master reset in crset that holds the core in reset during power up. this bit must be cleared in order to have the core leave reset state. 0 diagnostic mode when set, pcore is in diagnostic mode. when cleared, pcore is in normal mode. when in diagnostic mode, state machines are held in idle. if they are already active, when they next go to idle, they will hold there. bit(s) name description IBM2520L8767 ibm processor for atm resources processor core (pcore) page 360 of 553 atmrm.chapt05.01 08/27/99 18.2: pcore status register the pcore status register provides status information about pcore operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 3c08 and c0c power on reset value x?00 00 00 00? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. reserved instruction cache slave cycle aborted data cache slave cycle aborted 401 msr wait enabled 401 machine check occurred slave dead man timer expired during a write cycle slave dead man timer expired during a read cycle 401 processor stopped 401 processor sleeping 401 timers sleeping bridge translation type target error plb transaction size error plb transaction type error plb transaction timeout plb address out of range pcore locked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-14 reserved reserved 14 instruction cache slave cycle aborted. the current cycle associated with the instruction cache has been aborted. 13 data cache slave cycle aborted the current cycle associated with the data cache has been aborted. 12 401 msr wait enabled the 401 is in a wait state. 11 401 machine check occurred the 401 has encountered a machine check error. 10 slave dead man timer expired during a write cycle the long transaction timer post address acknowledge has expired. 9 slave dead man timer expired duringareadcycle the long transaction timer post address acknowledge has expired. 8 401 processor stopped this bit is set when the 401 is in stop mode. 7 401 processor sleeping this bit is set when the 401 is in sleep mode. 6 401 timers sleeping this bit is set when the timers of the 401 are in sleep mode. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 361 of 553 18.3: pcore user status register the pcore user status register provides user defined status information about pcore software opera- tions. see note on set/clear/read type registers on page 71 for more details on addressing. 5 bridge translation type target error this occurs when the bridge has an unsupported transaction target type issued. 4 plb transaction size error this occurs when the plb has an unsupported transaction size issued. 3 plb transaction type error this occurs when the plb has an unsupported transaction type issued. 2 plb transaction timeout this occurs when the address is not acknowledged in 16 cycles. 1 plb address out of range this happens when an address on the plb bus cannot be translated since it does not fall into a range covered by the address translation array. 0 pcore locked this bit is set when locking is enabled, an error has occurred and the lock mask bit is set that matches the error. length 32 bits type clear/set address xxxx 3c10 and c14 dcr address x?200 and 201? power on reset value x?00 00 00 00? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. user defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 user defined reserved bit(s) name description IBM2520L8767 ibm processor for atm resources processor core (pcore) page 362 of 553 atmrm.chapt05.01 08/27/99 18.4: pcore 401 external status register the pcore 401 external status register provides user defined status information about pcore software operations. see note on set/clear/read type registers on page 71 for more details on addressing. length 32 bits type clear/set address xxxx 3c6c and c70 dcr address x?202 and 203? power on reset value x?00 00 00 00? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. user defined memory controller locked critical interrupt memory controller locked non-critical interrupt serial port receive critical interrupt serial port receive non-critical interrupt serial port transmit critical interrupt serial port transmit non-critical interrupt critical interrupt non-critical interrupt external critical interrupt external non-critical interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-10 user defined reserved 9 memory controller locked criti- cal interrupt this occurs when the memory controller is locked and this condition is set as critical. 8 memory controller locked non-critical interrupt this occurs when the memory controller is locked and this condition is set as non-critical. 7 serial port receive critical interrupt this occurs when the serial controller has a transmit interrupt and the corresponding crit- ical-interrupt enable is on in the control register. 6 serial port receive non-critical interrupt this occurs when the serial controller has a transmit interrupt and the corresponding crit- ical-interrupt enable is on in the control register. 5 serial port transmit critical interrupt this occurs when the serial controller has a transmit interrupt and the corresponding crit- ical-interrupt enable is on in the control register. 4 serial port transmit non-criti- cal interrupt this occurs when the serial controller has a transmit interrupt and the corresponding crit- ical-interrupt enable is on in the control register. 3 critical interrupt this occurs when a bit in the IBM2520L8767 primary status register is set and the corre- sponding critical interrupt enable is on. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 363 of 553 18.5: pcore IBM2520L8767 shadow status register this register is used to shadow the intst interrupt source. the purpose of this register is to allow polling for IBM2520L8767 interrupts without having to use the pci bus. 18.6: pcore IBM2520L8767 shadow rxque status register this register is used to shadow the rxque status and enabled status registers. the purpose of this regis- ter is to allow polling for IBM2520L8767 interrupts without having to use the pci bus. 2 non-critical interrupt this occurs when a bit in the IBM2520L8767 primary status register is set and the corre- sponding non-critical interrupt enable is on. 1 external critical interrupt this occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. 0 external non-critical interrupt this occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. length 32 bits type read address xxxx 3c7c dcr address x?208? power on value x?00 00 00 00? restrictions none length 32 bits type read address xxxx 3c88 dcr address x?20f? power on value x?00 00 00 00? restrictions none bit(s) name description IBM2520L8767 ibm processor for atm resources processor core (pcore) page 364 of 553 atmrm.chapt05.01 08/27/99 18.7: pcore interrupt enable register this register is used to enable bits from the pcore status register and potentially generate interrupts to the control processor. when both a bit in this register and the corresponding bit(s) in the pcore status register are set, the pcore interrupt to pcint will be enabled. see note on set/clear/read type registers on page 71 for more details on addressing. see pcore status register on page 360 for the bit descriptions. . 18.8: pcore user interrupt enable this register is used to enable an interrupt based on bits from the corresponding pcore user status regis- ter and potentially generate interrupts to the control processor. when both a bit in this register and the corre- sponding bit(s) in the status register are set, the pcore status bit(s) will be set in the corresponding pcore user status register (described on page 361). see note on set/clear/read type registers on page 71 for more details on addressing. see pcore user status register on page 361 for the bit descriptions. 18.9: pcore 401 interrupt enable register this register is used to enable bits from the pcore 401 external status register and generate interrupts to the 401 processor. when both a bit in this register and the corresponding bit(s) in the pcore 401 external status register are set, the 401 interrupt to the 401 core will be enabled. see note on set/clear/read type registers on page 71 for more details on addressing. see pcore status register on page 360 for the bit descriptions. length 32 bits type clear/set address xxxx 3c18 and c1c power on value x?00 00 00 00? restrictions none length 32 bits type clear/set address xxxx 3c20 and c24 dcr address x?204 and 205? power on value x?00 00 00 00? restrictions none length 32 bits type clear/set address xxxx 3c74 and c78 dcr address x?206 and 207? power on value x?00 00 00 00? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 365 of 553 18.10: pcore error lock enable register the pcore error lock enable register provides the ability to halt pcore when the corresponding status bit in the status register are set and locking is enabled. when a bit in this register corresponds to a bit that is set in the status register, the state machines in pcore will be held in idle state until the lock is disabled. see note on set/clear/read type registers on page 71 for more details on addressing. 18.11: pcore user error lock enable register the pcore user error lock enable register provides the ability to halt pcore when the corresponding status bit in the user status register are set and locking is enabled. when a bit in this register corresponds to a bit that is set in the status register, the state machines in pcore will be held in idle state until the lock is disabled. see note on set/clear/read type registers on page 71 for more details on addressing. 18.12: pcore transaction dead man timer value register this register is used to load a timer that counts to zero from the value loaded in this register. the maximum wait for an i/o transaction is about 2ms when this is set to x?ffff?. the value of this register is written into the pcore transaction dead man timer value register after the slave address is validated during a proces- sor access to a slave device. length 32 bits type clear/set address xxxx 3c28 and c2c power on reset value x?00 00 7f ff? restrictions none length 32 bits type clear/set address xxxx 3c30 and c34 power on reset value x?ff ff ff ff? restrictions none length 16 bits type read/write address xxxx 3c80 power on reset value x?ff ff? restrictions none IBM2520L8767 ibm processor for atm resources processor core (pcore) page 366 of 553 atmrm.chapt05.01 08/27/99 18.13: pcore address translation base address array the pcore address translation base address array provides the base address of the region to which the 128mb 401 address range corresponds. when an address is issued from the 401 core it will fall within 1 of 32, 128-mb address ranges. the ranges may have special attributes associated with them in registers in the 401 core (cachable/noncachable etc.). the first address corresponds to the first 128-mb region of core memory. the second address corresponds to the second 128-mb region and so on. the address contained in this array is the base address of the target memory space. length 32x32 bits type read/write address xxxx 3e00 to e7c power on reset value x?00 00 00 00? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 367 of 553 18.14: pcore address transaction type and range array the pcore address transaction type and range array provides the transaction type (sram, packet, control...) information and valid range information. when an address is issued from the 401 core it will fall within one of thirty-two 128mb address ranges. the ranges may have special attributes associated with them in registers in the 401 core (cachable/noncachable etc.). the first address corresponds to the first 128mb region of core memory. the second address corresponds to the second 128mb region and so on. single range memory targets have address range checking as described below. however, dual target memory locations behave differently. the 27-bit range field is used to mark the processor address range crossover point. in the case of shared sram, the sram base address is assumed to be zero. the dram target address is the new base address plus the offset from the crossover point. in the case of shared control and packet memory access, the 27-bit range is the crossover point and the offset from the plb address is added to the new base address. however, when the crossover point is reached, the memory target is changed from control to packet memory. the 27-bit range field is used to check for invalid addresses. if the address translation base address plus the range are less than the translated address, an address out-of-range error is specified. length 32x32 bits type read/write address xxxx 3e80 to eff power on reset value x?00 00 00 00? restrictions none bit(s) description the transaction type information is as follows: ?00000? onchipsram ?00001? packet memory ?00010? control memory ?00011? control/packet ?11000? on chip sram/control memory ?11001? onchipsram/packetmemory ?00100? IBM2520L8767 registers ?00101? pci memory access (non-IBM2520L8767) ?01100? pci i/o access ?10100? pci config access IBM2520L8767 ibm processor for atm resources processor core (pcore) page 368 of 553 atmrm.chapt05.01 08/27/99 18.15: pcore last plb address register the pcore last plb address register is the address from the plb bus at the time of the hang condition. when a plb long timeout occurs, this register will hold the address of the failed access. length 32 bits type read address xxxx 3c38 dcr address x?209? power on reset value x?ff ff ff ff? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 369 of 553 18.16: pcore last plb error register the pcore last plb error register is the information associated with the last error on the plb bus. this register contains an error syndrome for a slave bus timeout. length 32 bits type read address xxxx 3c84 dcr address x?20d? power on reset value x?00 01 ff ff? restrictions none reserved read/not write one/four word sram memory access packet memory access control memory access combination control/packet pci master access off chip hang state bit IBM2520L8767 register access byte enables access type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-18 reserved reserved 17 read/not write when set, a read cycle; when not a write cycle. 16 one/four word this bit is set when one word is transferred. when not set, four words are transferred. 15 sram memory access this bit is set when sram is accessed. 14 packet memory access this bit is set when packet memory is accessed. 13 control memory access this bit is set when control memory is accessed. 12 combination control/packet this bit is set when the cycle is to the one combined IBM2520L8767 memory access region. 11 pci master access off chip this bit is set when an offchip pci master access is underway. 10 hang state bit indicates the hang state. 9 IBM2520L8767 register access this bit is set when the plb access was to the IBM2520L8767 registers. 8-5 byte enables these are the byte enables for the access. IBM2520L8767 ibm processor for atm resources processor core (pcore) page 370 of 553 atmrm.chapt05.01 08/27/99 18.17: pcore sram this sram is used by the 401 processor to hold on chip code and data. this sram is accessed via a window starting at the address starting at the srambase register. the window allows access to 64 locations in the sram at any given time. 18.18: pcore sram base address the sram base address register is used to select the base address of the window to access the sram. 4-0 access type these bits indicate the transaction type 1 ?00000? on chip sram 2 ?00001? packet memory 3 ?00010? control memory 4 ?00011? control/packet 5 ?11000? on chip sram/control memory 6 ?11001? on chip sram/packet memory 7 ?00100? IBM2520L8767 registers 8 ?00101? pci memory access (non IBM2520L8767) 9 ?01100? pci i/o access 10 ?10100? pci configuration access length 8kx32 type read/write(with window) address xxxx 3f00 to fff power on value x?uu uu uu uu? restrictions none length 32 bits type read/write address xxxx 3c5c description the sram base address used to point into a 64-entry region of the sram. power on value x?00 00 00 00? restrictions none bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 371 of 553 18.19: pcore read data transfer registers the pcore read data transfer registers holds the data that is being transferred between the core and one of the dram slave subsystems. on single word transfers data transfer register 0 will hold the data. on cache line transfers all four registers are used. these registers store the data that is being transferred between packet or control memory and the core. 18.20: pcore write data transfer registers the pcore write data transfer registers holds the data that is being transferred between the core and control memory. on single word transfers data transfer register 0 will hold the data. on cache line transfers all four registers are used. these registers store the data that is being transferred between control memory and the core. note: cc0-cfc is used by the serial port. length 32 bits type read address read data transfer register 0 xxxx 3c3c read data transfer register 1 xxxx 3c40 read data transfer register 2 xxxx 3c44 read data transfer register 3 xxxx 3c48 power on value x?00000000? restrictions none length 32 bits type read address write data transfer register 0 xxxx 3c4c write data transfer register 1 xxxx 3c50 write data transfer register 2 xxxx 3c54 write data transfer register 3 xxxx 3c58 power on value x?00000000? restrictions none IBM2520L8767 ibm processor for atm resources processor core (pcore) page 372 of 553 atmrm.chapt05.01 08/27/99 18.21: pcore IBM2520L8767 polling register the pcore IBM2520L8767 polling register provides status information to pcore about IBM2520L8767 operations. this allows pcore to poll specific IBM2520L8767 status without using pci bus bandwidth. 18.22: pcore integer input rate conversion register this register is the integer input port for the rate conversion logic. it is used as input to the rate conversion logic. an integer rate is placed in this register. the on-board logic converts it to an abr rate format. length 5bits type read address xxxx 3c60 dcr address x?20e? power on reset value x?00 00 00 00? restrictions during normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. memory locked control memory locked packet memory locked virtual lock arbit lock 43210 bit(s) name description 31-5 reserved reserved 4 memory locked memory is locked. 3 control memory locked control memory is locked. 2 packet memory locked packet memory is locked. 1 virtual lock vimem is the locker of memory. 0 arbit lock arbit is the locker of memory. length 32 bits type read/write address xxxx 3c64 dcr address x?20b? power on value x?00 00 00 00? restrictions none IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 processor core (pcore) page 373 of 553 18.23: pcore abr output rate register this register is the abr output port for the rate conversion logic.an integer rate was placed in the integer input register. the logic converts it to an abr rate and places the result in this register. 18.24: plb pacr register this is the plb arbitration control register. it contains information regarding the state of the transmit and receive interfaces. length 16 bits type read address xxxx 3c68 dcr address x?20c? power on value x?00 00? restrictions none length 32 bits type read/write address dcr only dcr address x?0f7? power on value x?00000000? restrictions accessible only through the dcr interface. ppmod - plb priority mode prioo - priority order reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31 ppmod - plb priority mode 0-fixed 1-fair 30-29 prioo - priority order note this looks strange because there are only two masters in this implementation. 00 - instruction - data 01 - data - instruction 10 - instruction - data 11 - instruction - data 28-0 reserved reserved IBM2520L8767 ibm processor for atm resources rs-232 interface logic (rs-232) page 374 of 553 atmrm.chapt05.01 08/27/99 entity 19: rs-232 interface logic (rs-232) the rs232 entity provides a means by which an external debugger and the processor core can communi- cate. the base rs-232 core operates on a byte transmit and receive basis. using the rs-232 mode register, however, the entity can be configured to operate on a four byte wide basis. 19.1: rs-232 line status register this register contains information regarding the state of the transmit and receive interfaces. bits in this regis- ter are cleared by writing ?1? to them. writing ?0? has no effect. when in single byte transmit or receive mode, reading the receive buffer will clear bit seven and writing the transmit buffer will clear bit two. length 8bits type read/write address xxxx 4cc0 dcr address x?210? power on value x?00000000? restrictions none receive buffer ready framing error overrun error parity error line break transmit buffer ready transmit shift register ready reserved 76543210 bit(s) name description 31-8 reserved reserved 7 receive buffer ready this bit indicates that a byte has been received on the interface. 6 framing error this bit indicates that a stop bit was not detected when expected. 5 overrun error this bit indicates that an overrun condition occurred. owing to internal buffering, this bit will be set when the spu core begins receiving a third byte when two unprocessed bytes have been received. 4 parity error this bit indicates a parity error was detected on a received byte. 3 line break this bit indicates a line break was received. 2 transmit buffer ready this bit indicates the transmit buffer is ready to accept data. 1 transmit shift register ready this bit indicates that the transmit logic serializer is ready to accept data. 0 reserved reserved. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 rs-232 interface logic (rs-232) page 375 of 553 19.2: rs-232 handshake status register this register contains information regarding the state of the handshaking signals. if either bit in this register is set, it must be cleared before the port will transmit. bits in this register are cleared by writing ?1? to them. writing ?0? has no effect. when in single byte transmit or receive mode, read the receive buffer will clear bit seven and writing the transmit buffer will clear bit two. length 2bits type read/write address xxxx 4cc8 dcr address x?212? power on value x?00000000? restrictions none dsr inactive cts inactive 76 bit(s) name description 31-8 reserved reserved 7 dsr inactive this bit indicates that the data set ready signal is inactive. 6 cts inactive this bit indicates that the clear to send signal is inactive. 5-0 reserved reserved IBM2520L8767 ibm processor for atm resources rs-232 interface logic (rs-232) page 376 of 553 atmrm.chapt05.01 08/27/99 19.3: rs-232 baud rate divisor high register this register contains the upper portion of the value used to determine the baud rate. the value to place in this register can be determined by this formula: baudrate = 33mhz/(16*((baud rate high) + 1)). 19.4: rs-232 baud rate divisor low register this register contains the lower portion of the value used to determine the baud rate. the value to place in this register can be determined by this formula: baudrate = 33mhz/(16*((baud rate low) + 1)). length 4bits type read/write address xxxx 4cd0 dcr address x?214? power on value: x?00000000? restrictions none baud rate divisor 3210 bit(s) name description 31-4 reserved reserved 3-0 upper byte of baud rate divisor. length 8bits type read/write address xxxx 4cd4 dcr address x?215? power on value x?00000000? restrictions none baud rate divisor 76543210 bit(s) name description 31-8 reserved reserved 7-0 upper byte of baud rate divisor. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 rs-232 interface logic (rs-232) page 377 of 553 19.5: rs-232 serial port control register this register controls how the port operates. length 8bits type read/write address xxxx 4cd8 dcr address x?216? power on value x?00000000? restrictions none loopback mode data terminal ready request to send data size parity enable parity type stop bits 76543210 bit(s) name description 31-8 reserved reserved 7-6 loopback mode these bits control how the incoming and outgoing data streams are processed. the bits are encoded as follows: ?00? normal transmit and receive operation. ?01? internal loopback - transmit stream is connected to the receive stream. ?10? automatic echo - received stream is connected to the transmit stream. ?11? reserved. 5 data terminal ready if dtr is under software control, this bit determines the state of dtr. if dtr is under hardware control, setting this bit to ?0? forces dtr inactive. 4 request to send if rts is under software control, this bit determines the state of rts. if rts is under hardware control, setting this bit to ?0? forces rts inactive. 3 data size this bit set to ?1? selects eight data bits. this bit set to ?0? selects seven data bits. 2 parity enable set to ?1?, this bit selects odd parity. set to ?0?, this bit selects even parity. 1 parity type set to ?1?, this bit selects odd parity. set to ?0?, this bit selects even parity. 0 stop bits set to ?1?, this bit selects 2 stop bits. set to ?0?, this bit selects 1 stop bit. IBM2520L8767 ibm processor for atm resources rs-232 interface logic (rs-232) page 378 of 553 atmrm.chapt05.01 08/27/99 19.6: rs-232 receive command register this register controls how the receive logic operates. length 8bits type read/write address xxxx 4cdc dcr address x?217? power on value x?00000000? restrictions none enable receiver dma/interrupt mode receive error interrupt enable pause mode enable reserved 76543210 bit(s) name description 31-8 reserved reserved 7 enable receiver set to ?1?, this bit enables the receiver logic. 6-5 dma/interrupt mode these bits control how the receive logic transfers received bytes. they are encoded as follows: ?00? no dma or interrupts (polled operation). ?01? dma disabled, receive interrupt driven on byte reception. ?10? dma enabled, receive interrupt on byte reception disabled - mode to select whenusing4-bytemode.thelogicexternaltothers-232corewilldrivean interrupt when four bytes have been received. ?11? reserved. 4 receive error interrupt enable. if set to ?1? an interrupt will be driven when a receive error is detected. the value of bits 6-5 have no effect on this bit. 3 pause mode enable. set to ?0?, this bit puts rts under software control. if this bit is ?1?, rts is under hard- ware control. if under hardware control, rts may be dropped if: the receive buffer internal to the rs-232 core is full and there are only six bits left to receive of another byte. a receive error is active. 2-0 reserved. reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 rs-232 interface logic (rs-232) page 379 of 553 19.7: rs-232 transmit command register this register controls how the transmit logic operates. length 8bits type read/write address xxxx 4ce0 dcr address x?218? power on value x?00000000? restrictions none enable transmitter dma/interrupt mode transmit shift register empty interrupt enable transmit shift register error interrupt enable pause/stop on cts inactive pause/stop on cts inactive reserved 76543210 bit(s) name description 31-8 reserved reserved 7 enable transmitter set to ?1?, this bit enables the transmitter logic. 6-5 dma/interrupt mode these bits control how the transmit logic transfers bytes to be transmitted. they are encoded as follows: ?00? no dma or interrupts (polled operation). ?01? dma disabled, transmit interrupt driven when rs-232 core can accept more data. ?10? reserved ?11? dma enabled, transmit interrupt on empty buffer disabled-mode to select when using four-byte mode. the logic external to the rs-232 core will drive an interrupt when the four bytes transmit buffer is empty. 4 transmit shift register empty interrupt enable. if set to ?1? an interrupt will be driven when the transmit shift register is empty. the value of bits 6-5 have no effect on this bit. 3 transmit shift register error interrupt enable. if set to ?1? an interrupt will be driven when a transmit shift register error is detected. the valueofbits6-5hasnoeffectonthisbit. 2 pause/stop on cts inactive. set to ?0?, this bit causes the hardware to pause transmitting when cts is inactive. set to ?0?, this bit causes the hardware to stop transmitting and discard the byte it was send- ing. 1 line break set to ?0?, this bit causes a line break to be sent. 0 reserved. reserved IBM2520L8767 ibm processor for atm resources rs-232 interface logic (rs-232) page 380 of 553 atmrm.chapt05.01 08/27/99 19.8: rs-232 byte transmit/receive buffer this register is both the receive and transmit buffer. writing this address places data in the transmit buffer and reading this address reads what is in the receive buffer. if using four-byte mode, code should use the rs-232 four byte transmit/receive buffer. length 8bits type read/write address xxxx 4ce4 dcr address x?219? power on value x?00000000? restrictions none tx/rx data 76543210 bit(s) name description 31-8 reserved reserved 7-0 tx/rx data. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 rs-232 interface logic (rs-232) page 381 of 553 19.9: rs-232 mode register this register is both the receive and transmit buffer when in four-byte mode. writing this address places data in the transmit buffer and reading this address reads what is in the receive buffer. length 12 bits type read/write address xxxx 4cf0 dcr address x?21c? power on value x?00000000? restrictions none receive valid bits transmit valid bits force cts active force dsr active reset enable 4-byte mode 11109876543210 bit(s) name description 31-12 reserved reserved. 11-8 receive valid bits these bits indicate which parts of the four-byte receive buffer are valid. this is provided to aid software in determining when an error occurred within a message. a bit with a value of ?1? represents a valid byte that has been received. bit 11 corresponds to bits 31-24 of the four-byte receive buffer, bit 10 to bits 23-16, etc. 7-4 ?transmit valid bits these bits indicate which parts of the four-byte transmit buffer have been sent. this is provided to aid soft- ware in determining when an error occurred within a message. a bit with a value of ?0? means the correspond- ing byte has been transmitted. bit seven corresponds to bits 31-24 of the four-byte transmit buffer, bit six to bits 23-16, etc. 3 force cts active set to ?1?, this bit forces clear to send to the rs-232 core active. 2 force dsr active set to ?1?, this bit forces data set ready to the rs-232 core active. 1 reset set to ?1?, bit one will reset the logic that provides the four-byte interface to the rs-232 core logic. this bit does not reset the rs-232 core. this bit need only be on for one cycle for the reset to occur. 0 enable four byte mode set to ?1?, this bit enables four-byte mode operation. set to ?0?, this bit enables single-byte operation. IBM2520L8767 ibm processor for atm resources rs-232 interface logic (rs-232) page 382 of 553 atmrm.chapt05.01 08/27/99 19.10: rs-232 four byte transmit/receive buffer this register is both the receive and transmit buffer when in four-byte mode. writing this address places data in the transmit buffer and reading this address reads what is in the receive buffer. length 32 bits type read/write address xxxx 4cf4 dcr address x?21d? power on value x?00000000? restrictions none tx/rx data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-0 tx/rx data. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 reset and power-on logic (crset) page 383 of 553 entity 20: reset and power-on logic (crset) this entity will perform bist and flush operations. chip software resets can be control by this entity, as well as the chip clock control. 20.1: reset status register this register is used to reflect what that last type of reset was. a hardware reset will clear software reset status bits, but a software reset will not have an effect on the hardware status bits. length 7bits type read/write address xxxx 0500 por value ?db00001? or ?db00010?, where b is the state of the bist results, and d is the pll phase detection. software reset value ?db001qq? or ?db010qq?, where q is the state of this bit before the software reset and b is the state of the bist results. restrictions none pll out-of-phase detect bist results pcore reset software reset software reset/bist por reset reserved 6543210 bit(s) name description 7 pci clock frequency change a value of ?1? means that the real time pci frequency calculator has detected a major change in frequency and has calculated new range bits for the pll. 6 pll out-of-phase detect a value of ?1? means that the out-of-phase detector circuit has triggered. this is just an indicator and is normal operation. 5 bist results a value of ?1? means that a failure occurred within the bist checking logic. 4 pcore reset the pcore entity has requested a chip reset via its hardware interface. 3 software reset a software reset has occurred, the chip was flushed. 2 software reset/bist a software reset has occurred, and bist/flush was run. 1 por reset a por hardware reset that flushed the chip has occurred. 0 reserved IBM2520L8767 ibm processor for atm resources reset and power-on logic (crset) page 384 of 553 atmrm.chapt05.01 08/27/99 20.2: software reset enable register this register protects the software reset register if this register is not set, then a reset will not occur. write a x?b4? to this register to enable software reset. a software reset will clear this register. 20.3: software reset register this register generates a scan path flush reset of the chip, or software initiated run of bist, with the excep- tion of the registers in the reset entity. length 8bits type read/write address xxxx 0504 por value x?0? restrictions none length 6bits type write only address xxxx 0508 por value ?0? restrictions writing to this register without first setting the software reset enable register will have no effect. the register will not be set, so the order of writing the enable and the software reset is important; the enable must be written first. additionally, all current operations being performed by the IBM2520L8767 must be terminated before doing a reset operation. a minimum number of enable bits to turn off would be bits four, five and six in intst control register and bit two in pcint config word 1. pcore system reset pcore chip reset pcore reset total software reset run bist software reset 543210 bit(s) name description 5 pcore system reset writing this bit to a ?1? delivers a system reset condition to the internal processor core. 4 pcore chip reset writing this bit to a ?1? delivers a chip reset condition to the internal processor core. 3 pcore reset writing this bit to a ?1? causes the internal processor core to reset. 2 total software reset writing this bit to a ?1? causes software reset, and will be cleared after the software reset has occurred. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 reset and power-on logic (crset) page 385 of 553 20.4: memory type register this register indicates the type of memory used for control and packet memory so that reset hardware will know how to properly preserve it during a reset. 1runbist writing this bit to a ?1? causes bist to run, and will be cleared after the software reset has occurred. this function is primarily for pre-loading the bist registers to get more test coverage. 0 software reset writing this bit to a ?1? causes software reset, and will be cleared after the software reset has occurred. length 4bits type read/write address xxxx 050c por value x?0? restrictions none packet memory type control memory type 3210 bit(s) name description 3-2 packet memory type decodes the same as bits 9-8 of comet/pakit control register on page 143. 1-0 control memory type decodes the same as bits 9-8 of comet/pakit control register on page 143. bit(s) name description IBM2520L8767 ibm processor for atm resources reset and power-on logic (crset) page 386 of 553 atmrm.chapt05.01 08/27/99 20.5: crset pll range debug used to debug the ppl operation. length 32 bits type read only address xxxx 0518 por value x?xxxxxxxx? tbd pll range bit 1 (a pll range bit 0 (a) pll range bit 1 (b) pll range bit 0 (b) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-4 tbd 3 pll range bit 1 (a) 2 pll range bit 0 (a) 1 pll range bit 1 (b) 0 pll range bit 0 (b) IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 reset and power-on logic (crset) page 387 of 553 20.6: crset control register used to control pci frequency detection logic. length 10 bits type read/write address xxxx 0510 por value x?30? freq. change reserved 9876543210 bit(s) name description 9 disable the frequency change detection interrupt (write only) setting this bit to a one will disable using the frequency change detection bit as an interrupt source to intst. 8-0 reserved IBM2520L8767 ibm processor for atm resources reset and power-on logic (crset) page 388 of 553 atmrm.chapt05.01 08/27/99 20.7: clock control register (nibble aligned) used to disable clocks for power conservation and provide the "select a clock" function for mpeg and front end support. to change a nibble field in this register, always set it to zero first, and then to the new value. length 29 bits type read/write address xxxx 0520 por value x?6676632? framer tree disabled (framr) encoded control for bist speed reserved (encoded con- trol for pcore clock rate) encoded control for vari- ous on-chip functions encoded control for cell opportunity logic (cello) encoded control for mpeg clocking logic (mpegt) encoded control for transmit logic (linkt) and sonet framer (framr) encoded control for receive logic (linkr) and sonet framer (framr) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 28) framer tree disabled (framr) when set this bit will disable the clock tree to the sonet framer logic. 27-24 encoded control for bist speed hardcoded to 6. 23-20 reserved (for encoded control for pcore clock rate.) hardcodedto6. 19-16 encoded control for various on chip timestamp logic (rxque,etc.) same as bits 3-0. 15-12 encoded control for cell opportunity logic (cello) same as bits 3-0. 11-8 encoded control for mpeg clocking logic (mpegt) same as bits 3-0. 7-4 encoded control for transmit logic (linkt) and sonet framer (framr) same as bits 3-0. 3-0 encoded control for receive logic (linkr) and sonet framer (framr) below is the encoded value of the bits that select a given clock. always refer to select a clock" selection matrix on page 389 for inputs supported for each clock out type. x?0? turn this clock off. x?1? use the external mpeg oscillator. x?2? use the external rx clock. x?3? use the external tx clock. x?4? use the internal 15-ns clock. assumes 33-mhz pci clock. x?5? use the internal 20-ns clock. assumes 33-mhz pci clock. x?6? use the internal 30-ns clock. assumes 33-mhz pci clock. x?7? use the internal 60-ns clock. assumes 33-mhz pci clock. x?8? use the internal 120-ns clock. assumes 33-mhz pci clock. x?9? use the internal 240-ns clock. assumes 33-mhz pci clock. x?a? use the internal 480-ns clock. assumes 33-mhz pci clock. x?b? use the differential receiver clock divided by 8. ]x?c? use the differential transmit clock divided by 8. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 reset and power-on logic (crset) page 389 of 553 20.8: cbist prpg results this is the prpg results register, updated after bist has run. it is used by the bist function for chip test. 20.9: cbist misr results this is the misr results register, updated after bist has run. it is used by the bist function for chip test. select a clock" selection matrix clock frequency base bist bbstng cbstng1 pcore cppul cello bco cco mpegt bmt cmt linkt(tx) btx ctx rtx linkr(rx) brx crx rrx selection encoding register bits htx osc xx ?1100? hrx osc xx ?1011? 480 xx xx ?1010? 240 ns xx xx ?1001? 120 ns xx xx ?1000? 60 ns xx xx ?0111? 30 ns xx xx xx xx xx xx ?0110? 20 ns xx ?0101? 15 ns xx ?0100? txoscxx xxxxxxxx?0011? rxoscxx xxxxxxxx?0010? mpegoscxx xxxxxxxx?0001? off xxxxxxxx?0000? control bits 27-24 23-20 15-12 11-8 7-4 3-0 length 32 bits type read/write address xxxx 05b0 por value x?ffffffff? length 32 bits type read/write address xxxx 05b4 por value x?00000000? IBM2520L8767 ibm processor for atm resources reset and power-on logic (crset) page 390 of 553 atmrm.chapt05.01 08/27/99 20.10: cbist bist rate this register will hold a counter value that will separate the time between when the a clock and the b clock are launched during bist. this allows finer tuning to how much power bist uses versus how much testing gets done within the time allowed. it is used by the bist function for chip test. 20.11: cbist prpg expected signature this is the prpg signature register, which should be written by crisco code with the expected value of signa- ture, based on the value in cbist cyct load value and the clock selected for bist to run from. it is used by the bist function for chip test. length 3bits type read/write address xxxx 05b8 por value x?0? length 32 bits type read/write address xxxx 05c0 por value x?ffffffff? IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 reset and power-on logic (crset) page 391 of 553 20.12: cbist misr expected signature this is the misr signature register, which should be written by crisco code with the expected value of signa- ture, based on the value in cbist cyct load value and the clock selected for bist to run from. it is used by the bist function for chip test. 20.13: cbist cyct load value this register is the loaded value for the cbist bist rate register. the time for bist to run can be computed by the following equation: (shift count) ? (c30 clock ? 2) ? (cycle time). it is used by the bist function for chip test. length 32 bits type read/write address xxxx 05c4 por value x?00000000? length 18 bits type read/write address xxxx 05c8 por value x?00005800? IBM2520L8767 ibm processor for atm resources jtag interface logic (cjtag) page 392 of 553 atmrm.chapt05.01 08/27/99 entity 21: jtag interface logic (cjtag) the cjtag entity contains logic to support a test access port (tap) controller compliant with the ieee 1149.1-1990 standard. the proper operation of these signals and the tap controller is defined in the ieee 1149.1-1993 standard. the tap controller is accessed via the following five pins: scanning the tap controller supports two types of scans: instruction scans and data scans. instruction scans control the type of operation and select which (if any) scan chains are involved in the operation. data scans generally clock the data on tdi into the selected scan chain. tck test clock. all activity of the jtag interface is clocked via tck. events occur on the rising or falling edge of tck. tck should have a maximum frequency of 20mhz. tms test mode select. test mode select is used to control state transitions in the tap controller. these transitions occur on the rising edge of tck. the btr selected for tms should be one with an internal pull-up. tdi test data in. serial data input to the jtag logic. the btr selected for tdi should be one with an internal pull-up. tdo test data out. serial data output to the jtag logic. trst test reset. asynchronous, minus active reset to the tap controller. assertion of this input causes the tap controller to reset and the jtag instruction register to load the idcode instruction. it is preferable to have trst be independent of any chip reset. with an independent reset, the jtag logic can be reset, allowing the chip?s state to be examined without having to reset the core logic. the btr selected for trst should be one with an internal pull-up. IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 jtag interface logic (cjtag) page 393 of 553 instruction format the jtag logic in the IBM2520L8767 supports 32-bit instructions in one of two formats. the first format uses opcodes compliant with the ieee standard; the other supports opcodes as defined by the walnut chip that are compatible but not compliant with the ieee standard. the general command format is as follows: as an instruction is scanned in, status for the previous instruction is presented on tdo. the 32 status bits have the following format: instruction opcode odd parity reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) description 31-17 instruction opcode 16 in compatible mode, this is odd parity over bits 15-0 15-0 reserved reserved walnut compliant mode bad modifier parity detected bist running reserved hardwired 313029282726252423222120191817161514131211109876543210 bit(s) description 31-6 reserved 5 walnut compliant mode. 4 bad modifier parity detected. 3 bist running. 2 reserved 1-0 hardwired to ?01? as required by ieee specification. IBM2520L8767 ibm processor for atm resources jtag interface logic (cjtag) page 394 of 553 atmrm.chapt05.01 08/27/99 the following instructions are supported: 21.1: idcode returns a 32-bit identification code when a data scan is performed. the idcode has the following structure: 21.2: sample/preload captures the state of the boundary scan i/o. as the values captured are scanned out, new values can be loaded into the boundary scan latches. this operation will not effect functional operation. 21.3: extest drives the values in the boundary scan latches onto their respective i/o. this function can be used in conjunction with sample/preload to perform card wire tests. 21.4: bypass selects the single bit bypass register for data scans. 21.5: runbist causes built in self test (bist) to execute. opcode x?0300 xxxx? version number part number manufacturer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit(s) name description 31-28 version number this is set to x?4? for the IBM2520L8767. 27-12 part number this is set to x?1d00? for the IBM2520L8767. 11-0 manufacturer this is set to x?049? for ibm. opcode x?0402 xxxx? opcode (compliant) x?00000000? opcode (compatible) x?0600 xxxx? opcode (compliant) x?ffffffff? opcode (compatible) x?ffffxxxx? or x? 0000x xxx? opcode x?0770 xxxx? IBM2520L8767 ibm processor for atm resources atmrm.chapt05.01 08/27/99 jtag interface logic (cjtag) page 395 of 553 21.6: bist_results returns a 64-bit value when a data scan is performed. bits 63-32 are the prpg and bits 31-0 are the misr from the bist logic. 21.7: walnut_mode this command enables walnut compatible mode. 21.8: compliant_mode this command enables jtag compliant mode. 21.9: stop this command halts the functional clocks of IBM2520L8767 in anticipation of a scan. after the stop command is scanned in, a data scan that takes the tap controller through the capture-dr, exit1-dr, and update-dr states should be performed. 21.10: scan this command causes tdi to be clocked into the scan chain during a subsequent data scan. the scan out of the scan chain is placed on tdo. this command will not work unless a stop command is sent down immediately before the scan command is issued. 21.11: scan_in this command causes tdi to be clocked into the scan chain during a subsequent data scan. tdo is forced to b?0?. this command will not work unless a stop command is sent down immediately before the scan_in command is issued. 21.12: scan_out this command causes the scan out of the scan chain to be placed on tdo. data is circulated through the scan chains. tdi is ignored. this command will not work unless a stop command is sent down immediately before the scan_out command is issued. opcode x?1f02xxxx? opcode x?3000? opcode x?33010000? opcode x?2002? opcode x?0802? opcode x?0900? opcode x?0a00? IBM2520L8767 ibm processor for atm resources jtag interface logic (cjtag) page 396 of 553 atmrm.chapt05.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint architecture page 397 of 553 sonet framer core refer to npbus control register to access registers in this section. gppint architecture the general purpose processor interface (gppint) provides direct access to registers located in the gppint module, but delayed access to registers and counters located in the gpphandler modules of the various chiplets of the sonet core. gppint controls the handshaking with the external microprocessor as well as the handshaking with the gpphandlers at the asynchronous chiplet interfaces. address decoding is done to the chiplet level in gppint. in addition, addresses are decoded to the register level for the local gppint registers. reset register each chiplet is controlled by one reset bit. at power-on, all reset bits are active and the chiplets disabled. they can be released by the general purpose processor (gpp) only after all global configuration parameters have been set and the clocks to the chiplets have been established. in addition, there are reset bits for the chiplets that do not have their own gpphandler. interrupt registers the interrupt register is used as a pointer to the chiplet interrupt registers with pending requests, the clock status error register and the handshaking error register. an active bit of the interrupt register is reset by removing the cause for the request in the corresponding chiplet or by masking the active irq bit(s) in the chiplet; therefore, the interrupt registers (including the pointer) are read-only. all interrupt and pointer regis- ters have a corresponding mask register (r/w). every un-masked, active interrupt bit causes an active pointer bit. every un-masked, active pointer bit causes activation of the interrupt signal to the microprocessor. framr chiplet address mapping chiplet name short name chiplet base address chiplet address range number of bytes reserved x?000? x?000 - 0ff? 256 ach_tx ht x?100? x?100 - 1ff? 256 ach_rx hr x?200 ? x?200 - 2ff ? 256 reserved x?300 ? x?300 - 3ff ? 256 ofp_tx ot x?400 ? x?400 - 7ff ? 1024 ofp_rx or x?800 ? x?800 - bff ? 1024 gppint gp x?c00 ? x?c00 - cff? 256 reserved x?d00 ? x?d00 - fff ? 768 IBM2520L8767 ibm processor for atm resources gppint architecture page 398 of 553 atmrm.chapt06.01 08/27/99 handshaking error registers each bit of the handshaking error registers indicates a locked interface to one of the chiplet gpphandlers. two additional bits indicate various timeout events. to reset an individual bit of the handshaking error regis- ter, the cause for the request must be removed and a ?1? must be written into the bit location of the register (r/w). reading the register will reset the whole (eight bit) register if the corresponding "clear-register" option is set in the configuration register. the handshaking error indication register has a corresponding mask register (r/w). every un-masked, active handshaking error bit causes activation of the pointer bit in the gppint interrupt register. clock monitor status registers the clock monitor status register bits indicate the loss of a specific chiplet?s clock. they are set whenever a difference between the clock test signal and the individual chiplet clock acknowledge signal occurs after one clock monitor test period. to reset an individual bit of the clock monitor status registers, the clock of the corre- sponding chiplet must be restored and a ?1? must be written into the bit location of the register (r/w). reading one of the registers will reset the whole (eight bit) register if the corresponding "clear-register" option is set in the configuration register. the clock monitor status register has corresponding mask register (r/w). every un-masked, active clock monitor status bit causes activation of the pointer bit in the gppint register. local gppint configuration registers there are registers (r/w) for the clock monitor test period, the watchdog timer period and the "clear-regis- ter" option. a read-only register provides the vital product data (vpd). global static configuration registers these are configuration parameters that are shared by many chiplets or that are needed by chiplets that have no gpphandler. the initial values can be modified by the microprocessor after power-on, but should not be changed later on. all global static configuration registers are r/w. status registers these registers provide status information from chiplets that have no gpphandler and are read-only. presently, there is only one status register for the sim chiplet (pll lock status). IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint architecture page 399 of 553 gppint chiplet address mapping overview: base address = x?c00 register name description (all registers are of 8-bit width) address offset type initial value resgp1 reset register x?00? r/w ?11111111? ... reserved x?01 - 0f? irqgp1 chiplet interrupt request register #1 x?10? r ?00000000? ... reserved x?11 - 17? irmgp1 chiplet interrupt mask register #1 x?18? r/w ?00000000? ... reserved x?19 - 1f? hshake1 handshaking error register #1 x?20? r/w ?00000000? ... reserved x?21 - 27? hsmask1 handshaking error mask register #1 x?28? r/w ?00000000? ... reserved x?29 - 2f? clkstat1 clock status register #1 x?30? r/w ?00000000? ... reserved x?31 - 37? clkmask1 clock status mask register #1 x?38? r/w ?00000000? ... reserved x?39 - 47? cmongp1 clock monitor test period x?48? r/w ?00000000? wdtgp1 watchdog timer period x?49? r/w ?11111111? confgp1 "clear-register" option register x?4a? r/w ?11111111? ... reserved x?4b - 4f? vmd vital macro data register x?50? r ?10000001? ... reserved x?51 - 57? gatmcs common atm/cs static configuration register x?58? r/w ?00000000? gcasc common cascading static configuration register x?59? r/w ?10101010? glooptx transmit loopback static configuration register x?5a? r/w ?00000000? glooprx receive loopback static configuration register x?5b? r/w ?00000000? gextres external clock recovery circuit reset register x?5c? r/w ?00000000? ... reserved x?5d - 67? ofptxgp ofp_tx static configuration register x?68? r/w ?00000000? ofprxgp1 ofp_rx static configuration register #1 x?69? r/w ?00000000? ofprxgp2 ofp_rx static configuration register #2 x?6a? r/w ?00000000? ... reserved x?6b - 71? pimrconf2 pim_rx static configuration register #2 x?73? r/w ?00000000? ... reserved x?74 - 7e? simstat sim status register x?7f? r n.a. ... reserved x?80 - ff? IBM2520L8767 ibm processor for atm resources gppint register description page 400 of 553 atmrm.chapt06.01 08/27/99 22: gppint register description chiplet reset register (resgp) the bits of the chiplet reset register control the resetting (enabling / disabling) of complete chiplets. for each bit position, 0 = reset inactive for this chiplet, 1 = reset active (chiplet is disabled; default). length 8bit type read/write address c00 power on value x?ff? resht reshr resot resor txrpis rxrpis reserved 76543210 bit(s) name description 7 resht reset to chiplet ach_tx 6 reshr reset to chiplet ach_rx 5 resot reset to chiplet ofp_tx 4 resor reset to chiplet ofp_rx 3 txrpis reset to chiplet pis_tx 2 rxrpis reset to chiplet pis_rx 1-0 reserved reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 401 of 553 chiplet interrupt and mask registers (irqgp1, irmgp1) the chiplet interrupt request register indicates pending interrupt requests from individual chiplets. an active bit of this register is reset by removing the cause for the request in the corresponding chiplet or by masking the active irq bit(s) in the chiplet; therefore, this register is read-only. for each bit position for irqgp1: 0 = no chiplet interrupt request pending 1 = chiplet has pending interrupt request(s). the chiplet interrupt request mask register bits control the propagation of a chiplet interrupt request to the sonet macro interrupt output pin. the mask registers allow read and write access. for each bit position for irmgp1: 0 = the corresponding interrupt request bit is masked (default), 1 = the corresponding interrupt request bit is active (for irmgp1: the corresponding interrupt request bit activates the sonet macro interrupt). length 8bits 8bits type read read address irqgp1 c10 irmgp1 c18 power on value x?00? x?00? irqht irqhr irqot irqor reserved feioccs feiochs 76543210 bit(s) name description 7 irqht irq from ach_tx 6 irqhr irq from ach_rx 5 irqot irq from ofp_tx 4 irqor irq from ofp_rx 3-2 reserved reserved 1 feloccs pending clock status error active 0 felochs pending handshaking error active IBM2520L8767 ibm processor for atm resources gppint register description page 402 of 553 atmrm.chapt06.01 08/27/99 handshaking error indication and mask registers (hshake1, hsmask1) the local handshaking error indication register indicates pending handshaking error requests from the gppint chiplets. for each bit position for hshake1: 0 = normal operation of the corresponding chiplet 1 = the corresponding chiplet did not de-assert its dtack signal. exception: the signals toerror and interror (hshake2(1-0)) have the following meaning: 00 = normal operation 01 = gpp de-asserts strobes without waiting for dtack assertion 10 = watchdog timeout in rest state 11 = watchdog timeout in req state. an active bit of the handshaking error indication register is reset by removing the cause for the malfunctioning of the chiplet and by writing a one into the corresponding bit position. reading one register will reset all bits of this register if the "clear-register" option is set in confgp1(2). the handshaking error indication mask register bits control the propagation of the gppint handshaking error request of the register hshake1. hsmask1 controls propagation to the signal felochs (bit 0 of irqgp1 register). the mask registers allow read and write access. for each bit position in hsmask: 0 = the corresponding handshaking error indication bit is masked (default) 1 = the corresponding request bit is active (for hsmask1, the corresponding request bit activates signal felochs (bit 0 of irqgp1 register)). "clear-register" option set in confgp1(2). IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 403 of 553 length 8bits type read/write address hshake1 c20 hsmask c28 power on value x?00? dtack from ach_tx dtack from ach_rx dtack from ofp_tx dtack from ofp_rx reserved toerror interror 76543210 bit(s) name description 7 dtack from ach_tx stuck at one 6 dtack from ach_rx stuck at one 5 dtack from ofp_tx stuck at one 4 dtack from ofp_rx stuck at one 3-2 reserved reserved 1 toerror time out error of the gpp interface (see above) 0 interror gpp interface error (see above) IBM2520L8767 ibm processor for atm resources gppint register description page 404 of 553 atmrm.chapt06.01 08/27/99 clock monitor status and mask registers (clkstat1, clkmask1) the clock monitor status register bits indicate the loss of a specific island?s clock. they are set whenever a difference between the clock test signal and the individual island?s clock acknowledge signal occurs after the clock monitor test period. for each bit position in clkstat1: 0 = normal operation of the corresponding clock island 1 = the corresponding island clock is lost. an active bit of this register is reset by restoring the clock of the corresponding clock island and by writing a one into the corresponding bit position. reading one register will reset all bits of this register if the "clear-register" option is set in bit confgp1(3). the clock monitor mask register clkmask1 controls the propagation of active clock monitor status signals. clkmask1 controls propagation to the signal feloccs (bit 1 of irqgp1 register). the mask registers allow read and write access. for each bit position in clkmask1: 0 = the corresponding clock status bit is masked (default) 1 = the corresponding clock status bit is active (for clkmask1: the corresponding bit activates the signal feloccs (bit 6 of irqgp1 register)). length 8bits type read/write address clkstat1 c30 clkmask1 c38 power on value x?00? island ach_tx island ach_rx island ofp_tx island ofp_rx reserved 76543210 bit(s) description 7 island ach_tx lost clock 6 island ach_rx lost clock 5 island ofp_tx lost clock 4 island ofp_rx lost clock 3-0 reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 405 of 553 clock monitor test period register (cmongp1) divider ratio to derive the clock monitor test period from the gppclk clock. clock monitoring is disabled if equal x?00? (default). watchdog timer period register (wdtgp1) divider ratio to derive the interface timeout period from the gppclk clock. this register is reset to x?ff? whenever a timeout occurs; it has to be reconfigured by a gpp write access. length 8bits type read/write address c48 power on value x?00? cmongp1 76543210 bit(s) name description 7-0 cmongp1(7-0) number of gppclk cycles/test period length 8bits type read/write address c49 power on value x?ff? wdtgp1 76543210 bit(s) name description 7-0 wdtgp1(7-0) number of gppclk clock cycles per timeout period IBM2520L8767 ibm processor for atm resources gppint register description page 406 of 553 atmrm.chapt06.01 08/27/99 gppint local configuration registers (confgp1) the bits of this local configuration register control the resetting of complete registers upon read access ("clear register" option). for each bit position0 = no action upon read access, 1 = the corresponding register is reset upon read access (default). length 8bits type read/write address c4a power on value x?ff? reserved clkstat1 & clkstat2 hshake1 & hshake2 simstat reserved 76543210 bit(s) name description 7-4 reserved reserved 3 clear-bit for registers clkstat1 & clkstat2 2 clear-bit for registers hshake1 & hshake2 1 clear-bit for register simstat 0 reserved reserved IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 407 of 553 vital macro data register (vpd) this read-only register displays the macro identification. static configuration register (gatmcs) common static configuration data, providing control signals that are distributed to multiple chiplets. set once by the gpp before the individual chiplets get enabled and not changing during normal operation. length 8bits type read address c50 power on value x?01? macro type version number 76543210 bit(s) description 7-5 macro type (000) 4-0 version number length 8bits type read/write address c58 power on value x?00? reserved gatmcsrx reserved gatmcstx 76543210 bit(s) name description 7-5 reserved reserved 4 gatmcsrx atm cell or cs mode for sdh macro in receive direction: 0 sdhmacroinatmmode 1 sdhmacroincsmode 3-1 reserved reserved 0 gatmcstx atm cell or cs mode for sdh macro in transmit direction: 0 sdhmacroinatmmode, 1 sdhmacroincsmode IBM2520L8767 ibm processor for atm resources gppint register description page 408 of 553 atmrm.chapt06.01 08/27/99 gcasc glooptx transmit loopback control. for each bit position, 0 = ach loopback disabled (default), 1 = ach loopback enabled. length 8bits type read/write address c59 power on value x?88? gcascrx gcasctx 76543210 bit(s) name description 7-4 gcascrx(7-4) defines sdh macros in receive direction 0001 sts3c 1000 stm1 others => reserved 3-0 gcasctx(7-4) defines sdh macros in transmit direction 0001 sts3c 1000 stm1 others => reserved length 8bits type read/write address c5a power on value x?00? reserved txlpb2 reserved txlpb1 76543210 bit(s) name description 7-5 reserved reserved 4 txlpb2 loopback #2 control, tx macro 3-1 reserved reserved 0 txlpb1 loopback #1 control, tx macro IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 409 of 553 glooprx receive loopback control. for each bit position, 0 = ach loopback disabled (default), 1 = ach loopback enabled. gextres external clock recovery circuit reset signal. delivered to external circuit (deserializer) via device pins. the active level depends on the external circuit used. default value at power-on-reset is low. length 8bits type read/write address c5b power on value x?00? reserved rxlpb2 76543210 bit(s) name description 7-1 reserved reserved 0 rxlpb2 loopback #2 control, rx macro length 8bits type read/write address c5c power on value x?00? reserved rstcrec 76543210 bit(s) name description 7-1 reserved reserved 0 rstcrec external recovery reset IBM2520L8767 ibm processor for atm resources gppint register description page 410 of 553 atmrm.chapt06.01 08/27/99 ofptxgp static configuration data, providing control signals for chiplet ofp_tx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. ofprxgp1 length 8bits type read/write address c68 power on value x?00? reserved ptrproc reserved cdhc1tx 76543210 bit(s) name description 7-5 reserved reserved 4 ptrproc 0 au pointer processing disabled in atm mode 1 au pointer processing enabled in atm mode 3-1 reserved reserved 0 sdhc1tx 0 c1 byte replaced by section trace j1 byte (itu-t standard) 1 old numbering scheme is used ofprxgp1 & 2 : static configuration data, providing control signals for chiplets ofp_rx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. length 8bits type read/write address c69 power on value x?00? reserved sdhc1rx 76543210 bit(s) name description 7-1 reserved reserved 0 sdhc1rx 0 the new (itu-t standard) numbering scheme is used 1 old numbering scheme is used IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gppint register description page 411 of 553 ofprxgp2 pimrconf2 static configuration data, providing control signals for chiplets pim_tx/pim_rx. set once by the gpp before the individual chiplets are enabled and not changing during normal operation. length 8bits type read/write address c6a power on value x?00? reserved a2frm 76543210 bit(s) name description 7-2 reserved reserved 1-0 a2frm ofp_rx rxsofrm assertion controls 00 rxsofrm asserted during 3rd a2 byte 01 rxsofrm asserted during 1st a2 byte 10 rxsofrm asserted during 2nd a2 byte 11 rxsofrm asserted during 3rd a2 byte length 8bits type read/write address c73 power on value x?00? reserved algo1 76543210 bit(s) name description 7-2 reserved reserved 1-0 algo1(7-6) selects frame pattern recognition algorithm: 00 all bits checked maximum 4 bad frames 01 12 bits checked only maximum 4 bad frames 10 all bits checked maximum 5 bad frames 11 12 bits checked only. maximum 5 bad frames IBM2520L8767 ibm processor for atm resources gppint register description page 412 of 553 atmrm.chapt06.01 08/27/99 simstat status register, providing the gpp with information from the sim chiplet via pim. either sim-internal or exter- nal pll lock status. "clear-register" option set in confgp1(1). length 8bits type read address c7f power on value n/a reserved rx_lock 76543210 bit(s) name description 7-1 reserved reserved 0 rx_lock 0 rx pll is still in phase aquisition process 1 rx pll is enabled and has locked to the incoming data stream incoming data stream IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 gpphandler architecture page 413 of 553 23: gpphandler architecture all gpp handlers for the various chiplets have the following general register structure. counter registers every counter has an enable bit in the counter enable register (addr 2 or 3), and optionally up to two program- mable thresholds. each counter has an interrupt bit for overflow and up to two interrupt bits for threshold crossing in the counter interrupt registers. for all counters in one handler there is one common read on the fly register?, that is used to store the higher order bytes to obtain a correct readback value for counter larger than eight bits. counters are read only registers, the count enable registers are read / write. note on counter reading: independent of the counter length, given that a counter has address n as base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no influence on the counter but reading address n-1 will reset the counter after the read. reading address n or n-1 will always latch the higher order bytes into the read on the fly register (before the optional automatic reset). counters can only be read and not written to. for a 16-bit counter the most significant byte should be read from rofmid (address 0). for a 24-bit counter, the most significant byte is read from rofhi (address 1), the next byte from rofmid (address 0). to completely read a 24-bit counter: first read least significant byte from counter address n or n-1, followed by reading rofmid and rofhi (address 0; address 1). reset registers each handler has a two bit reset register. bit zero is the chiplet reset control. this bit is active high after power on reset, causing the chiplet to be disabled. bit one is the chiplet halt signal, which for selected chiplets freezes the state machines for diagnostic purposes. this is a read / write register. command registers the optional command register(s) will generate events to the chiplet. when a bit is written high by the micro- processor, it will remain high for one chiplet clock cycle. therefore, reading back a command register will always read back zeros. this is a read / write register. gpphandler architecture address range register function x?0 - 1? read on the fly registers x?2 - 3? counter enable registers x?4 - 2f? counters and counter threshold registers x?30? reset register x?31 - 32? command registers x?33 - 37? event latch registers (was called status) x?38 - 47? interrupt registers (addr=int reg, addr-1=int mask reg) x?48 - 57? configuration registers IBM2520L8767 ibm processor for atm resources gpphandler architecture page 414 of 553 atmrm.chapt06.01 08/27/99 event latch registers the optional event latch register(s) remember one ore more occurrences of events that happen in a chiplet. this may be considered as a one-bit saturating counter. each bit in the register corresponds to an event in the chiplet. such bits remain high after the event happened until the microprocessor implicitly or explicitly resets the bit. this is configurable: implicit reset is done by writing a high value to the bit that is to be reset. explicit will reset all bits of one register when the register is read. this is a read / write register. interrupt registers when there are counters, user interrupts or fatal bits in a chiplet, a main interrupt register will be present. bit zero always is the fatal interrupt bit, which is set as soon as any of the fatal interrupt events occur. the other bits refer to counters or user interrupt registers, to allow easy determination of the interrupt cause. each interrupt register has an interrupt mask register to enable or disable interrupt. after power on reset, interrupts are disabled. the interrupt registers are the same as the event latch registers, with the addition that when an interrupt register bit is set, and the corresponding mask register bit is set, the interrupt signal to the gppint chiplet is activated. the same mechanism to reset the interrupt register bits is used as for the event latch registers. the interrupt mask registers are only changed by the microprocessor. the interrupt and interrupt mask registers are read / write. configuration registers these registers are programmed by the microprocessor with setup information, and are read/write. the first configuration register reserves bit one and seven to configure explicit or implicit reset of the event latch regis- ters and interrupt registers respectively (when such registers are present). f read-on-the-fly register (auto-generated) n counter register r reset register i interrupt register (auto-generated) c configuration register x control or mask register (auto-generated) s status (event latch) register o command register IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 415 of 553 atm cell handler architecture: transmit direction ach_tx gpp handler address mapping base address = x?100 register name description address offset type width initial value rofmid read-on-the-fly register x?0? f 8 ?00000000? rofhi read-on-the-fly register (msbyte) x?1? f 8 ?00000000? cnten1 count enable register x?2? x 3 ?000? acbc cell counter (read from external fifo),no threshold (2) x?4/5? * n 24 ?x?000000?? iuc idle/unassigned cell counter, no threshold (2) x?6/7?* n 24 ?x?000000?? acbe corrupted cell error counter (2) x?8/9? * n 8 ?00000000? acbeth11 threshold register for counter acbe x?a? x 8 ?10000000? reset default reset register x?30? r 2 ?01? stat1 status register #1 x?33? s 8 iucstat1 status register #2 x?34? s 2 mainirq main interrupt register x?38? i 2 m_mainirq int mask register (for mainirq) x?39? x 2 ?00? cntrirq1 counter interrupt register x?3a? i 4 m_cntrirq1 int mask register (for cntrirq1) x?3b? x 4 ?0000? celltenable chiplet cofiguration register x?48? c 6 ?001111? acbtxthrpae programmable almost empty threshold x?49? c 7 ?0001110? headerbyte1 iu-cell header byte 1 (1) x?4a? c 8 ?00000000? headerbyte2 iu-cell header byte 2 (1) x?4b? c 8 ?00000000? headerbyte3 iu-cell header byte 3 (1) x?4c? c 8 ?00000000? headerbyte4 iu-cell header byte 4 (1) x?4d? c 8 ?00000001? headerbyte5 iu-cell header byte 5 (1) x?4e? c 8 ?01010010? payloadbyte iu-cell payload byte x?4f? c 8 ?01101010? hecenctrl hec processing control x?50? c 7 ?0001100? hecoffset hec offset pattern register x?51? c 8 ?01010101? hecmaskand hec error corruption mask (and) x?52? c 8 ?11111111? hecmaskor hec error corruption mask (or) x?53? c 8 ?00000000? sdbtxthrpaf programmable almost full threshold x?54? c 6 ?110000? 1. defaults according itu i.432 2. meaning of counter address marked as (*) independant of the counter width, given that a counter has chiplet address n as a base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no effect on the counter but reading address n-1 resets the counter after read operation IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 416 of 553 atmrm.chapt06.01 08/27/99 counter registers rofmid read-on-the-fly register. middle significant byte rofhi read-on-the-fly register. most significant byte length 8bits type read address 100 power on value x?00? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register middle significant byte length 8bits type read address 101 power on value x?00? rofhi 76543210 bit(s) name description 7-0 rofhi(7-0) read-on-the-fly register most significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 417 of 553 acbc number of cells read from external fifo (24-bit counter). overflow leads to an interrupt request. iuc number of transmitted idle and unassigned cells (24-bit counter). overflow leads to an interrupt request. length 8bits type read address 104/105 power on value x?00? acbc(16:23) 76543210 bit(s) name description 7-0 acbc(16:23) external fifo cell counter least significant byte length 8bits type read address 106/107 power on value x?00? iuc(16:23) 76543210 bit(s) name description 7-0 iuc(16:23) idle/unassigned cell counter least significant byte IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 418 of 553 atmrm.chapt06.01 08/27/99 acbe number of errors (corrupted cell read from external fifo). eight-bit counter overflow leads to an interrupt request. acbeth11- threshold for number of errors. threshold overstep leads to an interrupt request. length 8bits type read address 108/109 power on value x?00? acbe 76543210 bit(s) name description 7-0 acbe(7-0) external fifo error counter length 8bits type read/write address 10a power on value x?80? acbeth11 76543210 bit(s) name description 7-0 acbeth11(7-0) threshold for error counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 419 of 553 cnten1 counter on/off control register for ach_tx. for each bit position, 0 = counter is disabled, 1 = counter is enabled. reset register (reset) reset / halt chiplet control register. this register is automatically preset to the default value by the reset signal resht from the gppint. for each bit position, 0 = reset/halt not active, 1 = reset/halt active. length 8bits type read/write address 102 power on value x?00? reserved en-acbe en-icu en-acbc 76543210 bit(s) name description 7-3 reserved reserved 2 en-acbe error counter enable 1 en-iuc idle/unassigned cell counter enable 0 en-acbc cell counter enable length 8bits type read/write address 130 power on value x?01? reserved halt ach_tx reset ach_tx 76543210 bit(s) name description 7-2 reserved reserved 1 halt (freeze) ach_tx chiplet 0 reset (disable) ach_tx chiplet IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 420 of 553 atmrm.chapt06.01 08/27/99 status registers stat1 status register #1 of this chiplet. this is an event latch register. length 8bits type read/write address 133 power on value - rxlpb2fe txlpb2fe txlpb1fe cellgenstatus sdbtxpaf sdbtxff acbtxpae acbtxef 76543210 bit(s) name description 7 rxlpb2fe rx loopback #2 configuration mismatch 6 txlpb2fe tx loopback #2 configuration mismatch 5 txlpb1fe tx loopback #1 configuration mismatch 4 cellgenstatus 0 idle/unassigned cell is transmitted 1 cell from external fifo is transmitted 3 sdbtxpaf programmable almost full flag from sdb_tx 2 sdbtxff fifo full flag from sdb_tx 1 acbtxpae programmable almost empty flag from external transmit fifo 0 acbtxef fifo empty flag from external transmit fifo IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 421 of 553 iucstat1 status register #2 of this chiplet. this is an event latch register. interrupt request and mask registers mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 134 power on value - reserved iucferr 76543210 bit(s) name description 7-1 reserved reserved 0 iucferr unexpected state transition in fsm length 8bits type read/write address 138 power on value - reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 422 of 553 atmrm.chapt06.01 08/27/99 m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates signal irqht1 to gppint. cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 139 power on value x?00? reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred length 8bits type read/write address 13a power on value - reserved th-acbe ov-acbe ov-iuc ov-acbc 76543210 bit(s) name description 7-4 reserved reserved 3 th-acbe threshold overstep error counter 2 ov-acbe overflow error counter 1 ov-iuc overflow idle/unassigned cell counter 0 ov-acbc overflow cell counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 423 of 553 m_cntrirq1 register to mask pending counter interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates the pointer bit in mainirq reg. configuration registers celltenable register to control various modes of operation of this chiplet. length 8bits type read/write address 13b power on value x?00? reserved th-acbe ov-acbe ov-iuc ov-acbc 76543210 bit(s) name description 7-4 reserved reserved 3 th-acbe threshold overstep error counter 2 ov-acbe overflow error counter 1 ov-iuc overflow idle/unassigned cell counter 0 ov-acbc overflow cell counter length 8bits type read/write address 148 power on value x?0f? reserved txlpb1only txlpb2only iucenable acbenable autrst_sta autrst_int 76543210 bit(s) name description 7-6 reserved reserved IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 424 of 553 atmrm.chapt06.01 08/27/99 5 txlpb1only 0 on the fly monitoring (lpb #1) 1 loopback #1 only 4 txlpb2only 0 on the fly monitoring (lpb #2) 1 loopback #2 only 3 iucenable 0 generation of iuc disabled 1 generation of iuc enabled 2 acbenable 0 external fifo read disabled 1 external fifo read enabled 1 autrst_sta 0 no action on read access 1 auto-reset status registers upon read access 0 autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access bit(s) name description IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 425 of 553 acbtxthrpae threshold for programmable almost empty flag of external fifo in transmit direction. sdbtxthrpaf threshold for programmable almost full flag (sdb_tx). length 8bits type read/write address 149 power on value x?0e? reserved acbtxthrpae 76543210 bit(s) name description 7 reserved reserved 6-0 acbtxthrpae(7-1) threshold for pae flag length 8bits type read/write address 154 power on value x?30? reserved sdbtxthrpaf 76543210 bit(s) name description 7-6 reserved reserved 5-0 sdbtxthrpaf(7-2) threshold for paf flag IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 426 of 553 atmrm.chapt06.01 08/27/99 headerbyte1 idle/unassigned cell header byte #1. default pattern according to itu i.432. headerbyte2 idle/unassigned cell header byte #2. default pattern according to itu i.432. length 8bits type read/write address 14a power on value x?00? headerbyte1 76543210 bit(s) name description 7-0 headerbyte1(7-0) iu-cell header byte #1 length 8bits type read/write address 14b power on value x?00? headerbyte2 76543210 bit(s) name description 7-0 headerbyte2(7-0) iu-cell header byte #2 IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 427 of 553 headerbyte3 idle/unassigned cell header byte #3. default pattern according to itu i.432. headerbyte4 idle/unassigned cell header byte #4. default pattern according to itu i.432. length 8bits type read/write address 14c power on value x?00? headerbyte3 76543210 bit(s) name description 7-0 headerbyte3(7-0) iu-cell header byte #3 length 8bits type read/write address 14d power on value x?01? headerbyte4 76543210 bit(s) name description 7-0 headerbyte4(7-0) iu-cell header byte #4 IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 428 of 553 atmrm.chapt06.01 08/27/99 headerbyte5 idle/unassigned cell header byte #5. default pattern according to itu i.432. pay l oa d b yt e idle/unassigned cell payload byte. length 8bits type read/write address 14e power on value x?52? headerbyte5 76543210 bit(s) name description 7-0 headerbyte5(7-0) iu-cell header byte #5 length 8bits type read/write address 14f power on value x?6a? payloadbyte 76543210 bit(s) name description 7-0 payloadbyte(7-0) iu-cell payload byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 429 of 553 hecenctrl hec processing control configuration register. length 8bits type read/write address 150 power on value x?0c? reserved payload byte control screnable hecenable heccntludf2 76543210 bit(s) name description 7 reserved 6-4 payload byte control 000 each payload byte is the same (default) 001 increment payload byte for each atm cell, start with default after reset 010 increment each payload byte of a cell, start each cell with default byte 011 increment each pl byte of a cell, cross cell boundaries, start first cell after reset with default byte 1xx each payload byte is the same 3 scre-enable 0 => atm cell payload scrambling disabled 1 => atm cell payload scrambling enabled 2 hecenable 0 => hec calculation/manipulation disabled 1 => hec calculation/manipulation enabled 1-0 heccntludf2 mode of final hec manipulation by udf1 byte after hecoffset, hecmaskand, hecmaskor operations: 00 no manipulation 01 hec xor udf1 10 hec and udf1 11 hec or udf1 IBM2520L8767 ibm processor for atm resources atm cell handler architecture: transmit direction page 430 of 553 atmrm.chapt06.01 08/27/99 hecoffset hec offset pattern register for the byte pattern used in the atm cell header hec calculation as base offset according to itu i.432. hecmaskand hec mask pattern register for the byte pattern used in the atm cell header hec calculation as dedicated (anding) hec error corruption mask. length 8bits type read/write address 151 power on value x?55? hecoffset 76543210 bit(s) name description 7-0 hecoffset(7-0) hec offset pattern length 8bits type read/write address 152 power on value x?ff? hecmaskand 76543210 bit(s) name description 7-0 hecmaskand(7-0) hec error corruption mask (and) IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: transmit direction page 431 of 553 hecmaskor hec mask pattern register for the byte pattern used in the atm cell header hec calculation as dedicated (oring) hec error corruption mask. length 8bits type read/write address 153 power on value x?00? hecmaskor 76543210 bit(s) name description 7-0 hecmaskor(7-0) hec error corruption mask (or) IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 432 of 553 atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction ach_rx gpp handler address mapping base address = x?200 register name description address offset type width initial value rofmid read-on-the-fly register x?0? f 8 ?00000000? rofhi read-on-the-fly register (msbyte) x?1? f 8 ?00000000? cnten1 count enable register x?2? x 4 ?0000? fhr counter, atm cells written into external fifo, no threshold x?4/5? * n 24 ?x?000000?? ihr counter, received idle cells from ofp, no threshold x?6/7? * n 24 ?x?000000?? ehr1 counter, detected hec errors with threshold x?8/9? * n 16 ?x?0000?? ehr1th12 threshold reg byte2 (lsbyte) for counter ehr1 x?a? x 8 ?00000001? ehr1th11 threshold reg byte1 for counter ehr1 x?b? x 8 ?10000000? bhr counter, fifo full discarded cells: (discpaf1=1) and (txlpb11=0) with threshold. 2 x?c/d? * n 16 ?x?0000?? bhrth12 threshold reg byte2 (lsbyte) for counter bhr x?e? x 8 ?00000001? bhrth11 threshold register byte1 for counter bhr x?f? x 8 ?10000000? reset default reset register x?30? r 2 ?01? cmd1 command register (fifo reset) x?31? o 2 ?00? stat1 status register x?33? s 6 mainirq main interrupt register x?38? i 2 m_mainirq interrupt mask register (for mainirq) x?39? x 2 ?00? cntrirq1 counter interrupt register x?3a? i 6 m_cntrirq1 interrupt mask register (for cntrirq1) x?3b? x 6 ?000000? conf5 chiplet configuration register x?48? c 8 ?00000011? conf6 chiplet configuration register (alpha/delta) x?49? c 8 ?01100101? h1conf 1 x?4a? c 8 ?00000000? h2conf 1 x?4b? c 8 ?00000000? h3conf 1 x?4c? c 8 ?00000000? h4conf 1 x?4d? c 8 ?00000001? h5conf dummy byte to align payload in external fifo x?4e? c 8 ?11010000? confc external fifo buffer almost full threshold x?4f? c 7 ?1100000? 1. confirmation bytes to identify idle or unassigned cells. 2. meaning of counter address marked as (*) independant of the counter width, given that a counter has chiplet address n as a base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no effect on the counter but reading address n-1 resets the counter after read operation. IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 433 of 553 counter registers rofmid read-on-the-fly registers. middle significant byte. rofhi read-on-the-fly registers. most significant byte. length 8bits type read address 200 power on value x?00? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register middle significant byte length 8bits type read address 201 power on value x?00? rofhi 76543210 bit(s) name description 7-0 rofhi(7-0) read-on-the-fly register most significant byte IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 434 of 553 atmrm.chapt06.01 08/27/99 fhr number of atm cells written into external fifo (24 bit counter). overflow leads to an interrupt request. ihr number of idle cells received from ofp_rx (24 bit counter). overflow leads to an interrupt request. length 8bits type read address 204/205 power on value x?00? fhr (16:23) 76543210 bit(s) name description 7-0 fhr(16:23) atm cell counter least significant byte length 8bits type read address 206/207 power on value x?00? ihr (16:23) 76543210 bit(s) name description 7-0 ihr(16:23) idle/unassigned cell counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 435 of 553 ehr1 number of detected hec errors (16-bit counter). overflow leads to an interrupt request. ehr1th11 threshold for number of hec cells (most significant byte). length 8bits type read address 208/209 power on value x?00? ehr1 (8:15) 76543210 bit(s) name description 7-0 ehr1(8:15) hec error counter least significant byte length 8bits type read/write address 20b power on value x?80? ehr1th11 76543210 bit(s) name description 7-0 ehr1th11(7-0) threshold for hec error counter most significant byte IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 436 of 553 atmrm.chapt06.01 08/27/99 eht1th12 threshold for number of hec errors (least significant byte). threshold overstep leads to an interrupt request. bhr number of discarded cells because of fifo full condition (16 bit counter). overflow leads to an interrupt request. length 8bits type read/write address 207 power on value x?01? ehr1th12 76543210 bit(s) name description 7-0 ehr1th12(7-0) threshold for hec error counter least significant byte length 8bits type read address 20c/20d power on value x?00? bhr (8:15) 76543210 bit(s) name description 7-0 bhr(8:15) discarded cell counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 437 of 553 bhrth11 threshold for number of discarded cells (most significant byte). bhrth12 threshold for number of discarded cells (least significant byte) threshold overstep leads to an interrupt request. length 8bits type read/write address 20f power on value x?80? bhrth11 76543210 bit(s) name description 7-0 bhrth11(7-0) threshold for discarded cell counter, most significant byte length 8bits type read/write address 20e power on value x?01? bhrth12 76543210 bit(s) name description 7-0 bhrth12(7-0) threshold for discarded cell counter, least significant byte IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 438 of 553 atmrm.chapt06.01 08/27/99 cnten1 counter on/off control register for ach_rx. for each bit position, 0 =counter is disabled, 1 = counter is enabled. reset register (reset) reset / halt chiplet control register. this register is automatically preset to the default value by the reset signal reshr from the gppint. for each bit position, 0 = reset/halt not active, 1 = reset/halt active. length 8bits type read/write address 202 power on value x?00? reserved en-bhr en-ehr1 en-ihr en-fhr 76543210 bit(s) name description 7-4 reserved reserved 3 en-bhr discarded cell counter enable 2 en-ehr1 hec error counter enable 1 en-ihr idle cell counter enable 0 en-fhr atm cell counter enable length 8bits type read/write address 230 power on value x?01? reserved halt ach_rx reset ach_rx 76543210 bit(s) name description 7-2 reserved reserved 1 halt (freeze) ach_rx chiplet 0 reset (disable) ach_rx chiplet IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 439 of 553 command register (cmd1) command register for this chiplet. single-cycle active if ?1? is written into bit position. length 8bits type read/write address 231 power on value x?00? reserved acbfifo sdbfifo 76543210 bit(s) name description 7-2 reserved 1 acbfifo reset external fifo 0 sdbfifo reset sdb_rx fifo IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 440 of 553 atmrm.chapt06.01 08/27/99 status register (stat1) status register of this chiplet. this is an event latch register. length 8bits type read/write address 233 power on value - reserved celldelo rdflagef wrflagpaf wrflagff 76543210 bit(s) name description 7-6 reserved 5-3 celldelo state of the cell delineation process: 000 reset state 001 hunt state 010 presync state 100 sync state 2 rdflagef sdb fifo: read fifo empty flag 1 wrflagpaf external fifo: write fifo programmable almost full flag 0 wrflagff external fifo: write fifo full flag IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 441 of 553 interrupt request and mask registers mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position, 0 = no interrupt request pending,1 = interrupt request pending m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates signal irqhr1 to gppint. length 8bits type read/write address 238 power on value - reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred length 8bits type read/write address 239 power on value x?00? reserved cntrirq1 fatal 76543210 bit(s) name description 7-2 reserved reserved 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 442 of 553 atmrm.chapt06.01 08/27/99 cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 240 power on value - reserved th-bhr ov-bhr th-ehr1 ov-ehr1 ov-ihr ov-fhr 76543210 bit(s) name description 7-6 reserved reserved 5 th-bhr threshold overstep discarded cell counter 4 ov-bhr overflow discarded cell counter 3 th-ehr1 threshold overstep hec error counter 2 ov-ehr1 overflow hec error counter 1 ov-ihr overflow idle cell counter 0 ov-fhr overflow atm cell counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 443 of 553 m_cntrirq1 register to mask pending counter interrupt requests for each bit position, 0 = the corresponding pending request bit is masked (default) 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 241 power on value x?00? reserved th-bhr ov-bhr th-ehr1 ov-ehr1 ov-ihr ov-fhr 76543210 bit(s) name description 7-6 reserved reserved 5 th-bhr threshold overstep discarded cell counter 4 ov-bhr overflow discarded cell counter 3 th-ehr1 threshold overstep hec error counter 2 ov-ehr1 overflow hec error counter 1 ov-ihr overflow idle cell counter 0 ov-fhr overflow atm cell counter IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 444 of 553 atmrm.chapt06.01 08/27/99 configuration registers conf5 register to control various modes of operation of this chiplet. length 8bits type read/write address 248 power on value x?03? detstrtoc nwrtofifo notdethecer wrtchece ndescramb wridlec autrst_sta autrst_int 76543210 no action on read access name description 7detstrtoc 0 do not detect start of cell 1 detect start of cell 6 nwrtofifo 0 write into acb fifo 1 do not write into acb fifo; all received cells are discarded 5notdethecer 0 detect atm cell with hec errors 1 do not detect atm cell with hec errors 4 wrtchece 0 do not write atm cell with hec errors 1 write atm cell with hec errors 3 ndescramb 0 de-scramble atm cell payload 1 do not de-scramble atm cell payload 2wridlec 0 do not write idle cell into external fifo 1 write idle cell into acb fifo 1autrst_sta 0 noactiononreadaccess 1 auto-reset status register upon read access 0autrst_int 0 noactiononreadaccess 1 auto-reset interrupt request registers upon read access IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 445 of 553 conf6 register to control atm cell synchronization in this chiplet. confc threshold for programmable almost full flag of the external fifo. length 8bits type read/write address 249 power on value x?65? alpha delta 76543210 bit(s) name description 7-4 alpha(7-4) required number of consecutive false hec detected to return from sync to hunt state 3-0 delta(7-4) required number of consecutive good hec detected to jump from presync to sync state length 8bits type read/write address 24f power on value x?60? reserved confc (7-1) 76543210 bit(s) name description 7 reserved reserved 6-0 confc(7-1) threshold for paf flag headerbyte1/2/3/4/5 : idle/unassigned cell header bytes, default pat- tern according to itu i.432. IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 446 of 553 atmrm.chapt06.01 08/27/99 h1conf header pattern #1 to identify idle/unassigned cells. h2conf header pattern #2 to identify idle/unassigned cells. length 8bits type read/write address 24a power on value x?00? h1conf 76543210 bit(s) name description 7-0 h1conf(7-0) header byte #1 length 8bits type read/write address 24b power on value x?00? h2conf 76543210 bit(s) name description 7-0 h2conf(7-0) header byte #2 IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 atm cell handler architecture: receive direction page 447 of 553 h3conf header pattern #3 to identify idle/unassigned cells. h4conf header pattern #4 to identify idle/unassigned cells. length 8bits type read/write address 24c power on value x?00? h3conf 76543210 bit(s) name description 7-0 h3conf(7-0) header byte #3 length 8bits type read/write address 24d power on value x?01? h4conf 76543210 bit(s) name description 7-0 h4conf(7-0) header byte #4 IBM2520L8767 ibm processor for atm resources atm cell handler architecture: receive direction page 448 of 553 atmrm.chapt06.01 08/27/99 h5conf dummybytetoalignthepayloadintheacb_rxbuffer. length 8bits type read/write address 24e power on value x?d0? h5conf 76543210 bit(s) name description 7-0 h5conf(7-0) payload alignment byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 449 of 553 overhead frame processor architecture: transmit direction ofp_tx gpp handler address mapping base address = x?400 (page 1 of 3) register name description address offset type width initial value cnten1 count enable register x?2? x 4 ?0000? ptrinc pointer increment event counter (1) x?4/5? * n 8 ?00000000? no threshold n8 ptrdec pointer decrement event counter (1) x?6/7? * n 8 ?00000000? no threshold n8 nd_evcnt new data event counter, no threshold (1) x?8/9? * n 8 ?00000000? juscnt justification error counter (1) x?a/b? * n 8 ?00000000? withnothreshold n8 juscntth11 threshold register for counter juscnt x?c? x 8 ?10000000? reset default reset register x?30? r 2 ?01? cmd1 njus, pjus, ndf x?31? o 3 ?000? stat1 init, hug, mode(7-5) x?33? s 6 stat2 njus, pjus, ndf x?34? s 3 mainirq main interrupt register x?38? i 3 m_mainirq interrupt mask register (for mainirq) x?39? x 3 ?000? cntrirq1 counter interrupt register x?3a? i 5 m_cntrirq1 interrupt mask register (for cntrirq1) x?3b? x 5 ?00000? irq3 user interrupt register x?3c? i 6 m_irq3 interrupt mask register (for irq3) x?3d? x 6 ?000000? conf1 configuration register #1 (general a) x?48? c 8 ?00000011? conf2 configuration register #2 (general b) x?49? c 3 ?000? conf3 configuration register #3 x?4a? c 8 ?11111110? (fscr reload pattern) n 8 conf4 configuration register #4 (errmask) x?4b? c 8 ?00000000? conf5 configuration register #5 (erraddress) x?4c? c 8 ?00000000? conf6 configuration register #6 (fscr control) x?4d? c 8 ?00000001? conf7 configuration register #7 (dcc control) x?4e? c 4 ?0000? conf8 configuration register #8 (thrlow) x?4f? c 6 ?000011? conf9 configuration register #9 (thrnow) x?50? c 6 ?010001? conf10 configuration register #10 (thrhiw) x?51? c 6 ?100000? soh-a11 first a1 x?100? 8 soh-a12 second1 a1 x?101? 8 soh-a13 third a1 x?102? 8 soh-a21 first a2 x?103? 8 soh-a22 second a2 x?104? 8 soh-a23 third a2 x?105? 8 soh-j0 j0 x?106? 8 reserved for national use and not included in frame scrambling x?107-8? 8 soh-b1 b1 x?109? 8 IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 450 of 553 atmrm.chapt06.01 08/27/99 media dependant bytes x?10a-0b? 8 soh-e1 e1 x?10c? 8 media dependant byte x?10d? 8 reserved for future standardization x?10e? 8 soh-f1 f1 x?10f? 8 reserved for national use x?110-11? 8 soh-d1 d1 x?112? 8 media dependant bytes x?113-14? 8 soh-d2 d2 x?115? 8 media dependant byte x?116? 8 reserved for future standardization x?117? 8 soh-d3 d3 x?118? 8 reserved for future standardization x?119-1a? 8 soh-h1 h1 x?11b? 8 soh-j0 b?1001ss11? with s unspecified x?11c-1d? 8 soh-h2 h2 x?11e? 8 soh-1s x?ff? x?11f-20? 8 soh-h31 first h3 x?121? 8 soh-h32 second h3 x?122? 8 soh-h23 third h3 x?123? 8 soh-b21 first b2 x?124? 8 soh-b22 second b2 x?125? 8 soh-b23 third b2 x?126? 8 soh-k1 k1 x?127? 8 reserved for future standardization x?128-29? 8 soh-k2 k2 x?12a ? 8 reserved for future standardization x?12b-2c? 8 soh-d4 d4 x?12d? 8 reserved for future standardization x?12e-2f? 8 soh-d5 d5 x?130? 8 reserved for future standardization x?131-32? 8 soh-d6 d6 x?133? 8 reserved for future standardization x?134-35? 8 soh-d7 d7 x?136? 8 reserved for future standardization x?137-38? 8 soh-d8 d8 x?139? 8 reserved for future standardization x?13a-3b? 8 soh-d9 d9 x?13c? 8 reserved for future standardization x?13d-3e? 8 soh-d10 d10 x?13f? 8 reserved for future standardization x?140-41? 8 soh-d11 d11 x?142? 8 ofp_tx gpp handler address mapping base address = x?400 (page 2 of 3) register name description address offset type width initial value IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 451 of 553 reserved for future standardization x?143-44? 8 soh-d12 d12 x?145? 8 reserved for future standardization x?146-47? 8 soh-s1 s1 x?148? 8 soh-z11 reserved for future standardization x?149-4c? 8 soh-m1 m1 x?14d? 8 soh-m1 e2 x?14e? 8 reserved for future standardization x?14f-50? 8 justification stuff bytes x?151-53? 8 poh-j1 j1 x?154? 8 poh-b3 b3 x?155? 8 poh-c2 c2 x?156? 8 poh-g1 g1 x?157? 8 poh-f2 f2 x?158? 8 poh-h4 h4 x?159? 8 poh-f3 f3 x?15a? 8 poh-k3 k3 x?15b? 8 x?poh-n1? n1 15c 8 reserved x?15d-5f? 8 poh-j0-16 16 byte j0 section trace x?160-6f? 8 reserved x?170-7f? 8 poh-j1-16 16bytej1pathtrace(3) x?180-8f? 8 poh-j1-64 64bytej1pathtrace(3) x?190-bf? 8 1. meaning of counter address marked as (*) independant of the counter width, given that a counter has chiplet address n as a base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no effect on the counter but reading address n-1 resets the counter after read operation 2. address range 100-17f located in 128x8 gra address range 180-1bf located in 64x8 gra. 3. the 64 byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space ofp_tx gpp handler address mapping base address = x?400 (page 3 of 3) register name description address offset type width initial value IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 452 of 553 atmrm.chapt06.01 08/27/99 counter registers ptrinc number of pointer increment events (eight-bit counter). overflow leads to an interrupt request. ptrdec number of pointer decrement events (eight-bit counter) overflow leads to an interrupt request. length 8bits type read address 404/405 power on value x?00? ptrinc 76543210 bit(s) name description 7-0 ptrinc(7-0) pointer increment counter length 8bits type read address 406/407 power on value x?00? ptrdec 76543210 bit(s) name description 7-0 ptrdec(7-0) pointer decrement counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 453 of 553 nd_evcnt number of new data events (eight-bit counter) overflow leads to an interrupt request. juscnt number of justification errors detected (eight-bit counter) overflow leads to an interrupt request. length 8bits type read address 408/409 power on value x?00? nd_evcnt 76543210 bit(s) name description 7-0 nd_evcnt(7-0) new data event counter length 8bits type read address 40a/40b power on value x?00? juscnt 76543210 bit(s) name description 7-0 juscnt(7-0) justification error counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 454 of 553 atmrm.chapt06.01 08/27/99 juscntth11 threshold for number of justification errors. threshold overstep leads to an interrupt request. cnten1 counter on/off control register for ofp_tx. for each bit position, 0 = counter is disabled, 1 = counter is enabled. length 8bits type read/write address 40c power on valuex?80? juscntth11 76543210 bit(s) name description 7-0 juscntth11(7-0) threshold for justificication error counter length 8bits type read/write address 402 power on value x?00? reserved en-juscnt en-nd_evcnt en-ptrdec en-ptrinc 76543210 bit(s) name description 7-4 reserved reserved 3 en-juscnt justification error counter enable 2 en-nd_evcnt new data event counter enable 1 en-ptrdec pointer decrement counter enable 0 en-ptrinc pointer increment counter enable IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 455 of 553 reset register reset reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal resot coming from gppint chiplet. for each bit position, 0 = reset/halt not active, 1 = reset/halt active. command register cmd1 command register for the chiplet. single-cycle active if b?1? is written into bit position. length 8bits type read/write address 430 power on value x?01? reserved halt ofp_tx reset ofp_tx 76543210 bit(s) name description 7-2 reserved reserved 1 halt (freeze) ofp_tx chiplet 0 reset (disable) ofp_tx chiplet length 8bits type read/write address 431 power on value x?00? reserved ndf pjus njus 76543210 bit(s) name description 7-3 reserved reserved 2 ndf force a start-of-new-vc-4 event 1 pjus perform a positive frequency justification 0 njus perform a negative frequency justification IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 456 of 553 atmrm.chapt06.01 08/27/99 status registers stat1 status register #1 of the chiplet. this is an event latch register. stat2 status register #2 of the chiplet. this is an event latch register. length 8bits type read/write address 433 power on value x?00? reserved hug init 76543210 bit(s) name description 7-2 reserved reserved 1 hug 0 higher order unequipped generator inactive 1 higher order unequipped generator active 0 init 0 default gra initialization not completed 1 default gra initialization completed? length 8bits type read/write address 434 power on value - reserved ndf pjus njus 76543210 bit(s) name description 7-3 reserved reserved 2 ndf 0 no ndf transmitted 1 ndf transmitted 1 pjus 0 no positive frequency justification transmitted 1 positive frequency justification transmitted 0 njus 0 no negative frequency justification transmitted 1 negative frequency justification transmitted IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 457 of 553 interrupt and mask registers mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 438 power on value - reserved irq3 cntrirq1 fatal 76543210 bit(s) name description 7-3 reserved reserved 2 irq3 active request in irq3 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 458 of 553 atmrm.chapt06.01 08/27/99 m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates signal irqot to gppint. length 8bits type read/write address 439 power on value x?00? reserved irq3 cntrirq1 fatal 76543210 bit(s) name description 7-3 reserved reserved 2 irq3 active request in irq3 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 459 of 553 cntrirq1 register to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 43a power on value - reserved th-juscnt ov-juscnt ov-nd_evcnt ov-ptrinc ov-ptrdec 76543210 bit(s) name description 7-5 reserved reserved 4 th-juscnt threshold overstep justification error counter 3 ov-juscnt overflow justification error counter 2 ov-nd_evcnt overflow new data event counter 0 ov-ptrinc overflow pointer increment counter 1 ov-ptrdec overflow pointer decrement counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 460 of 553 atmrm.chapt06.01 08/27/99 m_cntrirq1 register to mask pending counter interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 43b power on value x?00? reserved th-juscnt ov-juscnt ov-nd_evcnt ov-ptrinc ov-ptrdec 76543210 bit(s) name description 7-5 reserved reserved 4 th-juscnt threshold overstep justification error counter 3 ov-juscnt overflow justification error counter 2 ov-nd_evcnt overflow new data event counter 0 ov-ptrinc overflow pointer increment counter 1 ov-ptrdec overflow pointer decrement counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 461 of 553 irq3 register to indicate active user interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 43c power on value - reserved dloss flow fhigh frmerr spcir txlpow 76543210 bit(s) name description 7-6 reserved reserved 5 dloss data loss = data fifo empty 4 flow fifo low threshold overflow 3 fhigh fifo high threshold overflow 2: frmerr framing error detected 1 spcir spc fsm interrupt request 0 txlpow low power indication from optical/electrical module IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 462 of 553 atmrm.chapt06.01 08/27/99 m_irq3 register to mask pending user interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 43d power on value x?00? reserved dloss flow fhigh frmerr spcir txlpow 76543210 bit(s) name description 7-6 reserved reserved 5 dloss data loss = data fifo empty 4 flow fifo low threshold overflow 3 fhigh fifo high threshold overflow 2 frmerr framing error detected 1 spcir spc fsm interrupt request 0 txlpow low power indication from optical/electrical module IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 463 of 553 configuration registers conf1 configuration register #1. general ofp_tx configuration signals a. length 8bits type read/write address 448 power on value x?03? spci j1mode jusfrm autrst_sta autrst_int 76543210 bit(s) name description 7-4 spci(7-4) specifies stm-n row number in which an interrupt request will be issued 3 j1mode 0 transmit 16 byte j1 path trace 1 transmit64bytej1pathtrace 2 jusfrm 0 allow pointer modification to be performed on frame to frame basis 1 enforces three frames being interleaved between two pointer modification operations 1 autrst_sta 0 no action on read access 1 auto-reset status register upon read access 0 autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 464 of 553 atmrm.chapt06.01 08/27/99 conf2 configuration register #2. general ofp_tx configuration signals b. conf3 configuration register #3 length 8bits type read/write address 449 power on value x?00? reserved txsdown hug msais 76543210 bit(s) name description 7-3 reserved 2 txsdown directly connected to output pin : 0 optical/electrical normal operation 1 transmit shutdown for optical/electrical module 1 hug 0 no unequipped stm-n signal 1 enforce unequipped stm-n signal 0 msais 0 no multiplex section ais 1 enforce multiplex section ais length 8bits type read/write address 44a power on value x?fe? fscr 76543210 bit(s) name description 7-0 fscr(7-0) reload pattern for frame scrambler IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 465 of 553 conf4 configuration register #4. conf5 configuration register #5. length 8bits type read/write address 44b power on value x?00? errmask 76543210 bit(s) name description 7-0 errmask(7-0) mask register forcing bit error insertion. xored with retrieved soh/poh length 8bits type read/write address 44c power on value x?00? erraddr 76543210 bit(s) name description 7-0 erraddr(7-0) error mask address register. indicates address of soh/poh byte to be corrupted IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 466 of 553 atmrm.chapt06.01 08/27/99 conf6 configuration register #6 frame scrambling control register. length 8bits type read/write address 44d power on value x?01? cidnum ciden scren 76543210 bit(s) name description 7-2 cidnum(7-2) number of all - ?1?/?0? bytes 1 ciden cid insertion enable 0nocidinsertion 1 perform cid insertion 0 scren scramble enable 0 no scrambling 1performscrambling IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: transmit direction page 467 of 553 conf7 configuration register #7 dcc control register. conf8 configuration registers #8 low water fifo threshold register. length 8bits type read/write address 44e power on value x?00? reserved edge mode clkmode opmode enable 76543210 bit(s) name description 7-4 reserved reserved 3 edgemode 0 active falling edge 1 active rising edge 2 clkmode 0 continuous clock 1 strobed clock 1 opmode 0 dcc1 channel (d1 - d3) 1 cc2 channel (d4 - d12) 0 enable 0 disable dcc1 processing 1 enable dcc1 processing length 8bits type read/write address 44f power on value x?03? reserved thrlow (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrlow(7-2) low water fifo threshold, default value is 3 IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: transmit direction page 468 of 553 atmrm.chapt06.01 08/27/99 conf9 configuration registers #9 normal water fifo threshold register. conf10 configuration registers #10 high water fifo threshold register. length 8bits type read/write address 450 power on value x?11? reserved thrnow (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrnow(7-2) normal water fifo threshold, default value is 17 length 8bits type read/write address 451 power on value x?20? reserved thrhiw (7-2) 76543210 bit(s) name description 7-6 reserved reserved 5-0 thrhiw(7-2) high water fifo threshold, default value is 32 IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 469 of 553 overhead frame processor architecture: receive direction ofp_rx gpp handler address mapping base address = x?800c (page 1 of 4) register name description address offset type width initial value rofmid read-on-the-fly register x?0? f 8 ?00000000? cnten1 count enable register #1 x?2? x 8 ?00000000? cnten2 count enable register #2 x?3? x 3 ?000? b1bitcnt bip-8 b1 bit error counter x?4/5? * n 16 ?x?0000?? b1bitcntth12 threshold register byte2 (least significant byte) for b1bitcnt x?6? x 8 ?00000000? b1bitcntth11 threshold register byte1 for counter b1bitcnt x?7? x 8 ?01111101? b1blkcnt bip-8 b1 block error counter (1) x?8/9? * n 16 ?x?0000?? b1blkcntth12 threshold register byte2 (least significant byte) for b1blkcnt x?a? x 8 ?00000000? b1blkcntth11 threshold register byte1 for counter b1blkcnt x?b? x 8 ?01111101? b2bitcnt bip-24 b2 bit error counter, 2 thresholds (1) x?c/d? * n 16 ?x?0000?? b2bitcntth12 degradation threshold byte2 (least significant byte) for b2bitcnt x?e? x 8 ?00100000? b2bitcntth11 degradation threshold byte1 for b2bitcnt x?f? x 8 ?01001110? b2bitcntth22 failure threshold byte2 (least significant byte) for b2bitcnt x?10? x 8 ?00000000? b2bitcntth21 failure threshold byte1 for b2bitcnt x?11? x 8 ?01111101? b2blkcnt bip-24 b2 block error counter, 2 thresholds (1) x?12/13? * n 16 ?x?0000?? b2blkcntth12 degration threshold byte2 (least significant byte) for b2blkcnt x?14? x 8 ?00100000? b2blkcntth11 degradation threshold byte1 forb2blkcnt x?15? x 8 ?01001110? b2blkcntth22 failure threshold byte2 (least significant byte) for b2blkcnt x?16? x 8 ?00000000? b2blkcntth21 failure threshold byte1 for b2blkcnt x?17? x 8 ?01111101? b3bitcnt bip-8 b3 bit error counter (1) x?18/19? * n 16 ?x?0000?? b3bitcntth12 threshold register byte2 (least significant byte) for b3bitcnt x?1a? x 8 ?00000000? b3bitcntth11 threshold register byte1 for counter b3bitcnt x?1b? x 8 ?01111101? b3blkcnt bip-8 b3 block error counter (1) x?1c/1d? * n 16 ?x?0000?? b3blkcntth12 threshold register byte2 (least significant byte) for b3blkcnt x?1e? x 8 ?00000000? b3blkcntth11 threshold register byte1 for counter b3blkcnt x?1f? x 8 ?01111101? msreicnt multiplex section remote error indication counter (1) x?20/21? * n 16 ?x?0000?? msreicntth12 threshold register byte2 (least significant byte) for msreicnt x?22? x 8 ?00000000? msreicntth11 threshold register byte1 for counter msreicnt x?23? x 8 ?01111101? hpreicnt higher-order path remote error indication counter (1) x?24/25? * n 16 ?x?0000?? hpreicntth12 threshold register byte2 (least significant byte) for hpreicnt x?26? x 8 ?00000000? hpreicntth11 threshold register byte1 for counter hpreicnt x?27? x 8 ?01111101? pj_evcnt positive justification counter, no threshold (1) x?28/29? * n 8 ?00000000? nj_evcnt negative justification counter, no threshold (1) x?2a/2b? * n 8 ?00000000? nd_evcnt new data event counter, no threshold (1) x?2c/2d? * n 8 ?00000000? reset default reset register x?30? r 2 ?01? stat1 status register #1 (mode) x?33? s 3 stat2 status register #2 (au pointer) x?34? s 6 stat3 status register #3 (soh) x?35? s 6 stat4 status register #4 (poh) x?36? s 4 IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 470 of 553 atmrm.chapt06.01 08/27/99 mainirq main interrupt register x?38? i 7 m_mainirq interrupt mask register for mainirq x?39? x 7 ?0000000? cntrirq1 counter interrupt register x?3a? i 8 m_cntrirq1 interrupt mask register for cntrirq1 x?3b? x 8 ?00000000? cntrirq2 counter interrupt register x?3c? i 8 m_cntrirq2 interrupt mask register for cntrirq2 x?3d? x 8 ?00000000? cntrirq3 counter interrupt register x?3e? i 5 m_cntrirq3 interrupt mask register for cntrirq3 x?3f? x 5 ?00000? irq6 user interrupt register x?40? i 4 m_irq6 interrupt mask register for irq6 x?41? x 4 ?0000? irq7 user interrupt register x?42? i 8 m_irq7 interrupt mask register for irq7 x?43? x 8 ?00000000? irq8 user interrupt register x?44? i 8 m_irq8 interrupt mask register for irq8 x?45? x 8 ?00000000? conf1 configuration register #1 (general) x?48? c 8 ?00111111? conf2 configuration register #2 (soh processing) x?49? c 6 ?0000? conf3 configuration register #3 (poh processing) x?4a? c 4 ?0000? conf4 configuration register #4 (aps processing) x?4b? c 8 ?00000000? conf7 configuration register #7 (miscellaneous) x?4e? c 8 ?00100000? conf8 configuration register #8 (fscr) x?4f? c 8 ?11111110? conf9 configuration register #9 (sl) x?50? c 8 ?00010011? soh-a11 first a1 x?100? 8 soh-a12 second1 a1 x?101? 8 soh-a13 third a1 x?102? 8 soh-a21 first a2 x?103? 8 soh-a22 second a2 x?104? 8 soh-a23 third a2 x?105? 8 soh-j0 j0 x?106? 8 reserved for national use and not included in frame scrambling (c1) x?107-8? 8 soh-b1 b1 x?109? 8 media dependant bytes x?10a-0b? 8 soh-e1 e1 x?10c? 8 media dependant byte x?10d? 8 reserved for future standardization x?10e? 8 soh-f1 f1 x?10f? 8 reserved for national use x?110-11? 8 soh-d1 d1 x?112? 8 media dependant bytes x?113-14? 8 soh-d2 d2 x?115? 8 media dependant byte x?116? 8 ofp_rx gpp handler address mapping base address = x?800c (page 2 of 4) register name description address offset type width initial value IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 471 of 553 reserved for future standardization x?117? 8 soh-d3 d3 x?118? 8 reserved for future standardization x?119-1a? 8 soh-h1 h1 x?11b? 8 soh-j0 b?1001ss11? with s unspecified x?11c-1d? 8 soh-h2 h2 x?11e? 8 soh-1s x?ff? x?11f-20? 8 soh-h31 first h3 x?121? 8 soh-h32 second h3 x?122? 8 soh-h23 third h3 x?123? 8 soh-b21 first b2 x?124? 8 soh-b22 second b2 x?125? 8 soh-b23 third b2 x?126? 8 soh-k1 k1 x?127? 8 reserved for future standardization x?128-29? 8 soh-k2 k2 x?12a? 8 reserved for future standardization x?12b-2c? 8 soh-d4 d4 x?12d? 8 reserved for future standardization x?12e-2f? 8 soh-d5 d5 x?130? 8 reserved for future standardization x?131-32? 8 soh-d6 d6 x?133? 8 reserved for future standardization x?134-35? 8 soh-d7 d7 x?136? 8 reserved for future standardization x?137-38? 8 soh-d8 d8 x?139? 8 reserved for future standardization x?13a-3b? 8 soh-d9 d9 x?13c? 8 reserved for future standardization x?13d-3e? 8 soh-d10 d10 x?13f? 8 reserved for future standardization x?140-41? 8 soh-d11 d11 x?142? 8 reserved for future standardization x?143-44? 8 soh-d12 d12 x?145? 8 reserved for future standardization x?146-47? 8 soh-s1 s1 x?148? 8 reserved for future standardization x?149-9c? 8 soh-m1 m1 x?14d? 8 soh-m1 e2 x?14e? 8 reserved for future standardization x?14f-50? 8 reserved x?151-53? 8 poh-j1 j1 x?154? 8 ofp_rx gpp handler address mapping base address = x?800c (page 3 of 4) register name description address offset type width initial value IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 472 of 553 atmrm.chapt06.01 08/27/99 poh-b3 b3 x?155? 8 poh-c2 c2 x?156? 8 poh-g1 g1 x?157? 8 poh-f2 f2 x?158? 8 poh-h4 h4 x?159? 8 poh-f3 f3 x?15a? 8 poh-k3 k3 x?15b? 8 poh-n1 n1 x?15c? 8 reserved x?15d-5f? 8 poh-j0-16-e expected16bytej0sectiontrace x?160-6f? 8 poh-j0-16-r received 16 byte j0 section trace x?170-7f? 8 poh-j1-16 expected16bytej1pathtrace(3) x?180-8f? 8 poh-j1-64 64bytej1pathtrace(3) x?190-bf? 8 1. meaning of counter address marked as (*) independant of the counter width, given that a counter has chiplet address n as a base, reading address n or address n-1 both yield the least significant byte of the counter. reading address n has no effect on the counter but reading address n-1 resets the counter after read operation. 2. address range 100-17f located in 128x8 gra address range 180-1bf located in 64x8 gra. 3. the 64 byte j1 path trace processing uses the 16 byte addresses of 16 byte j1 path trace to map a full 64 byte space. ofp_rx gpp handler address mapping base address = x?800c (page 4 of 4) register name description address offset type width initial value IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 473 of 553 counter registers rofmid read-on-the-fly registers. b1bitcnt number of bip-8 b1 bit errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. length 8bits type read address 800 power on value x?00? rofmid 76543210 bit(s) name description 7-0 rofmid(7-0) read-on-the-fly register most significant byte length 8bits type read address 804/805 power on value x?00? b1bitcnt (8:15) 76543210 bit(s) name description 7-0 b1bitcnt(8:15) bip-8 b1 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 474 of 553 atmrm.chapt06.01 08/27/99 b1bitcntth11 threshold for number of bip-8 b1 bit errors. b1bitcntth12 threshold for number of bip-8 b1 bit errors. threshold overstep leads to an interrupt request. length 8bits type read/write address 807 power on value x?7d? b1bitcntth11 76543210 bit(s) name description 7-0 b1bitcntth11(7-0) threshold for bip-8 b1 bit error counter most significant byte length 8bits type read/write address 806 power on value x?00? b1bitcntth12 76543210 bit(s) name description 7-0 b1bitcntth12(7-0) threshold for bip-8 b1 bit error error counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 475 of 553 b1blkcnt number of bip-8 b1 block errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. b1blkcntth11 threshold for number of bip-8 b1 block errors. length 8bits type read address 808/809 power on value x?00? b1blkcnt (8:15) 76543210 bit(s) name description 7-0 b1blkcnt(8:15) bip-8 b1 block error counter least significant byte length 8bits type read/write address 80b power on value x?7d? b1blkcntth11 76543210 bit(s) name description 7-0 b1blkcntth11(7-0) threshold for bip-8 b1 block error counter most significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 476 of 553 atmrm.chapt06.01 08/27/99 b1blkcntth12 threshold for number of bip-8 b1 block errors. threshold overstep leads to an interrupt request. b2bitcnt number of bip-24 b2 bit errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. length 8bits type read/write address 80a power on value x?00? b1blkcntth12 76543210 bit(s) name description 7-0 b1blkcntth12(7-0) threshold for bip-8 b1 block error counter least significant byte length 8bits type read address 80c/80d power on value x?00? b2bitcnt (8:15) 76543210 bit(s) name description 7-0 b2bitcnt(8:15) bip-24 b2 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 477 of 553 b2bitcntth11 degradation threshold for number of bip-24 b2 bit errors. b2bitcntth12 degradation threshold for number of bip-24 b2 bit errors. threshold overstep leads to an interrupt request. length 8bits type read/write address 80f power on value x?4e? b2bitcntth11 76543210 bit(s) name description 7-0 b2bitcntth11(7-0) degradation threshold for bip-24 b2 bit error counter most significant byte length 8bits type read/write address 80e power on value x?20? b2bitcntth12 76543210 bit(s) name description 7-0 b2bitcntth12(7-0) degradation threshold for bip-24 b2 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 478 of 553 atmrm.chapt06.01 08/27/99 b2bitcntth21 failure threshold for number of bip-24 b2 bit errors. b2bitcntth22 failure threshold for number of bip-24 b2 bit errors. threshold overstep leads to an interrupt request. length 8bits type read/write address 811 power on value x?7d? b2bitcntth21 76543210 bit(s) name description 7-0 b2bitcntth21(7-0) failure threshold for bip-24 b2 bit error counter most significant byte length 8bits type read/write address 810 power on value x?00? b2bitcntth22 76543210 bit(s) name description 7-0 b2bitcntth22(7-0) failure threshold for bip-24 b2 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 479 of 553 b2blkcnt number of bip-24 b2 block errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. b2blkcntth11 degradation threshold for number of bip-24 b2 block errors. length 8bits type read address 812/813 power on value x?00? b2blkcnt 76543210 bit(s) name description 7-0 b2blkcnt(8:15) bip-24 b2 block error counter least significant byte length 8bits type read/write address 815 power on value x?4e? b2blkcntth11 76543210 bit(s) name description 7-0 b2blkcntth11(7-0) degradation threshold for bip-24 b2 block error counter most significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 480 of 553 atmrm.chapt06.01 08/27/99 b2blkcntth12 degradation threshold for number of bip-24 b2 block errors. threshold overstep leads to an interrupt request. b2blkcntth21 failure threshold for number of bip-24 b2 block errors. length 8bits type read/write address 814 power on value x?20? b2blkcntth12 76543210 bit(s) name description 7-0 b2blkcntth12(7-0) degradation threshold for bip-24 b2 block error counter least significant byte length 8bits type read/write address 817 power on value x?7d? b2blkcntth21 76543210 bit(s) name description 7-0 b2blkcntth21(7-0) failure threshold for bip-24 b2 block error counter most significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 481 of 553 b2blkcntth22 failure threshold for number of bip-24 b2 block errors. threshold overstep leads to an interrupt request. b3bitcnt number of bip-8 b3 bit errors counted since last counter reset (16-bit counter). overflow leads to an interrupt request. length 8bits type read/write address 816 power on value x?00? b2blkcntth22 76543210 bit(s) name description 7-0 b2blkcntth22(7-0) failure threshold for bip-24 b2 block error counter least significant byte length 8bits type read address 818/819 power on value x?00? b3bitcnt 76543210 bit(s) name description 7-0 b3bitcnt(8:15) bip-8 b3 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 482 of 553 atmrm.chapt06.01 08/27/99 b3bitcntth11 threshold for number of bip-8 b3 bit errors. b3bitcntth12 threshold for number of bip-8 b3 bit errors. threshold overstep leads to an interrupt request. length 8bits type read/write address 81b power on value x?7d? b3bitcntth11 76543210 bit(s) name description 7-0 b3bitcntth11(7-0) threshold for bip-8 b3 bit error counter most significant byte length 8bits type read/write address 81a power on value x?00? b3bitcntth12 76543210 bit(s) name description 7-0 b3bitcntth12(7-0) threshold for bip-8 b3 bit error counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 483 of 553 b3blkcnt number of bip-8 b3 block errors counted since last counter reset (16-bit counter). overflow leads to an inter- rupt request. b3blkcntth11 threshold for number of bip-8 b3 block errors. length 8bits type read address 81c/81d power on value x?00? b3blkcnt 76543210 bit(s) name description 7-0 b3blkcnt(8:15) bip-8 b3 block error counter least significant byte length 8bits type read/write address 81f power on value x?7d? b3blkcntth11 76543210 bit(s) name description 7-0 b3blkcntth11(7-0) threshold for bip-8 b3 block error counter most significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 484 of 553 atmrm.chapt06.01 08/27/99 b3blkcntth12 threshold for number of bip-8 b3 block errors. threshold overstep leads to an interrupt request. msreicnt multiplex section remote error indication counter (16-bit counter). overflow leads to an interrupt request. length 8bits type read/write address 81e power on value x?00? b3blkcntth12 76543210 bit(s) name description 7-0 b3blkcntth12(7-0) threshold for bip-8 b3 block error counter least significant byte length 8bits type read address 820/821 power on value x?00? msreicnt (8:15) 76543210 bit(s) name description 7-0 msreicnt(8:15) multiplex section remote error indication counter least significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 485 of 553 msreicntth11 threshold for number of multiplex section remote errors. msreicntth12 threshold for number of multiplex section remote errors. threshold overstep leads to an interrupt request. length 8bits type read/write address 823 power on value x?7d? msreicntth11 76543210 bit(s) name description 7-0 msreicntth11(7-0) threshold for multiplex indication counter section remote error most significant byte length 8bits type read/write address 822 power on value x?00? msreicntth12 76543210 bit(s) name description 7-0 msreicntth12(7-0) threshold for multiplex indication counter section remote error least significant byte IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 486 of 553 atmrm.chapt06.01 08/27/99 hpreicnt higher-order path remote error indication counter (16-bit counter). overflow leads to an interrupt request. hpreicntth11 threshold for number of higher-order path remote errors. length 8bits type read address 824/825 power on value x?00? hpreicnt (8:15) 76543210 bit(s) name description 7-0 hpreicnt(8:15) higher-order path remote error indication counter least significant byte length 8bits type read/write address 827 power on value x?7d? hpreicntth11 76543210 bit(s) name description 7-0 hpreicntth11(7-0) threshold for higher-order path remote error indication counter most significant byte IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 487 of 553 hpreicntth12 threshold for number of higher-order path remote errors. threshold overstep leads to an interrupt request. pj_evcnt positive justification event counter (eight-bit counter). overflow leads to an interrupt request. length 8bits type read/write address 826 power on value x?00? hpreicntth12 76543210 bit(s) name description 7-0 hpreicntth12(7-0) threshold for higher-order path remote error indication counter least significant byte length 8bits type read address 828/829 power on value x?00? pj_evcnt 76543210 bit(s) name description 7-0 pj_evcnt(7-0) positive justification event counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 488 of 553 atmrm.chapt06.01 08/27/99 nj_evcnt negative justification event counter (eight-bit counter). overflow leads to an interrupt request. nd_evcnt new data event counter (eight-bit counter). overflow leads to an interrupt request. length 8bits type read address 82a/82b power on value x?00? nj_evcnt 76543210 bit(s) name description 7-0 nj_evcnt(7-0) negative justification event counter length 8bits type read address 82c/82d power on value x?00? nd_evcnt 76543210 bit(s) name description 7-0 nd_evcnt(7-0) new data event counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 489 of 553 cnten1 counter on/off control register #1 for ofp_rx. for each bit position, 0 = counter is disabled, 1 = counter is enabled. length 8bits type read/write address 802 power on value x?00? en-hpreicnt en-msreicnt en-b3blkcnt en-b3bitcnt en-b2blkcnt en-b2bitcnt en-b1blkcnt en-b1bitcnt 76543210 bit(s) name description 7 en-hpreicnt higher-order path remote error indication counter enable 6 en-msreicnt multiplex section remote error indication counter enable 5 en-b3blkcnt bip-8 b3 block error counter enable 4 en-b3bitcnt bip-8 b3 bit error counter enable 3 en-b2blkcnt bip-24 b2 block error counter enable 2 en-b2bitcnt bip-24 b2 bit error counter enable 1 en-b1blkcnt bip-8 b1 block error counter enable 0 en-b1bitcnt bip-8 b1 bit error counter enable IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 490 of 553 atmrm.chapt06.01 08/27/99 cnten2 counter on/off control register #2 for ofp_rx. for each bit position, 0 = counter is disabled, 1 = counter is enabled. reset register (reset) reset/halt chiplet control register. this register is automatically preset to the default value by the reset signal resot coming from gppint chiplet. for each bit position, 0 = reset/halt not active, 1 = reset/halt active. length 8bits type read/write address 803 power on value x?00? reserved en-nd_evcnt en-nj_evcnt en-pj_evcnt 76543210 bit(s) name description 7-3 reserved reserved 2 en-nd_evcnt new data event counter enable 1 en-nj_evcnt negative justification event counter enable 0 en-pj_evcnt positive justification event counter enable length 8bits type read/write address 830 power on value x?01? reserved halt ofp_rx reset ofp_rx 76543210 bit(s) name description 7-2 reserved reserved 1 halt (freeze) ofp_rx chiplet 0 reset (disable) ofp_rx chiplet IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 491 of 553 status registers stat1 status register #1 of the chiplet. ofp_rx mode status information. this is an event latch register. stat2 status register #2 of the chiplet. au pointer status information of ofp_rx. this is an event latch register. length 8bits type - address 833 power on value - reserved 76543210 bit(s) name description 7-0 reserved reserved length 8bits type read/write address 834 power on value - reserved concrx newptr invptr ndf pjus njus 76543210 bit(s) name description 7-6 reserved reserved 5 concrx concatenation indication received 4 newptr valid new pointer received 3 invptr invalid pointer received 2 ndf ndf received 1 pjus positive frequency justification received 0 njus negative frequency justification received IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 492 of 553 atmrm.chapt06.01 08/27/99 stat3 status register #3 of the chiplet. section overhead (soh) status of ofp_rx. this is an event latch register. length 8bits type read/write address 835 power on value - reserved e1chg e2chg f1chg d1chg d4chg m1chg 76543210 bit(s) name description 7-6 reserved reserved 5 e1chg orderwire channel e1 content changed 4 e2chg orderwire channel e2 content changed 3 f1chg user communication channel f1 content changed 2 d1chg d1-d3 communication channel content changed 1 d4chg d4-d12 communication channel content changed 0 m1chg number of bit blocks in error changed IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 493 of 553 stat4 status register #4 of the chiplet. path overhead (poh) status of ofp_rx. this is an event latch register. length 8bits type read/write address 836 power on value - reserved c2chg g1chg f2chg z5 76543210 bit(s) name description 7-4 reserved reserved 3 c2chg payload composition indication changed 2 g1chg path status indication changed 1 f2chg user communication channel f2 content changed 0 z5 z5 content changed IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 494 of 553 atmrm.chapt06.01 08/27/99 interrupt and mask registers mainirq register to indicate fatal interrupt events and to point to user irq registers with active requests. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 838 power on value - reserved irq8 irq7 irq6 cntrirq3 cntrirq2 cntrirq1 fatal 76543210 bit(s) name description 7 reserved reserved 6 irq8 active request in irq8 register 5 irq7 active request in irq7 register 4 irq6 active request in irq6 register 3 cntrirq3 active request in cntrirq3 register 2 cntrirq2 active request in cntrirq2 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occured IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 495 of 553 m_mainirq register to mask pending interrupt requests. a masked request will not generate an outgoing irq to the gppint. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates signal irqor to gppint. length 8bits type read/write address 839 power on value x?00? reserved irq8 irq7 irq6 cntrirq3 cntrirq2 cntrirq1 fatal 76543210 bit(s) name description 7 reserved reserved 6 irq8 active request in irq8 register 5 irq7 active request in irq7 register 4 irq6 active request in irq6 register 3 cntrirq3 active request in cntrirq3 register 2 cntrirq2 active request in cntrirq2 register 1 cntrirq1 active request in cntrirq1 register 0 fatal fatal event occurred IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 496 of 553 atmrm.chapt06.01 08/27/99 cntrirq1 register #1 to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 83a power on value - ov-b2blkcnt t2-b2bitcnt th-b2bitcnt ov-b2bitcnt th-b1blkcnt ov-b1blkcnt th-b1bitcnt ov-b1bitcnt 76543210 bit(s) name description 7 ov-b2blkcnt overflow bip-24 b2 block error counter 6 t2-b2bitcnt failure threshold overstep bip-24 b2 bit error counter 5 th-b2bitcnt degradation threshold overstep bip-24 b2 bit error counter 4 ov-b2bitcnt overflow bip-24 b2 bit error counter 3 th-b1blkcnt threshold overstep bip-8 b1 block error counter 2 ov-b1blkcnt overflow bip-8 b1 block error counter 1 th-b1bitcnt threshold overstep bip-8 b1 bit error counter 0 ov-b1bitcnt overflow bip-8 b1 bit error counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 497 of 553 m_cntrirq1 register to mask pending counter interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default),1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 83b power on value x?00? ov-b2blkcnt t2-b2bitcnt th-b2bitcnt ov-b2bitcnt th-b1blkcnt ov-b1blkcnt th-b1bitcnt ov-b1bitcnt 76543210 bit(s) name description 7 ov-b2blkcnt overflow bip-24 b2 block error counter 6 t2-b2bitcnt failure threshold overstep bip-24 b2 bit error counter 5 th-b2bitcnt degradation threshold overstep bip-24 b2 bit error counter 4 ov-b2bitcnt overflow bip-24 b2 bit error counter 3 th-b1blkcnt threshold overstep bip-8 b1 block error counter 2ov-b1blkcnt overflow bip-8 b1 block error counter 1 th-b1bitcnt threshold overstep bip-8 b1 bit error counter 0 ov-b1bitcnt overflow bip-8 b1 bit error counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 498 of 553 atmrm.chapt06.01 08/27/99 cntrirq2 register #2 to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 83c power on value - th-msreicnt ov-msreicnt th-b3blkcnt ov-b3blkcnt th-b3bitcnt ov-b3bitcnt t2-b2blkcnt th-b2blkcnt 76543210 bit(s) name description 7 th-msreicnt threshold overstep multiplex section remote error indication counter 6 ov-msreicnt overflow multiplex section remote error indication counter 5 th-b3blkcnt threshold overstep bip-8 b3 block error counter 4 ov-b3blkcnt overflow bip-8 b3 block error counter 3 th-b3bitcnt threshold overstep bip-8 b3 bit error counter 2 ov-b3bitcnt overflow bip-8 b3 bit error counter 1 t2-b2blkcnt failure th. overstep bip-24 b2 block error counter 0 th-b2blkcnt degrad. th. overstep bip-24 b2 block error counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 499 of 553 m_cntrirq2 register to mask pending counter interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default),1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 83d power on value x?00? th-msreicnt ov-msreicnt th-b3blkcnt ov-b3blkcnt th-b3bitcnt ov-b3bitcnt t2-b2blkcnt th-b2blkcnt 76543210 bit(s) name description 7 th-msreicnt threshold overstep multiplex section remote error indication counter 6 ov-msreicnt overflow multiplex section remote error indication counter 5 th-b3blkcnt threshold overstep bip-8 b3 block error counter 4 ov-b3blkcnt overflow bip-8 b3 block error counter 3 th-b3bitcnt threshold overstep bip-8 b3 bit error counter 2 ov-b3bitcnt overflow bip-8 b3 bit error counter 1 t2-b2blkcnt failure th. overstep bip-24 b2 block error counter 0 th-b2blkcnt degrad. th. overstep bip-24 b2 block error counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 500 of 553 atmrm.chapt06.01 08/27/99 cntrirq3 register #3 to indicate active counter interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 83e power on value - reserved ov-nd_evcnt ov-nj_evcnt ov-pj_evcnt th-hpreicnt ov-hpreicnt 76543210 bit(s) name description 7-5 reserved reserved 4 ov-nd_evcnt overflow new data event counter 3 ov-nj_evcnt overflow negative justification event counter 2 ov-pj_evcnt overflow positive justification event counter 1 th-hpreicnt threshold overstep higher-order path remote error indication counter 0 ov-hpreicnt overflow hpr error indication counter IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 501 of 553 m_cntrirq3 register to mask pending counter interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default),1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 83f power on value x?00? reserved ov-nd_evcnt ov-nj_evcnt ov-pj_evcnt th-hpreicnt ov-hpreicnt 76543210 bit(s) name description 7-5 reserved reserved 4 ov-nd_evcnt overflow new data event counter 3 ov-nj_evcnt overflow negative justification event counter 2 ov-pj_evcnt overflow positive justification event counter 1 th-hpreicnt threshold overstep higher-order path remote error indication counter 0 ov-hpreicnt overflow hpr error indication counter IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 502 of 553 atmrm.chapt06.01 08/27/99 irq6 register to indicate active user interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 840 power on value - reserved sdbfull frmerr s1chg hprei 76543210 bit(s) name description 7-4 reserved reserved 3 sdbfull sdb_rx fifo full 2 frmerr interrupt from orxaug fsm 1 s1chg synchronization status changed 0 hprei higher-order path remote error indication IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 503 of 553 m_irq6 register to mask pending user interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default),1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 841 power on value x?00? reserved sdbfull frmerr s1chg hprei 76543210 bit(s) name description 7-4 reserved reserved 3 sdbfull sdb_rx fifo full 2 frmerr interrupt from orxaug fsm 1 s1chg synchronization status changed 0 hprei higher-order path remote error indication IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 504 of 553 atmrm.chapt06.01 08/27/99 irq7 register to indicate active user interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 842 power on value - oof los lof lop hpais hprdi uneq slm 76543210 bit(s) name description 7 oof out of frame alarm 6 los loss of signal alarm 5 lof loss of frame alarm 4 lop loss of pointer alarm 3 hpais higher-order path ais 2 hprdi higher-order path rdi 1 uneq unequipped signal 0 slm signal label mismatch alarm IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 505 of 553 m_irq7 register to mask pending user interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default), 1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 843 power on value x?00? oof los lof lop hpais hprdi uneq slm 76543210 bit(s) name description 7 oof out of frame alarm 6 los loss of signal alarm 5 lof loss of frame alarm 4 lop loss of pointer alarm 3 hpais higher-order path ais 2 hprdi higher-order path rdi 1 uneq unequipped signal 0 slm signal label mismatch alarm IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 506 of 553 atmrm.chapt06.01 08/27/99 irq8 register to indicate active user interrupt requests of this chiplet. for each bit position, 0 = no interrupt request pending, 1 = interrupt request pending. length 8bits type read/write address 844 power on value - msais msrdi reserved mstim hptim ptrerr 76543210 bit(s) name description 7 msais multiplex section ais 6 msrdi multiplex section rdi 5-3 reserved reserved 2 mstim multiplex section trace identifier mismatch 1 hptim higher-order path trace identifier mismatch 0 ptrerr pointer processing error IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 507 of 553 m_irq8 register to mask pending user interrupt requests. for each bit position, 0 = the corresponding pending request bit is masked (default),1 = the corresponding pending request bit activates the pointer bit in mainirq register. length 8bits type read/write address 845 power on value x?00? msais msrdi reserved mstim hptim ptrerr 76543210 bit(s) name description 7 msais multiplex section ais 6 msrdi multiplex section rdi 5-3 reserved reserved 2 mstim multiplex section trace identifier mismatch 1 hptim higher-order path trace identifier mismatch 0 ptrerr pointer processing error IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 508 of 553 atmrm.chapt06.01 08/27/99 configuration registers conf1 configuration register #1. general ofp_rx configuration signals. length 8bits type read/write address 848 power on value x?3f? reshunt bellcore j1gra j0gra fifoen graen autrst_sta autrst_int 76543210 bit(s) name description 7 reshunt 0 hunt free running 1 reset hunt to pim 6 bellcore 0 operate according to itu standard 1 operate according to bellcore specification 5 j1gra 0 donotwritej1sectiontracetogra 1 write j1 section trace to gra 4 j0gra 0 donotwritej0sectiontracetogra 1 write j0 section trace to gra 3 fifoen 0 do not write c4 payload to fifo 1 write c4 payload to fifo 2 graen 0 do not write soh/poh info to gra 1 write received soh/poh info to gra 1 autrst_sta 0 no action on read access 1 auto-reset status register upon read access 0 autrst_int 0 no action on read access 1 auto-reset interrupt request registers upon read access IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 509 of 553 conf2 configuration register #2. soh processing configuration signals. length 8bits type read/write address 849 power on value x?00? reserved k2en s1en m1en oproc 76543210 bit(s) name description 7-4 reserved 3 k2en 0 disable k2 ais processing 1 enable k2 ais processing 2 s1en 0 disable s1 synchronization status processing 1 enable s1 synchronization status processing 1 m1en 0 disable m1 rei processing 1 enable m1 rei processing 0 0proc 0 disable j0 section trace processing 1 enable j0 section trace processing IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 510 of 553 atmrm.chapt06.01 08/27/99 conf3 configuration register #3. poh byte processing configuration signals. length 8bits type read/write address 84a power on value x?00? reserved c2en g1en j1mode64 j1proc 76543210 bit(s) name description 7-4 reserved 3 c2en 0 disable c2 signal label processing 1 enable c2 signal label processing 2 g1en 0 disable g1 path status processing 1 enable g1 path status processing 1 j1mode64 0 16 byte j1 trace 1 64bytej1trace 0 j1proc 0 disable j1 path trace processing 1 enable j1 path trace processing IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 511 of 553 conf4 configuration register #4. aps processing configuration signals. length 8bits type read/write address 84b power on value x?00? sfen aaen sdfen prior chnum (7-4) 76543210 bit(s) name description 7 sfen 0 disable sf k2 ms_rdi processing 1 enable sf k2 ms_rdi processing 6 aaen 0 disable automatic alarm processing for k2 1 enable automatic alarm processing for k2 5 sdfen 0 disable automatic sdf k1 processing 1 enable automatic sdf k1 processing 4 prior priority level 3-0 chnum(7-4) channel number IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 512 of 553 atmrm.chapt06.01 08/27/99 conf7 configuration register #7. miscellaneous ofp_rx configuration signals. length 8bits type read/write address 84e power on value x?20? edgemode clkmode opmode dccen outnum (7-6) innum (7-6) 76543210 bit(s) name description 7 edgemode 0 active falling edge 1 active rising edge 6 clkmode 0 continuous clock mode 1 strobed clock mode 5 opmode 0 dcc 1 channel selected 1 dcc 2 channel selected 4 dccen 0 disable dcc processing 1 enable dcc processing 3-2 outnum(7-6) number of s for in-frame to out-of-frame transition 1-0 innum(7-6) number of s for out-of-frame to in-frame transition IBM2520L8767 ibm processor for atm resources atmrm.chapt06.01 08/27/99 overhead frame processor architecture: receive direction page 513 of 553 conf8 configuration register #8. pattern register signals. conf9 configuration register #9. pattern register signals. length 8bits type read/write address 84f power on value x?fe? fscrrx 76543210 bit(s) name description 7-0 fscrrx(7-0) frame descrambling reload pattern length 8bits type read/write address 850 power on value x?13? slexpct 76543210 bit(s) name description 7-0 slexpct(7-0) expected signal label IBM2520L8767 ibm processor for atm resources overhead frame processor architecture: receive direction page 514 of 553 atmrm.chapt06.01 08/27/99 IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 memory map for registers and arrays page 515 of 553 printed circuit board considerations connect the bist0di1 output to the ibdinh1 input so that the device drivers are driven to high imped- ance during a device reset or while the IBM2520L8767 bist is running. add a pullup resistor to this net. a filter circuit should be added to the vdda input for the pll. connect mforcebp to mbypass, with a 1-k pullup on this net. pullups are required on the ibdrinh signal. pulldowns (or grounds) are required on the ppllti signal. memory map for registers and arrays address entity elements accessed xxxx 0000 - ff pcint registers xxxx 0400 - ff intst registers xxxx 0500 - ff crset registers xxxx 0600 - 7ff dmaqs registers & array xxxx 0100 - ff gpdma registers xxxx 0900 - ff comet/pakit registers xxxx 0a00 - ff chksm registers xxxx 0b00 - ff linkc registers xxxx 0c00 - ff raall registers xxxx 0d00 - ff vimem registers xxxx 0e00 - ff arbit registers xxxx 1000 - 1ff bcach registers & array xxxx 1200 - 3ff csked registers & array xxxx 1400 - 5ff segbf registers & array xxxx 1600 - 7ff reasm registers & array xxxx 1800 - fff rxque registers xxxx 2000 - fff npbus/framr registers & external eeprom xxxx 3000 - bff pools registers & arrays xxxx 4c00 - fff pcore registers & arrays IBM2520L8767 ibm processor for atm resources pin assignments and dc characteristics page 516 of 553 atmrm.chapt07.01 08/27/99 pin assignments and dc characteristics this table lists the complete pinout of the IBM2520L8767 by pin name and gives the book name for the elec- trical driver code associated with the pin. please refer to pinout viewed from above on page 6 for an illustra- tion of the grid positions. refer to book definitions on page 530 to learn the dc characteristics for the books. signal pin listing by family (page 1 of 14) pin family name pin name grid position book name input/output mbypass 0n15 pll in pvdda 0m17 pll in ppllti 0m19 pll in bist0di1 0p03 f inout cmaddr cmaddr<17> 0g01 cinout cmaddr<16> 0k08 cmaddr<15> 0f02 cmaddr<14> 0h04 cmaddr<13> 0g02 cmaddr<12> 0g03 cmaddr<11> 0k07 cmaddr<10> 0j05 cmaddr<9> 0k06 cmaddr<8> 0d02 cmaddr<7> 0h05 cmaddr<6> 0l05 cmaddr<5> 0f04 cmaddr<4> 0d01 cmaddr<3> 0d03 cmaddr<2> 0c01 cmaddr<1> 0b01 cmaddr<0> 0c02 IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 517 of 553 cmcas cmcas<1> 0c07 b inout cmcas<0> 0e07 cmclk 0d04 z inout cmclkrp 0b02 z inout cmcs cmcs<6> 0f08 c inout cmcs<5> 0g07 cmcs<4> 0f06 cmcs7 0a07 b inout signal pin listing by family (page 2 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 518 of 553 atmrm.chapt07.01 08/27/99 cmdata cmdata<35> 0y02 hinout cmdata<34> 0r09 cmdata<33> 0w01 cmdata<32> 0u03 cmdata<31> 0r07 cmdata<30> 0v02 cmdata<29> 0t04 cmdata<28> 0t02 cmdata<27> 0r03 cmdata<26> 0p10 cmdata<25> 0u01 cmdata<24> 0r02 cmdata<23> 0r01 cmdata<22> 0p08 cmdata<21> 0p04 cmdata<20> 0n03 cmdata<19> 0p07 cmdata<18> 0n09 cmdata<17> 0p06 cmdata<16> 0p02 cmdata<15> 0r05 cmdata<14> 0n01 cmdata<13> 0n05 cmdata<12> 0m02 cmdata<11> 0m04 cmdata<10> 0m07 cmdata<9> 0l01 cmdata<8> 0l02 cmdata<7> 0j01 cmdata<6> 0m08 cmdata<5> 0l03 cmdata<4> 0k02 cmdata<2> 0k04 cmdata<2> 0h02 cmdata<1> 0l07 signal pin listing by family (page 3 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 519 of 553 cmdata2 cmdata2<38> 0w03 h inout cmdata2<37> 0w02 cmdata2<36> 0v04 cmras cmras<1> 0a05 b inout cmras<2> 0c05 cmsyncas 0m06 c inout cmsynras 0n07 c inout cmwe cmwe<1> 0c09 b inout cmwe<0> 0e09 cts 0k05 k inout dsr 0p01 k inout dtr 0k03 d inout signal pin listing by family (page 4 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 520 of 553 atmrm.chapt07.01 08/27/99 enstate enstate<63> 0h10 ginout enstate<62> 0k13 enstate<61> 0h16 enstate<60> 0k18 enstate<59> 0h18 enstate<58> 0l17 enstate<57> 0r18 enstate<56> 0v18 enstate<55> 0t18 enstate<54> 0w18 enstate<53> 0p12 enstate<52> 0u17 enstate<51> 0w17 enstate<50> 0r13 enstate<49> 0v16 enstate<48> 0t13 enstate<47> 0y17 enstate<46> 0y19 enstate<45> 0t14 enstate<44> 0v15 enstate<43> 0v13 enstate<42> 0v12 enstate<41> ae17 enstate<40> ad16 enstate<39> 0v14 enstate<38> 0u13 enstate<37> ab15 enstate<36> ab16 enstate<35> 0w11 enstate<34> ae16 enstate<33> ad15 enstate<32> 0y14 signal pin listing by family (page 5 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 521 of 553 fy0emp 0c10 l inout fy0ful 0l09 l inout fy0renb 0m18 e inout fy0tenb 0n19 e inout fydiscrd 0k12 j inout fydtct 0g17 l inout fyrca 0k16 l inout fyrdat fyrdat<11> 0p15 win fyrdat<10> 0t15 fyrdat<9> 0t17 fyrdat<8> 0t19 fyrdat<7> 0v17 fyrdat<6> 0v19 fyrdat<5> ac15 fyrdat<4> ae07 fyrdat<3> aa13 fyrdat<2> ac13 fyrdat<1> ae13 fyrdat<0> aa11 fyrdatb fyrdatb<15> 0m12 l inout fyrdatb<14> 0m14 fyrdatb<13> 0l19 fyrdatb<12> 0m16 fyrpar fyrpar<1> 0m13 l inout fyrpar<0> 0l18 fyrrdb 0n17 e inout fyrsclkn 0e19 n inout fyrsclkp 0c19 n inout fyrsdatp 0j19 n inout fyrsdatn 0g19 n inout fyrsoc 0l15 j inout fysetclp 0k10 j inout fytca 0f18 l inout signal pin listing by family (page 6 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 522 of 553 atmrm.chapt07.01 08/27/99 fytdat fytdat<15> 0n13 ginout fytdat<14> 0p14 fytdat<13> 0t16 fytdat<12> 0p16 fytdat<11> 0n11 fytdat<10> 0r19 fytdat<9> 0p13 fytdat<8> 0r15 fytdat<7> 0r17 fytdat<6> 0y18 fytdat<5> 0u15 fytdat<4> ab18 fytdat<3> 0y16 fytdat<2> ab19 fytdat<1> ab17 fytdat<0> aa17 fytpar fytpar<1> ad19 ginout fytpar<0> ac18 fytsclkn ac19 n inout fytsclkp aa19 n inout fytsdatp 0w19 p inout fytsdatn 0u19 p inout fytsoc 0y15 g inout fytwrb 0p18 e inout ibdinh1 0v01 q in ibdinh2 0v03 r in ibdrinh 0k01 t in jtag0rst 0k17 w in jtag0rstc 0k15 k in jtagtck 0h17 k in jtagtckc 0c15 k in jtagtdi 0c11 w in jtagtdic 0e11 w in jtagtdo 0a13 f inout signal pin listing by family (page 7 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 523 of 553 jtagtdoc 0c13 f inout jtagtms 0a15 k in jtagtmsc 0e13 k in leaktst 0k19 v in mack64 0d17 a inout mdevsel 0d10 a inout mforcebp 0h19 f inout mframe 0l11 a inout mgnt 0d14 m inout mhalt401 0t01 k in mint2 0f15 a inout minta 0e15 a inout mirdy 0d11 a inout mlock 0c17 m inout mpcirst 0a11 x inout mpegclk ae09 w in mperr 0d09 a inout mreq 0d13 a inout mreq64 0b11 a inout mserr 0a08 a inout mstop 0f10 a inout mtrdy 0f11 a inout nselft 0p05 s in signal pin listing by family (page 8 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 524 of 553 atmrm.chapt07.01 08/27/99 pad pad<31> 0f17 ainout pad<30> 0f19 pad<29> 0k14 pad<28> 0h15 pad<27> 0h13 pad<26> 0a18 pad<25> 0g15 pad<24> 0b17 pad<23> 0e16 pad<22> 0j13 pad<21> 0a17 pad<20> 0b16 pad<19> 0h14 pad<18> 0h12 pad<17> 0d15 pad<16> 0d16 pad<15> 0g11 pad<14> 0a16 pad<13> 0b15 pad<12> 0f14 pad<11> 0h11 pad<10> 0c14 pad<9> 0g13 pad<8> 0a14 pad<7> 0f13 pad<6> 0f12 pad<5> 0k11 pad<4> 0b13 pad<3> 0d12 pad<2> 0j11 pad<1> 0a12 pad<0> 0m10 signal pin listing by family (page 9 of 14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 525 of 553 pad64 pad64<63> 0f09 a inout pad64<62> 0k09 pad64<61> 0b08 pad64<60> 0b07 pad64<59> 0h09 pad64<58> 0d08 pad64<57> 0d07 pad64<56> 0a06 pad64<55> 0g09 pad64<54> 0f07 pad64<53> 0c06 pad64<52> 0h08 pad64<51> 0d06 pad64<50> 0b05 pad64<49> 0a04 pad64<48> 0h07 pad64<47> 0e05 pad64<46> 0d05 pad64<45> 0j07 pad64<44> 0f05 pad64<43> 0b04 pad64<42> 0a03 pad64<41> 0h06 pad64<40> 0e04 pad64<39> 0b03 pad64<38> 0g05 pad64<37> 0c03 pad64<36> 0a02 pad64<35> 0f03 pad64<34> 0f01 pad64<33> 0e03 pad64<32> 0e01 pb0eprm ab12 e inout pb0phy1 ad13 e inout signal pin listing by family (page10of14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 526 of 553 atmrm.chapt07.01 08/27/99 pb0phy2 ad18 e inout pbaddr16 ad09 e inout pbaddr17 0u11 e inout pbale1 0t11 e inout pbale2 ae12 e inout pbdata pbdata<7> 0v11 minout pbdata<6> ac14 pbdata<5> 0w13 pbdata<4> 0t12 pbdata<3> ae14 pbdata<2> 0y13 pbdata<1> 0y12 pbdata<0> 0v10 pbintra ad17 l inout pbphyrst ac10 e inout pbrdrdy 0w15 l inout pbrnwrt ad11 e inout pbsclk 0r11 e inout pbsdata ae18 m inout pcbe pcbe<3> 0d19 ainout pcbe<2> 0f16 pcbe<1> 0e17 pcbe<0> 0b18 pcbe64 pcbe64<7> 0d18 ainout pcbe64<6> 0a10 pcbe64<5> 0b09 pcbe64<4> 0j15 pciclk 0a09 x in pdblclk 0l13 e inout pffcfg pffcfg<2> 0m15 win pffcfg<1> 0p17 pffcfg<0> 0p19 pffosc 0t05 w in pidsel 0b12 m inout signal pin listing by family (page11of14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 527 of 553 pintclk 0j17 e inout pmaddr pmaddr<17> ac03 c inout pmaddr<16> ad02 pmaddr<16> ac02 pmaddr<16> ad01 pmaddr<16> ac01 pmaddr<16> ab03 pmaddr<16> ab01 pmaddr<16> 0y04 pmaddr<16> 0t08 pmaddr<16> aa03 pmaddr<16> aa01 pmaddr<16> 0v05 pmaddr<16> ab02 pmaddr<16> 0t06 pmaddr<16> 0y01 pmaddr<16> 0y03 pmaddr<16> 0u05 pmaddr<16> 0t07 pmcas pmcas<1> ac07 b inout pmcas<0> aa07 pmclk aa15 z inout pmclkrp aa16 z inout pmcs pmcs<6> ab13 c inout pmcs<5> ad12 pmcs<4> ab14 pmcs7 ae15 b inout signal pin listing by family (page12of14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources signal pin listing by family page 528 of 553 atmrm.chapt07.01 08/27/99 pmdata pmdata<35> ac17 hinout pmdata<34> 0t10 pmdata<33> 0u09 pmdata<32> ab09 pmdata<31> ad08 pmdata<30> 0t09 pmdata<29> ae08 pmdata<28> ab08 pmdata<27> ad07 pmdata<26> 0v09 pmdata<25> 0y08 pmdata<24> ab07 pmdata<23> 0y07 pmdata<22> ae06 pmdata<21> 0w09 pmdata<20> 0w07 pmdata<19> ac06 pmdata<18> 0y09 pmdata<17> ab06 pmdata<16> 0y06 pmdata<15> ad05 pmdata<14> ae04 pmdata<13> 0v08 pmdata<12> aa05 pmdata<11> ab04 pmdata<10> ab05 pmdata<9> 0u07 pmdata<8> 0y05 pmdata<7> 0v06 pmdata<6> ad04 pmdata<5> ae03 pmdata<4> 0v07 pmdata<3> aa04 pmdata<2> ad03 pmdata<1> 0w05 signal pin listing by family (page13of14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 signal pin listing by family page 529 of 553 pmdata2 pmdata2<38> 0y10 h inout pmdata2<37> ae10 pmdata2<36> ab10 pmras pmras<1> ae05 b inout pmras<0> ac05 pmsyncas ab11 c inout pmsynras 0y11 c inout pmwe pmwe<1> ac09 b inout pmwe<0> aa09 b inout ppar 0g18 a inout ppar64 0j09 a inout ppllout 0c18 g inout rts 0m05 d inout rxclk ae11 w in rxd 0m03 w in testct 0h03 s in testm 0h01 s in tmmcore 0t03 s in txclk ac11 w in txd 0m01 d inout signal pin listing by family (page14of14) pin family name pin name grid position book name input/output IBM2520L8767 ibm processor for atm resources book definitions page 530 of 553 atmrm.chapt07.01 08/27/99 book definitions (page 1 of 2) book name insta nces description v il (v) v ih (v) i il (@0v) max i ih (@v dd ) max v oh (v) min v ol (v) min i oh (ma) min i ol (ma) min note min max min max a86 -5.0v-tolerant pci non-test three-state cio 0.0 0.8 2.0 5.5 >0 <0 2.4 0.5 - - b14 -3.3v lvttl test 35 ohm three-state cio 0.0 0.8 2.0 v dd + 0.6 002.40.4 13.0/ 12.0 9.0 c51 -3.3v lvttl non-test 35 ohm three-state cio 0.0 0.8 2.0 v dd + 0.6 002.40.4 13.0/ 12.0 9.0 d3 -3.3v lvttl test 50 ohm three-state cio w/pull-up 0.0 0.8 2.0 v dd + 0.6 -250 a 0 2.4 0.4 10.0 7.0 e16 -3.3v lvttl non-test 50 ohm three-state cio w/pull-up 0.0 0.8 2.0 v dd + 0.6 -250 a 0 2.4 0.4 10.0 7.0 f4 -3.3v lvttl test 50 ohm three-state cio 0.0 0.8 2.0 v dd + 0.6 0 0 2.4 0.4 10.0 7.0 g52 -3.3v lvttl non-test 50 ohm three-state cio 0.0 0.8 2.0 v dd + 0.6 0 0 2.4 0.4 10.0 7.0 h77 -5.0v-tolerant lvttl non-test 50 ohm three-state cio 0.0 0.8 2.0 5.5 0 0 2.4 0.4 13.0/ 12.0 9.0 j3 -5.0v-tolerant lvttl non-test 50 ohm three-state cio w/pull-down 0.0 0.8 2.0 5.5 0 400 a 2.4 0.4 10.0 7.0 k8 -5.0v-tolerant lvttl test 50 ohm three-state cio w/pull-up 0.0 0.8 2.0 5.5 -250 a 0 2.4 0.4 10.0 7.0 l13 -5.0v-tolerant lvttl non-test 50 ohm three-state cio w/pull-up 0.0 0.8 2.0 5.5 -250 a 0 2.4 0.4 10.0 7.0 m12 -5.0v-tolerant lvttl non-test 50 ohm three-state cio 0.0 0.8 2.0 5.5 0 0 2.4 0.4 10.0 7.0 n3 -3.3v sti non-test differential receiver -0.5 v ref +0.5 v ref +0.5 v ddq +0.3 00----1 p1 -3.3v sti non-test differential driver v oh minimum voltage: v ddq =-0.4v v ol maximum voltage = 0.4v 10.0 7.0 1 q1 -3.3v lvttl test di1 receiver w/pull-up 0.0 0.8 2.0 v dd + 0.6 0400 a- - - - r1 -3.3v lvttl test di2 receiver w/pull-up 0.0 0.8 2.0 v dd + 0.6 0400 a- - - - s4 -3.3v lvttl test receiver w/pull-up 0.0 0.8 2.0 v dd + 0.6 0 400 a ---- 1. v ref = differential input voltage. v ddq = output supply voltage. IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 book definitions page 531 of 553 t 1 -3.3v lvttl test ri receiver 0.0 0.8 2.0 v dd + 0.6 0400 a- - - - v1 -5.0v-tolerant lvttl test lt w/pull-up 0.0 0.8 2.0 5.5 0 400 a- - - - w23 -5.0v-tolerant lvttl test receiver w/pull-up 0.0 0.8 2.0 5.5 0 400 a- - - - x2 -5.0v-tolerant lvttl test receiver 0.0 0.8 2.0 5.5 0 0 - - - - z 4 -3.3v non-test 20 ohm 0.0 0.8 2.0 v dd + 0.6 002.40.4 23.0/ 12.0 16.0 pll 3 pll(phaselockedloopthat connects at i/o pads) 0.0 0.8 2.0 v dd + 0.6 00---- book definitions (page 2 of 2) book name insta nces description v il (v) v ih (v) i il (@0v) max i ih (@v dd ) max v oh (v) min v ol (v) min i oh (ma) min i ol (ma) min note min max min max 1. v ref = differential input voltage. v ddq = output supply voltage. IBM2520L8767 ibm processor for atm resources phy timing page 532 of 553 atmrm.chapt07.01 08/27/99 ac timing characteristics phy timing description min max units fytwrb high to fytdat[15:0] 20 ns fytwrb high to fytpar[1:0] 20 ns fytwrb high to fytsoc 20 ns fytwrb high to fy0tenb 20 ns fytca to fytwrb setup 9 -- ns fytca to fytwrb hold 0 -- ns fy0ful to fytwrb setup 9 -- ns fy0ful to fytwrb hold 0 -- ns fyrrdb high to fyrenb 20 ns fyrdat[15:0] to fyrrdb setup 9 -- ns fyrdat[15:0] to fyrrdb hold 0 -- ns fyrpar[1:0] to fyrrdb setup 9 -- ns fyrpar[1:0] to fyrrdb hold 0 -- ns fyrsoc to fyrrdb setup 9 -- ns fyrsoc to fyrrdb hold 0 -- ns fy0ful to fyrrdb setup 9 -- ns fy0ful to fyrrdb hold 0 -- ns fy0emp to fyrrdb setup 9 -- ns fy0emp to fyrrdb hold 0 -- ns fy0discrd to fyrrdb setup 9 -- ns fy0discrd to fyrrdb hold 0 -- ns fy0setclp to fyrrdb setup 9 -- ns fy0setclp to fyrrdb hold 0 -- ns fy0dtct to fyrrdb setup 9 -- ns fy0dtct to fyrrdb hold 0 -- ns IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 npbus sideband interface timing page 533 of 553 npbus sideband interface timing i/o pci bus timing npbus timing description min max units refclk high to pbdata[7:0] 35 ns refclk high to pbdatap 35 ns refclk high to pbrnwrt 15 ns refclk high to pbrdrdy 25 ns refclk high to pbaddr[15:0] 30 ns pbdata[7:0] to refclk setup 30 -- ns pbdata[7:0] to refclk hold 0 -- ns pbdatap to refclk setup 30 -- ns pbdatap to refclk hold 0 -- ns pbrdrdy to refclk setup 15 -- ns pbrdrdy to refclk hold 0 -- ns pbrnwrt to refclk setup 15 -- ns pbrnwrt to refclk hold 0 -- ns pci bus timing (page 1 of 2) description min max units refclk high to pad[31:0] 2 11 ns refclk high to ppar 2 11 ns refclk high to pcbe[3:0] 2 11 ns refclk high to mframe 2 11 ns refclk high to mtrdy 2 11 ns refclk high to mirdy 2 11 ns refclk high to mstop 2 11 ns refclk high to mdevsel 2 11 ns refclk high to u0req 2 11 ns refclk high to mperr 2 11 ns refclk high to mserr 2 11 ns refclk high to minita 2 11 ns refclk high to u0int2 2 12 ns refclk high to ule0be 2 11 ns IBM2520L8767 ibm processor for atm resources page 534 of 553 atmrm.chapt07.01 08/27/99 refclk high to u0dir 2 11 ns mframe to refclk setup 7 -- ns mframe to refclk hold 0 -- ns pcbe[3:0] to refclk setup 7 -- ns pcbe[3:0] to refclk hold 0 -- ns pad[31:0] to refclk setup 7 -- ns pad[31:0] to refclk hold 0 -- ns ppar to refclk setup 7 -- ns ppar to refclk hold 0 -- ns mperr to refclk setup 7 -- ns mperr to refclk hold 0 -- ns pidsel to refclk setup 7 -- ns pidsel to refclk hold 0 -- ns mdevsel to refclk setup 7 -- ns mdevsel to refclk hold 0 -- ns mtrdy to refclk setup 7 -- ns mtrdy to refclk hold 0 -- ns mirdy to refclk setup 7 -- ns mirdy to refclk hold 0 -- ns mlocktorefclksetup 7 -- ns mlocktorefclkhold 0 -- ns mstoptorefclksetup 7 -- ns mstoptorefclkhold 0 -- ns u0extio to refclk setup 27 -- ns u0extio to refclk hold 0 -- ns u0extpm to refclk setup 27 -- ns u0extpm to refclk hold 0 -- ns u0gnt to refclk setup 10 -- ns u0gnt to refclk hold 0 -- ns pci bus timing (page 2 of 2) description min max units IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 synchronous dram timing page 535 of 553 synchronous dram timing sdram read cycle (1 of 4) sdram read cycle (2 of 4) t1 t2 t3 t4 t5 t6 t7 row column data out cmclk cmsras camras0 cmscas cmwe0 cmcas0 cmaddr cmdata t1 t2 t3 t4 t5 t6 t7 row xxxxxxxxxxx data out column cmclk cmsras camras0 cmscas cmwe0 cmcas0 cmaddr cmdata t8 IBM2520L8767 ibm processor for atm resources sdram read cycle page 536 of 553 atmrm.chapt07.01 08/27/99 sdram read cycle (3 of 4) sdram read cycle (4 of 4) t1 t2 t3 t4 t5 t6 t7 row column data out cmclk cmsras camras0 cmscas cmwe0 cmcas0 cmaddr cmdata t1 t2 t3 t4 t5 t6 t7 row data out column cmclk cmsras camras0 cmscas cmwe0 cmcas0 cmaddr cmdata t8 IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 sdram write cycle page 537 of 553 sdram write cycle (1 of 4) cmclk t1 zzzzzzzzzzz t2 t3 t4 t5 t6 t7 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata xxxxxxxx xxxxxx col xxxxxxxxxx row zzzzzzzz xxxxxx data cas latency=2, burst length=1 IBM2520L8767 ibm processor for atm resources sdram write cycle page 538 of 553 atmrm.chapt07.01 08/27/99 sdram write cycle (2 of 4) cmclk t1 xxxxxx t2 t3 t4 t5 t6 t7 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata cas latency=3, burst length=1 xxxxxxxx row zzzzzzzz xxxxxxxxxx col xxxxxx zzzzzzzzzzz data IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 sdram write cycle page 539 of 553 sdram write cycle (3 of 4) cmclk data t1 t2 t3 t4 t5 t6 t7 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata cas latency=2, burst length=2 xxxxxxxx row col xxxxxxxxx zzzzzzzzzz zzzzzzzzzzz 00000000 IBM2520L8767 ibm processor for atm resources sdram write cycle page 540 of 553 atmrm.chapt07.01 08/27/99 sdram write cycle (4 of 4) t9 cmclk t1 t2 t3 t4 t5 t6 t7 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata cas latency=3, burst length=2 t8 xxxxxxxx row col xxxxxxx zzzzzzzz 00000000 data zzzzzzzz IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 sdram write of 64-byte burst with cas latency=2 page 541 of 553 sdram write of 64-byte burst with cas latency=2 cas latency=2, burst length=2 cmclk t1 t2 t3 t4 t5 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata t17 t18 xxx row col0 col1 col2 zzzzzzzz data 0 data 1 data 2 t19 t20 t21 t22 t23 t24 t25 data 14 data 15 zzzzzzzz col 14 col 15 xxxxxxxx t6 IBM2520L8767 ibm processor for atm resources sdram write of 64-byte burst with cas latency=3 page 542 of 553 atmrm.chapt07.01 08/27/99 sdram write of 64-byte burst with cas latency=3 cas latency=3, burst length=2 cmclk t1 t2 t3 t4 t5 cmcas0 cmwe0 cmscas cmras0 cmsras cmaddr cmdata t18 t19 xxx t20 t21 t22 data 14 data 15 t6 xxxxxxxx t23 col0 row col1 col 14 col 15 zzzzzzzz data 1 data 0 zzzzzzzz IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 sram timing page 543 of 553 sram timing sram read cycle cmclk cmwe0 cmaddr cmdata zzzzzzzz xxxxxxxx zzz 56 1234 addr xxxxxxxx cmras1 (chip select 1) (35:0) cmbe cmsyncas + cmdata (35:38) data IBM2520L8767 ibm processor for atm resources sram write cycle page 544 of 553 atmrm.chapt07.01 08/27/99 sram write cycle cmclk f cmwe0 cmras1 cmaddr cmdata acmbe xxxxxxxx addr t5 t6 t1 t2 t3 t4 zzzzzzzz data zzzzzzzz f0 IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 sram read cycle with byte enables page 545 of 553 sram read cycle with byte enables cmclk cmwe0 cmras1 cmaddr cmdata 56 1234 f addr 0 zzzzzzzz xxxxxxxx f zzzzzzzz data xxxxxxxx cmbe cmsyncas + cmdata (38:35) (35:0) (chip select 1) IBM2520L8767 ibm processor for atm resources sramwritecyclewithbyteenables page 546 of 553 atmrm.chapt07.01 08/27/99 sram write cycle with byte enables cmclk cmwe0 cmras1 cmaddr cmdata acmbe t5 t6 t1 t2 t3 t4 data zzzzzzzz f addr 0 zzzzzzzz xxxxxxxx f IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 eprom timing page 547 of 553 eprom timing parallel eprom read zzzz t1 t3 t5 t7 t9 clock (pci iclk) pbphy1 pbale1 pbale2 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbeprm pbdata t11t13t15t17 (7:0) dont care dont care addr1 addr2 xxxx xxxx data IBM2520L8767 ibm processor for atm resources parallel eprom write page 548 of 553 atmrm.chapt07.01 08/27/99 parallel eprom write xxxx t1 t3 t5 t7 t9 t11 t13 t15 t17 dont care dont care addr1 addr2 data clock (pci iclk) pbphy1 pbale1 pbale2 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbeprm pbdata (7:0) IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 serial eprom read page 549 of 553 serial eprom read serial eprom read follows i2c bus protocol pbsdata is single sequence split over several lines) pbsclk pbsdata pbsdata pbsdata pbsdata (continued) (continued) (continued) IBM2520L8767 ibm processor for atm resources serial eprom write page 550 of 553 atmrm.chapt07.01 08/27/99 serial eprom write pbsclk pbsdata pbsdata pbsdata (continued) (continued) serial eprom write follows i2c bus protocol pbsdata is single sequence split over several lines) IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 phy timing page 551 of 553 phy timing phy read dont care t1 t3 t5 t7 t9 t11 t13 t15 t17 xxxx addr1 addr2 data xxx zzzz dont care clock (pci iclk) pbphy1 pbale1 pbale2 pbaddr16 pbaddr17 pbrnwrt pdrdrdy pbeprm pbdata (7:0) IBM2520L8767 ibm processor for atm resources phy write page 552 of 553 atmrm.chapt07.01 08/27/99 phy write xxxx t1 t3 t5 t7 t9 /b30 /apb0phy1 /apbale1 /apbale2 /apbaddr16 /apbaddr17 /apbrnwrt /apbrdrdy /apb0eprm apbdata t11 t13 t15 t17 (7:0) dont care dont care addr1 addr2 data IBM2520L8767 ibm processor for atm resources atmrm.chapt07.01 08/27/99 revision log page 553 of 553 revision log rev. description 12/15/98 initial release (00). 08/27/99 first revision (01). no content changes. refined format and corrected typographical errors. |
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