2.5v/3.3v, 200 mhz multi-output zero delay buffer z9960 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07087 rev. *b revised december 21, 2002 features ? 2.5v or 3.3v operation output frequency up to 200 mhz supports powerpc ? , and pentium ? processors 21 clock outputs: drive up to 42 clock lines lvpecl or lvcmos/lvttl clock input output-to-output sskew < 150 ps split 2.5v/3.3v outputs spread spectrum compatible glitch-free output clocks transitioning output disable control pin-compatible with mpc9600 industrial temperature range: ? 40 c to +85 c 48-pin lqfp package table 1. frequency table [1] s e l aqa s e l bqb s e l cqc f b _ s e lfb_out 0 vco/2 0 vco/2 0 vco/2 0 vco/8 1 vco/4 1 vco/4 1 vco/4 1 vco/12 note: 1. input frequency range: 16 mhz to 33 mhz (fb_sel = 1), or 25 mhz to 50 mhz (fb_sel = 0). /2 /4 /8 /12 ref_sel tclk pecl_clk pecl_clk# fb_in sela selb selc fb_sel oe# fb_out 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 d q d q d q d q 0 1 0 1 0 1 0 1 fb c b a 0 1 ref fb 0 1 avdd pll block diagram pin configuration z9960 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 vss tclk pecl_clk pecl_clk# vdd ref_sel fb_sel avdd sela selb selc vssc vddc oe# qc6 qc5 vssc qc4 qc3 vddc qc2 qc1 qc0 vssb vss fb_in qa0 qa1 vdda qa2 qa3 vssa qa4 qa5 qa6 vdda vssa fb_out qb0 qb1 vddb qb2 qb3 vssb qb4 qb5 qb6 vddb
z9960 document #: 38-07087 rev. *b page 2 of 7 a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (< 0.2 ? ). if these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. pin definitions pin name pin no. pin type pin description pecl_clk 3 i, pd pecl clock input . pecl_clk# 4 i, pu pecl clock input . tclk 2 i, pd external reference/test clock input . qa(6:0) 38, 39, 40, 42, 43, 45, 46 o v dda clock outputs . see table 1 for frequency selections. qb(6:0) 26, 27, 28, 30, 31, 33, 34 o v ddb clock outputs . see table 1 for frequency selections. qc(6:0) 15, 16, 18, 19, 21, 22, 23 o v ddc clock outputs . see table 1 for frequency selections. fb_out 35 o v dd feedback clock output . connect to fb_in for normal operation. the divider ratio for this output is set by fb_sel; see table 1 . a bypass delay capacitor at this output will control input reference/ output banks phase relationships. sela 9 i, pu frequency select inputs . these inputs select the divider ratio at qa(0:6) outputs. see table 1 . selb 10 i, pu frequency select inputs . these inputs select the divider ratio at qb(0:6) outputs. see table 1 . selc 11 i, pu frequency select inputs . these inputs select the divider ratio at qc(0:6) outputs. see table 1 . fb_sel 7 i, pu feedback select inputs . these inputs select the divide ratio at fb_out output. see table 1 . fb_in 47 i, pd feedback clock input . connect to fb_out for accessing the pll. ref_sel 6 i, pu reference select input . when high, the pecl clock is selected. and when low, tclk is the reference clock. oe# 14 i, pd output enable input . when asserted low, enables all of the outputs. when pulled high, disables to high impedance all of the outputs except fb_out. v dda 37, 44 power supply for bank a clock buffers v ddb 25, 32 power supply for bank b clock buffers v ddc 13, 20 power supply for bank c clock buffers v dd 5 power supply for core av dd 8 power supply for pll . when avdd is set low, pll is bypassed. v ssa 36, 41 common ground for bank a v ssb 24, 29 common ground for bank b v ssc 12, 17 common ground for bank c v ss 1, 48 common ground
z9960 document #: 38-07087 rev. *b page 3 of 7 overview the z9960 has an integrated pll that provides low skew and low jitter clock outputs for high-performance microprocessors. three independent banks of seven outputs as well as an independent pll feedback output, fb_out, provide excep- tional flexibility for possible output configurations. the pll is ensured stable operation given that the vco is configured to run between 200 mhz to 400 mhz. this allows a wide range of output frequencies up to 200 mhz. the phase detector compares the input reference clock to the external feedback input. for normal operation, the external feedback input, fb_in, is connected to the feedback output, fb_out. the internal vco is running at multiples of the input reference clock set by fb_sel select inputs; refer to table 1 . the vco frequency is then divided down to provide the required output frequencies. zero delay buffer when used as a zero delay buffer the z9960 will likely be in a nested clock tree application. for these applications the z9960 offers a low-voltage pecl clock input as a pll reference. this allows the user to use lvpecl as the primary clock distribution device to take advantage of its far-superior skew performance. the z9960 then can lock onto the lvpecl reference and translate with near zero delay to low skew outputs. by using one of the outputs as a feedback to the pll, the propagation delay through the device is eliminated. the pll works to align the output edge, with the input reference edge thus producing a near-zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. because the static phase offset is a function of the reference clock, the tpd of the z9960 is a function of the configuration used. absolute maximum ratings [2] input voltage relative to v ss : .............................. v ss ? 0.3v input voltage relative to v dd : ..............................v dd + 0.3v storage temperature:................................. -65 c to + 150 c operating temperature: ............................... -40 c to + 85 c maximum esd protection ............................................... 2kv maximum power supply:................................................ 5.5v maximum input current: ................................................. 20ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). note: 2. the voltage on any input or i/o or pin cannot exceed the power pin during power-up. power supply sequencing is not required. function table control pin 0 1 ref_sel tclk pecl_clk avdd pll bypass, outputs controlled by oe# pll power oe# outputs enabled outputs disabled (except fb_out) sela output bank a at vco/2 output bank a at vco/4 selb output bank b at vco/2 output bank b at vco/4 selc output bank c at vco/2 output bank c at vco/4 fb_sel feedback output at vco/8 feedback output at vco/12
z9960 document #: 38-07087 rev. *b page 4 of 7 dc electrical characteristics v dd = 2.5v 5%, t a = ? 40 c to +85 c parameter description test condition min. typ. max. unit v il [3] input low voltage v ss -0.7v v ih [3] input high voltage 1.7 - v dd v v pp peak-to-peak input voltage pecl_clk 500 - 1000 mv vcmr [4] common mode range pecl_clk v dd ? 1.4 - v dd ? 0.6 v i il [5] input low current (@ v il = v ss ) ? 120 a i ih [5] input high current (@ v ih = v dd ) 120 a v ol [6] output low voltage i ol = 15 ma 0.6 v v oh [6] output high voltage i oh = ? 15 ma 1.8 v i dd quiescent supply current v dd and av dd -1013ma c in input pin capacitance - 4 - pf notes: 3. the lvcmos inputs threshold is at 30% of v dd . 4. the vcmr is the difference from the most positive side of the differential input signal. normal operation is obtained when hi gh input is within the vcmr range and the input lies within the v pp specification. 5. inputs have pull-up/pull-down resistors that affect input current . 6. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines. dc electrical characteristics v dd = 3.3v + 5%, t a = ? 40 c to +85 c parameter description test condition min. typ. max. unit v il [3] input low voltage v ss -0.8v v ih [3] input high voltage 2.0 - v dd v v pp peak-to-peak input voltage pecl_clk 500 - 1000 mv vcmr [4] common mode range pecl_clk v dd ? 1.4 - v dd ? 0.6 v i il [5] input low current (@ v il = v ss ) ? 120 a i ih [5] input high current (@ v ih = v dd ) 120 a v ol [6] output low voltage i ol = 24 ma 0.55 v v oh [6] output high voltage i oh = ? 24 ma 2.4 v i dd quiescent supply current v dd and av dd -1520ma c in input pin capacitance - 4 - pf
z9960 document #: 38-07087 rev. *b page 5 of 7 ac electrical characteristics v dd = 2.5v 5% or 3.3v 5%, t a = ? 40 c to +85 c [7] symbol parameter test condition min. typ. max. unit fref reference input frequency fb_sel = 1 16 33 mhz fb_sel = 0 25 50 frefdc reference input duty cycle 25 75 % fvco pll vco lock range 200 400 mhz tlock maximum pll lock time 10 ms tr / tf output clocks rise / fall time [8],[9] 0.55v to 2.0v, v dd = 3.3v 0.1 1.0 ns 0.5v to 1.8v, v dd = 2.5v fout maximum output frequency q ( 2) 100 200 mhz q ( 4) 50 100 foutdc output duty cycle [8],[9] 45 50 55 % tpzl, tpzh output enable time [8] (all out- puts) 210ns tplz, tphz output disable time [8] (all out- puts) 28ns tccj cycle to cycle jitter [8],[9] +/- 100 ps tskew any output to any output skew [8],[9] same frequency 150 ps different frequency 300 tskew bank to bank skew banks at different voltages 400 ps tskew(pp) part to part skew [10] 450 ps tpd phase er- ror [8],[9] tclk or pecl_clk to fb_in v dd = 3.3v 0 100 200 ps v dd = 2.5v 25 125 225 note: 7. parameters are guaranteed by design and characterization. not 100% tested in production. 8. outputs loaded with 30pf each. 9. 50 ? transmission line terminated into vdd/2. 10. part to part skew at a given temperature and voltage ordering information ordering code package name package type z9960al 48 lqfp industrial, -40 c to +85 c the ordering part number is formed by a combination of device number, device revision, package style, and screening, as shown below. example: cypress z9960al date code, lot # z9960al package l = lqfp revision device number
z9960 document #: 38-07087 rev. *b page 6 of 7 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. powerpc is a trademark of ibm ? . pentium ? is a trademark of intel corporation. all product or company names mentioned in this document are the trademarks of their respective holders. package diagram d d 1 a 2 b e 10 a l a 1 48 pin lqfp outline dimensions inches millimeters symbol min. nom. max. min. nom. max. a - - 0.063 - - 1.60 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.053 - 0.057 1.35 - 1.45 d-0.354--9.00- d 1 - 0.276 - - 7.00 - b 0.007 - 0.011 0.17 - 0.27 e 0.02 bsc 0.50 bsc l 0.018 - 0.030 0.45 - 0.75
z9960 document #: 38-07087 rev. *b page 7 of 7 document title: z9960 2.5v/3.3v, 200 mhz multi-output zero delay buffer document number: 38-07087 rev. ecn no. issue date orig. of change description of change ** 107123 06/06/01 ika convert from imi to cypress *a 108715 11/07/01 ndp updated avdd pin functionality. *b 122772 12/21/02 rbi add power up requirements to maximum ratings information
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