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nx2138 1 rev. 1.6 12/09/09 typical application description the nx2138 controller ic is a compact buck controller ic with 16 lead mlpq package designed for step down dc to dc converter in portable applications. it can be selected to operate in synchronous mode or non-syn- chronous mode to improve the efficiency at light load.constant on time control provides fast response, good line regulation and nearly constant frequency un- der wide voltage input range. the nx2138 controller is optimized to convert single supply up to 24v bus volt- age to as low as 0.75v output voltage. over current protection and fb uvlo followed by latch feature. other features includes: internal boost schottky diode, 5v gate drive capability, power good indicator, over current pro- tection, over voltage protection and adaptive dead band control. n internal boost schottky diode n ultrasonic mode operation available n bus voltage operation from 4.5v to 24v n less than 1ua shutdown current with enable low n excellent dynamic response with constant on time control n selectable between synchronous ccm mode and diode emulation mode to improve efficiency at light load n programmable switching frequency n current limit and fb uvlo with latch off n over voltage protection with latch off n power good indicator available n pb-free and rohs compliant ordering information features single channel mobile pwm controller applications n notebook pcs and desknotes n tablet pcs/slates n on board dc to dc such as 12v to 3.3v, 2.5v or 1.8v n hand-held portable instruments production data sheet figure1 - typical application of nx2138 device temperature package pb-free NX2138CMTR -10 o c to 100 o c 4x4 mlpq-16l yes pb free product vin 7v~22v ton hdrv bst sw ldrv ocset fb vout ensw /mode 5v 10 vcc pvcc pgood vout 1.8v/7a agnd pgood 1meg 4 9 2 15 6 3 1 10 8 11 13 12 16 100k 1u 1u 7.5k 10.5k 2r5tpe330mc 5k 1u 2x10uf 1n irf7807 ao4714 1.5uh n x 2 1 3 8 330uf pgnd 7 nc 2 nc 14 2.2
nx2138 2 rev. 1.6 12/09/09 9 10 11 12 4 3 2 1 vcc ton fb pgood pvcc ocset sw hdrv 8 7 6 5 pgnd ldrv nc agnd 16 15 14 13 nc vo ensw/mode bst pad 17 absolute maximum ratings vcc,pvcc to gnd & bst to sw voltage ............ -0.3v to 6.5v ton to gnd ......................................................... -0.3v to 28v hdrv to sw voltage .......................................... -0.3v to 6.5v sw to gnd ......................................................... -2v to 30v all other pins ........................................................ vcc+0.3v storage temperature range ..................................-65 o c to 150 o c operating junction temperature range .................-40 o c to 150 o c esd susceptibility ............................................... 2kv caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 4x4 16-lead plastic mlpq electrical specifications unless otherwise specified, these specifications apply over vcc =5v, vin=15v and t a =25 o c , unless otherwise specified. o ja cw q?46/ parameter sym test condition min typ max units vin recommended voltage range 4.5 24 v shut down current ensw=gnd 1 ua vcc,pvcc supply input voltage range v in 4.5 5.5 v operating quiescent current no switching, ensw=5v 1.6 ma shut down current ensw=gnd 1 ua
nx2138 3 rev. 1.6 12/09/09 n parameter sym test condition min typ max units vcc uvlo under-voltage lockout threshold v cc _uvlo 3.9 4.1 4.5 v falling vcc threshold 3.7 3.9 4.3 v on and off time ton operating current vin=15v, rton=1mohm 15 ua on -time vin=9v,vout=0.75v,rton= 1mohm 312 390 468 ns minimum off time 380 590 800 ns fb voltage internal fb voltage vref 0.739 0.75 0.761 v input bias current 100 na line regulation vcc from 4.5 to 5.5 -1 1 % output voltage output range 0.75 3.3 v vout shut down discharge resistance ensw/mode=gnd 30 ohm soft start time 1.5 ms pgood power good high rising threshold 90 % vref pgood propagation delay filter note1 2 us power good hysteresis note1 5 % pgood output switch impedance 13 ohm pgood leakage current 1 ua sw zero cross comparator offset voltage 5 mv high side driver (cl=3300pf) output impedance , sourcing current r source (hdrv) i=200ma 1.5 ohm output impedance , sinking current r sink (hdrv) i=200ma 1.5 ohm rise time thdrv(rise) 10% to 90% 50 ns fall time thdrv(fall) 90% to 10% 50 ns deadband time tdead(l to h) ldrv going low to hdrv going high, 10% to 10% 30 ns low side driver (cl=3300pf) output impedance, sourcing current r source (ldrv) i=200ma 1.5 ohm output impedance, sinking current r sink (ldrv) i=200ma 0.5 ohm rise time tldrv(rise) 10% to 90% 50 ns fall time tldrv(fall) 90% to 10% 50 ns 10 ns deadband time tdead(h to l) sw going low to ldrv going high, 10% to 10%
nx2138 4 rev. 1.6 12/09/09 parameter sym test condition min typ max units ensw/mode threshold and bias current pfm/non synchronous mode 80% vcc vcc+0 .3v v ultrasonic mode 60% vcc 80% vcc v synchronous mode leave it open or use limits in spec 2 60% vcc v shutdown mode 0 0.8 v ensw/mode=vcc 5 ua ensw/mode=gnd -5 ua current limit ocset setting current 20 24 28 ua over temperature threshold 155 o c hysteresis 15 o c under voltage fb threshold 70 %vref over voltage over voltage tripp point 125 %vref internal schottky diode forward voltage drop forward current=50ma 500 mv input bias current
nx2138 5 rev. 1.6 12/09/09 pin descriptions pin number pin symbol pin description this pin is directly connected to the output of the switching regulator and senses the vout voltage. an internal mosfet discharges the output during turn off. this pin supplies the internal 5v bias circuit. a 1uf x7r ceramic capacitor is placed as close as possible to this pin and ground pin. this pin is the error amplifiers inverting input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage from 0.75v to 3.3v. pgood indicator for switching regulator. it requires a pull up resistor to vcc or lower voltage. when fb pin reaches 90% of the reference voltage pgood transitions from lo to hi state. not used. analog ground. power ground. low side gate driver output. provide the voltage supply to the lower mosfet drivers. place a high frequency decoupling capacitor 1uf x5r to this pin. this pin is connected to the drain of the external low side mosfet and is the input of over current protection(ocp) comparator. an internal current source is flown to the external resistor which sets the ocp voltage across the rdson of the low side mosfet. this pin is connected to source of high side fets and provide return path for the high side driver. it is also the input of zero current sensing comparator. high side gate driver output. this pin supplies voltage to high side fet driver. a high freq 1uf x7r ceramic capacitor and 2.2ohm resistor in series are recommended to be placed as close as possible to and connected to this pin and sw pin. not used. switching converter enable input. connect to vcc for pfm/non synchronous mode, connected to an external resistor divider equals to 70%vcc for ultra- sonic, connected to gnd for shutdown mode, floating or connected to 2v for the synchronous mode. vin sensing input. a resistor connects from this pin to vin will set the fre- quency. a 1nf capacitor from this pin to gnd is recommended to ensure the proper operation. used as thermal pad. connect this pad to ground plane through multiple vias. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vout vcc fb pgood nc agnd pgnd ldrv pvcc ocset sw hdrv bst nc ensw/ mode ton pad
nx2138 6 rev. 1.6 12/09/09 block diagram figure 2 - simplified block diagram of the nx2138 vin bst(13) hdrv(12) ldrv(8) sw(11) pvcc(9) 5v fet driver start odb hd_in start vout(1) 0.9*vref ss_finished pgood(4) ocset(10) ensw /mode(15) start por fb(3) ton(16) hd vref=0.75v fbuvlo_latch r s q mini offtime 400ns ocp_comp hd diode emulation ocp_comp 0.7*vref fb 1.25*vref/0.7vref fb ovp fbuvlo_latch vout sync pfm_nonultrasonic 4.3/4.1 vcc(2) bias por disable disable_b vout vin 1.8v thermal shutdown soft start on time pulse genearation vout mode selection vcc 1m 1m agnd(6) pgnd(7)
nx2138 7 rev. 1.6 12/09/09 figure 3 - demo board schematic 2.2 1.5n vin 7v~22v ton hdrv bst sw ldrv ocset fb vout ensw /mode 5v 10 vcc pvcc pgood vout 1.8v/7a agnd pgood 1meg 4 9 2 15 6 3 1 10 8 11 13 12 16 100k 1u 1u 2r5tpe330mc 5k 1u 1n irf7807 ao4714 1.5uh n x 2 1 3 8 330uf pgnd 7 nc 2 nc 14 r1 r2 c1 c2 c3 r4 r5 m1 m2 lo ci1 2x10uf co1 r3 c5 7.5k 10.5k r6 r7 c4 2.2 r8 typical application (vin=7v to 22v, vout=1.8v/7a)
nx2138 8 rev. 1.6 12/09/09 bill of materials item quantity reference value manufacture 1 2 ci1 10uf/x5r/25v 2 1 co1 2r5tpe330mc sanyo 3 2 c1,c2,c4 1uf 4 2 c3 1nf 5 1 c5 1.5nf 6 1 lo do5010h-152 coilcraft 7 1 m1 irf7807 ir 8 1 m2 ao4714 ir 9 1 r1 100k 10 1 r2 10 11 2 r3,r8 2.2 12 1 r4 1m 13 1 r5 5k 14 1 r6 10.5k 15 1 r7 7.5k 16 1 u1 nx2138 nexsem inc.
nx2138 9 rev. 1.6 12/09/09 demoboard waveforms fig.4 startup (ch2 1.8v output, ch3 pgood) fig.5 turn off (ch2 1.8v output, ch3 pgood) fig. 9 output ripple at full load (ch1 sw, ch2 1.8v output ac, ch4 output current) fig.7 output transient in pfm mode (ch1 sw, ch2 1.8v output ac, ch4 output current) fig.8 start into short (ch3 vout, ch4 output current) fig. 10 output ripple at light load in pfm mode(ch1 sw, ch2 1.8v output ac)
nx2138 10 rev. 1.6 12/09/09 fig. 11 output ripple at no load in synchronous mode (ch1 sw, ch2 1.8v output ac, ch4 output current) demoboard waveforms(cont') fig. 12 dynamic response in synchronous mode (ch2 1.8v output ac, ch4 output current) fig. 13 dynamic response in synchronous mode (ch2 1.8v output ac, ch4 output current) fig. 14 dynamic response in pfm mode (ch2 1.8v output ac, ch4 output current) fig. 15 dynamic response in pfm mode (ch2 1.8v output ac, ch4 output current) vin=12v, vout=1.8v 50.00% 55.00% 60.00% 65.00% 70.00% 75.00% 80.00% 85.00% 90.00% 95.00% 10 100 1000 10000 output current(ma) output efficiency(%) fig. 16 output efficiency
nx2138 11 rev. 1.6 12/09/09 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - working frequency d i ripple - inductor current ripple design example the following is typical application for nx2138, the schematic is figure 1. v in = 7 to 22v v out =1.8v f s =220khz i out =7a d v ripple <=60mv d v droop <=60mv @ 3a step on_time and frequency calculation the constant on time control technique used in nx2138 delivers high efficiency, excellent transient dy- namic response, make it a good candidate for step down notebook applications. an internal one shot timer turns on the high side driver with an on time which is proportional to the input supply v in as well inversely proportional to the output voltage v out . during this time, the output inductor charges the output cap increasing the output voltage by the amount equal to the output ripple. once the timer turns off, the hdrv turns off and cause the output voltage to decrease until reaching the internal fb volt- age of 0.75v on the pfm comparator. at this point the comparator trips causing the cycle to repeat itself. a minimum off time of 400ns is internally set. the equation setting the on time is as follows: 12 tonout in 4.4510rv ton v0.5v - = - ...(1) out s in v f vton = ...(2) in this application example, the rton is chosen to be 1mohm , when vin=22v, the ton is 372ns and f s is around 220khz. output inductor selection the value of inductor is decided by inductor ripple current and working frequency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and lower efficiency. the ripple current is a design free- dom which can be decided by design engineer accord- ing to various application requirements. the inductor value can be calculated by using the following equa- tions: ( ) inout on out ripple rippleoutput v-vt l= i i=ki ...(3) where k is percentage of output current. in this example, inductor from coilcraft do5010h-152 with l=1.5uh is chosen. current ripple is recalculated as below: inout on ripple out (v-v)t i= l (22v-1.8v)372ns = 1.5uh =5a ...(4) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specifica- tion for the load transient. the optimum design may require a couple of iterations to satisfy both conditions. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(5). d d=d+ ripple rippleripple sout i vesri 8fc ...(5) where esr is the output capacitors' equivalent series resistance,c out is the value of output capaci- tors. typically poscap is recommended to use in nx2139's applications. the amount of the output volt- age ripple is dominated by the first term in equation(5)
nx2138 12 rev. 1.6 12/09/09 and the second term can be neglected. for this example, one poscap 2r5tpe330mc is chosen as output capacitor, the esr and inductor current typically determines the output voltage ripple. when vin reach maximum voltage, the output volt- age ripple is in the worst case. ripple desire ripple v 60mv esr=12m i5a d ==w d ...(6) if low esr is required, for most applications, mul- tiple capacitors in parallel are needed. the number of output capacitor can be calculate as the following: eripple ripple esri n v d = d . ..(7) 12m5a n 60mv w = n =1 the number of capacitor has to be round up to a integer. choose n =1. based on transient requirement typically, the output voltage droop during tran- sient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the over- shoot when load from high load to light load with a di step transient load, if assuming the bandwidth of sys- tem is high enough, the overshoot can be estimated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(8) where t is the a function of capacitor,etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(9 where outouteeout crit stepstep esrcvesrcv l ii == dd ...(10) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency ca- pacitor such as electrolytic capacitor, the product of esr and capacitance is high and crit ll is true. in that case, the transient spec is mostly like to depen- dent on the esr of capacitor. most case, the output capacitor is multiple ca- pacitor in parallel. the number of capacitor can be cal- culated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(11) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(12) for example, assume voltage droop during tran- sient is 60mv for 3a load step. if one poscap 2r5tpe330mc(330uf, 12mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 12m3300f1.8v 23.76h 3a == d wm =m the selected inductor is 1.5uh which is smaller than critical inductance. in that case, the output volt- age transient mainly dependent on the esr. number of capacitor is estep tran esri n v 12m3a 60mv 0.6 d = d w = = choose n=1.
nx2138 13 rev. 1.6 12/09/09 based on stability requirement esr of the output capacitor can not be chosen too low which will cause system unstable. the zero caused by output capacitor's esr must satisfy the re- quirement as below: sw esr out f 1 f 2esrc4 = p ...(13) besides that, esr has to be bigger enough so that the output voltage ripple can provide enough volt- age ramp to error amplifier through fb pin. if esr is too small, the error amplifier can not correctly dectect the ramp, high side mosfet will be only turned off for minimum time 400ns. double pulsing and bigger out- put ripple will be observed. in summary, the esr of output capacitor has to be big enough to make the sys- tem stable, but also has to be small enough to satify the transient and dc ripple requirements. input capacitor selection input capacitors are usually a mix of high fre- quency ceramic capacitors and bulk capacitors. ce- ramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the mosfets. usually 1uf ceramic capacitor is chosen to decouple the high frequency noise.the bulk input capacitors are decided by voltage rating and rms cur- rent rating. the rms current in the input capacitors can be calculated as: rmsout ons iid1-d dtf = = ...(14) when v in = 22v, v out =1.8v, i out =7a, the result of input rms current is 1.9a. for higher efficiency, low esr capacitors are recommended. one 10uf/x5r/25v and two 4.7uf/ x5r/25v ceramic capacitors are chosen as input capacitors. power mosfets selection the nx2138 requires at least two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source volt- age, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall con- verter efficiency. in this application, one irf7807 for high side and one ao4714 with integrated schottky di- ode for low side are used. there are two factors causing the mosfet power loss:conduction loss, switching loss. conduction loss is simply defined as: - + 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idrk p=i(1d)rk p=pp ...(15) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case. conduction loss should not exceed package rating or overall system thermal budget. switching loss is mainly caused by crossover conduction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(16) where i out is output current, t sw is the sum of t r and t f which can be found in mosfet datasheet, and f s is switching frequency. swithing loss p sw is fre- quency dependent. also mosfet gate driver loss should be consid- ered when choosing the proper power mosfet. mosfet gate driver loss is the loss generated by dis- charg i ng the gate capacitor and is dissipated in driver circuits.it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(17) where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. this power dissipation should not exceed maxi- mum power dissipation of the driver device. output voltage calculation output voltage is set by reference voltage and external voltage divider. the reference voltage is fixed
nx2138 14 rev. 1.6 12/09/09 mode selection nx2138 can be operated in pfm mode, ultrasonic pfm mode, ccm mode and shutdown mode by apply- ing different voltage on ensw/mode pin. when vcc applied to ensw/mode pin, nx2138 is in pfm mode. the low side mosfet emulates the function of diode when discontinuous continuous mode happens, often in light load condition. during that time, the inductor current crosses the zero ampere border and becomes negative current. when the inductor cur- rent reaches negative territory, the low side mosfet is turned off and it takes longer time for the output volt- age to drop, the high side mosfet waits longer to be turned on. at the same time, no matter light load and heavy load, the on time of high side mosfet keeps the same. therefore the lightier load, the lower the switching frequency will be. in ultrosonic pfm mode, the lowest frequency is set to be 25khz to avoid audio frequency modulation. this kind of reduction of fre- quency keeps the system running at light light with high efficiency. in ccm mode, inductor current zero-crossing sensing is disabled, low side mosfet keeps on even when inductor current becomes negative. in this way the efficiency is lower compared with pfm mode at light load, but frequency will be kept constant. over current protection over current protection for nx2138 is achieved by sensing current through the low side mosfet. an typical internal current source of 24ua flows through an external resistor connected from ocset pin to sw node sets the over current protection threshold. when synchronous fet is on, the voltage at node sw is given as swldson v=-ir the voltage at pin ocset is given as ocpocpsw ir+v when the voltage is below zero, the over current occurs as shown in figure below. ocp comparator ocp 24ua ocp i ocp r sw vbus figure 18 - over voltage protection the over current limit can be set by the following equation. = setocpocpdson iir/r if the low side mosfet r dson =10m w at the ocp occuring moment, and the current limit is set at 12a, then setdson ocp ocp ir 12a10m r5k i24ua w ===w choose r ocp =5k w power good output power good output is open drain output, a pull up resistor is needed. typically when softstart is at 0.75v. the divider consists of two ratioed resistors so that the output voltage applied at the fb pin is 0.75v when the output voltage is at the desired value. the following equation applies to figure 11, which shows the relationship between out v , ref v and volt- age divider. vout vref fb r2 r1 figure 17 - voltage divider 2ref 1 out ref rv r= v-v ...(18) where r 2 is part of the compensator, and the value of r 1 value can be set by voltage divider.
nx2138 15 rev. 1.6 12/09/09 finised and fb pin voltage is over 90% of v ref , the pgood pin is pulled to high after a 1.6ms delay. smart over output voltage protection active loads in some applications can leak cur- rent from a higher voltage than v out , cause output volt- age to rise. when the fb pin voltage is sensed over 112% of v ref , the high side mosfet will be turned off and low side mosfet will be turned on to discharge the v out . nx2138 resumes its switching operation after fb pin voltage drops to v ref . if fb pin voltage keeps rising and is sensed over 125% of v ref , the low side mosfet will be latched to be on to discharge the output voltage and over voltage protection is triggered. to resume the switching opera- tion, resetting voltage on pin vcc or pin en is neces- sary. under output voltage protection typically when the fb pin voltage is under 70% of v ref , the high side and low side mosfet will be turned off. to resume the switching operation, vcc or ensw has to be reset. layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy en- vironment is generated by the power components due to the switching power. small signal components are connected to sensitive pins or nodes. a multilayer lay- out which includes power plane, ground plane and sig- nal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practi- cally touching the drain pin of the upper mosfet, a plane connection is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired. 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane and as close as possible. a snubber needs to be placed as close to this junction as possible. 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be wide and short. a place for gate drv resistors is needed to fine tune noise if needed. 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals, should be kept away from the in- ductor and other noise sources. the resistor divider must be located as close as possible to the fb pin of the device. 9. all gnds need to go directly thru via to gnd plane. 10. in multilayer pcb, separate power ground and analog ground. these two grounds must be con- nected together on the pc board layout at a single point. the goal is to localize the high current path to a sepa- rate loop that does not interfere with the more sensi- tive analog control function.
nx2138 16 rev. 1.6 12/09/09 4x4 16 pin mlpq outline dimensions note: all dimensions are displayed in millimeters.

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