1 ps8131a 03/17/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features PI74ALVCT16260 is designed for low voltage operation v cc = 2.3v to 3.6v 5v tolerant inputs and outputs hysteresis on all inputs typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t a = 25c typical v ohv (output v oh undershoot) < 2.0v at v cc = 3.3v, t a = 25c industrial operation at ?40c to +85c packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v) PI74ALVCT16260 12-bit to 24-bit multiplexed d-type latch with 3-state outputs product description pericom semiconductors pi74alvct series of logic circuits are produced in the companys advanced 0.5 micron cmos technology, achieving industry leading speed. the PI74ALVCT16260 is a 12-bit to 24-bit multiplexed d-type latch designed for 2.3v to 3.6 vcc operation. it is used in applications where two separate datapaths must be multiplexed onto, or demultiplexed from, a single data path. typical applications include multiplexing and/or demulti-plexing address and data information in microprocessor or bus-interface applications. this device is also useful in memory-interleaving applications. three 12-bit i/o ports (a1-a12, 1b1-1b12, and 2b1-2b12) are available for address and/or data transfer. the output-enable (oe1b, oe2b, and oea) inputs control the bus transceiver functions. the oe1b and oe2b control signals also allow bank control in the a-to-b direction. address and/or data information can be stored using the internal storage latches. the latch-enable (le1b, le2b, lea1b, and lea2b) inputs are used to control data storage. when the latch-enable input is high, the latch is transparent. when the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. to ensure the high-impedance state during power up or power down, oe should be tied to vcc through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. the alvct16260 can be driven from either 3.3v or 5v devices allowing it to be used in mixed 3v/5v systems. logic block diagram g1 oe2b c1 1d 1 b 1 to 11 other channels oe1b oea a1 le1b le2b lea1b lea2b sel 1 1 c1 1d c1 1d c1 1d 2 b 1 23 6 28 8 1 29 56 55 30 27 2
2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8131a 03/17/98 PI74ALVCT16260 12-bit to 24-bit multiplexed d-type latch with 3-state outputs pin name description oe output enable input (active low) sel select le latch enable a,1b,2b data inputs a,1b,2b 3-state outputs gnd ground v cc power product pin description truth tables (1) b to a (oeb = h) inputs output a 1b 2b sel le1b le2b oea hx h h x l h lxh h x l l xx h l x l a 0 xh l x h l h xl l x h l l xx l x l l a 0 xx x x x h z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 note: 1. h = high signal level l = low signal level x = irrelevant z = high impedance product pin configuration 56-pin v56 a56 oea le1b 2b3 gnd 2b2 2b1 v cc a1 a2 a3 gnd a4 a5 a6 a7 a8 a9 gnd a10 a11 a12 v cc 1b1 1b2 gnd 1b3 le2b sel oe2b lea2b 2b4 gnd 2b5 2b6 v cc 2b7 2b8 2b9 gnd 2b10 2b11 2b12 1b12 1b11 1b10 gnd 1b9 1b8 1b7 v cc 1b6 1b5 gnd 1b4 lea1b oe1b a to b (oea = h) s t u p n is t u p t u o ab 1 a e lb 2 a e lb 1 e ob 2 e ob 1b 2 hh h l l h h lh h l l l l hh l l l h 0 b 2 lh l l l l 0 b 2 hl h l l 0 b 1h ll h l l 0 b 1l xl l l l 0 b 10 b 2 xx x h h z z xx x l h e v i t c az xx x h l z e v i t c a xx x l l e v i t c ae v i t c a
PI74ALVCT16260 12-bit to 24-bit multiplexed d-type latch with 3-state outputs 3 ps8131a 03/17/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 storage temperature ........................................................... ?65c to +150c ambient temperature with power applied ........................ ?40c to +85c input voltage range, v in ...................................................... ?0.5v to v cc +0.5v output voltage range, v out ............................................... ?0.5v to v cc +0.5v dc input voltage .................................................................... ?0.5v to +5.0v dc output current ............................................................................ 100 ma power dissipation .................................................................................. 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v c c e g a t l o v y l p p u s3 . 26 . 3 v v h i ) 3 ( e g a t l o v h g i h t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 15 . 5 v c c v 6 . 3 o t v 7 . 2 =0 . 25 . 5 v l i ) 3 ( e g a t l o v w o l t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 7 . 2 =8 . 0 v n i ) 3 ( e g a t l o v t u p n i05 . 5 v t u o ) 3 ( e g a t l o v t u p t u o05 . 5 v h o t u p t u o h g i h e g a t l o v i h o 0 0 1 - = m v , a c c =. x a m o t . n i mv c c 2 . 0 - v h i i , v 7 . 1 = h o 6 - =v , a m c c =v 3 . 20 . 2 v h i i , v 7 . 1 = h o 2 1 - =v , a m c c =v 3 . 27 . 1 v h i i , v 0 . 2 = h o 2 1 - =v , a m c c =v 7 . 22 . 2 v h i i , v 0 . 2 = h o 2 1 - =v , a m c c =v 0 . 34 . 2 v h i i , v 0 . 2 = h o 4 2 - =v , a m c c =v 0 . 30 . 2 v l o t u p t u o w o l e g a t l o v i l o 0 0 1 = m v , a l i =. x a m o t . n i m2 . 0 v l i i , v 7 . 0 = l o 6 =v , a m c c =v 3 . 24 . 0 v l i i , v 7 . 0 = l o 2 1 =v , a m c c =v 3 . 27 . 0 v l i i , v 8 . 0 = l o 2 1 =v , a m c c =v 7 . 24 . 0 v l i i , v 8 . 0 = l o 4 2 =v , a m c c =v 0 . 35 5 . 0 i h o ) 3 ( t u p t u o h g i h t n e r r u c v c c v 3 . 2 =2 1 - a m v c c v 7 . 2 =2 1 - v c c v 0 . 3 =4 2 - i l o ) 3 ( t u p t u o w o l t n e r r u c v c c v 3 . 2 =2 1 v c c v 7 . 2 =2 1 v c c v 0 . 3 =4 2
4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8131a 03/17/98 PI74ALVCT16260 12-bit to 24-bit multiplexed d-type latch with 3-state outputs notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient and maximum loading. 3. unused control inputs must be held high or low to prevent them from floating. dc electrical characteristics- continued (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) timing requirements over operating range note: 1. unused control inputs must be held high or low to prevent them from floating. s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u i n i t n e r r u c t u p n iv n i v = c c v , d n g r o c c v 6 . 3 =5 m a i z o ) s t u p t u o e t a t s - 3 ( t n e r r u c t u p t u ov t u o =d n g r o v 5 . 50 1 i c c t n e r r u c y l p p u s v c c =v 6 . 3i , t u o 0 = m , a v n i v r o d n g = c c 0 4 d i c c t u p n i r e p t n e r r u c y l p p u s h g i h l t t @ v c c v 0 . 3 =o t6 . 3v v t a t u p n i e n o c c -v 6 . 0 v t a s t u p n i r e h t o c c d n g r o 0 5 7 c i s t u p n i l o r t n o cv n i v = c c v , d n g r o c c v 3 . 3 =5 . 3 f p c o i s t u p t u ov o v = c c v , d n g r o c c v 3 . 3 =9 s r e t e m a r a pn o i t p i r c s e d v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m. x a m. n i m. x a m. n i m. x a m t w , b 1 a e l , b 2 e l , b 1 e l , n o i t a r u d e s l u p h g i h b 2 a e l r o 3 . 33 . 33 . 3 s n t u s e r o f e b a t a d e m i t p u t e s, b 2 e l , b 1 e l b 2 a e l r o , b 1 a e l 4 . 11 . 11 . 1 t h r e t f a a t a d e m i t d l o h, b 2 e l , b 1 e l b 2 a e l r o , b 1 a e l 6 . 19 . 15 . 1 d / t d v ) 1 ( l l a f r o e s i r n o i t i s n a r t t u p n i00 100 10 0 1v / s n
PI74ALVCT16260 12-bit to 24-bit multiplexed d-type latch with 3-state outputs 5 ps8131a 03/17/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m ) 2 ( . x a m. n i m ( ) 2 . x a m. n i m ) 2 ( . x a m t d p b r o aa r o b2 . 10 . 61 . 52 . 19 . 4 s n e lb r o a0 . 12 . 62 . 50 . 10 . 5 l e sa2 . 15 . 76 . 61 . 16 . 5 t n e e o b r o a 0 . 12 . 74 . 60 . 14 . 5 t s i d e o7 . 19 . 50 . 53 . 16 . 4 switching characteristics over operating range (1) notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. operating characteristics, t a = 25 o c r e t e m a r a ps n o i t i d n o c t s e t v c c v 2 . 0 v 5 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u l a c i p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e s t u p t u o c l , f p 0 5 = z h m 0 1 = f 7 80 2 1 f p d e l b a s i d s t u p t u o5 . 0 88 1 1
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