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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2003 mos integrated circuit pd8670 7400 pixels ccd linear image sensor data sheet document no. s16749ej1v0ds00 (1st edition) date published july 2003 ns cp (k) printed in japan the pd8670 is a high sensitive and high-speed ccd (charge coupled device) linear image sensor which changes optical images to electrical signal. the pd8670 is a 2-output type ccd sensor wit h 2 rows of high-speed charge trans fer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. and it has reset feed-through level clamp circuits and voltage amplifiers. therefore, it is suitable for 600 dpi/a3 high-speed digital copiers, multi-function products and so on . features ? valid photocell : 7400 pixels ? photocell pitch : 4.7 m ? photocell size : 4.7 4.7 m 2 ? resolution : 24 dot/mm (600 dpi) a3 (297 420 mm) size (shorter side) ? data rate : 44 mhz max. (22 mhz/1 output) ? output type : 2 outputs in-phase operat ion, and out of phase also supported ? high sensitivity : 17.0 v/lx ? s typ. (light source: daylight color fluorescent lamp) ? peak response wavelength : 550 nm (green) ? low image lag : 1 % max. ? drive clock level : cmos output under +5 v operation ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits : voltage amplifiers ordering information part number package pd8670cy ccd linear image sensor 32-pin plastic dip (10.16 mm (400))
data sheet s16749ej1v0ds 2 pd8670 difference between pd8670cy and pd3747d part item pd8670cy pd3747d referential page features output type 2 outputs out of phase or in phase 2 outputs in phase only 1 sensitivity (daylight color fluorescent lamp) typ. 17 v/lx ? s typ. 19 v/lx ? s ordering information package 32-pin plasti c dip 22-pin ceramic dip (cerdip) pin configuration input clock 4 block diagram 3 application circuit cp1, cp2 separated, r1, r2 separated, 2l1, 2l2 separated (output: in/out of phase) cp common, r common, 2l common (output: in phase) 21 example equivalent circuit tr. 2sa1206, 2sc1842 2sa1005, 2sc945 absolute maximum ratings operating ambient temperature 0 to +60c ?25 to +55c 5 storage temperature ?40 to +70c ?40 to +100c recommended operating condition each clock amplitude addition of specifications (from 4.5 v to 5.8 v) ? electrical characteristics ads, dsnu, dr1, dr2 change of specifications ? 6 r f typ. 17 v/lx ? s typ. 19 v/lx ? s rftn addition of prftn, rftn1, rftn2 only rftn t d typ. 13 ns addition of min. max. typ. 14 ns bit, line, shot addition of condition (t6) ? input pin capacitance capacitance change of specification addition of note ? 7 timing chart operation addition of out-of-phase timing chart ? 8, 9 t6 min. 5 ns min. 0 ns 12, 14 t10 min. 0 ns min. t3 t13, t16, t17 max. 10000 ns ? 14 close point ? cange of specifications ? 15 definitions v os , rftn additional item ? 19 recommended soldering condition partial heating method 350c or blow, 3 seconds or less 300c or blow, 3 seconds or less 24 package drawing package 32-pin plastic dip 22-pin ceramic dip (cerdip) 23 cap plastic cap 0.7t glass cap 0.7t from ccd to bottom of package 2.45 0.3 mm 2.38 0.3 mm from ccd to top of cap (2.0) mm (1.95) mm remark t a = +25c, v od = 12 v
data sheet s16749ej1v0ds 3 pd8670 block diagram transfer gate transfer gate ccd analog shift register ccd analog shift register d1 d6 s2 s1 s7399 s7400 d7 d12 ob1 ob96 22 23 24 28 29 30 32 1 31 10 11 9 5 4 tg 12 22 21 11 2l1 v out 2 (even) v out 1 (odd) gnd gnd 2l2 r2 cp2 r1 3 cp1 2 v od
data sheet s16749ej1v0ds 4 pd8670 pin configuration (top view) ccd linear image sensor 32-pin plastic dip (10.16 mm (400)) ? pd8670cy 1 2 3 4 5 6 7 8 9 10 11 nc ic v out 2 gnd ic 22 2l2 r2 2l1 cp1 cp2 12 internal connection reset feed-through level clamp clock 2 no connection output signal 2 (even) ground reset gate clock 2 internal connection shift register clock 2-2 transfer gate clock v out 1 v od output signal 1 (odd) output drain voltage reset feed-through level clamp clock 1 shift register clock 1-1 ic internal connection ic internal connection last stage shift register clock 2 shift register clock 1-2 shift register clock 2-1 11 21 r1 gnd ground reset gate clock 1 last stage shift register clock 1 no connection nc 12 13 14 ic internal connection ic internal connection no connection nc 15 16 nc no connection nc no connection tg 32 31 30 29 28 27 26 25 24 23 22 ic ic internal connection internal connection 21 20 nc no connection 19 nc no connection 18 nc no connection 17 cautions 1. leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (ic) unconnected. 2. connect the no connection pins (nc) to gnd. photocell structure diagram 4.7 3.2 m 1.5 channel stopper aluminum shield m m
data sheet s16749ej1v0ds 5 pd8670 absolute maximum ratings (t a = +25 c) parameter symbol ratings unit output drain voltage v od ? 0.3 to +14.0 v shift register clock voltage v 1 , v 2 ? 0.3 to +8.0 v last stage shift regist er clock voltage v 2l ? 0.3 to +8.0 v reset gate clock voltage v r ? 0.3 to +8.0 v transfer gate clock voltage v tg ? 0.3 to +8.0 v reset feed-through level clamp clock voltage v cp ? 0.3 to +8.0 v operating ambient temperature note t a 0 to +60 c storage temperature t stg ? 40 to +70 c note use at the condition without dew condensation. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. recommended operating conditions (t a = +25 c) parameter symbol conditions min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v 1h , v 2h 4.5 5.0 5.5 v shift register clock low level v 1l , v 2l ? 0.3 0 +0.5 v last stage shift register clock high level v 2lh 4.5 5.0 5.5 v last stage shift register clock low level v 2ll ? 0.3 0 +0.5 v reset gate clock high level v rh 4.5 5.0 5.5 v reset gate clock low level v rl ? 0.3 0 +0.5 v reset feed-through level clamp clock high level v cph 4.5 5.0 5.5 v reset feed-through level clamp clock low level v cpl ? 0.3 0 +0.5 v transfer gate clock high level v tgh 4.5 5.0 5.5 v transfer gate clock low level v tgl ? 0.3 0 +0.5 v shift register clock amplitude v 1_pp , f < 10 mhz/ch 4.0 5.0 5.8 v v 2_pp f 10 mhz/ch 4.5 5.0 5.8 v last stage shift register clock amplitude v 2l_pp 4.5 5.0 5.8 v reset gate clock amplitude v r_pp 4.5 5.0 5.8 v reset feed-through level clamp clock amplitude v cp_pp 4.5 5.0 5.8 v transfer gate clock amplitude v tg_pp 4.5 5.0 5.8 v data rate 2f r 1 2 44 mhz
data sheet s16749ej1v0ds 6 pd8670 electrical characteristics t a = +25 c, v od = 12 v, f r = 1 mhz, data rate = 2 mhz, storage time = 10 ms, input signal clock = 5 v p-p , light source : 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm) + ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.5 2.0 ? v saturation exposure se daylight color fluorescent lamp ? 0.10 ? lx ? s photo response non-uniformity prnu v out = 500 mv ? 5.0 10.0 % average dark signal ads light shielding ? 1.0 6.0 mv dark signal non-uniformit y dsnu light shielding ? 16.0 28.0 mv power consumption p w ? 350 600 mw output impedance z o ? 0.2 0.3 k ? response r f daylight color fluorescent lamp 13.6 17.0 20.4 v/lx ? s image lag il v out = 500 mv ? 0.5 1.0 % offset level note 1 v os 3.7 4.7 5.7 v output fall delay time note 2 t d v out = 500 mv 11.0 13.0 14.0 ns total transfer efficiency tte v out = 1 v, data rate = 44 mhz 94 98 ? % register imbalance ri v out = 500 mv 0 1.0 4.0 % response peak ? 550 ? nm dr1 v sat /dsnu ? 125 ? times dynamic range dr2 v sat / bit, t6 20 ns ? 1000 ? times reset feed-through noise note 1 prftn light shielding, t4 = 5 ns ? 1.0 ? v rftn1 ? 0.3 + 0.3 + 0.9 v rftn2 ? 0.3 + 0.3 + 0.9 v random noise bit light shielding, t6 = 5 ns ? 2.6 ? mv bit clamp mode t6 20 ns ? 2.0 ? mv line light shielding, t6 5 ns ? 8.0 ? mv line clamp mode shot noise shot v out = 500 mv, t6 5 ns ? 10.0 ? mv bit clamp mode notes 1. refer to 13 and 14 of definition of characteristic items . 2. when the fall time of 2l (t2?) is the typ. value (refer to timing chart 5, 6 ). note that v out 1 and v out 2 are the outputs of the two steps of emitter-follower shown in application circuit example .
data sheet s16749ej1v0ds 7 pd8670 input pin capacitance (t a = +25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c 1 note 11 9 225 250 275 pf 12 23 200 220 240 pf shift register clock pin capacitance 2 c 2 note 21 10 200 220 240 pf 22 24 225 250 275 pf last stage shift register clock pin capacitance c l 2l1 5 4 5 6 pf 2l2 28 4 5 6 pf reset gate clock pin capacitance c r r1 4 4 5 6 pf r2 29 4 5 6 pf reset feed-through level clamp clock pin capacitance c cp cp1 3 7 8 9 pf cp2 30 7 8 9 pf transfer gate clock pin capacitance c tg tg 22 240 270 300 pf note c 1 , c 2 are equivalent capacitance with driving device, including the co-capacitance between 1 and 2. remark pins 9 and 23 ( 11 and 12), pins 10 and 24 ( 21 and 22) aren't each connected inside of the device.
data sheet s16749ej1v0ds 8 pd8670 tg 11 21 r1 cp1 cp2 2l1 12 22 r2 2l2 35 125 127 129 131 133 1 3 5 29 31 33 137 135 7531 7541 7533 7537 7539 7535 36 126 128 130 132 134 2 4 6 30 32 34 138 136 7532 7542 7534 7538 7540 7536 v out 1 v out 2 note optical black (96 pixels) dummy cell (32 pixels) valid photocells (7400 pixels) invalid photocell (6 pixels) invalid photocell (6 pixels) note set the r1, cp2 to low level during this period. cp1 and r2, timing chart 1 (bit clamp mode, out of phase operation)
data sheet s16749ej1v0ds 9 pd8670 tg 11 21 r1 cp1 cp2 2l1 12 22 r2 2l2 35 125 127 129 131 133 1 3 5 29 31 33 137 135 7531 7541 7533 7537 7539 7535 36 126 128 130 132 134 2 4 6 30 32 34 138 136 7532 7542 7534 7538 7540 7536 v out 1 v out 2 note set the r1, cp2 to low level during this period. cp1 and r2, note optical black (96 pixels) dummy cell (32 pixels) valid photocells (7400 pixels) invalid photocell (6 pixels) invalid photocell (6 pixels) timing chart 2 (line clamp mode, out of phase operation)
data sheet s16749ej1v0ds 10 pd8670 tg 12 11, 22 21, r2 r1, cp2 cp1, 2l2 2l1, 35 125 127 129 131 133 1 3 5 29 31 33 137 135 7531 7541 7533 7537 7539 7535 36 126 128 130 132 134 2 4 6 30 32 34 138 136 7532 7542 7534 7538 7540 7536 v out 1 v out 2 note optical black (96 pixels) dummy cell (32 pixels) valid photocells (7400 pixels) invalid photocell (6 pixels) invalid photocell (6 pixels) note set the r1, cp2 to low level during this period. cp1 and r2, timing chart 3 (bit clamp mode, in phase operation)
data sheet s16749ej1v0ds 11 pd8670 tg 12 11, 22 21, r2 r1, cp2 cp1, 2l2 2l1, 35 125 127 129 131 133 1 3 5 29 31 33 137 135 7531 7541 7533 7537 7539 7535 36 126 128 130 132 134 2 4 6 30 32 34 138 136 7532 7542 7534 7538 7540 7536 v out 1 v out 2 note set the r1, cp2 to low level during this period. cp1 and r2, note optical black (96 pixels) dummy cell (32 pixels) valid photocells (7400 pixels) invalid photocell (6 pixels) invalid photocell (6 pixels) timing chart 4 (line clamp mode, in phase operation)
data sheet s16749ej1v0ds 12 pd8670 timing chart 5 (bit clamp mode) v os t1 t1' t2 t2' t3 t5 t6 t4 t d 11 21 r1 cp1 v out 1 2l1 10% 10% 90% t7 t9 t11 t8 t10 10% 90% 10% 90% 10% 10% 90% 90% symbol min. typ. max. unit t1, t2 0 50 ? ns t1?, t2? 0 5 ? ns t3 10 125 ? ns t4, t5 0 5 ? ns t6 5 125 ? ns t7 5 125 ? ns t8, t9 0 5 ? ns t10 0 125 ? ns t11 0 250 ? ns caution this shows timing chart of v out 1 side ( 11, 21, 2l1, r1, cp1, v out 1). the timing chart of v out 2 side ( 12, 22, 2l2, r2, cp2, v out 2) is equal.
data sheet s16749ej1v0ds 13 pd8670 timing chart 6 (line clamp mode) v os t1 t1' t2 t2' t3 t5 t12 t4 t d 11 21 r1 cp1 v out 1 2l1 10% 10% 90% 10% 90% 10% 10% 90% 90% "l" symbol min. typ. max. unit t1, t2 0 50 ? ns t1?, t2? 0 5 ? ns t3 10 125 ? ns t4, t5 0 5 ? ns t12 5 250 ? ns caution this shows timing chart of v out 1 side ( 11, 21, 2l1, r1, cp1, v out 1). the timing chart of v out 2 side ( 12, 22, 2l2, r2, cp2, v out 2) is equal.
data sheet s16749ej1v0ds 14 pd8670 timing chart 7 (bit clamp mode, line clamp mode) t16 t14 t13 t15 t3 t5 t6 t17 t4 tg r1 cp1 11 2l1 21, 10% 90% t7 t9 t11 t10 t8 10% 90% 90% 90% 10% 90% note note set the r and cp to low level during this period. symbol min. typ. max. unit t3 10 125 ? ns t4, t5 0 5 ? ns t6 5 125 ? ns t7 5 125 ? ns t8, t9 0 5 ? ns t10 0 125 ? ns t11 0 250 ? ns t13 1000 1500 10000 ns t14, t15 0 50 ? ns t16, t17 200 300 10000 ns caution this shows timing chart of v out 1 side ( 11, 21, 2l1, r1, cp1, v out 1). the timing chart of v out 2 side ( 12, 22, 2l2, r2, cp2, v out 2) is equal.
data sheet s16749ej1v0ds 15 pd8670 11, 21 cross points 11, 2l1 cross points 11 21 1.5 v or more 1.5 v or more 11 2l1 1.5 v or more 0 v or more 12, 22 cross points 12, 2l2 cross points 12 22 1.5 v or more 1.5 v or more 12 2l2 1.5 v or more 0 v or more remark adjust cross points of ( 11, 21), ( 11, 2l1), ( 12, 22) and ( 12, 2l2) with input resistance of each pin. 11, 12, 21, 22, 2l1, 2l2 clock width 0 ns or more 0 ns or more 11, 12, 21, 22, 2l1, 2l2 0.5 v 4.5 v
data sheet s16749ej1v0ds 16 pd8670 definitions of characteristic items 1. saturation voltage : v sat output signal voltage at whic h the response linearity is lost. 2. saturation exposure : se product of intensity of illumination (lx) and storag e time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels when the photosensiti ve surface is applied with the light of uniform illumination. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j ? x ? x: maximum of ? x j ? x ? x 7400 j = 1 7400 x j 100 x register dark dc level v out ? x 4. average dark signal : ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. ads (mv) = d j : dark signal of valid pixel number j 7400 j = 1 7400 d j
data sheet s16749ej1v0ds 17 pd8670 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and voltage of the highest or lowest out put pixel of all the valid pixels at light shielding. this is calculated by the following formula. d j : dark signal of valid pixel number j dsnu (mv): maximum of ? d j ? ads ? j = 1 to 7400 ads dsnu register dark dc level v out 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lx ? s). note that the response varies with a light source (spectral characteristic). 8. image lag : il the rate between the last output voltage and the next one after read out the data of a line. v out tg light v out on off v 1 il (%) = v 1 v out 100 9. total transfer efficiency : tte the total transfer rate of ccd analog shift register. this is calculated by the following formula, it is difined by each output. tte (%) = (1 ? v b / average output of all the valid pixels) 100 v a ? 1 : the last pixel output ? 1 (odd pixel: 7537th pixel) v a : the last pixel output (odd pixel: 7539th pixel) v b : the spilt pixel output (odd pixel: 7541st pixel) v a ? 1 v a v b
data sheet s16749ej1v0ds 18 pd8670 10. register imbalance : ri the rate of the difference between the averages of the output voltage of odd and even pixels, against the average output voltage of all the valid pixels. ri (%) = 2 n j = 1 n 2 (v 2j ? 1 ? v 2j ) 1 n j = 1 n v j 100 : number of valid pixels : output voltage of each pixel n v j 11. random noise : random noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). (mv) = , v = i = 1 100 (v i ? v) 2 i = 1 100 v i 100 100 1 v i : a valid pixel output signal among all of the valid pixels v 1 v 100 v 2 line 2 line 100 line 1 v out this is measured by the dc level sampling of only the si gnal level, not by cds (correlated double sampling). 12. shot noise : shot shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. this includes the random noise. the formula is the same with that of random noise.
data sheet s16749ej1v0ds 19 pd8670 13. offset level : v os dc level of output signal is defined as follows. 14. reset feed-through noise and peak reset feed-through noise : rftn and prftn rtfn is switching noise of r and cp. reset feed-through noise (rftn) and peak of rftn (prftn) are defined as follows. <1> bit clamp operation v os prftn rftn1 rftn2 cp1 v out 1 r1 2l1 caution this shows timing of v out 1 side ( 2l1, r1, cp1, v out 1). the definition of v out 2 side ( 2l2, r2, cp2, v out 2) is equal. <2> line clamp operation v os prftn cp1 "l" v out 1 r1 2l1 rftn1 caution this shows timing of v out 1 side ( 2l1, r1, cp1, v out 1). the definition of v out 2 side ( 2l2, r2, cp2, v out 2) is equal.
data sheet s16749ej1v0ds 20 pd8670 standard characteristic curves (reference value) 01020304050 0.1 0.25 1 2 0.5 4 8 510 1 0.1 0.2 1 2 1200 600 400 1000 800 0 20 40 60 80 100 dark output temperature characteristic storage time output voltage characteristic (t a = + 25 c) operating ambient temperature t a ( c) relative output voltage relative output voltage storage time (ms) wavelength (nm) response ratio (%) total spectral response characteristic (without infrared cut filter and heat absorbing filter) (t a = +25 c)
data sheet s16749ej1v0ds 21 pd8670 application circuit example v out 1 pd8670 gnd gnd v od 22 12 11 21 tg 132 31 30 29 28 27 26 25 2 v out 2 ic ic ic ic nc ic ic nc nc nc nc ic ic nc nc nc cp2 b2 b1 +5 v cp2 r2 2l2 cp1 cp1 r1 r1 2l1 2l1 r2 2l2 +12 v 0.1 f 10 f/16 v 47 ? 47 ? 47 ? 47 ? 47 ? 47 ? 24 2 ? 23 2 ? 2 ? 2 ? 22 21 10 ? 20 19 18 17 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +5 v 0.1 f 10 f/16 v 0.1 f 47 f/25 v 22 12 tg 11 21 cautions 1. leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (ic) unconnected. 2. connect the no connection pins (nc) to gnd. remark the inverters shown in the above applic ation circuit example are the 74ac04.
data sheet s16749ej1v0ds 22 pd8670 +12 v 110 ? 4.7 k ? 47 f/25 v 2sa1206 2sc1842 1 k ? 47 ? + ccd v out b1, b2 equivalent circuit output
data sheet s16749ej1v0ds 23 pd8670 package drawing 55.2 0.5 54.8 0.5 12.6 0.5 9.05 0.3 9.25 0.3 4.1 0.5 1st valid pixel 3.2 0.3 1 4 4 32 17 16 1 2.0 46.7 2.54 0.25 0.46 0.1 1.02 0.15 (5.42) 4.21 0.5 4.55 0.5 (2.0) 2.45 0.3 0.25 0.05 10.16 0.20 3 5 2 10.16 + 0.70 ? 0.20 name dimensions refractive index plastic cap 52.2 6.4 0.8 (0.7 ) 1.5 1 1st valid pixel the center of the pin1 2 the surface of the ccd chip the top of the cap 3 the bottom of the package the surface of the ccd chip 4 mirror finishied surface 5 thickness of mirror finished surface 32c-1ccd-pkg10-1 (unit : mm) ccd linear image sensor 32-pin plastic dip (10.16 mm (400) ) pd8670cy
data sheet s16749ej1v0ds 24 pd8670 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8670cy : ccd linear image sensor 32- pin plastic dip (10.16 mm (400)) process conditions partial heating method pin temperature : 350 c or below, heat time : 3 seconds or less (per pin) cautions 1. during assembly care should be taken to prevent solder or flux from contacting the plastic cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. so the method cannot be guaranteed.
data sheet s16749ej1v0ds 25 pd8670 notes on handling the packages cleaning the plastic cap dust and dirt protecting mounting of the package operate and storage environments ethyl alcohol methyl alcohol isopropyl alcohol n-methyl pyrrolidone etoh meoh ipa nmp the optical characteristics of the ccd will be degraded if the cap is scratched during cleaning. don?t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. should dirt stick to a plastic cap surface, blow it off with an air blower. for dirt stuck through electricity ionized air is recommended. and if the plastic cap surface is grease stained, clean with our recommended solvents. care should be taken when cleaning the surface to prevent scratches. we recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. excessive pressure should not be applied to the cap during cleaning. if the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. the following are the recommended solvents for cleaning the ccd plastic cap. use of solvents other than these could result in optical or physical degradation in the plastic cap. please consult your sales office when considering an alternative solvent. the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with plastic cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) 1 2 electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m ? . 4 3 recommended solvents solvents symbol
data sheet s16749ej1v0ds 26 pd8670 [ note ]
data sheet s16749ej1v0ds 27 pd8670 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd8670 the information in this document is current as of july, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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