1 data sheet acquired from harris semiconductor schs188a features ? buffered inputs ? common three-state output-enable control ? three-state outputs ? bus line driving capability ? typical propagation delay = 13ns at v cc = 5v, c l = 15pf, t a = 25 o c (clock to output) ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh description the hc534, hct534, hc564, and hct564 are high speed octal d-type flip-flops manufactured with silicon gate cmos technology. they possess the low power consumption of stan- dard cmos integrated circuits, as well as the ability to drive 15 lsttl loads. due to the large output drive capability and the three-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. the two types are functionally identical and differ only in their pinout arrangements. the hc534, hct534, hc564, and hct564 are positive edge triggered flip-flops. data at the d inputs, meeting the setup and hold time requirements, are inverted and trans- ferred to the q outputs on the positive going transition of the clock input. when a high logic level is applied to the out- put enable input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. the hct logic family is speed, function, and pin compatible with the standard ls logic family. ordering information part number temp. range ( o c) package cd54hc534f3a -55 to 125 20 ld cerdip cd74hc534e -55 to 125 20 ld pdip CD54HCT534F3A -55 to 125 20 ld cerdip cd74hct534e -55 to 125 20 ld pdip cd54hc564f3a -55 to 125 20 ld cerdip cd74hc564e -55 to 125 20 ld pdip cd74hc564m -55 to 125 20 ld soic cd54hct564f3a -55 to 125 20 ld cerdip cd74hct564e -55 to 125 20 ld pdip cd74hct564m -55 to 125 20 ld soic notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. wafer and die for this part number is available which meets all electrical specifications. please contact your local ti sales office or customer service for ordering information. january 1998 - revised may 2000 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? 2000, texas instruments incorporated cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564 high speed cmos logic octal d-type flip-flop, three-state inverting positive-edge triggered [ /title (cd74 hc534 , cd74 hct53 4, cd74 hc564 , cd74 hct56
2 functional diagram pinouts cd54hc534, cd54hct534 (cerdip) cd74hc534, cd74hct534 (pdip) top view cd54hc564, cd54hct564 (cerdip) cd74hc564, cd74hct564 (pdip, soic) top view truth table inputs output oe cp dn qn l - hl l - lh l l x no change hxxz note: h = high level (steady state) l = low level (steady state) x = dont care - = transition from low to high level z = high impedance state 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 oe q0 d0 d1 q1 q2 d3 d2 q3 gnd v cc d7 d6 q6 q7 q5 d5 d4 q4 cp 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 oe d0 d1 d2 d3 d4 d6 d5 d7 gnd v cc q1 q2 q3 q0 q4 q5 q6 q7 cp q 0 d 0 cp oe q 1 d 1 q 2 d 2 q 3 d 3 q 4 d 4 q 5 d 5 q 6 d 6 o 7 d 7 d q d q d q d q d q d q d q d q cp cp cp cp cp cp cp cp cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 35ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -6 4.5 3.98 - - 3.84 - 3.7 - v -7.8 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 6 4.5 - - 0.26 - 0.33 - 0.4 v 7.8 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
4 quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 m a three- state leakage current v il or v ih v o =v cc or gnd -6-- 0.5 - 5.0 - 10 m a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -6 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 6 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 m a three- state leakage current v il or v ih v o =v cc or gnd - 5.5 - - 0.5 - 5.0 - 10 m a additional quiescent device current per input pin: 1 unit load d i cc v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) speci?cation is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads d0 - d7 0.15 cp 0.30 oe 0.55 note: unit load is d i cc limit speci?c in dc electrical speci?cations table, e.g., 360 m a max. at 25 o c. cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
5 prerequisite for switching speci?cations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max hc types maximum clock frequency f max 2 6 - - 5 - - 4 - - mhz 4.5 30 - - 25 - - 20 - - mhz 6 35 - - 29 - - 23 - - mhz clock pulse width t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns setup time data to clock t su 260- -75- -90- -ns 4.5 12 - - 15 - - 18 - - ns 610- -13- -15- -ns hold time data to clock t h 25--5- -5--ns 4.5 5 - - 5 - - 5 - - ns 65--5- -5--ns hct types maximum clock frequency f max 4.5 25 - - 20 - - 16 - - mhz clock pulse width t w 4.5 20 - - 25 - - 30 - - ns setup time data to clock t su 4.5 20 - - 25 - - 30 - - ns hold time data to clock (534) t h 4.5 5 - - 5 - - 5 - - ns hold time data to clock (564) t h 4.5 3 - - 3 - - 3 - - ns switching speci?cations c l = 50pf, input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh , t phl c l = 50pf clock to output 2 - - 165 - 205 - 250 ns 4.5 - - 33 - 41 - 50 ns c l = 15pf 5 - 13 - - - - - ns c l = 50pf 6 - - 28 - 35 - 43 ns output disable to q (534) t plz ,t phz c l = 50pf 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - - - - - ns c l = 50pf 6 - - 26 - 33 - 38 ns cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
6 output disable to q (564) t plz ,t phz c l = 50pf 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns c l = 15pf 5 - 12 - - - - - ns c l = 50pf 6 - - 23 - 29 - 35 ns output enable to q t pzl ,t pzh c l = 50pf 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - - - - - ns c l = 50pf 6 - - 26 - 33 - 38 ns maximum clock frequency f max c l = 15pf 5 - 60 - - - - - mhz output transition time t thl , t tlh c l = 50pf 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns input capacitance c i c l = 50pf - 10 - 10 - 10 - 10 pf three-state output capacitance c o - - 20 - 20 - 20 - 20 pf power dissipation capacitance (notes 4, 5) c pd -5-32-----pf hct types propagation delay t phl, t plh clock to output c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - - - - - ns output disable to q t plz ,t phz c l = 50pf 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - - - - - ns output enable to q t pzl ,t pzh c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - - - - - ns maximum clock frequency f max c l = 15pf 5 - 50 - - - - - mhz output transition time t tlh , t thl c l = 50pf 4.5 - - 12 - 15 - 18 ns input capacitance c i c l = 50pf - 10 - 10 - 10 - 10 pf three-state output capacitance c o - - 20 - 20 - 20 - 20 pf power dissipation capacitance (notes 4, 5) c pd -5-36-----pf notes: 4. c pd is used to determine the dynamic power consumption, per package. 5. p d =c pd v cc 2 f i + ? c l v cc 2 f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations c l = 50pf, input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
7 test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc transition times and propagation delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
8 figure 7. hc three-state propagation delay waveform figure 8. hct three-state propagation delay waveform note: open drain waveforms t plz and t pzl are the same as those for three-state shown on the left. the test circuit is output r l =1k w to v cc , c l = 50pf. figure 9. hc and hct three-state propagation delay test circuit test circuits and waveforms (continued) 50% 10% 90% gnd v cc 10% 90% 50% 50% output disable output low to off output high to off outputs enabled outputs disabled outputs enabled 6ns 6ns t pzh t phz t pzl t plz 0.3 2.7 gnd 3v 10% 90% 1.3v 1.3v output disable output low to off output high to off outputs enabled outputs disabled outputs enabled t r 6ns t pzh t phz t pzl t plz 6ns t f 1.3 ic with three- state output other inputs tied high or low output disable v cc for t plz and t pzl gnd for t phz and t pzh output r l = 1k w c l 50pf cd54/74hc534, cd54/74hct534, cd54/74hc564, cd54/74hct564
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated
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