30 n-channel logic level enhancement mode field effect transistor features 30v , 75a , r ds(on) =6.0m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-220 & to-263 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v -pulsed i d 75 a i dm a drain-source diode forward current i s 75 a maximum power dissipation p d w operating and storage temperautre range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 2.0 62.5 /w c /w c ? r ds(on) =9.0m @v gs =4.5v. ? @tc=25 c derate above 25 c 75 0.5 w/ c drain current-continuous s g d ceb series to-263(dd-pak) cep series to-220 g s s d d g 4-117 sep. 2002 225 CEP72A3/ceb72a3 4
electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d = 250 a 30 v zero gate voltage drain current i dss v ds =30v,v gs =0v 1 a gate-body leakage i gss v gs =20v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d =250 a 13 v drain-source on-state resistance r ds(on) v gs =10v,i d =40a 6.0 m ? v gs = 4.5v, i d =37a 9.0 m ? on-state drain current i d(on) v gs =10v,v ds =10v 75 50 a s forward transconductance fs g v ds =10v,i d = 40a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f =1.0mh z 2447 p f p f p f 187 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f fall time ? 50 ns ns ns ns 100 total gate charge gate-source charge gate-drain charge q g q gs q gd nc nc nc 5.0 7.0 983 35 45 11 16 v ds =15v, i d =40a v gs =5v v dd = 15v, i d =60a, r gen =6 v gs =10v 25 21 58 13 CEP72A3/ceb72a3 4-118 45 33 4
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =40a 1 1.3 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 4-119 figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) c, capacitance (pf) i d , drain current (a) CEP72A3/ceb72a3 120 105 90 75 60 45 30 15 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v gs =10,9,8,7,6,5,4v v gs =3v v gs =2v r ds(on) , normalized figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , ciss coss crss 3600 3000 2400 1800 1200 600 0 0 5 10 15 20 25 30 -55 c 48 60 36 24 12 0 1 1.5 2 2.5 3.5 34 25 c t j =125 c -100 -50 0 50 100 200 2.2 1.9 1.6 1.3 1.0 0.7 0.4 v gs =10v i d =40a 150 4
with temperature with temperature is, source-drain current (a) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) i d , drain current (a) 4-120 CEP72A3/ceb72a3 vth, normalized gate-source threshold voltage tj, junction temperature ( c) 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a figure 6. breakdown voltage variation with temperature bv dss , normalized drain-source breakdown voltage tj, junction temperature ( c) -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a figure 5. gate threshold variation g fs , transconductance (s) figure 7. transconductance variation with drain current i ds , drain-source current (a) 100 80 60 40 20 0 0 20 40 60 80 v ds =10v v gs , gate to source voltage (v) figure 9. gate charge qg, total gate charge (nc) 10 0 2 4 6 8 020 40 6080 v ds =15v i d =40a 50 10 0.1 1 0.4 0.6 0.8 1.0 1.2 1.4 10 10 -1 10 10 2 1 0 10 -1 10 1 10 2 10 0 t c =25 c single pulse tj=175 c rds( o n) li m i t dc 100ms 10ms 1ms 100 3 s 4
f 4-121 transient thermal impedance square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve r(t),normalized effective figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t 90% pulse width inverted v dd r d v v r s v g gs in gen out l CEP72A3/ceb72a3 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 0.1 0.05 0.02 0.01 single pulse 10 10 10 4 3 2 10 1 10 0 10 -1 10 -2 10 -2 10 -1 10 0 0.2 d=0.5 4
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