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1 features ? high-density, high-performance, electrically-erasable complex programmable logic device ? 32 macrocells ? 5 product terms per macrocell, expandable up to 40 per macrocell ?44pins ? 7.5 ns maximum pin-to-pin delay ? registered operation up to 125 mhz ? enhanced routing resources in-system programmability (isp) via jtag flexible logic macrocell ? d/t latch configurable flip-flops ? global and individual register control signals ? global and individual output enable ? programmable output slew rate ? programmable output open collector option ? maximum logic utilization by burying a register with a com output advanced power management features automatic10astandbyfor?l?version pin-controlled 1 ma standby mode programmable pin-keeper inputs and i/os reduced-power feature per macrocell available in commercial and industrial temperature ranges available in 44-lead plcc and tqfp advanced eeprom technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20-year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing to ieee std. 1149.1-1990 and 1149.1a-1993 supported pci-compliant security fuse feature enhanced features improved connectivity (additional feedback routing, alternate input routing) output enable product terms d latch mode combinatorial output with registered feedback within any macrocell three global clock pins itd (input transition detection) circuits on global clocks, inputs and i/o (?l? versions) fast registered input from product term programmable ?pin-keeper? option v cc power-up reset option pull-up option on jtag pins tms and tdi advanced power management features ? input transition detection ? power-down (?l? versions) ? individual macrocell power option ? disable itd on global clocks, inputs and i/o high- performance eeprom cpld atf1502as ATF1502ASL rev. 0995j?pld?09/02
2 atf1502as(l) 0995j?pld?09/02 44-lead tqfp top view 44-lead plcc top view description the atf1502as is a high-performance, high-density complex programmable logic device (cpld) that utilizes atmel?s proven electrically-erasable technology. with 32 logic macrocells and up to 36 inputs, it easily integrates logic from several ttl, ssi, msi, lsi and classic plds. the atf1502as?s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. the atf1502as has up to 32 bi-directional i/o pins and four dedicated input pins, depending on the type of device package selected. each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gclk2/oe2/i gclr/i i/oe1 gclk1/i gnd gclk3/i/o i/o 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gclk2/oe2/i gclr/i oe1/i gclk1/i gnd gclk3/i/o i/o
3 atf1502as(l) 0995j?pld?09/02 block diagram each of the 32 macrocells generates a buried feedback that goes to the global bus. each input and i/o pin also feeds into the global bus. the switch matrix in each logic block then selects 40 individual signals from the global bus. each macrocell also generates a foldback logic term that goes to a regional bus. cascade logic between macrocells in the atf1502as allows fast, efficient generation of complex logic functions. the atf1502as contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. the atf1502as macrocell, shown in figure 1, is flexible enough to support highly complex logic functions operating at high speed. the macrocell consists of five sections: product terms and product term select multiplexer, or/xor/cascade logic, a flip-flop, output select and enable, and logic array inputs. unused product terms are automatically disabled by the compiler to decrease power con- sumption. a security fuse, when programmed, protects the contents of the atf1502as. two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf1502as device is an in-system programmable (isp) device. it uses the industry stan- dard 4-pin jtag interface (ieee std. 1149.1), and is fully compliant with jtag?s boundary- scan description language (bsdl). isp allows the device to be programmed without remov- ing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. b 32
4 atf1502as(l) 0995j?pld?09/02 figure 1. atf1502as macrocell product terms and select mux each atf1502as macrocell has five product terms. each product term receives as its inputs all signals from both the global bus and regional bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is determined by the design compiler, which selects the optimum macrocell configuration. or/xor/ cascade logic the atf1502as?s logic structure is designed to efficiently support all types of logic. within a single macrocell, all the product terms can be routed to the or gate, creating a 5-input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. the macrocell?s xor gate allows efficient implementation of compare and arithmetic func- tions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high or low level. for combinatorial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimization of product terms. the xor gate is also used to emulate t- and jk-type flip-flops. flip-flop the atf1502as?s flip-flop has very flexible data and control functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (this feature is automatically implemented by the fitter soft- ware). in addition to d, t, jk and sr operation, the flip-flop can also be configured as a flow- through latch. in this mode, data passes through when the clock is high and is latched when the clock is low.
5 atf1502as(l) 0995j?pld?09/02 the clock itself can be either one of the global clk signals (gck[0 : 2]) or an individual prod- uct term. the flip-flop changes state on the clock?s rising edge. when the gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop?s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a prod- uct term. the asynchronous preset (ap) can be a product term or always off. extra feedback the atf1502as(l) macrocell output can be selected as registered or combinatorial. the extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (this enhancement function is automatically implemented by the fitter software.) feedback of a buried combinatorial output allows the cre- ation of a second latch within a macrocell. i/o control the output enable multiplexer (moe) controls the output enable signal. each i/o can be indi- vidually configured as an input, output or for bi-directional operation. the output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the i/o pins, or a subset of the i/o macrocells. this selection is automatically done by the fitter software when the i/o is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic. global bus/switch matrix the global bus contains all input and i/o pin signals as well as the buried feedback signal from all 32 macrocells. the switch matrix in each logic block receives as its inputs all signals from the global bus. under software control, up to 40 of these signals can be selected as inputs to the logic block. foldback bus each macrocell also generates a foldback product term. this signal goes to the regional bus and is available to four macrocells. the foldback is an inverse polarity of one of the macrocell?s product terms. the four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. programmable pin-keeper option for inputs and i/os the atf1502as offers the option of programming all input and i/o pins so that pin-keeper cir- cuits can be utilized. when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption.
6 atf1502as(l) 0995j?pld?09/02 input diagram i/o diagram speed/power management the atf1502as has several built-in speed and power management features. the atf1502as contains circuitry that automatically puts the device into a low-power standby mode when no logic transitions are occurring. this not only reduces power consumption dur- ing inactive periods, but also provides proportional power savings for most applications running at system speeds below 50 mhz. this feature may be selected as a design option. to further reduce power, each atf1502as macrocell has a reduced-power bit feature. this feature allows individual macrocells to be configured for maximum power savings. this feature may be selected as a design option. the atf1502as also has an optional power-down mode. in this mode, current drops to below 10 ma. when the power-down option is selected, either pd1 or pd2 pins (or both) can be used to power down the part. the power-down option is selected in the design source file. when enabled, the device goes into power-down when either pd1 or pd2 is high. in the power-down mode, all internal logic signals are latched and held, as are any enabled outputs.
7 atf1502as(l) 0995j?pld?09/02 all pin transitions are ignored until the pd pin is brought low. when the power-down feature is enabled, the pd1 or pd2 pin cannot be used as a logic input or output. however, the pin?s macrocell may still be used to generate buried foldback and cascade logic signals. all power-down ac characteristic parameters are computed from external input or i/o pins, with reduced-power bit turned on. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t rpa , must be added to the ac parameters, which include the data paths t lad ,t lac ,t ic ,t acl ,t ach and t sexp . the atf1502as macrocell also has an option whereby the power can be reduced on a per- macrocell basis. by enabling this power-down option, macrocells that are not used in an appli- cation can be turned down, thereby reducing the overall power consumption of the device. each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching, and may be specified as fast switching in the design file. design software support atf1502as designs are supported by several third-party tools. automated fitters allow logic synthesis using a variety of high-level description languages and formats. power-up reset the atf1502as is designed with a power-up reset, a feature critical for state machine initial- ization. at a point delayed slightly from v cc crossing v rst , all registers will be initialized, and the state of each output will depend on the polarity of its buffer. however, due to the asynchro- nous nature of reset and uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. the clock must remain stable during t d . the atf1502as has two options for the hysteresis about the reset level, v rst , small and large. during the fitting process users may configure the device with the power-up reset hys- teresis set to large or small. atmel pof2jed users may select the large option by including the flag ?-power_reset? on the command line after ?filename.pof?. to allow the registers to be properly reinitialized with the large hysteresis option selected, the following condition is added: 4. if v cc falls below 2.0v, it must shut off completely before the device is turned on again. when the large hysteresis option is active, i cc is reduced by several hundred microamps as well. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf1502as fuse patterns. once programmed, fuse verify is inhibited. however, the 16-bit user signature remains accessible. programming atf1502as devices are in-system programmable (isp) devices utilizing the 4-pin jtag pro- tocol. this capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes.
8 atf1502as(l) 0995j?pld?09/02 atmel provides isp hardware and software to allow programming of the atf1502as via the pc. isp is performed by using either a download cable, a comparable board tester or a simple microprocessor interface. when using the isp hardware or software to program the atf1502as devices, four i/o pins must be reserved for the jtag interface. however, the logic features that the macrocells have associated with these i/o pins are still available to the design for burned logic functions. to facilitate isp programming by the automated test equipment (ate) vendors, serial vector format (svf) files can be created by atmel-provided software utilities. atf1502as devices can also be programmed using standard third-party programmers. with a third-party programmer, the jtag isp port can be disabled, thereby allowing four additional i/opinstobeusedforlogic. contact your local atmel representatives or atmel pld applications for details. isp programming protection the atf1502as has a special feature that locks the device and prevents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a condition. in addition, the pin-keeper option preserves the previous state of the input and i/o pms during programming. all atf1502as devices are initially shipped in the erased state, thereby making them ready to use for isp. note: for more information refer to the ?designing for in-system programmability with atmel cplds? application note. jtag-bst/isp overview the jtag boundary-scan testing is controlled by the test access port (tap) controller in the atf1502as. the boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing methods. each input pin and i/o pin has its own boundary-scan cell (bsc) to support boundary-scan testing. the atf1502as does not include a test reset (trst) input pin because the tap controller is automatically reset at power-up. the five jtag modes supported include: sample/preload, extest, bypass, idcode and highz. the atf1502as?s isp can be fully described using jtag?s bsdl as described in ieee standard 1149.1b. this allows atf1502as programming to be described and implemented using any one of the third-party development tools supporting this standard. the atf1502as has the option of using four jtag-standard i/o pins for boundary-scan test- ing (bst) and in-system programming (isp) purposes. the atf1502as is programmable through the four jtag pins using the ieee standard jtag programming protocol established by ieee standard 1149.1 using 5v ttl-level programming signals from the isp interface for in-system programming. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins.
9 atf1502as(l) 0995j?pld?09/02 jtag boundary-scan cell (bsc) testing the atf1502as contains up to 32 i/o pins and four input pins, depending on the device type and package type selected. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan registers and up to two update regis- ters. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the capture registers. input to the capture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are generated internally by the jtag tap controller. the bsc configuration for the input and i/o pins and macrocells is shown below. bsc configuration for input and i/o pins (except jtag tap pins) note: 1. the atf1502as has a pull-up option on tms and tdi pins. this feature is selected as a design option. bsc configuration for macrocell 0 1 0 1 dq dq capture dr update dr 0 1 0 1 dq dq tdi outj oej shift clock mode tdo bsc for i/o pins and macrocells 0 1 d q tdi clock tdo pin
10 atf1502as(l) 0995j?pld?09/02 pci compliance the atf1502as also supports the growing need in the industry to support the new peripheral component interconnect (pci) interface standard in pci-based designs and specifications. the pci interface calls for high current drivers, which are much larger than the traditional ttl drivers. in general, plds and fpgas parallel outputs to support the high current load required by the pci interface. the atf1502as allows this without contributing to system noise while delivering low output to output skew. having a programmable high drive option is also possible without increasing output delay or pin capacitance. the pci electrical characteristics appear on the next page. pci voltage-to- current curves for +5v signaling in pull-up mode pci voltage-to- current curves for +5v signaling in pull-down mode 2.4 vcc 1.4 -2 -44 -178 current (ma) ac drive point dc drive point voltage pull up test point 2.2 vcc 0.55 3,6 95 380 current (ma) ac drive point dc drive point voltage pull down test point
11 atf1502as(l) 0995j?pld?09/02 note: 1. leakage current is with pin-keeper off. notes: 1. equation a: i oh =11.9(v out - 5.25) * (v out + 2.45) for v cc >v out >3.1v. 2. equation b: i ol = 78.5 * v out *(4.4-v out )for0v2.2v 95 ma 2.2 > v out >0 v out /0.023 ma 0.1 > v out > 0 equation b ma v out =0.71 206 ma i cl low clamp current -5 < v in -1 -25 + (v in +1) /0.015 ma slew r output rise slew rate 0.4v to 2.4v load 1 5 v/ns slew f output fall slew rate 2.4v to 0.4v load 1 5 v/ns
12 atf1502as(l) 0995j?pld?09/02 power-down mode the atf1502as includes an optional pin-controlled power-down feature. when this mode is enabled, the pd pin acts as the power-down pin. when the pd pin is high, the device supply current is reduced to less than 5 ma. during power-down, all output data and internal logic states are latched and held. therefore, all registered and combinatorial output data remain valid. any outputs that were in a high-z state at the onset will remain at high-z. during power-down, all input signals except the power-down pin are blocked. input and i/o hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. the power-down pin feature is enabled in the logic design file. designs using the power-down pin may not use the pd pin logic array input. however, all other pd pin mac- rocell resources may still be used, including the buried feedback and foldback product term array inputs. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. power-down ac characteristics (1)(2) symbol parameter -7 -10 -15 -25 units min max min max min max min max t ivdh valid i, i/o before pd high 7 10 15 25 ns t gvdh valid oe (2) before pd high 7 10 15 25 ns t cvdh valid clock (2) before pd high 7 10 15 25 ns t dhix i, i/o don?t care after pd high 12 15 25 35 ns t dhgx oe (2) don?t care after pd high 12 15 25 35 ns t dhcx clock (2) don?t care after pd high 12 15 25 35 ns t dliv pd low to valid i, i/o 1 1 1 1 s t dlgv pd low to valid oe (pin or term) 1 1 1 1 s t dlcv pd low to valid clock (pin or term) 1 1 1 1 s t dlov pd low to valid output 1 1 1 1 s absolute maximum ratings* temperature under bias .................................. -40c to +85c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc +0.75vdc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1)
13 atf1502as(l) 0995j?pld?09/02 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. dc and ac operating conditions commercial industrial operating temperature (ambient) 0 c-70 c-40 c-85 c v cc (5v) power supply 5v 5% 5v 10% dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current v in =v cc -2 -10 a i ih input or i/o high leakage current 210 i oz tri-state output off-state current v o =v cc or gnd -40 40 a i cc1 power supply current, standby v cc =max v in =0,v cc std mode com. 60 ma ind. 75 ma ?l? mode com. 10 a ind. 10 a i cc2 power supply current, power-down mode v cc =max v in =0,v cc ?pd? mode 1 5 ma i cc3 (2) reduced-power mode supply current, standby v cc =max v in =0,v cc std mode com. 35 ma ind. 40 ma v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v ccio +0.3 v v ol output low voltage (ttl) v in =v ih or v il v cc =min,i ol =12ma com. 3.0 0.45 v ind. 0.45 output low voltage (cmos) v in =v ih or v il v cc =min,i ol =0.1ma com. 0.2 v ind. 0.2 v v oh output high voltage (ttl) v in =v ih or v il v cc =min,i oh =-4.0ma 2.4 v
14 atf1502as(l) 0995j?pld?09/02 note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. timing model input test waveforms and measurement levels t r ,t f =1.5nstypical output ac test loads pin capacitance (1) typ max units conditions c in 810pf v in =0v;f=1.0mhz c i/o 810pf v out =0v;f=1.0mhz
15 atf1502as(l) 0995j?pld?09/02 ac characteristics (1) symbol parameter -7 -10 -15 -25 units min max min max min max min max t pd1 input or feedback to non-registered output 7.5 10 3 15 25 ns t pd2 i/o input or feedback to non-registered feedback 7931225ns t su global clock setup time 6 7 11 20 ns t h global clock hold time 0 0 0 0 ns t fsu global clock setup time of fast input 3 3 3 5 ns t fh global clock hold time of fast input 0.5 0.5 1 2 mhz t cop global clock to output delay 4.5 5 8 13 ns t ch global clock high time 3 4 5 7 ns t cl global clock low time 3 4 5 7 ns t asu array clock setup time 3 3 4 5 ns t ah array clock hold time 2 3 4 6 ns t acop array clock output delay 7.5 10 15 25 ns t ach array clock high time 3 4 6 10 ns t acl array clock low time 3 4 6 10 ns t cnt minimum clock global period 8 10 13 22 ns f cnt maximum internal global clock frequency 125 100 76.9 50 mhz t acnt minimum array clock period 8 10 13 22 ns f acnt maximum internal array clock frequency 125 100 76.9 50 mhz f max maximum clock frequency 166.7 125 100 60 mhz t in input pad and buffer delay 0.5 0.5 2 2 ns t io i/o input pad and buffer delay 0.5 0.5 2 2 ns t fin fast input delay 1 1 2 2 ns t sexp foldback term delay 4 5 8 12 ns t pexp cascade logic delay 0.8 0.8 1 2 ns t lad logic array delay 3 5 6 8 ns t lac logic control delay 3 5 6 8 ns t ioe internal output enable delay 2 2 3 4 ns t od1 output buffer and pad delay (slow slew rate = off; v cc =5v;c l =35pf) 21.5 4 6ns t zx1 output buffer enable delay (slow slew rate = off; v ccio =5.0v;c l =35pf) 4.0 5.0 7 10 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio =3.3v;c l =35pf) 4.5 5.5 7 10 ns
16 atf1502as(l) 0995j?pld?09/02 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad ,t lac ,t tic ,t acl ,andt sexp parameters for macrocells running in the reduced- power mode. t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5.0v/3.3v; c l =35pf) 9 9 10 12 ns t xz output buffer disable delay (c l = 5 pf) 4 5 6 8 ns t su register setup time 3 3 4 6 ns t h register hold time 2 3 4 6 ns t fsu register setup time of fast input 3 3 2 3 ns t fh register hold time of fast input 0.5 0.5 2 5 ns t rd register delay 1 2 1 2 ns t comb combinatorial delay 1 2 1 2 ns t ic array clock delay 3 5 6 8 ns t en register enable time 3 5 6 8 ns t glob global control delay 1 1 1 1 ns t pre register preset time 2 3 4 6 ns t clr register clear time 2 3 4 6 ns t uim switch matrix delay 1 1 2 2 ns t rpa reduced-power adder (2) 10 11 13 15 ns ac characteristics (continued) (1) symbol parameter -7 -10 -15 -25 units min max min max min max min max
17 atf1502as(l) 0995j?pld?09/02 supply current vs. supply voltage as version (t a = 25c, f = 0) 0 10 20 30 40 50 60 70 4.5 4.75 5 5.25 5.5 v cc (v) i cc (ma) standard power reduced power supply current vs. supply voltage pin-controlled power-down mode (t a =25c,f=0) 0 2 4 6 8 10 12 14 4.5 4.75 5 5.25 5.5 v cc (v) i cc (ma) tbd supply current vs. frequency as version (t a = 25c) 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.00 20.00 40.00 60.00 80.00 100.00 frequency (mhz) i cc (ma) standard power reduced power output source current vs. supply voltage (v oh =2.4v,t a = 25c) -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 4.50 4.75 5.00 5.25 5.50 supply voltage (v) i oh (ma) supply current vs. supply voltage (t = 25c, non-turbo, bit6 = 0, bit 30 = 0) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 4.00 4.50 4.75 5.00 5.25 5.50 6.00 vcc (v) i cc (a) supply current vs. frequency asl (low-power) version (t a = 25c) 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.00 10.00 20.00 30.00 40.00 50.00 freq ue ncy (mhz ) i cc (ma) standard power reduced power output source current vs. output voltage (v cc =5v,t a = 25c) -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 output voltage (v) ioh (ma)
18 atf1502as(l) 0995j?pld?09/02 input clamp current vs. input voltage (v cc =5v,t a = 25c) -60 -50 -40 -30 -20 -10 0 -1.00 -0.80 -0.60 -0.40 -0.20 0.00 input voltage (v) input current (ma) output sink current vs. supply voltage (vol = 0.5v, t a = 25c) 34 35 36 37 38 39 40 41 42 43 4.50 4.75 5.00 5.25 5.50 supply voltage (v) iol (ma) normalized tpd vs. supply voltage (t a = 25c) 0.80 0.90 1.00 1.10 1.20 4.54.85.05.35.5 supply voltage (v) normalized tpd input current vs. input voltage (v cc =5v,t a =25c) -30 -20 -10 0 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) input current (ma) output sink current vs. output voltage (v cc =5v,t a = 25c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 output voltage (v) iol (ma) normalized tpd vs. temperature (v cc =5.0v) 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized tpd
19 atf1502as(l) 0995j?pld?09/02 normalized tco vs. supply voltage (t a =25c) 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized tpd normalized tsu vs. supply voltage (t a =25c) 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized tsu normalized tco vs. temperature (v cc =5.0v) 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized tco normalized tsu vs. temperature (v cc =5.0v) 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized tsu
20 atf1502as(l) 0995j?pld?09/02 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gnd ground pins vcc vcc pins for the device (+5v) atf1502as dedicated pinouts dedicated pin 44-lead tqfp 44-lead j-lead input/oe2/gclk2 40 2 input/gclr 39 1 input/oe1 38 44 input/gclk1 37 43 i/o / gclk3 35 41 i/o / pd (1,2) 5, 19 11, 25 i/o / tdi (jtag) 1 7 i/o / tms (jtag) 7 13 i/o / tck (jtag) 26 32 i/o/tdo(jtag) 32 38 gnd 4, 16, 24, 36 10, 22, 30, 42 vcc 9, 17, 29, 41 3, 15, 23, 35 # of signal pins 36 36 # user i/o pins 32 32
21 atf1502as(l) 0995j?pld?09/02 atf1502as i/o pinouts mc plc 44-lead plcc 44-lead tqfp 1a442 2a543 3a/ pd1 644 4/ tdi a71 5a82 6a93 7a115 8a126 9/ tms a137 10 a 14 8 11 a 16 10 12 a 17 11 13 a 18 12 14 a 19 13 15 a 20 14 16 a 21 15 17 b 41 35 18 b 40 34 19 b 39 33 20/ tdo b3832 21 b 37 31 22 b 36 30 23 b 34 28 24 b 33 27 25/ tck b3226 26 b 31 25 27 b 29 23 28 b 28 22 29 b 27 21 30 b 26 20 31 b 25 19 32 b 24 18
22 atf1502as(l) 0995j?pld?09/02 using ?c? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ?i? to the ?c? device (7 ns ?c? = 10 ns ?i?) and de-rate power by 30%. ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 7.5 4.5 166.7 atf1502as-7 ac44 atf1502as-7 jc44 44a 44j commercial (0 cto70 c) 10 5 125 atf1502as-10 ac44 atf1502as-10 jc444 44a 44j commercial (0 cto70 c) atf1502as-10 ai44 atf1502as-10 ji44 44a 44j industrial (-40 cto+85 c) 15 8 100 atf1502as-15 ac44 atf1502as-15 jc44 44a 44j commercial (0 cto70 c) atf1502as-15 ai44 atf1502as-15 ji44 44a 44j industrial (-40 cto+85 c) 25 13 60 ATF1502ASL-25 ac44 ATF1502ASL-25 jc44 44a 44j commercial (0 cto70 c) ATF1502ASL-25 ai44 ATF1502ASL-25 ji44 44a 44j industrial (-40 cto+85 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier otp (plcc)
23 atf1502as(l) 0995j?pld?09/02 packaging information 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
24 atf1502as(l) 0995j?pld?09/02 44j?plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 17.399 17.653 d1 16.510 16.662 note 2 e 17.399 17.653 e1 16.510 16.662 note 2 d2/e2 14.986 16.002 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45 ? pin no. 1 identifier 1.14(0.045) x 45 ? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 ? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 0995j?pld?09/02 xm at m e l ? is the registered trademark of atmel. other terms and product names may be the trademarks of others.

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