PM50CTJ060-3 mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type outline drawing dimensions in mm application air-conditioner, general purpose inverter, servo drives and other motor controls ? 4th gen. planer igbts are integrated ? 3 50a, 600v current-sense igbt type inverter ? monolithic gate drive & protection logic ? detection, protection & status indication circuits for over-current, short-circuit, over-temperature & under-voltage ? acoustic noise-less 3.7kw class inverter application label 2 1 16 17 18 19 20 35 46 8 79 11 10 12 14 13 15 pnuvw a : detail b : detail 2?5 2 4.5 56 0.8 84.5 0.5 3.5 0.5 33.6 0.8 44 1 5.5 5.5 5.5 10.5 3.5 8 6.35 0.8 0.1 8 0.5 3.4 0.1 3.45 1.25 7.95 (1) 16 1 19.4 1 x=3.56 0.25mm 8. 9. 10. 11. 12. 13. 14. terminal code 1. 2. 3. 4. 5. 6. 7. v upc u p v up1 v vpc v p v vp1 v wpc vw p1 v p v nc v n1 u n v n w n f o p u n v w ab 14 0.3 (14.25) 94.5 1 64 0.5 2 0.8 76 3.56 ? 17=60.52 0.8 3.56 0.3 19 (11.99) 7.12 7.12 7.12 (t = 0.4) tab #250(t = 0.8) 1.65 15. 16. 17. 18. 19. 20. (t=0.8) mar. 2001
mar. 2001 v v v a a w c 450 500 600 50 100 100 20 ~ +125* applied between : p-n applied between : p-n, surge value t c = 25 c t c = 25 c t c = 25 c supply voltage supply voltage (surge) collector-emitter voltage collector current collector current (peak) collector dissipation junction temperature v nc v n1 f o w n v n u n v wpc w p v wp1 v vpc v p v vp1 v upc u p v up1 gnd in v cc gnd out gnd in v cc gnd out gnd in v cc gnd out s wn o wn s vn o vn s un o un gnd v cc f o w n v n u n tc tb gnd nwvup v cc v cc(surge) v ces i c i cp p c t j mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type maximum ratings (tj = 25 c, unless otherwise noted) inverter part symbol parameter conditions ratings unit equivalent circuit diagram * the item defines the maximum junction temperature for the power elements (igbt/diode) of the ipm to ensure safe operation. ho wever, these power elements can endure junction temperature as high as 150 c instantaneously. to make use of this additional temperature allowance, a detailed study of the exact applica- tion conditions is required and, accordingly, necessary information is requested to be provided before use. ratings applied between : v up1 -v upc , v vp1 -v vpc v wp1 -v wpc , v n1 -v nc at : u p , v p, w p, u n , v n , w n terminals applied between : f o -v nc sink current of f o terminals i cin v fo i fo input current fault output supply voltage fault output current conditions control part symbol parameter unit ma v ma 20 20 20 v d supply voltage 20 v
mar. 2001 t j = 25 c t j = 125 c pnuvw tc total system parameter symbol supply voltage protected by oc & sc module case operating temperature storage temperature isolation voltage conditions t c t stg v iso ratings v cc(prot) 400 20 ~ +100 40 ~ +125 2500 unit c c v rms v v d = 13.5 ~ 16.5v, inverter part, t j = 125 c start (note 1) 60hz, sinusoidal, charged part to base, ac 1 min. note 1 : t c measurement point. inverter igbt part (per 1/6 module) inverter fwd part (per 1/6 module) case to fin, (per 1 module) thermal grease applied thermal resistances symbol parameter test conditions unit r th(j-c)q r th(j-c)f r th(c-f) c / w c / w c / w limits min. tye. max. 1.2 2.9 0.4 junction to case thermal resistances contact thermal resistance collector-emitter saturation voltage collector-emitter cutoff current min. typ. max. i c = 50a, v d = 15v, i cin = 0ma (fig. 2) t j = 25 c t j = 125 c v ma unit parameter symbol test conditions v ce(sat) i ces v ec t on t rr t c(on) t off t c(off) limits v s s s s s 2.6 3.0 3.5 2.0 0.9 4.0 2.0 1 10 0.5 1.8 2.0 2.5 1.0 0.1 0.3 3.0 1.0 fwd forward voltage switching time v d = 15v, i cin = 0ma ? 10ma v cc = 300v, i c = 50a t j = 125 c inductive load (upper-lower arm) (fig. 3) v ce = v ces , v d = 15v (fig. 4) electrical characteristics (tj = 25 c, unless otherwise noted) inverter part v d = 15v, i cin = 10ma i c = 50a, pulsed (fig. 1) mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type
mar. 2001 v n1 -v nc v xp1 -v xpc at : u p -v upc , v p -v vpc , w p -v wpc u n v n w n -v nc terminals 20 c t j 125 c, v d = 15v (fig. 5, 6) (lower arm only) 20 c t j 125 c, v d = 15v (fig. 5, 6) (lower arm only) v d = 15v (fig. 5, 6) v d = 15v (note 2) parameter 1.47 1.18 80 mounting torque weight v d = 15v, i cin = 0ma baseplate temperature detection, v d = 15v 20 c t j 125 c (lower arm only) v d = 15v, v fo = 15v (note 2) ma ma a a s c c v v ma ma ms 35 10 5 5 120 12.5 0.01 15 25 5 3 3 91 130 10 110 90 12.0 12.5 10 1.8 min. input on threshold current input off threshold current over current trip level short circuit trip level over current delay time minimum fault output pulse width 1 1 65 100 11.5 1.0 over temperature protection supply circuit under voltage protection fault output current trip level reset level trip level reset level note 2 : fault output is given only when the internal oc, sc, ot & uv protections schemes of lower arm device operate to protect it. circuit current parameter symbol test conditions max. typ. unit limits control part i d ma i th(on) i th(off) oc sc t off(oc) ot ot r uv uv r i fo(h) i fo(l) t fo applied across p-n terminals applied between : v up1 -v upc , v vp1 -v vpc v wp1 -v wpc , v n1- v nc for ipm s each input signals, (fig. 7) for ipm s each input signals, (fig. 7) at : u p , v p , w p , u n , v n , w n terminals v cc i cin(on) i cin(off) f pwm t dead v ma ma khz s input on current input off current pwm input frequency arm shoot-through blocking time v d supply voltage v 0.98 mechanical ratings and characteristics symbol parameter test conditions limits unit n m g min. typ. max. mounting part screw : m4 recommended conditions for use symbol test conditions limits unit 0 13.5 5 0 3.5 min. typ. max. 300 15.0 10 400 16.5 20 1 8 mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type
mar. 2001 10% 90% trr irr tr td (on) tc (on) tc (off) td (off) i cin vce 10% 90% tf ton= td (on) + tr toff= td (off) + tf v d (all) u,v,w,(n) p,(u,v,w) a pulse v cc i cin i cin v d (all) u,v,w,(n) p,(u,v,w) v cc i c i c i c oc sc i cin toff (oc) toff (oc) u,v,w snubber n i cinn i cinp v d v d p i c v cc i cinn 0a 0a i cinp t t t dead t dead t dead p, (u,v,w,b) u,v,w, (n) u,v,w,(n) v d (all) v d (all) i cin ic v v p,(u,v,w) all open p n n u,v,w v cc v cc i c i c i c v d (all) v d (all) p u,v,w i cin i cin short circuit over current constant current constant current fig. 5 oc and sc test fig. 6 oc and sc test waveform fig. 7 dead time measurement point example fig. 3 switching time test circuit and waveform fig.1 v ce(sat) test fig.2 v ec test a) lower arm switching signal input (upper arm) signal input (lower arm) signal input (upper arm) signal input (lower arm) b) upper arm switching fig.4 i ces test signal input signal input ic precautions for testing 1. before appling any control supply voltage (v d ), the input signals should be turned on from its off state. after this, the specified on and off level setting for each input signal should be done. 2. when performing oc and sc tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above v ces rating of the device. (these test should not be done by using a curve tracer or its equivalent.) mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type
mar. 2001 v d1 v d2 v d3 560 v up1 v cc gnd out gnd in p u v w n v upc u p 560 v vp1 v cc gnd out gnd in v vpc v p 560 v wp1 v cc gnd gnd tc tb out gnd in v wpc u n u n 560 560 560 33 v n v d4 v n1 v nc w n f o v n w n f o v cc o un s un o vn o wn s wn s vn gnd w p + + + notes for stable and safe operation ; design the pcb pattern to minimize wiring length between opto-coupler and ipm s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. connect low impedance capacitor between the vcc and gnd terminal of each switching opto-coupler. slow switching opto-coupler : ctr = 100%~200% use 4 isolated control power supplies (v d ). also, care should be taken to minimize the instantaneous voltage charge of the power supply. make inductance of dc bus line as small as possible, and minimize surge voltage using snubber capacitor between p and n terminal. use line noise filter capacitor (ex. 4.7nf) between each input ac line and ground to reject common-mode noise from ac line and improve noise immunity of the system. mitsubishi semiconductor PM50CTJ060-3 insulated package flat-base type
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