83 real time clock module external dimensions terminal connection ( unit: mm ) nc is not connected internally. 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 specifications (characteristics) absolute max. rating operating conditions frequency characteristics dc characteristics ? 1 ? storage temperature as a discrete component. ( v dd = 5.0 v 10 %, ta = -10 to + 70 c ) 1: the frequency deviation (o x 10 -6 ) at ta=+25 c for top or at v dd =5 v for fv is used as the reference value. note: for information on handling batteries, please independently refer to the pertinent regulations, as this product does not come equipped with batteries. no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 no. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a 0 a 1 tmode tclock stby d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd pin terminal rtc xram wr nc rd reset irq nc a 5 a 4 sqw v dd a 3 a 2 pin terminal 36.8 max. 14.6 9.0 max. 0.75 3.3 15.24 15.24 to 18.0 2.54 0.46 rtc 65271 5201c e 8-bit real time clock module RTC-65271 built-in crystal unit allows adjustment-free efficient operation. a builtin power supply switching circuit makes it possible to provide automatic power supply backup to both the rtc and extended ram. the real-time clock block consists of: indirect register: 1-byte control register: 4-bytes clock, alarm, calendar: 10-bytes user ram: 50-bytes extended ram: 4k-bytes of builtin s-ram page register: 1-byte configuration: 32-bytes x 128 pages the package is a 28-pin dip ic with a battery holder that makes battery replacement possible. b atteries (br1225) are available as an option. (batteries are packed separately from the rtc .) item supply voltage input voltage storage temperature soldering condition symbol v dd v in t stg t sol condition v dd - gnd input pin ? 1 unit v c item supply voltage operating temperature symbol v dd t opr condition ------- item frequency tolerance temperature characteristics voltage characteristics aging symbol ? f/fo t op fv f a ta=+25 c, v dd =5 v ta=-10 to +70 c, v dd =5 v ? 1 ta=stable, v dd =3 v ? 1 ta=+25 c, v dd =5 v, first year condition item input voltage input leak current output voltage power supply current current when using battery backup input current symbol v ih v il i i v oh v ol i dd i bat i stby condition ______ ___ ___ ____ reset,rd, wr, rtc, ______ xram, d 0 to d 7 , a 0 to a 5 v dd =5 v, i load =-4 ma v dd =5 v, i load =4 ma output unloaded ta=+25 c ______ stby=gnd max. v dd +0.3 0.8 1 0.4 15 1.0 2 unit v a v ma a min. 2.2 -0.3 2.4 min. -0.3 -40 max. +7.0 v dd +0.3 +85 +260 c or less, for 10 s or less; (package should be +150 c or less) unit v c min. 4.75 -10 max. 5.5 +70 typ. 5.0 max. 520 +10 -120 5 5 unit x 10 -6 x 10 -6 /v x 10 -6 /year typ. 0.5 actual size batteries in this photograph are used only to show the inserted condition. this rtc is not supplied with the batteries inserted .
84 real time clock module indirect address reg rtc data register 14-bytes rtc 14-bytes real time clock 50-bytes user-ram indirect address 00 00 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0d 0e 3f 3f seconds second alarm minutes minute alarm hour alarm hours day of week day of month month year register a register b register c register d 128 pages of 32-bytes extended ram page 7f 02 01 page 00 xram xram page register xram + 1f xram + 3f xram + 20 xram + 21 thru thru aliases of page register a 0 to a 5 rtc valid valid valid xram wr data bus write (d o to d 7 ) data data rd data bus read (d o to d 7 ) t cyc t f t f t cws t dsw t ch t ah t dhw t aws t rwl t r t r t crs t ch t dhr t ah t ars t rwl t ddr tclock tmode v dd bus interface stby d o to d 7 rd wr a 0 to a 5 a 0 to a 4 rtc xram selector 50 %duty 8.192 khz osc on / off power switching reference pok vpp ce data / control divider chain 13 taps to selector periodic intr / sq wave selector rs0 to rs3 decoder register index 4 10 1 3 3 registers a,b,c,d clock, calendar, and alarm registers column decoder, 1 of 8 50-bytes user-ram row decoder, 1 of 8 row decoder, 1 of 32 dv0 to dv2 sqw reset irq clock calendar update extended ram register extended ram 4096-bytes column decoder, 1 of 128 switching characteristics timing chart address map block diagram rtc address map extended ram address map (v dd = 5 v 10 %, gnd =0 v, ta = -10 to +70 c) item cycle time pulse width rd __ /wr __ = l interval signal rise / fall time cs, rd __ , wr __ address holding time address setup before rd __ address setup before wr __ chip select setup time before rd __ chip select setup time before wr __ chip select hold time a after rd __ /wr __ read data holding time write data holding time rd __ peripheral output data delay time peripheral write data setup time symbol t cyc t rwl t r, t f t ah t ars t aws t crs t cws t ch t dhr t dhw t ddr t dsw min. 395 325 __ 20 50 0 50 0 20 10 0 20 200 max. dc 30 100 240 remarks ns __ __ __ __
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