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semiconductor group 1 1998-02-01 2.5-a high performance smart power stepper-motor driver with diagnostic interface spt-ic overview features ? single phase driver for stepper motor 2.5 a ? low on-resistance (typical 0.3 w ) ? wide supply range 6 v to 45 v ? wide current range 10 ma to 3 a ? fast nominal/actual comparator for micro stepper mode ? wide temperature range ? short circuit protection ? under voltage shutdown ? overtemperature shutdown ? serial diagnostic interface ? fast freewheeling diodes ? ttl-compatible inputs p-sip-15-1 tle 5250 description tle 5250 is a monolithic ic in smart power technology for controlling and regulating the motor current in one phase of a bipolar stepping motor. there are other applications in driving dc motors and inductive loads that are operated on constant current. the device has ttl-compatible logic inputs, includes a h-bridge with integrated, fast free-wheeling diodes plus dynamic limiting of the motor current by a chopper mode. the nominal current can be set continuously by a control voltage. microstep mode can be produced by applying a sinusoidal control voltage. two tle 5250s, with a minimum of external circuitry and a single supply voltage, form a complete system - that can be driven direct by an mc- for two-phase, bipolar stepping motors with output current of up to 2.5 a per phase. the outputs of the ic are internally protected against shorted to ground, supply voltage and shorted load. the output stages are also disabled by undervoltage and overtemperature. all fault functions can be detected by the internal diagnostics, which can be read out serially. type ordering code package tle 5250 q67000-a9103 p-sip-15-1
tle 5250 semiconductor group 2 1998-02-01 figure 1 pin configuration (top view) 15 1 diag ph en q1 q1 sense gnd sense q2 q2 rs nom act aep01471 v s s v
tle 5250 semiconductor group 3 1998-02-01 pin definitions and functions pin no. symbol function 1 diag open-drain diagnostics output 2 ph input for determining source/sink on outputs q1 and q2; when enable = low, this pin serves as clock input for reading out diagnostics 3 en input for activating or turning off device (all output transistors turned off); enable high = output active, enable low = diagnostics 4, 12 v s supply voltage of ic 5, 6 q1 power output with integrated free-wheeling diodes 7, 9 sense actual-current output: shared, open-source output of sink transistors 8 gnd ground 10, 11 q2 power output with integrated free-wheeling diodes 13 rs determines turning back on of sink transistor by internally driven, external rc element or external ttl trigger signal 14 nom input for reference potential (nominal current) for nominal/ actual comparator 15 act input for actual current for nominal/actual comparator
tle 5250 semiconductor group 4 1998-02-01 figure 2 block diagram aeb01468 + - q1 high q2 high q1 low q2 low g on t4 g on t5 driver 1 functional logic undervoltage overtemperature overload driver 4 t3 driver 3 - + - + - + - + - + t1 t2 t3 t4 diagnostics logic + - off/ i charge chop logic - + v ref 1 ma nom/act comp pwm logic 15 actual rc/sync 13 8 gnd 14 nominal 1 diagn 2 phase enable 3 t4 sense 7 sense 9 t2 t1 driver 2 v s -1.5 v -1.5 v s v 3 v 3 v 5 v 5 v h-bridge output stage 5 6 q1 q2 11 10 bandgap/bias charge pump -6 v s v cc1 v v cc2 bias v s s vv s 412 cooling pin 16
tle 5250 semiconductor group 5 1998-02-01 application two tle 5250 drivers are required to operate a bipolar stepping motor. to implement full-step operation, a squarewave voltage with the required stepping frequency is applied to the phase input of the upper driver, and the same squarewave voltage, but offset in phase by 90 el, to the phase input of the lower driver. motor-current limiting is produced by a dc signal that is applied to both nominal-current inputs. in microstep operation the nominal current tracks sinusoidally and synchronously with the required stepping frequency. this produces a sinusoidal current in the motor windings to ensure very smooth running and a high stepping frequency. if an instantaneous nominal value (sine or cosine) is held on the second driver, it is possible to set a certain angle of rotation while the motor is stationary. the motor current produced by this depends on nominal voltage and sense resistance (normally 0.5 w ), i.e. the actual voltage should be thoroughly filtered for precise current regulation, especially in microstep operation. so the actual input is accessible, and an rc element is necessary between the sense output and actual input. the resistance r r should correspond to the internal resistance of the nominal-current input-voltage source to prevent additional voltage offset on the nominal/actual comparator. circuit description outputs outputs q1 and q2 are fed by push-pull output stages. four integrated free-wheeling diodes referred to ground or the supply voltage protect the integrated circuit against reverse voltages from an inductive load. enable and phase outputs q1 and q2 can be disabled by a voltage v inh of 0.8 v on the enable pin. the sink transistors are enabled by v inh 3 2v. the voltage on the phase input determines the phase of the output current. output q1 acts as a sink for v ph 0.8 v and as a source for v ph 3 2v. for output q2 this is reversed: sink for v ph 3 2 v and source for v ph 0.8 v. the sink transistors are chopped. low signal on the enable pin plus a clock signal on the phase pin enable readout of the multiplexer. i m v [] v nom v [] r s w [] ---------------------- - =
tle 5250 semiconductor group 6 1998-02-01 nominal-current input the peak current in the motor winding is defined by the voltage on the nominal input. this is compared by a fast comparator to the voltage drop on the actual-current sensor. if the nominal current is exceeded, the sink transistors of the outputs are turned off by the logic. rc/sync input the outputs are turned on by the signal applied to the rc input. synchronization is possible by ttl signal or chopper mode with an external rc combination. chopper mode after the supply voltage is applied, capacitor ct is charged with constant current of 1 ma. a regulator limits the maximum voltage on the capacitor to 2.3 v. as a result of the rising current in the motor winding, the voltage on the actual sensor increases. once the value defined by the nominal-current input is exceeded, the fast comparator resets an rs flipflop. thus sink transistors t3 and t4 are turned off by the logic. the charge current is turned off and the parallel rt discharges ct. the internal logic is designed so that capacitor ct is always charged before the discharge operation is triggered. this guarantees a constant charge time, even for very small coil currents (see figure 7 ). sync operation if a sync signal with ttl level is applied to the rc input, the negative edge will set the rs flipflop - by way of the combined schmitt trigger and monoflop - if the voltage on the current sensor is smaller than the nominal value on the nominal-current input. as in chopper mode, the appropriate output transistors conduct. they are again turned off by resetting the rs flipflop when the voltage on the current sensor becomes greater than the nominal value (see figure 8 ). output-stage control this part of the circuit handles turn-off of the output stages when the output is shorted to ground. there is separate current monitoring for this purpose in the source transistors. the temperature of the output stages is also monitored. if this exceeds 175 c, all output stages are turned off, and then turned on again when the temperature drops. undervoltage also causes turn-off of the transistors in the output stages. these possible fault states are stored in the diagnostics register.
tle 5250 semiconductor group 7 1998-02-01 diagnostics the information from the different parts of the circuit is collected in the diagnostics and stored in the fault logic. the information is read out on the diagnostics output (open collector). the fault logic consists of a 16-bit multiplexer that switches information in three categories through to the diagnostics output. bit 0 always appears inverted on diag when en is high. this means that, if there is overcurrent on the upper transistor, undervoltage or overtemperature, it will be signaled immediately on the diagnostics output. diag changes from high to low. bit 1: check bit. bits 2, 3, 4 and 5 indicate the momentary status of the comparators on the two outputs (see figure 2 ). changes in the status of the comparators for output monitoring can be observed on diag when en is low and the counter of the multiplexer is on 2, 3, 4 or 5. this is necessary for detecting underload. bits 6, 7, 8, 9 the monoflop generates a short strobe signal when the en edge changes from high to low. the status of the comparators for output monitoring is stored with this signal and can be read out in bits 6, 7, 8 and 9. when enable is low, the phase input is used as a clock input. as the edge rises, an internal counter is incremented and the corresponding channel of the multiplexer is switched through. as the edge falls, the signal is output inverted. when enable is high, the counter is reset to zero. figure 3 aed01467 en strobe reset
tle 5250 semiconductor group 8 1998-02-01 bits 10, 11 with these bits it is possible to detect the status of the gate voltages of the lower output- stage transistors t3 and t4. bit 10: status for en edge transition. bit 11: whether the lower transistor has at all been turned on. bit 12 indicates whether the nominal/actual comparator has switched. the comparator switches when the output current is regulated. bits 13, 14, 15 these bits indicate the presence of overcurrent, undervoltage or overtemperature. a fault is ored and output direct by bit 0 on di. when the multiplexer is read out, bits 0 through 15 are output once non-inverted (phase = low) and once inverted (phase = high). bit assignment in error register bit 0 = high for overtemperature/undervoltage/overcurrent bit 1 = always high bit 2 = high when sink transistor q1 turned on bit 3 = high when sink transistor q2 turned on bit 4 = high when source transistor q1 turned on bit 5 = high when source transistor q2 turned on bits 2-5 = momentary states for readout bit 6 = bit 2 state for falling edge of enable signal bit 7 = bit 3 state for falling edge of enable signal bit 8 = bit 4 state for falling edge of enable signal bit 9 = bit 5 state for falling edge of enable signal bits 6-10 represent status of outputs for negative change in edge of enable signal bit 11 = high if gate-source voltage of sink transistors is > 5 v at moment of readout bits 11-15 are set if event occurs during switching (enable = high) bit 11 = high if sink transistor v gs > 5 v bit 12 = high if actual current lower than nominal current bit 13 = high if overcurrent detected on source transistors bit 14 = high if undervoltage detected bit 15 = high if thermal link tripped the memories are erased by a rising edge on the enable input.
tle 5250 semiconductor group 9 1998-02-01 logic assignment: control inputs, output transistors l = low voltage level, input open h = high voltage level x = transistor turned off C = transistor conducting C = transistor conducting, switched in current limiting / = output high-impedance enable l l h h phase l h l h output q1 / / l h output q2 / / h l transistor t1 transistor t2 transistor t3 transistor t4 x x x x x x x x x C C x C x x C
tle 5250 semiconductor group 10 1998-02-01 figure 4 pwm logic & & input input gate gate + - nominal actual s r rs ff q n/a output t dq r dff charge-current and switching- threshold control, reset-pulse generation + - deadtime comparator - + rc/sync nom/act comparator dt output 5 v 5 v 1 ma 2.3 v aes01469 ff 1.8 v 0.8 v t3 t4 t3 t4 qrs
tle 5250 semiconductor group 11 1998-02-01 figure 5 diagnostics logic s rq q 15 overtemperature latched 14 latched undervoltage 13 latched overcurrent t1/t2 12 to nominal latched actual current up 11 strobed gon status 10 strobed q2 high status 9 strobed q1 high status 8 strobed q2 low status 7 strobed q1 low status 6 continuous q2 high status 5 continuous q1 high status 4 continuous q2 low status 3 continuous q1 low status 2 check bit low 1 continuous error status 0 q q r s q q r s q q r s q q r s q q r s q q r s q q r s q q r s q q r s latched gon status mux 16-to-1 sequential multiplexer 1 reset clock & & & & & & & & & & overtemperature status undervoltage status overcurrent t1/t2 status nom/act stat. act>nom->high 1 1 gon t3 gon t4 gon status q2 high status q1 high status q2 low status q1 low status overcurrent flag 1 monoflop monoflop phase strobe latch reset enable m & 1 1 1 diagn. pin aes01470 q u x c h a n n e l _ < _ < _ < _ <
tle 5250 semiconductor group 12 1998-02-01 absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit min. max. supply voltage v s C 0.3 45 v supply current i s 03a peak currents on outputs i q C 3 3 a diode forward currents diode to + v s i fh C3a diode to sense i fl C3a output current on actual-current pin i act C3a voltage on actual-current pin v act C 0.3 5 v ground current, pin 6 i gnd C3a chip temperature t c C 40 150 c storage temperature t stg C 125 c thermal resistances junction to ambient r thja C70k/w junction case r thjc C3k/w operating range supply voltage v s 640v input voltage enable, phase, rc/sync v i C 0.3 5.5 v voltage on nominal pin v nom C 0.3 2 v voltage on actual pin v act C2v output current q1, q2 i q C 2.5 2.5 a junction temperature t j C 40 150 c enable and phase inputs h input voltage v ih 2Cv l input voltage v il C0.8v
tle 5250 semiconductor group 13 1998-02-01 characteristics v s = 6 to 25 v; t j 150 c parameter symbol limit values unit test condition min. typ. max. supply current i s C C 11 ma enable = high output q1, q2 turn-on resistance of output transistors r ds on 0.3 C 0.5 w i = 2.5 a, 150 c phase deadtime t d C10C m sC diode forward voltage output to + v s v fq CC1.5v i fh = 2.5 v diode forward voltage actual-current pin to output C CC1.5v i fh = 2.5 v nominal current input current i i8 012 m aC offset voltage measured for 0 v actual/nominal pin v i(8 C 4) C 4 C 8 mv C actual current turn-off delay of nom/act comparator t d CC0.5 m sC common-mode error v comm C 5 C 10 mv C rc/sync sync frequency f C20100khzC trigger threshold lower upper v tl v th 0.8 1.7 C C 1 2 v v C C maximum charge voltage v chm 2.2 2.3 2.4 v r = 39 k w c = 820 pf
tle 5250 semiconductor group 14 1998-02-01 characteristics (contd) parameter symbol limit values unit test condition min. typ. max. undervoltage cutout disable v udiag 4CCvC enable v uen CC5.3vC hysteresis v uh CC400mvC diagnostics output activating delay (enable high ? low) t def C C 400 ns C delay phase low to high t ddr C C 500 ns enable = low v s > 5.5 v delay phase high to low t ddf C C 450 ns enable = low v s > 5.5 v output voltage low v diag CC0.4v i ql = 5 ma leakage current high i diag CC10 m a v qh = 5 v
tle 5250 semiconductor group 15 1998-02-01 figure 6 application circuit 1 aes01472 actual rc/sync. sense c f 680 pf r r 1 k w r k r t 39.2 k w w 0.5 s r t c 820 pf 68 pf n c w 1 k r n nominal enable phase diagnostics w 2 k r 5 v cooling pin q2 q1 m gnd c m v batt 100 nf 22 m f (tantalum) 1 nf 1 nf s v tle 5250
tle 5250 semiconductor group 16 1998-02-01 figure 7 chopper mode with external capacitor ct and resistor rt aed01475 discharge operation is started when nominal current is reached. is discharged by voltage on rc/sync was limited internally to 2.3 v in charge operation. c t r t . when coil current reaches nominal value, sink transistor is turned off. independently of this, rc element is charged up to 1.8 v and then discharged. charge operation is controlled by deadtime comparator. rc element is charged with 1ma. actual voltage coil current si out qrsff enable v rc/sync 2.3 v phase = high or low 1.8 v 0.8 v
tle 5250 semiconductor group 17 1998-02-01 figure 8 synchron mode aed01476 falling edge turns on sink transistor. sink transistor is turned off again when nominal voltage is reached. n/a output actual voltage qrsff rc/sync nominal voltage coil current
tle 5250 semiconductor group 18 1998-02-01 figure 9 response to inductive loads a) normal operation (no current regulation) aed01477 q2 bit 9 bit 0 strobe reset i l bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 q1 ph en q1 low q2 low q1 high q2 high q1 low strobed q2 low strobed q1 high strobed q2 high strobed for inductive load and faultfree operation, diagnostics when read out must show bit 2 inverted to bit 6 bit 3 inverted to bit 7 bit 4 inverted to bit 8 bit 5 inverted to bit 9
tle 5250 semiconductor group 19 1998-02-01 figure 10 response to inductive loads b) q1 shorted to + v s (phase = high) aed01478 q2 bit 9 bit 0 strobe reset i l bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 q1 ph en q1 low q2 low q1 high q2 high q1 low strobed q2 low strobed q1 high strobed q2 high strobed bit 2 identical to bit 6 bit 4 identical to bit 8 = fault
tle 5250 semiconductor group 20 1998-02-01 figure 11 response to inductive loads c) q2 shorted to + v s (phase = high) aed01479 q2 rc/sync bit 9 bit 10 bit 11 bit 12 strobe reset i l bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 q1 ph en
tle 5250 semiconductor group 21 1998-02-01 figure 12 response to inductive loads d) low load aed01480 q2 rc/sync bit 9 strobe reset i l bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 q1 ph en i l = 0 indication of low load: bit 2 = bit 3 bit 4 = bit 5 while enable = low and conditions bit 2 = /bit 6 bit 3 = /bit 7 bit 4 = /bit 8 bit 5 = /bit 9 are not all satisfied
tle 5250 semiconductor group 22 1998-02-01 package outlines 20 0.3 3.8 0.06 15 1.27 0.69 9.37 4.29 0.5 0.13 17.5 0.15 10.7 +0.15 17.78 1.52 0.08 0.1 4.62 max 4.14 0.33 0.25 21 max 1 17.78 m 0.25 15x m 0.61 15x p-sip-15-1 (plastic single in-line) gpi09015 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm

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