View A42U2604SERIES_3194854.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a42u2604 series preliminary 4m x 4 cmos dynamic ram with edo page mode preliminary (june, 2001, version 0.0) amic technology, inc. document title 4m x 4 cmos dynamic ram with edo page mode revision history rev. no. history issue date remark 0.0 initial issue june 13, 2001 preliminary
a42u2604 series preliminary 4m x 4 cmos dynamic ram with edo page mode preliminary (june, 2001, version 0.0) 1 amic technology, inc. features n organization: 4,194,304 words x 4 bits n part identification - a42u2604 (2k ref. ) n single 2.5v power supply/built - in vbb generator n low power consumption - operating: 120ma ( - 50 max) - standby: 1ma (ttl), 0.2ma (cmos), 250 a (self - refresh current) n high speed - 50/60/80 ns ras access time - 25/30/40 ns column add ress access time - 13/15/20 ns cas access time - 20/25/35 ns edo page mode cycle time n fast page mode with extended data out n read - modify - write, ras - only, cas - before - ras , hidd en refresh capability n ttl - compatible, three - state i/o n jedec standard packages - 300mil, 24/26 - pin soj - 300mil, 24/26 - pin tsop type ii package general description the a42u2604 is a new generation randomly accessed memory for graphics, organized in a 4,1 94,304 - word by 4 - bit configuration. this product can execute write and read operation via cas pin. the a42u2604 offers an accelerated fast page mode cycle with a feature called extended data out (edo). pin configuration n n soj n n tsop vcc i/o 0 i/o 1 a3 cas i/o 2 i/o 3 vss a42u2604s oe we ras a10 a0 a1 a2 vcc nc vss a4 a5 a6 a7 a8 a9 13 12 11 10 9 8 6 5 4 3 2 1 14 15 16 17 18 19 21 22 23 24 25 26 vcc i/o 0 i/o 1 a3 cas i/o 2 i/o 3 vss a42u2604v oe we ras a10 a0 a1 a2 vcc nc vss a4 a5 a6 a7 a8 a9 13 12 11 10 9 8 6 5 4 3 2 1 14 15 16 17 18 19 21 22 23 24 25 26 this allow random access of up to 2048(2k ref.) words within a row at a 50/40/28 mhz edo cycle, making the a42u2604 ideally suited for graphics, digital signal processing and high performance computing systems. pin descrip tions symbol description a0 - a10 address inputs (2k product) i/o 0 - i/o 3 data input/output ras row address strobe cas column address strobe we write enable oe outp ut enable vcc 2.5v power supply vss ground nc no connection
a42u2604 series prelimin ary (june, 2001, version 0.0) 2 amic technology, inc. selection guide symbol description - 50 - 60 - 80 unit t rac maximum ras access time 50 60 80 ns t aa maximum column address access time 25 30 40 ns t cac maximum cas access time 13 15 20 ns t oea maximum output enable ( oe ) access time 13 15 20 ns t rc minimum read or write cycle time 84 104 134 ns t pc minimum edo cycle time 20 25 35 ns functional description the a42u2604 reads and writes data by multiplexing an 22 - bit address into a 11 - bit(2k) row and column address. ras and cas are used to strobe the row address and the column address, respectively. a read cycle is performed by holding the we signal high during ras / cas operation. a write cycle is executed by holding the we signal low during ras / cas operation; the input data is latc hed by the falling edge of we or cas , whichever occurs later. the data inputs and outputs are routed through 4 common i/o pins, with ras , cas , we and oe controlling the in direction. edo page mode operation all 2048(2k) columns within a selected row to be randomly accessed at a high data rate. a edo page mode cycle is initiated with a row address latched by ras followed by a column address latched by cas . while holding ras low, cas can be toggled to strobe changing column addresses, thus achieving shorter cycle times. the a42u2604 offers an accelerated fast page mode cycle through a feature called extended data out, which keeps the output drivers on during the cas precharge time (t cp ). since data can be output after cas goes high, the user is not required to wait for valid data to appear before starting the next access cycle. data - out will remain valid as long as ras and oe are low, and we is high; this is the only characteristic which differentiates extended data out operat ion from a standard read or fast page read. a memory cycle is terminated by returning both ras and cas high. memory cell data will retain its correct state by maintaining power and accessing all 2048(2k) combinations of the 11 - bit(2k) row addresses, regardless of sequence, at least once every 32ms through any ras cycle (read, write) or ras refresh cycle ( ras - only, cbr, or hidden). the cbr refresh cycle automatica lly controls the row addresses by invoking the refresh counter and controller. power - on the initial application of the vcc supply requires a 200 s wait followed by a minimum of any eight initialization cycles containing a ras clock. d uring power - on, the vcc current is dependent on the input levels of ras and cas . it is recommended that ras and cas track with vcc or be held at a valid v ih during power - on to avoid current surges.
a42u2604 series prelimin ary (june, 2001, version 0.0) 3 amic technology, inc. block diagram recommended operating conditions (ta = 0 c to +70 c) symbol description min. typ. max. unit vcc power supply 2.25 2.5 2.75 v vss input high voltage 0 0 0 v v ih input high voltage 1.8 - vcc + 0.2 v v il inp ut low voltage - 1.0 - 0.8 v control clocks vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer row decoder column decoder memory array 4,194,304 x 4 cells sense amps & i/o data in buffer data out buffer vcc vss ras cas we a0~a10 a0~a10 i/o 0 to i/o 3 oe
a42u2604 series preliminary (june, 2001, version 0.0) 4 amic technology, inc. truth table function ras cas we oe address i/os standby h h x x x high - z read: word l l h l row/col. data out read l l h l row/col. data out wri te: word (early) l l l x row/col. data in write (early) l l l x row/col. data in read - write l l h ? l l ? h row/col. data out ? data in edo - page - mode read: hi - z - first cycle - subsequent cycles l l h ? l h ? l h h h ? l h ? l row/col. col. data out data out edo - page - mode write(early) - first cycle - subsequent cycles l l h ? l h ? l l l x x row/col. col. data in data in edo - page - mode read - write - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l l ? h l ? h row /col. col. data out ? data in data out ? data in hidden refresh read l ? h ? l l h l row/col. data out hidden refresh write l ? h ? l l l x row/col. data in ? high - z ras - only refresh l h x x row high - z cbr refresh h ? l l x x x high - z self r efresh h ? l l h x x high - z
a42u2604 series prelimin ary (june, 2001, version 0.0) 5 amic technology, inc. absolute maximum ratings* input voltage (vin) . . . . . . . . . . . . . . . - 0.5v to vcc+0.5v output voltage (vout) . . . . . . . . . . . . . - 0.5v to vcc+0.5v power supply voltage (vcc) . . . . . . . - 0.5v to vcc+0.5v o perating temperature (t opr ) . . . . . . . . . . 0 c to +70 c storage temperature (t stg ) . . . . . . . . . - 55 c to +150 c soldering temperature x time (t solder ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c x 10sec power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . . 1w short circuit output current (iout) . . . . . . . . . . . . . . 50ma latch - up current . . . . . . . . . . . . . . . . . . . . . . . . . . 200ma *comments stresse s above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (vcc = 2.5v 10%, vss = 0v, ta = 0 c to +70 c) - 50 - 60 - 80 symbol parameter min. max. min. max. min. max. unit test conditions notes i il input leakage current - 5 +5 - 5 +5 - 5 +5 m a 0v vin vin + 0.2v pins not under test = 0v i ol output leakage current - 5 +5 - 5 +5 - 5 +5 m a d out disabled, 0v vout + vcc i cc1 ope rating power supply current - 120 - 110 - 100 ma ras , ucas , lcas address cycling; t rc = min. 1, 2 i cc2 ttl standby power supply current - 1 - 1 - 1 ma ras = ucas = lcas =v ih i cc3 average power supply current, ras refresh mode - 120 - 110 - 100 ma ras cycling, ucas = lcas = v ih , t rc = min. 1 i cc4 edo page mode average power su pply current - 100 - 90 - 80 ma ras = v il , ucas , lcas address cycling; t pc = min. 1, 2 i cc5 cas - before - ras refresh power supply current - 110 - 100 - 90 ma ras , ucas , lcas cycling; t rc = min. 1 i cc6 cmos standby power supply current - 0.2 - 0.2 - 0.2 ma ras = ucas = lcas = vcc - 0.2v i cc7 self refresh mode current - 250 - 250 - 250 a ras = cas vss+0.2v all other input high levels are vcc - 0.2v or input low levels are vss +0.2v v oh 2.0 - 2.0 - 2.0 - v i out = - 2ma v ol output voltage - 0.4 - 0.4 - 0.4 v i out = 2ma
a42u2604 series preliminary (june, 2001, version 0.0) 6 amic technology, inc. ac characteristics (vcc = 2.5v 10%, vss = 0v, ta = 0 c to +70 c) test conditions: input timing reference level: v ih /v il =1.8v/0.8v output reference level: v oh /v ol =1.6v/0.8v output load: 1ttl gate + cl (100pf) assumed t t =2ns - 50 - 6 0 - 80 # std symbol parameter min. max. min. max. min . max. unit notes t t transition time (rise and fall) 1 50 1 50 1 50 ns 4, 5 2k - 32 - 32 - 32 ms 3 t ref refresh period self - ref - 128 - 128 - 128 ms 3 1 t rc random read or write cycle time 84 - 104 - 134 - ns 2 t rp ras precharge time 30 - 40 - 50 - ns 3 t ras ras pulse width 50 10k 60 10k 80 10k ns 4 t cas cas pulse width 7 10k 10 10k 15 10k ns 5 t rcd ras to cas d elay time 11 37 14 45 20 60 ns 6 6 t rad ras to column address delay time 9 25 12 30 15 40 ns 7 7 t rsh cas to ras hold time 7 - 10 - 10 - ns 8 t csh cas hold time 37 - 40 - 50 - ns 9 t crp cas to ras precharge time 5 - 5 - 5 - ns 10 t asr row address setup time 0 - 0 - 0 - ns 11 t rah row address hold time 7 - 10 - 10 - ns 12 t clz cas to output in low z 0 - 0 - 0 - ns 8 13 t rac access time from ras - 50 - 60 - 80 ns 6,7 14 t cac access time from cas - 13 - 15 - 20 ns 6, 12 15 t aa access time from column address - 25 - 30 - 40 ns 7, 12 16 t ar column address hold time from ras 44 - 55 - 70 - ns 17 t rcs read command setup time 0 - 0 - 0 - ns 18 t rch read command hold time 0 - 0 - 0 - ns 9
a42u2604 series preliminary (june, 2001, version 0.0) 7 amic technology, inc. ac characteristics (continued) (vcc = 2.5v 10%, vss = 0v, ta = 0 c to +70 c) test conditions: input timing reference l evel: v ih /v il =1.8v/0.8v output reference level: v oh /v ol =1.6v/0.8v output load: 1ttl gate + cl (100pf) assumed t t =2ns - 50 - 60 - 80 # std symbol parameter min. max. min. max. min . max. unit notes 19 t rrh read command hold time reference to ras 0 - 0 - 0 - ns 9 20 t ral column address to ras lead time 25 - 30 - 40 - ns 21 t coh output hold after cas low 5 - 5 - 3 - ns 22 t ods output disable setup time 0 - 0 - 0 - ns 23 t off output buffer t urn - off delay time 0 13 0 15 0 20 ns 8, 10 24 t asc column address setup time 0 - 0 - 0 - ns 25 t cah column address hold time 7 - 10 - 10 - ns 26 t oes oe low to cas high set up 5 - 5 - 10 - ns 27 t wcs write comm and setup time 0 - 0 - 0 - ns 11 28 t wch write command hold time 7 - 10 - 10 - ns 11 29 t wcr write command hold time to ras 44 - 55 - 70 - ns 30 t wp write command pulse width 7 - 10 - 10 - ns 31 t rwl write command to ras lead time 13 - 15 - 20 - ns 32 t cwl write command to cas lead time 7 - 10 - 10 - ns 33 t ds data - in setup time 0 - 0 - 0 - ns 34 t dh data - in hold time 7 - 10 - 15 - ns 35 t dhr data - in hold time to ras 4 4 - 55 - 70 - ns 36 t rwc read - modify - write cycle time 110 - 135 - 180 - ns 37 t rwd ras to we delay time (read - modify - write) 67 - 79 - 107 - ns 11 38 t cwd cas to we delay tim e (read - modify - write) 30 - 34 - 47 - ns 11
a42u2604 series preliminary (june, 2001, version 0.0) 8 amic technology, inc. ac characteristics (continued) (vcc = 2.5v 10%, vss = 0v, ta = 0 c to +70 c) test conditions: input timing reference level: v ih /v il =1.8v/0.8v output reference level: v oh /v ol =1.6v/0.8v output load: 1ttl gate + cl (100pf) assumed t t =2ns - 50 - 60 - 80 # std symbol parameter min. max. min. max. min. max. unit notes 39 t awd column address to we delay time (read - modify - write) 42 - 49 - 67 - ns 11 40 t oeh oe hold time from we 7 - 10 - 20 - ns 41 t oep oe high pulse width 2 - 2 - 5 - ns 42 t pc read or write cycle time (edo page) 20 - 25 - 35 - ns 13 43 t cpa access time from cas precharge (edo page) - 28 - 33 - 45 ns 12 44 t cp cas precharge time (edo page) 7 - 10 - 10 - ns 45 t pcm edo page mode rmw cycle time 58 - 68 - 80 - ns 46 t crw edo page mode cas pulse width (rmw) 34 - 38 - 42 - ns 47 t rasp ras pulse width (edo page) 50 100k 60 100k 80 100k ns 48 t csr cas setup time ( cas - before - ras ) 5 - 5 - 5 - ns 3 49 t chr cas hold time ( cas - before - ras ) 10 - 10 - 15 - ns 3 50 t rpc ras to cas precharge time ( cas - before - ras ) 5 - 5 - 5 - ns 51 t roh ras hold time reference to oe 5 - 5 - 5 - ns 52 t oea oe access time - 13 - 15 - 20 ns 53 t oed oe to data delay 13 - 15 - 20 - ns 54 t oez output buffer turn - off delay from oe 0 13 0 15 0 20 ns 8 55 t rass ras pulse width ( c - b - r self - refresh) 100 - 100 - 100 - m s 56 t rps ras precharge time ( c - b - r self - refresh) 84 - 104 - 134 - ns 57 t chs cas hold time ( c - b - r self - refresh) - 50 - 50 - 50 ns
a42u2604 series preliminary (june, 2001, version 0.0) 9 amic technology, inc. notes: 1. i cc1 , i cc3 , i cc4 , and i cc5 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. specified values are obtained with the outputs open. 3. an initial pause of 200 m s is required after power - up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas - before - ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without. 4. ac characteristics assume t t = 2ns. all ac parameters are measured with a load equivalent to one ttl load and 100pf, v il (min.) 3 gnd and v ih (max.) vcc. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6. operation within the t rcd (max.) limit insures that t rac (max.) can be m et. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled exclusively by t cac . 7. operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled exclusively by t aa . 8. assumes three state test load (5pf and a 500 w thevenin equivalent). 9. either t rch or t rrh must be satisfied for a read cycle. 10. t off (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. t wcs , t wch , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.) and t wch 3 t wch (min.), the cycle is an early write cycle and data - out pins will remain open circuit, high impedance, throughout the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read - modify - write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. access time is determined by the longer of t aa or t cac or t cpa . 13. t asc 3 t cp to achieve t pc (min.) and t cpa (max.) values.
a42u2604 series preliminary (june, 2001, version 0.0) 10 amic technology, inc. word read cycle t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(20) t rch(18) t rrh(19) t ar(16) t rcs(17) t roh(51) t oea(52) t rac(13) t aa(15) t cac(14) t clz(12) t oez(54) t off(23) high-z : high or low valid data-out row address column address i/o 0 ~ i/o 3 oe we address cas ras
a42u2604 series preliminary (june, 2001, version 0.0) 11 amic technology, inc. word write cycle (early write) t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(20) t wch(28) : high or low row address column address i/o 0 ~ i/o 3 oe address cas ras t ar(16) t cwl(32) t rwl(31) t wp(30) t wcs(27) valid data-in t ds(33) t dh(34) we t wcr(29) t dhr(35)
a42u2604 series preliminary (june, 2001, version 0.0) 12 amic technology, inc. word write cyc le ( late write) t ras(3) t rp(2 ) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) t ral(20) row address column address address cas ras t ar(16 ) t cwl(32) t rwl(31) t wp(30) t rah(11) t oeh(40) t oed(53) t ds(33) t dh(34) i/o 0 ~ i/o 3 : high or low oe we high-z vaild data-in t wcr(29) t dhr(35)
a42u2604 series preliminary (june, 2001, version 0.0) 13 amic technology, inc. word read - modify - write cycle t ras(3) t rp(2) t rwc(36) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t cah(25) t rad(6) row address column address address cas ras t ar(16) t rwl(31) t asc(24) t cwl(32) t awd(39) t cwd38) t rwd(37) t wp(30) t oea(52) t oez(54) t clz(12) t cac(14) t oed(53) t aa(15) t rac(13) t ds(33) t dh(34) high-z data-out data-in : high or low i/o 0 ~ i/o 3 oe we t oeh(40) t rcs(17)
a42u2604 series preliminary (june, 2001, version 0.0) 14 amic technology, inc. edo page mode word read cycle t rasp(47) t rp(2) ras cas t cas(4) t cas(4) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t ar(16) t ral(20) address oe we i/o 0 ~ i/o 3 : high or low t asc(24) t cp(44) t csh(8) t asc(24) t cah(25) t cah(25) row column column column t rch(25) t rcs(17) t rcs(17) t rch(25) t rcs(17) t cah(25) t rrh(19) t off(23) t oez(54) t aa(15) t oea(52) t oep(41) t cac(14) t clz(12) t oez(54) t cpa(43) t oes(26) t aa(15) t oea(52) t coh (21) t cac(14) t rac(13) t cac(14) t clz(12) data-out data-out data-out
a42u2604 series preliminary (june, 2001, version 0.0) 15 amic technology, inc. edo page mode early word write cycle t rasp(47) t rp(2) ras cas t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t cah(25) t asc(24) t ral(20) row column column address we t cwl(32) t wch(28) t wcs(27) t wcs(27) column t cwl(32) t wch(28) t wcs(27) t wch(28) t cwl(32) t rwl(31) t wp(30) t wp(30) t wp(30) t dh(34) t ds(33) t dh(34) t ds(33) t ds(33) t dh(34) data-in data-in data-in i/o 0 ~ i/o 3 oe : high or low
a42u2604 series preliminary (june, 2001, version 0.0) 16 amic technology, inc. edo page mode word read - modify - write cycle t rasp(47) ras t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pcm(45) t rsh(7) t rp(2) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t asc(24) t cah(25) t ral(20) t rcs(17) t cwd(38) t rwd(37) t cwl(32) t cwd(38) t cwl(32) t cwd(38) t cwl(32) t rwl(31) t oea(52) t oea(52) t oea(52) t wp(30) t wp(30) t wp(30) t awd(39) t awd(39) t awd(39) t roh(51) t cac(14) t aa(15) t rac(13) t oed(53) t oez(54) t ds(33) t aa(15) t cpa(43) t dh(34) t oez(54) t oed(53) t ds(33) t dh(34) t oez(54) t ds(33) t oed(53) t dh(34) t aa(15) t cpa(43) t clz(12) t clz(12) t clz(12) high-z : high or low i/o 0 ~ i/o 3 oe we address cas data-out data-in data-out data-in data-out data-in row column column column t oeh(40)
a42u2604 series preliminary (june, 2001, version 0.0) 17 amic technology, inc. ras only refresh cycle cas before ras refresh cycle t ras(3) t rp(2) t rc(1) ras t crp(9) t rpc(50) t asr(10) t rah(11) address : high or low row note: we, oe = don't care. cas t ras(3) t rp(2) t rc(1) ras t rp(2) t rpc(50) t pc(42) t csr(48) t chr(49) t off(23) i/o 0 ~ i/o 3 cas high-z : high or low note: we, oe, address = don't care.
a42u2604 series preliminary (june, 2001, version 0.0) 18 amic technology, inc. hidden refresh cycle (word read) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(16) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) address cas ras t rah(11) t rrh(19) t rcs(17) i/o 0 ~ i/o 3 : high or low oe high-z t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(20) t cac(14) t off(23) t aa(15) t clz(12) t rac(13) we row column valid data-out
a42u2604 series preliminary (june, 2001, version 0.0) 19 amic technology, inc. hidden refresh cycle (early word write) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(16) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) address ras t rah(11) : high or low oe t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(20) we row column t wcs(27) t wch(28) t wp(30) t ds(33) t dh(34) valid data-in i/o 0 ~ i/o 3 cas
a42u2604 series preliminary (june, 2001, version 0.0) 20 amic technology, inc. edo page mode read - early - write cycle (pseudo read - modify - write) ras : high or low i/o 0 ~ i/o 3 oe we address cas t rp(2) t rasp(47) t crp(9) t csh(8) t rcd(5) t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t cpr(9) t rsh(7) t pc(42) t pc(42) row column column t ral(20) t cah(25) t asc(24) t cah(25) t asc(24) t cah(25) t asc(24) t asr(10) t rah(11) t rad(6) t rad(6) column t rcs(17) t rch(18) t wcs(27) t wch(28) data-out data-out data-in t dh(34) t ds(33) t aa(15) t cap(43) t cac(14) t coh(21) t aa(15) t rac(13) t cac(14) t oea(52)
a42u2604 series preliminary (june, 2001, version 0.0) 21 amic technology, inc. self refresh mode n self refresh mode. a. entering t he self refresh mode: the a42u2604 self refresh mode is entered by using cas before ras cycle and holding ras and cas signal "low" longer than 100 m s. b. continuing the self refresh mo de: the self refresh mode is continued by holding ras "low" after entering the self refresh mode. it does not depend on cas being "high" or "low" after entering the self refresh mode continue the self refresh mode. c. ex iting the self refresh mode: the a42u2604 exits the self refresh mode when the ras signal is brought "high". t rass(55) t rp(2) t crp(9) t csr(48) t rpc(50) ras t rps(56) t chs(57) t asr(10) t cpn(42) t off(23) a0 ~ a10 : high or low high-z i/o 0 ~ i/o 3 ucas lcas row col note: we, oe = don't care.
a42u2604 series preliminary (june, 2001, version 0.0) 22 amic technology, inc. capacitance (ta = room temperature, vcc = 2.5v 10%) symbol signals parameter max. unit test conditions c in1 a0 - a10 5 pf vin = 0v c in2 ras , cas , we , oe input capacitance 7 pf vin = 0v c i/o i/o 0 - i/o 3 i/o capacitance 10 pf vin = vout = 0v ordering codes package \ ras access time 50ns 60ns 80ns refresh cycle self - refresh 24/26l soj (300mil) a42u2604s - 50 a42u2604s - 60 a42u2604s - 80 2k yes 24/26l tsop type ii (300mil) a42u2604v - 50 a42u2604v - 60 a42u2604v - 80 2k yes
a42u2604 series preliminary (june, 2001, version 0.0) 23 amic technology, inc. package information soj 24l/26l (300mil) outline dimensions unit: inches/mm e 1 e a 2 e e 2 12 13 24 s y a 1 b 2 b 19 18 1 6 7 pin 1 identifier - y - seating plane 0.004 a a a q d c dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.140 - - 3.56 a 1 0.070 0.080 0.090 1.78 2.03 2.29 a 2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.022 0.41 0.46 0.56 b 2 0.026 0. 028 0.032 0.66 0.71 0.81 c 0.008 0.010 0.014 0.20 0.25 0.36 d - 0.675 0.686 - 17.15 17.42 e 0.327 0.337 0.347 8.31 8.56 8.81 e 1 0.295 0.300 0.305 7.49 7.62 7.75 e 2 0.245 0.265 0.285 6.22 6.73 7.24 e 0.044 0.050 0.056 1.12 1.27 1.42 s - - 0.048 - - 1.22 q 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension e 2 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
a42u2604 series preliminary (june, 2001, version 0.0) 24 amic technology, inc. packa ge information tsop 24/26l (type ii) outline dimensions unit: inches/mm e d s b 13 12 1 24 e h e l 1 q 0.010 d y a 2 a 1 a l 1 l c dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - - 0.05 - - a 2 0.037 0.039 0.041 0.95 1.00 1 .05 b 0.012 0.016 0.020 0.30 0.40 0.50 c - 0.005 - - 0.127 - d 0.671 0.675 0.679 17.04 17.14 17.24 e 0.298 0.300 0.302 7.57 7.62 7.67 e - 0.050 - - 1.27 - h e 0.359 0.363 0.367 9.12 9.22 9.32 l - 0.031 - - 0.80 - l 1 0.016 0.020 0.024 0.40 0.50 0. 60 s - 0.037 - - 0.95 - y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. dimension d&e do not included interiead flash. 2. dimension b does not included dambar protrusion / intrusion. 3. dimension s includes end flash.

▲Up To Search▲

Price & Availability of A42U2604SERIES

	To Download A42U2604SERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .