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preliminary information AMD-761? system controller software/bios design guide publication # 24081 rev: d issue date: february 2002
preliminary information ? 2001, 2002 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd logo, amd athlon, and combinations thereof, amd-751, amd-760, AMD-761, amd-762, and amd-766 are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
table of contents 3 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information contents 1overview 1 1.1 general bios initialization requirements . . . . . . . . . . . . . . . 2 1.1.1 AMD-761? configuration spaces . . . . . . . . . . . . . . . . . . 2 1.1.2 special configur ation sequencing requirements . . . . 2 1.1.3 power-on reset initialization . . . . . . . . . . . . . . . . . . . . . 4 1.1.4 programming reserved bits . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 power management considerations . . . . . . . . . . . . . . . . 7 1.2 recommended amd athlon? processor sys_config settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 AMD-761? system controller programmer?s interface 9 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 iack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 pci configuration accesses . . . . . . . . . . . . . . . . . . . . . 15 2.3 address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 socket2000 address decoding . . . . . . . . . . . . . . . . . . . 16 2.3.2 pci/agp master address decoding . . . . . . . . . . . . . . . 17 2.4 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.1 i/o register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.2 configuration register access . . . . . . . . . . . . . . . . . . . 26 2.4.3 device 0: pci configuration registers . . . . . . . . . . . . . 27 2.4.4 device 0, function 1: ddr pdl configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.4.5 device 1: pci-to-pci bridge configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 117 2.5 memory-mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . 138 2.5.1 AMD-761 system controller gart cache overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 2.5.2 memory-mapped register map . . . . . . . . . . . . . . . . . . 140
4 table of contents AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 3 ddr sdram interface 149 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.2 ddr dimms and ddr sdrams . . . . . . . . . . . . . . . . . . . . . 150 3.2.1 ddr speed grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 3.2.2 ddr dimm data from serial presence detect (spd) device . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.3 memory space configuration . . . . . . . . . . . . . . . . . . . . . . . . 152 3.4 ddr memory dimm timings . . . . . . . . . . . . . . . . . . . . . . . . 157 3.4.1 memory timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.5 additional memory controller settings . . . . . . . . . . . . . . . 161 3.6 dram mode/status settings . . . . . . . . . . . . . . . . . . . . . . . . 165 3.7 ecc and memory scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . 169 3.7.1 ecc and memory scrubbing configuration . . . . . . . 172 3.8 programmable delay lines (pdl) . . . . . . . . . . . . . . . . . . . . 174 3.8.1 manual pdl window detection . . . . . . . . . . . . . . . . . 180 3.9 ddr i/o drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4 power management 185 4.1 c1 halt state requirements . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.2 c2 stop grant state requirements . . . . . . . . . . . . . . . . . . . 187 4.3 s1 power-on suspend state requirements . . . . . . . . . . . . . 189 4.4 s3 suspend to ram state requirements . . . . . . . . . . . . . . 190 4.4.1 str bit control for s3 support . . . . . . . . . . . . . . . . . . 191 4.5 clock throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.6 ddr dram clock enables . . . . . . . . . . . . . . . . . . . . . . . . . . 194
table of contents 5 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 5 pci bus interface 195 5.1 delayed transactions and ordering rules usage . . . . . . . 195 5.1.1 delayed transactions and target latency . . . . . . . . 196 5.1.2 transaction ordering rules . . . . . . . . . . . . . . . . . . . . 199 5.1.3 special arbitrat ion considerations for the southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.2 pci performance optimization options . . . . . . . . . . . . . . . . 202 5.2.1 read prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.2.2 pci chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.2.3 pci bus parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6agp interface 205 6.1 agp dynamic compensation require ments . . . . . . . . . . . . 205 6.1.1 the agp 4x dynamic compensation register . . . . . 206 6.1.2 selection of 1.5- or 3.3-v agp signalling . . . . . . . . . . 207 6.2 feature override bits for agp cards . . . . . . . . . . . . . . . . . 208 6.3 bios initialization requirements . . . . . . . . . . . . . . . . . . . . 209 6.4 agp miniport driver requirements . . . . . . . . . . . . . . . . . . 210 7 recommended bios settings 211 7.1 pci bus 0, device 0, function 0 registers . . . . . . . . . . . . . 212 7.1.1 example settings for memory timing . . . . . . . . . . . . 218 7.1.2 examples: agp compensation register settings (0xb4-0xbb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.1.3 pci bus 0, device 0, function 1 registers . . . . . . . . . 236 7.2 pci bus 0, device 1, function 0 registers . . . . . . . . . . . . . 246
6 table of contents AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information
list of figures 7 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information list of figures figure 1. amd athlon processor family address mapping . . . . . . . . . . 9 figure 2. amd athlon processor family x86 processor address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. AMD-761 system controller logical bus hierarchy . . . . . . . 19 figure 4. two-level gart indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 5. suspend to ram (str_control) bits usage. . . . . . . . . . . . . 193 figure 6. example of system with flag and data stored across pci bus domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
8 list of figures AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information
list of tables 9 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information list of tables table 1. AMD-761 system controller configuration register bits unknown at reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. recommended settings for amd athlon processor syscfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. AMD-761 system controller socket2000 memory map . . . . . 10 table 4. amd athlon processor special cycle encodings . . . . . . . . . . . 12 table 5. i/o register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. device 0, function 0 configuration register map . . . . . . . . . . 27 table 7. AMD-761 system controller serr# assertion control and status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. wait state settings for dram timing register . . . . . . . . . . . . 55 table 9. i/o pad drive strength and input type . . . . . . . . . . . . . . . . . . . 90 table 10. ddr memory base address register locations . . . . . . . . . . . . 95 table 11. AMD-761 dram addressing modes . . . . . . . . . . . . . . . . . . . . . 96 table 12. device 0, function 1 configuration register map . . . . . . . . . . 97 table 13. pdl calibration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 14. ddr pdl configuration register locations. . . . . . . . . . . . . . 101 table 15. device 1 configuration register map . . . . . . . . . . . . . . . . . . . 117 table 16. AMD-761 system controller memory-mapped registers . . . 140 table 17. typical cl parameter settings for pc1600 and pc2100 . . . . 151 table 18. dimm bank address bit definition. . . . . . . . . . . . . . . . . . . . . 152 table 19. memory size addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 20. total memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 21. AMD-761 system controller ddr sdram addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 22. memory sizing example, 128 mbytes total . . . . . . . . . . . . . . 156 table 23. memory sizing example, 320 mbytes total . . . . . . . . . . . . . . 157 table 24. cas latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 25. ddr device timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 26. dev 0:f0:0x54 bit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 27. system related timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 28. refresh rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
10 list of tables AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information table 29. AMD-761 system controller ecc behavior (with ecc enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 30. default dqs delay versus system clock frequency . . . . . . . 176 table 31. AMD-761 system controller power management features for acpi support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 32. AMD-761 processor system controller pci read transaction options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 33. allowable agp rate versus signalling level . . . . . . . . . . . . . 207 table 34. agp i/o settings for 1.5- and 3.3-v signalling . . . . . . . . . . . . 210
revision history 11 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information revision history date rev description 2/2002 d text added in the following locations explaining that the registers must be saved and restored when entering and exiting the s3 state: section 1.1.5 on page 7, 2nd paragraph added section 4 on page 185, first note expanded section 4.4 on page 190, paragraph two added section 7 on page 211, paragraph added directly after last bullet in bulleted list the following additional changes were incorporated: table 34 on page 210, values for pslewxfer and nslewxfer changed from 01 and 00, respectively, to 11 and 11 updated ?revision history? 8/2001 c public release. added bidirectional wsc# feature configuration register description. 4/2001 b modified descriptions for wsc# and wsc# feature additions. nda version only. 3/2001 a initial public release.
12 revision history AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information
chapter 1 overview 1 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 1 overview the amd athlon? proce ssor powers the next generation in computing platforms, delivering the ultimat e performance for cutting-edge applications and an unprecede nted computing experience. the AMD-761? system controller provides standard northbridge functionality for desktop personal computers using the amd athlon? family of processors. this functionality includes the proce ssor interface as well as pci, agp, and main memory interface implementing state of the art double data rate (ddr) synchronous dram technology. this document provides information typically required for development of the system bios and device drivers to properly program the AMD-761 system controller configuration registers. the document is organized as follows: section 1 provides an overview of the general bios requirements for initializing the AMD-761 system controller configuration registers. section 2 on page 9 contains a description of all AMD-761 system controller configuration registers. section 3 on page 149 contains additional information on setup of the ddr sdram interface configuration registers. section 4 on page 185 contains additional information on configuration of the power ma nagement features of the AMD-761 system controller. section 5 on page 195 contains additional information on setup of the pci bus interf ace configuration registers. section 6 on page 205 contains additional information on setup of the agp interface configuration registers. section 7 on page 211 cont ains a list of recommended settings for many of the AMD-761 system controller configuration registers.
2 overview chapter 1 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 1.1 general bios initialization requirements the following sections provid e general requirements for bios when programming the AMD-761 system controller configuration registers. note that the register descriptions also include some specific programming notes. 1.1.1 AMD-761? configuration spaces the AMD-761 system controller contains both i/o and memory- mapped configuration sp aces as listed below. i/o mapped space ? pci configuration space address and data (cf8h, cfch) host bridge registers ma pped in pci configuration space, device 0, function 0 ddr interface pdl and i/o controls mapped in pci configuration space to device 0, function 1 pci to pci bridge/agp registers mapped in pci configuration space to device 1, function 0 gart memory-mapped registers mapped in memory space as defined by the programming of base address 1: gart memory mapped register base 1.1.2 special configuration sequencing requirements this section outlines a few cases in the AMD-761 system controller configuration register s that require special handling for proper bios programming. configuration cycles enable the AMD-761 system controller supports configuration address space as defined by the pci local bus specification , revision 2.2, which defines a unique 256-byte space that is accessed through two 32-bit index registers mapped in i/o space. as defined in the pci specificat ion, configuration cycles are generated on the pci bus only when bit 31 of the configuration address register is set.
chapter 1 overview 3 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information function 1 space the configuration registers that control the memory interface?s programmable delay lines (pdls) and i/o drive strengths are mapped to device 0: function 1 in the host bridge. this configuration space is disabled by default and requires a write to the pci control register?s func1_en (dev 0:f0:0x4c, bit 0). the intent of this separate configuration space is that it is configured at initial power-on , subsequently disabled, and essentially protected from further writes. note that the AMD-761 system controller does not report as a multifunction device (bit 7 is not set in the header_type field in the pci latency timer and header type register in dev 0:f0:0x0c). reads to the pci header that normally occupies offsets 00h? 3fh return all 1s?that is, the normal pci header registers are not implemented. memory-mapped bars five dword registers are accessed by the AMD-761 system controller agp miniport driver as memory-mapped space. this space is defined by the base address 1: gart memory- mapped register base (dev 0:f0:0x14), which provides address bits [31:12] of the memory-mapped space. note that this space is defined as a 4-kbyte region, hence the lower address bits [11:4] are 0s. this register must be properly programmed by bios to allow the driver to access the memory-mapped space. memory holes legacy memory holes are decoded in the normal region of main memory from 640 kbyte to 1 mbyte. the AMD-761 system controller does not allow pci masters to access dram in this region unless the ev6_mode bit is set in the pci arbitration control register. see ?bit defi nitions pci arbitration control (dev0:f0:0x84)? on page 71. agp override bits for 4x rate and fast writes the agp status register (dev 0:f0:0xa4) reports the AMD-761 system controller?s capability to support agp fast writes and the agp-4x rate. the operating system normally reads these bits along with the same bits in the agp card?s status register, and uses this information to configure the agp command register (dev 0:f0:0xa8) in the AMD-761 system controller and the agp card.
4 overview chapter 1 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information the AMD-761 system controller provides bios the ability to override the reporting of fast write and 4x rate support. this override function is accomplishe d through a write to a separate register, which is required because the agp status register is specified as read-only in the agp specification. refer to section 6.2 on page 208 for details of this implementation. interrupt pin control r/w attributes the int_pin field in the agp/pci interrupt and bridge control register (dev 1:f0:0x3c) is read -only by default and initializes to all 0s. if the bios is requir ed to initialize this field to another value, it must first change this field to r/w by setting the int_pin_cntl bit in the mi scellaneous device 1 control register (dev 1:f0:0x40). the AMD-761 system controller does not use the int_pin field internally, the register is provided for software compatibility only. silicon revisions the reader is advised to read the AMD-761? system controller revision guide , order# 23613, for the most current information for the version of silicon being used. the silicon revision is available by reading the pci revision id and class code register in dev 0:f0:0x08. 1.1.3 power-on reset initialization all of the AMD-761 system controller?s configuration registers must be initialized by bios after initial power-on, paying especially close attention to the registers that are not initialized to a known value. the AMD-761 system controller is reset when the southbridge?s pcirst# pin is asserted, which occurs when transitioning from the mechanical off, s5, s4, or s3 sleep states. to accommodate support of the advanced configuration and power interface (acpi) s3 (suspend to ram) power management state, the registers listed in table 1 on page 5 are not initialized to a known state after reset (reset# asserted), and they must be initialized by bios after initial power-on for proper operation. these registers retain the value programmed by bios after subsequent asse rtions of the reset# pin when transitioning to and from the s3 sleep state.
chapter 1 overview 5 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information table 1. AMD-761? system controller conf iguration register bits unknown at reset# register name offset bit name bit(s) ecc mode/status dev 0:f0:0x48 serr_enable [15:14] ecc_diag [12] ecc_mode [11:10] dram timing dev 0:f0:0x54 sbpwaitstate [31] addr_timing_a [30] addr_timing_a [29] rd_wait_state [28] reg_dimm_en [27] t wtr [26] t wr [25:24] t rrd [23] idle_cyc_limit [18:16] ph_limit [15:14] t rc [11:9] t rp [8:7] t ras [6:4] t cl [3:2] t rcd [1:0] dram mode/status dev 0:f0:0x58 burst_ref_en [20] ref_dis [19] reserved [18] cyc_per_ref [17:16] cs7_x4mode [7] cs6_x4mode [6] cs5_x4mode [5] cs4_x4mode [4] cs3_x4mode [3] cs2_x4mode [2] cs1_x4mode [1] cs0_x4mode [0] status/control dev 0:f0:0x70 self_ref_en [18] memory base address 0?7 dev 0:f0:0xc0 through dev 0:f0:0xdc cs_base [31:23] cs_mask [15:7] addr_mode [2:1] cs_en [0]
6 overview chapter 1 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr pdl calibration control dev 0:f1:0x40 sw_recal [7] use_act_dly [6] auto_cal_en [5] act_dly_inh [4] auto_cal_period [1:0] ddr pdl configuration 0?17 dev 0:f1:0x44 through dev 0:f1:0x88 clk_dly [31:24] sw_cal_dly [23:16] cal_dly [15:8] act_dly [7:0] ddr dqs/mdat pad configuration dev 0:f1:0x8c pslewmdat [29:27] nslewmdat [26:24] pdrvmdat [19:18] ndrvmdat [17:16] pslewdqs [13:11] nslewdqs [10:8] pdrvdqs [3:2] ndrvdqs [1:0] ddr clk/cs pad configuration dev 0:f1:0x90 pslewclk [29:27] nslewclk [26:24] pdrvclk [19:18] ndrvclk [17:16] pslewcs [13:11] nslewcs [10:8] pdrvcs [3:2] ndrvcs [1:0] ddr cmdb/cmda pad configuration dev 0:f1:0x94 pslewcmdb [29:27] nslewcmdb [26:24] pdrvcmdb [19:18] ndrvcmdb [17:16] pslewcmda [13:11] nslewcmda [10:8] pdrvcmda [3:2] ndrvcmda [1:0] table 1. AMD-761? system contr oller c onfiguration register bits unknown at reset# (continued) register name offset bit name bit(s)
chapter 1 overview 7 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information refer to section 7 on page 211 fo r suggested values for these configuration registers. 1.1.4 programming reserved bits the AMD-761 system controller has many bits that are specified as reserved and which may be used in future silicon revisions. bios must always wr ite a 0 to these bits and not depend on the value read back. 1.1.5 power management considerations there are several requirements for bios initialization of the AMD-761 system controller?s configuration register when supporting power management. re fer to section 4 on page 185 for further details of these requirements. for any system enabling the s3 state, a number of core logic pci configuration registers and processor msrs must be saved or restored prior to suspending or restoring s3. also, certain hidden bits must be unmasked. these requirements apply to all platforms regardless of segment and whether or not amd powernow!? is used. ddr mab/maa pad configuration dev 0:f1:0x98 pslewmab [29:27] nslewmab [26:24] pdrvmab [19:18] ndrvmab [17:16] pslewmaa [13:11] nslewmaa [10:8] pdrvmaa [3:2] ndrvmaa [1:0] table 1. AMD-761? system contr oller c onfiguration register bits unknown at reset# (continued) register name offset bit name bit(s)
8 overview chapter 1 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 1.2 recommended amd athlon? processor sys_config settings table 2 provides recommendations for settings in the amd athlon processor system configuration register in systems that utilize the AMD-761 system controller. table 2. recommended settings for amd athlon? processor syscfg register bit field name bios setting comments [22] evicten 0 an evict command, when set, is sent as part of an invd instruction. the evict command has no function in the AMD-761? system controller. [17] sysuclocken 0 a locktoggle command, when set, is sent as part of a lock instruction prefix and certain other instructions. locktoggle has no function in the AMD-761 system controller. [16] chxtodirtydis 0 the amd athlon? processor and the AMD-761 system controller support change-to-dirty commands. [13] sysfillvalisd1 0 [11] clvicblken 0 clvicblken, when set, causes all evicted clean blocks to cause the cleanvictimblk system interface command. this setting has no function with the AMD-761 system controller. [10:8] setdirtyene 0 there are three set-to-dirty enables: set- dirtyene, setdirtyeno, and setdirtyens. if a given enable is set and a cache block must make a transition from e-to-m, o-to- m, or s-to-m, then the amd athlon proces- sor performs the action indicated by the setting of the chxtodirtydis field. how- ever, if a given enable is cleared, the pro- cessor takes no externally visible action when the desired transition is performed. change to dirty commands are not needed by the AMD-761 system controller. setdirtyeno 0 setdirtyens 0
chapter 2 AMD-761? system controller programmer?s interface 9 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 2 AMD-761? system controller programmer?s interface 2.1 overview the amd-760? chipset suppo rts both x86 and alpha? processors that conform to th e socket2000 bus specification. both processors share a compatible view of system memory and peripherals. legacy x86 (ibm pc-at) memory mappings are implemented by x86 processors (amd athlon? processor) as shown in figure 1. figure 1. amd athlon? processor family address mapping x86 processor mapping logic pc memory view northbridge southbridge socket2000 pci alpha processor conventional view northbridge southbridge socket2000 pci memory same view of the system processor family processor family AMD-761? system controller AMD-761 system controller amd-766? peripheral bus controller amd-766 peripheral bus controller amd athlon? amd athlon
10 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.2 address map table 3 shows the address map implemented by the AMD-761? system controller. table 3. AMD-761? system controller socket2000 memory map address space start address space end name/command description sysaddout msb =0 & 1 ff000 0000 sysaddout msb =0 & 3 ffff ffff reserved (masked) may be used by the northbridge for other purposes (used for ev6 northbridges). sysaddout msb =0 & 1 fe00 0000 sysaddout msb =0 & 1 feff ffff pci configuration space (masked) this space is used to creat e pci configuration cycles using wrbytes, wrlws, rdbytes, and rdlws commands only. see section 2.2.3 on page 15. sysaddout msb =0 & 1 fc00 0000 sysaddout msb =0 & 1 fdff ffff pci i/o space (masked) this space is used to create pci i/o cycles using only wrbyteswrlws, rdbytes and rdlws commands. sysaddout msb =0 & 1 f800 0000 sysaddout msb =0 & 1 fbff ffff pci iack/special cycle generation (masked) wrlws commands to this space are used to create pci special cycles. the lower 16 bits of the data is passed on to the pci bus as both the address and data with the special cycle pci command. see section 2.2.1 on page 12 for all special cycles generated by the amd athlon? processor. rdbytes commands to this space are used to create pci iack. the lower 16 bits of these addresses are passed on unmodified to the pci with the iack pci command. see section 2.2.2 on page 15. sysaddout msb =0 & 1 0000 0000 sysaddout msb =0 & 1 f7ff ffff reserved (masked) may be used by the northbridge for other purposes (used for ev6 northbridges). sysaddout msb =0 & 0 0000 0000 sysaddout msb =0 & 0 ffff ffff pci memory space (masked) the lower 32 bits of these addresses are forwarded unmodified to the pci. accessed only with wr/rdbytes, wr/rdlws, wr/rdqws. the AMD-761? system controller generates low-order address bit as required from the amd athlon processor system bus mask field. sysaddout msb =1 & 0 0000 0000 sysaddout msb =1 & 3 ffff ffff normal memory (masked writes) dram, accessed only with masked write commands wrbytes, wrlws, wrqws. sysaddout msb =1 & 0 0000 0000 sysaddout msb =1 & 3 ffff ffff reserved (masked reads) the AMD-761 system controller does not support masked reads to this address space. sysaddout msb =1 & 0 ff000 0000 sysaddout msb =1 & 3 ffff ffff reserved (blocks) may be used by the northbridge for other purposes (used for ev6 northbridges). sysaddout msb =0 & 0 0000 0000 sysaddout msb = 0 & 3 ffff ffff normal memory (blocks) dram, accessed with read and write block commands. note that the AMD-761 system controller only uses 32 address bits internally and the address space wraps. address 1 0000 0000 is treated the same as 0 0000 0000.
chapter 2 AMD-761? system controller programmer?s interface 11 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information for reference, the x86 view of memory from the perspective of the amd athlon processor and the mapping to the socket2000 memory map is shown in figure 2. figure 2. amd athlon? processor family x86 processor address mapping x86 memory address space agp virtual pci memory socket2000 address space pci memory pci iack/special pci i/o pci config gart dram i/o space x86 in and out address space vga bios dos memory extended memory reserved reserved note : not to scale. reserved tom cf8, cfc (bar0) apic registers 640?1-mbyte addresses are sent to pci or dram as a function of amd athlon tm processor msrs.
12 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.2.1 special cycles special cycles generated by the amd athlon processor are forwarded down to the pci bus with specific values in the address and data fields of the pci special cycle command. table 4 defines these values. the amd athlon processor generates amd athlon processor system bus wrlws commands to a single address (1 f8000 0000) with the data field specifying the desired special cycle. the AMD-761 system controller maps the amd athlon processor system bus data value onto the pci for both address and data phases of the special cycle transaction. . table 4. amd athlon? processor special cycle encodings special cycle pci address and data field contents processor description northbridge and southbridge description shutdown 0000 0000 the amd athlon? processor gener- ates in response to a shutdown condi- tion. amd athlon processor system bus wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0000 0000 the AMD-761? system controller forwards onto the pci bus the pci special cycle command: ad[31:0] = 0000 0000 (address and data). amd-766? peripheral bus controllers asserts init to processor. halt 0000 0001 the amd athlon processor generates in response to executing a halt instruction: wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0000 0001 the AMD-761 system controller waits for all queues to memory to be empty (assumes the pci grant enable register is clear, ?dev0:f0:0x84? on page 70). AMD-761 system controller optionally (via ?dev0:f0:0x60? on page 61) initiates an amd athlon system bus disconnect to this specific cpu. the AMD-761 system controller forwards onto the pci bus (after the optional amd athlon system bus disconnect). pci special cycle command: ad[31:0] = 0000 0001 (address and data) amd-766 peripheral bus controllers ignores. wb invalidate 0001 0002 the amd athlon processor generates in response to executing a wbinv instruction wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0001 0002 the AMD-761 system controller forwards onto the pci bus, pci special cycle command: ad[31:0] = 0001 0002 (address and data). amd-766 peripheral bus controllers ignores.
chapter 2 AMD-761? system controller programmer?s interface 13 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information invalidate 0002 0002 the amd athlon? processor gener- ates in response to executing an invd instruction wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0002 0002 the AMD-761? system controller forwards onto the pci bus the pci special cycle command: ad[31:0] = 0002 0002 (address and data). amd-766? peripheral bus controllers ignores. flushack 0003 0002 the amd athlon processor generates in response to assertion of the flush pin after all caches have been flushed to memory. wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0003 0002 the AMD-761 system controller forwards onto the pci bus, pci special cycle command: ad[31:0] = 0003 0002 (address and data). amd-766 peripheral bus controllers ignores. connect 0004 0002 the amd athlon processor generates connect as the first cycle after stop/grant or halt amd athlon system bus special cycle regardless of whether or not a disconnect is achieved (or even attempted). wrlws command: sysaddout: msb= 0 & [33: 0] = 1 f8000 0000 sysdatout: [31: 0] = 0004 0002 the AMD-761 system controller forwards onto the pci bus, pci special cycle command: ad[31: 0] = 0004 0002 (address and data) amd-766 peripheral bus controllers ignores. smm ack (enter) 0005 0002 the amd athlon processor generates an smm ack (enter) when entering a system management interrupt. wrlws command: sysaddout: msb= 0 & [33: 0] = 1 f8000 0000 sysdatout: [31: 0] = 0005 0002 the AMD-761 system controller forward onto the pci bus, special cycle command: ad[31: 0] = 0005 0002. smm ack (exit) 0006 0002 the amd athlon processor generates smm ack (exit) when exiting from a system management interrupt. wrlws command: sysaddout: msb= 0 & [33: 0] = 1 f8000 0000 sysdatout: [31: 0] = 0006 0002 the AMD-761 system controller forwards to the pci bus. command: ad[31: 0] = 0006 0002. table 4. amd athlon? processor special cycle encodings (continued) special cycle pci address and data field contents processor description northbridge and southbridge description
14 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information stop/grant 0012 0002 amd athlon? processor generates in response to assertion of the stpclk. wrlws command: sysaddout: msb=0 & [33:0] = 1 f8000 0000 sysdatout: [31:0] = 0012 0002 the AMD-761? system controller waits for all queues to memory to be empty (assumes the pci grant enable register is clear, ?dev0:f0:0x84? on page 70). the AMD-761 system controller system controller optionally (via ?dev0:f0:0x60? on page 61) initiates an amd athlon processor system bus disconnect to this specific processor. the AMD-761 system controller forwards onto the pci bus (after the optional system bus disconnect) pci special cycle command: ad[31:0] = 0012 0002 (address and data). the amd-766? peripheral bus controllers receives and enters the appropriate power state. the amd-766 peripheral bus controllers may then assert dcstop# to the northbridge to signal that it should deassert cke to ddr sdrams and stop its internal clocks. table 4. amd athlon? processor special cycle encodings (continued) special cycle pci address and data field contents processor description northbridge and southbridge description
chapter 2 AMD-761? system controller programmer?s interface 15 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 2.2.2 iack in x86 compatible socket2000 systems, apic is used as the interrupt controller. to fetch the appropriate vector during iack cycles, x86 processors are required to assert their apic id (cpu id) on bits [15:12] of the address field when reading the iack generation space. iack return data flushes all pci and agp/pci write buffers to memory. 2.2.3 pci configuration accesses in legacy x86 pc systems, pci configuration cycles are generated via an indirect me thod. a configuration address register is defined at i/o address 0cf8 that allows software to load a value that is asserted on the pci address wires during the next configuration read/write cycle. a configuration data register is defined at i/o address 0cfc that allows software to generate configuration read and write cycles on the pci using in and out instructions. data sent during out instructions to the configuration data register is asserted on the pci data wires during the generated configuration write transaction. data received in response to a generated configuration read transaction is returned to satisfy the in from the configuration data register. in socket2000 systems, pci configuration cycles are generated in one of two ways: in ev6 compatible mode, the x86 processor must detect in and out instructions that reference 0cf8 and 0cfc and generate the appropriate, explicit rdbytes/rd/lws and wrbytes/wrlws socket2000 commands to a 16-mbyte region as follows: when an out instruction is detected to 0cf8, the write data is saved into a register and the instruction retired. when an in/out instruction is detected to 0cfc, an appropriate amd athlon system bus rd/wr transaction is launched with the sysadd fi eld[23:0] taken from the register that saved the most recent write to 0cf8 (above). in traditional mode, which the AMD-761 system controller implements, in and out instructions that reference 0cf8 and 0cfc are passed normally on to the amd athlon processor system bus where the northbridge generates the appropriate pci configuration access.
16 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.3 address decoding a consistent view of memory and pci devices is enforced by decoding logic in the AMD-761 system controller in the amd athlon processor system bus and pci interfaces. 2.3.1 socket2000 address decoding the AMD-761 system controller must consider both the amd athlon processor system bus sysaddout field and the command field when deciding what to do with a given command. this amd athlon processor system bus decoding is summarized as follows: sysaddout msb = 0 and command is a block command, dram is accessed: if sysaddout [31:0] falls between dev0:bar0 and dev0:bar0+len, address is to agp virtual address space and needs to passed through the gart before presentation to dram. sysaddout msb = 1 and co mmand is a masked write command (wrqws, wrlws, wrbytes), dram is accessed: if sysaddout [31:0] falls between dev0:bar0 and dev0:bar0+len, address is to agp virtual address space and needs to passed through the gart before presentation to dram. sysaddout msb = 0 and sysaddout [35:32] = 0 and command is a masked command, pci memory-mapped i/o is accessed: using dev0:f0:0x14, bar1, send to the AMD-761 system controller memory-mapped ga rt control registers (see section 2.5 on page 138). memory range address decodi ng, send to either pci or agp/pci using address bits [31:0] based on the following: dev1:0x20, 0x24 (see ?agp/pci memory limit and base (dev1:0x20)? on page 131 and ?agp/pci prefetchable memory limit and base (dev1:0x24)? on page 133). dev 0:f0:0x84 agp vga bios bits, see ?bit definitions pci arbitration control (dev0:f0:0x84)? on page 71).
chapter 2 AMD-761? system controller programmer?s interface 17 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information sysaddout msb = 0 and sysaddout [35:24] = 1f8 and command is rdbytes, an iack special cycle is generated on the primary pci. sysaddout[15:0] are asserted on pci ad[15:0] during this cycle. th e data returned on the pci is returned to the processor. sysaddout msb = 0 and sysaddout [35:24] = 1f8 and command is wrbytes, a pci special cycle is generated on the primary pci. sysaddout[15:0] are asserted on pci ad[15:0] during this cycle (address = data). sysaddout msb = 0 and sysaddout [35:24] = 1fc/1fd and command is rdbytes or wrbytes, a pci i/o command is generated. sysaddout[23:0] are asserted on pci ad[23:0] with the pci i/o read or write command. using dev1:0x1c, i/o rang e address decoding, send to either pci or agp/pci. note: low-order amd athlon processor system bus address bits, per the amd athlon processor system bus specification, sysaddout only goes down to pa[3]. for mask operations, the mask[7:0] bits are encoded to logically create pa[2:0] in the above. 2.3.2 pci/agp master address decoding the pci controllers in the AMD-761 system controller must consider the received pci/agp address in conjunction with the bar registers and the memory co nfiguration registers to route the transaction. the AMD-761 system controller does not allow pci masters to access i/o regions or main memory from 640 kbyte to 1 mbyte (unless the ev6_mode bit is set as described in ?bit definiti ons pci arbitration control (dev0:f0:0x84)? on page 71). this decoding is summarized as follows: 1. ad[31:0] is less than the physical top of memory (from the memory controller), dram is accessed. 2. ad[31:0] is above the physical top of memory and it falls between dev0:bar0 and dev0 :bar0+len, address is to agp virtual address space and needs to be passed through the gart before presentation to dram.
18 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 3. memory range address deco ding, send to agp/pci using address bits [31:0] based on the following (for writes only from the primary pci): dev1:0x20, 0x24 (see ?agp/pci memory limit and base (dev1:0x20)? on page 131 and ?agp/pci prefetchable memory limit and base (dev1:0x24)? on page 133). dev 0:f0:0x84 agp vga bios bits (see ?bit definitions pci arbitration control (dev0:f0:0x84)? on page 71). 4. else, the primary pci is accessed (for writes only from the agp/pci). note: gart control register ac cess. the AMD-761 system controller does not allow access to the memory-mapped gart control registers from either pci or agp/pci masters. 2.4 configuration registers all functional registers in the AMD-761 system controller are implemented as pci configuration registers. the AMD-761 system controller implements a standard pci hierarchy that allows bios software to enumerate devices on the primary pci, the agp port, and future interfaces. see the logical bus hierarchy in figure 3 on page 19. note that the AMD-761 system controller only responds to function 0 and 1, device 0 and function 0, device 1. all other configuration accesses return fs. function 1, device 0 accesses are ignored unless enabled by the appropriate bit in the pci control register (see ?dev0:f0:0x4c? on page 47).
chapter 2 AMD-761? system controller programmer?s interface 19 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information figure 3. AMD-761? system controller logical bus hierarchy processor host to pci bridge pci-to-pci bridge pci devices agp master agp pci processor device 0:f0/f1 pci-to-pci bridge device 1:f0 device 1:f1 southbridge 2 processor system only (future interface)
20 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.4.1 i/o register map the AMD-761 system controller implements some i/o registers (accessed by processor i/o instructions). these registers, as presented in table 5, are th e configuration address and configuration data registers as specified in pci local bus specification , revision 2.2. table 5. i/o register map register amd athlon? processor system bus address reference configuration address sysaddout msb =0 & 1 fc000 0cf8 ?i/o:0cf8? on page 21 and ?i/o:0cf8? on page 23 configuration data sysaddout msb =0 & 1 fc000 0cfc ?i/o:0cfc? on page 25
chapter 2 AMD-761? system controller programmer?s interface 21 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information configuration address register type 0 i/o:0cf8 register description when writes to the configuration address register have [23: 16] == 0h00, a type 0 configuration access is specified. 31 30 29 28 27 26 25 24 bit config_en reserved reset00000000 r/w r/w r 23 22 21 20 19 18 17 16 bit pci_bus_num reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit dev_num func_num reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit reg_num reserved reset00000000 r/w r/w r
22 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions configuration address register type 0 (i/o:0cf8) bit name function 31 config_en configuration enable 0 = pci configuration cycles are not generated. 1 = accesses to the configuration data and address registers are converted to configuration cycles on the pci. 30?24 reserved reserved 23?16 pci_bus_num pci bus number this bit field defines which pci bus in the sy stem is referenced with this address. the AMD-761? system controller logically impl ements two pci buses. the main pci bus normally enumerates as bus 0 and the agp bus enumerates as bus 1. 15?11 dev_num device number this bit field defines which device is accessed in the system. devices are assigned numbers in a system by tying the device idsel wire to a specific pci ad wire. the AMD-761 system controller decodes this field and asserts the appropriate ad wire during the address phase to select the defined device. in the AMD-761 system controller there are two ?hard-wired? device numbers for the host to pci bridge (0b00000) and p2p bridge (0b00001). 10?8 func_num function number this bit field defines which function is accessed in a given device. the AMD-761 system controller responds to function 0 only (0b000) by default. function 1 (ddr pdl registers) can be enabled via writing to the pci control register (dev 0:f0:0x4c) as described on page 47. 7?2 reg_num register number this bit field defines which specific pci regi ster is accessed in the device and function specified above. the register numbers for th e AMD-761 system controller device 0 are listed in table 6, ?device 0, function 0 configuration register map,? on page 27. the register numbers for the AMD-761 device 1 are listed in table 15, ?device 1 configuration register map,? on page 117. 1?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 23 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information configuration address register type 1 i/o:0cf8 register description when writes to the configuration address register have [23: 16] ~= 0h00, a type 1 configuration access is specified. 31 30 29 28 27 26 25 24 bit config_en reserved reset00000000 r/w r/w r 23 22 21 20 19 18 17 16 bit pci_bus_num reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit dev_num func_num reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit reg_num reserved reset00000000 r/w r/w r
24 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions configuration address register type 1 (i/o:0cf8) bit name function 31 config_en configuration enable 0 = pci configuration cycles are not generated. 1 = accesses to the configuration data and address registers are converted to configuration cycles on the pci. 30?24 reserved reserved 23?16 pci_bus_num pci bus number this bit field defines which pci bus in the sy stem is referenced with this address. the AMD-761? system controller logically impl ements two pci buses. the main pci bus normally enumerates as bus 0 and the agp bus enumerates as bus 1. 15?11 dev_num device number this bit field defines which device is accessed in the system on the target pci bus. this field is passed on directly to the ad wires undecoded. 10?8 func_num function number this bit field defines which function is accessed in a given device. this field is passed on directly to the ad wires undecoded. 7?2 reg_num register number this bit field defines which specific pci regi ster is accessed in the device and function specified above. 1?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 25 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information configuration data i/o:0cfc register description programming notes 31 30 29 28 27 26 25 24 bit config_data resetxxxxxxxx r/w r/w 23 22 21 20 19 18 17 16 bit config_data resetxxxxxxxx r/w r/w 15 14 13 12 11 10 9 8 bit config_data resetxxxxxxxx r/w r/w 7 6 5 4 3 2 1 0 bit config_data resetxxxxxxxx r/w r/w bit definitions configuration data (i/o:0cfc) bit name function 31?0 config_data configuration data this bit field is used to access the pci configuration register specified in the configuration address register above.
26 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.4.2 configuration register access the AMD-761 system controller implements most registers as pci configuration registers. the x86 software executes in and out instructions to i/o addresses of 0cf8 and 0cfc to access all configuration registers. these are translated by the amd athlon? processor into amd athlon processor system bus rdbytes and wrbytes commands wi th the lower 24 bits of the address field containing the logi cal contents of the configaddr register (i/o address 0cf8). the fo rmat of this register is shown in ?i/o:0cf8? on page 21 and ?i/o:0cf8? on page 23. configuration accesses in th e AMD-761 system controller conform to the following rules: the AMD-761 system controller is defined to be function 0 and 1, device 0; and function 0, device 1. the idsel pin of all external pci devices must be wired to 1 of ad[31:13] as logically [12:11] are assigned to device 0, 1 (AMD-761 system controller). function 1, device 0 configur ation space contains only the ddr programmable delay line (pdl) registers. this space is enabled only when the appropriate bit is set in the pci control register (see ?dev0:f0:0x4c? on page 47). accesses to the normal reserved pci space of function 1 yields all 1s. accesses to function 1 are ignored when function 1 is not enabled. device 0 accesses correspond to the host to pci bridge registers defined in section 2.4.3 on page 27. device 1 accesses correspond to the pci-to-pci bridge registers defined in section 2.4.5 on page 117. access can be byte, word or dword in length and must be naturally aligned. northbridges are required to crea te type 0 and type 1 accesses as follows: if sysadd[23:16] = 0 (bus# = 2' h00), a type 0 config cycle is generated and pci ad[1:0] = 2' b00. device#, sysadd[15:11] is decoded and asserted on pci ad[31:11] for idsel. if sysadd[23:16] != 0 (bus# != 2'h00), a type 1 config cycle is generated and pci ad[1:0] = 2' b01. bus# and device# fields are passed onto the pci directly with no decoding. pci ad[31:24] = 2'h00.
chapter 2 AMD-761? system controller programmer?s interface 27 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 2.4.3 device 0: pci configuration registers in table 6, the column entitled offset consists of the register number specified in the config uration address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. reserved configuration registers return 0 when read. table 6. device 0, function 0 configuration register map host to pci bridge (device 0, function 0) offset reference device id vendor id 0x00?0x03 ?dev0:f0:0x00? on page 30 status command 0x04?0x07 ?dev0:f0:0x04? on page 32 class code = 0x060000 revision id 0x08?0x0b ?dev0:f0:0x08? on page 35 reserved header type latency timer reserved 0x0c?0x0f ?dev0:f0:0x0c? on page 36 bar0 - agp virtual address space 0x10?0x13 ?dev0:f0:0x10? on page 37 bar1 - gart memory-mapped control registers pointer 0x14?0x17 ?dev0:f0:0x14? on page 39 reserved 0x18?0x1b reserved 0x1c?0x33 reserved capabilities pointer: a0 0x34?0x37 ?dev0:f0:0x34? on page 41 reserved 0x38?0x43 extended biu control 0x44?0x53 ?dev0:f0:0x44? on page 42 ecc mode/status 0x48?0x4b ?dev0:f0:0x48? on page 44 pci control 0x4c?0x4f ?dev0:f0:0x4c? on page 47 amd athlon? processor system bus dynamic compensation 0x50?0x53 ?dev0:f0:0x50? on page 49 dram timing 0x54?0x57 ?dev0:f0:0x54? on page 51 dram mode/status 0x58?0x5b ?dev0:f0:0x58? on page 56 reserved 0x5c?0x5f biu0 status/control 0x60?0x63 ?dev0:f0:0x60? on page 61 biu0 sip 0x64?0x67 ?dev0:f0:0x64? on page 64
28 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information reserved 0x68?0x6b reserved 0x6c?0x6f memory status/control 0x70?0x73 ?dev0:f0:0x70? on page 66 reserved 0x74?0x77 reserved 0x78?0x7b reserved 0x7c?0x7f reserved boot proc whami 0x80?0x83 ?dev0:f0:0x80? on page 68 pci arbitration control 0x84?0x87 ?dev0:f0:0x84? on page 70 configuration status 0x88?0x8b ?dev0:f0:0x88? on page 74 reserved 0x8c?0x8f reserved 0x90?0x93 reserved 0x94?0x97 reserved 0x98?0x9b pci top of memory reserved 0x9c?0x9f ?dev0:f0:0x9c? on page 77 agp capability identifier 0xa0?0xa3 ?dev0:f0:0xa0? on page 79 agp status 0xa4?0xa7 ?dev0:f0:0xa4? on page 80 agp command 0xa8?0xab ?dev0:f0:0xa8? on page 82 agp virtual address space size 0xac?0xaf ?dev0:f0:0xac? on page 84 gart/agp mode control 0xb0?0xb3 ?dev0:f0:0xb0? on page 86 agp 4x dynamic compensation 0xb4?0xb7 ?dev0:f0:0xb4? on page 88 agp compensation bypass 0xb8?0xbf ?dev0:f0:0xb8? on page 91 memory base address 0 0xc0?0xc3 ?dev0:f0:0xc0? on page 95 memory base address 1 0xc4?0xc7 ?dev0:f0:0xc4? on page 95 table 6. device 0, function 0 configuration register map (continued) host to pci bridge (device 0, function 0) offset reference
chapter 2 AMD-761? system controller programmer?s interface 29 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information memory base address 2 0xc8?0xcb ?dev0:f0:0xc8? on page 95 memory base address 3 0xcc?0xcf ?dev0:f0:0xcc? on page 95 memory base address 4 0xd0?0xd3 ?dev0:f0:0xd0? on page 95 memory base address 5 0xd4?0xd7 ?dev0:f0:0xd4? on page 95 memory base address 6 0xd8?0xdb ?dev0:f0:0xd8? on page 95 memory base address 7 0xdc?0xdf ?dev0:f0:0xdc? on page 95 reserved 0xe0?0xff table 6. device 0, function 0 configuration register map (continued) host to pci bridge (device 0, function 0) offset reference
30 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information pci id dev0:f0:0x00 register description 31 30 29 28 27 26 25 24 bit dev_id reset01110000 r/w r 23 22 21 20 19 18 17 16 bit dev_id reset00001110 r/w r 15 14 13 12 11 10 9 8 bit vend_id reset00010000 r/w r 7 6 5 4 3 2 1 0 bit vend_id reset00100010 r/w r
chapter 2 AMD-761? system controller programmer?s interface 31 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions pci id (dev0:f0:0x00) bit name function 31?16 dev_id device identifier this 16-bit field is assigned by the device manufacturer and identifies the type of device. the current northbridge device id assignments are: AMD-761? system controller ? amd athlon? processor, 1p ddr 133 mhz 0x700e host to pci bridge 0x700f pci-to-pci bridge (4-x agp) amd-762? system controller ? amd athlon processor, 2p ddr 133 mhz 0x700c host to pci bridge 0x700d pci-to-pci bridge (4-x agp) amd-751? system controller ? amd athlon processor, 1p sdram-100 0x7006 host to pci bridge 0x7007 pci-to-pci bridge (1x/2x agp) 15?0 vend_id vendor identifier this 16-bit field identifies the manufacturer of the device.
32 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information pci command and status dev0:f0:0x04 register description 31 30 29 28 27 26 25 24 bit perr_rcv serr_sent mas_abrt trgt_abrt trgt_abrt _ signaled devsel_timing data_perr reset00000010 r/w r r/w1c r/w1c r/w1c r r r 23 22 21 20 19 18 17 16 bit fast_b2b udf 66m cap_lst reserved reset00010000 r/w r 15 14 13 12 11 10 9 8 bit reserved fback serr reset00000000 r/w r r/w 7 6 5 4 3 2 1 0 bit step perr vga mwinv scyc mstr mem i/o reset00000100 r/w r r/w r
chapter 2 AMD-761? system controller programmer?s interface 33 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions pci command and status (dev0:f0:0x04) bit name function 31 perr_rcv detected parity error this bit is always 0 because the AMD-761? system controller does not support data parity checking. 30 serr_sent signaled system error this bit is set whenever the AMD-761 syst em controller generates a system error and asserts the serr# line (ecc, gart error). this bit is cleared by writing a 1. refer to table 7 on page 34 for details about serr# assertion and status. 29 mas_ abrt received master abort this bit is set whenever a cpu to pci transact ion (except for a special cycle) is terminated due to a master abort. this bit is cleared by writing a 1. 28 trgt_abrt received target abort this bit is set whenever a cpu to pci transact ion (except for a special cycle) is terminated due to a target abort. this bit is cleared by writing a 1. 27 trgt_abrt_ signaled signaled target abort this bit is always 0 because the AMD-761 system controller does not terminate transactions with target aborts. 26?25 devsel_timing devsel# timing this bit field defines the timing of devsel# on the AMD-761 system controller. the AMD-761 system controller supports medium devsel# timing. 24 data_perr data parity error this bit is always 0 because the AMD-761 system controller does not report parity errors. 23 fast b2b fast back-to-back capable this bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. 22 udf user-definable features this bit is always 0, indicating that udf is not supported on the AMD-761 system controller. 21 66m 66-mhz capable this bit is always 0, indicating that the AMD-761 system controller is not 66-mhz capable. 20 cap_lst capabilities list this bit is set to indicate that this device?s configuration space supports a capabilities list. 19?10 reserved reserved 9fback fast back-to-back to different devices enable this bit is always 0, because the AMD-761 system controller does not allow generation of fast back-to-back transactions to different agents. 8 serr system error enable 0 = serr# driver disabled 1 = serr# driver enabled refer to table 7 for details about serr# assertion and status.
34 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes table 7 lists the controls required to enable the assertion of the AMD-761 serr# pin and the various status bits that can be read to determine when the serr# and a_serr# pins have been asserted. 7 step address stepping this bit is always 0 because the AMD-761? system controller does not perform address stepping. 6perr parity error response this bit is always 0 because the AMD-761 system controller does not report data parity errors. 5vga vga palette snoop enable this bit is always 0, indicating that the AMD-761 system controller does not snoop the vga palette address range. 4mwinv memory write and invalidate enable this bit is always 0 because the AMD-761 system controller does not generate memory write and invalidate commands. 3scyc special cycle this bit is always 0 because the AMD-761 sy stem controller ignores pci special cycles. 2 mstr bus master enable this bit is always set, indicating that the AMD-761 system controller is allowed to act as a bus master on the pci bus. 1mem memory access enable 0 = pci memory accesses ignored 1 = pci memory accesses responded to 0i/o i/o access enable this bit is always 0 because the AMD-761 system controller does not respond to i/o cycles on the pci bus. table 7. AMD-761? system controller serr# assertion control and status bits serr# source serr# pin assertion control signalled system error status bit gart or ecc error enabled by bit 8, dev 0:f0:0x04, pci status/command register. read bit 30, dev 0:f0:0x04, pci status/command register. a_serr# assertion on agp interface forwarded to serr# pin enabled by bit 8, dev 1:f0:0x04, pci status/command register, and bit 17, dev 1:f0:0x3c, agp/pci interrupt and bridge control. read bit 30, dev 1:f0:0x1c, agp/pci status, i/o and base limit, and bit 30, dev 1:f0:0x04, agp/pci command/status. bit definitions (continued) pci command and status (dev0:f0:0x04) bit name function
chapter 2 AMD-761? system controller programmer?s interface 35 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information pci revision id and class code dev0:f0:0x08 register description programming notes refer to the AMD-761? system controller revision guide , order# 23613, for details of the rev_id field for each silicon revision. 31 30 29 28 27 26 25 24 bit class_code reset00000110 r/w r 23 22 21 20 19 18 17 16 bit sub-class_code reset00000000 r/w r 15 14 13 12 11 10 9 8 bit prog_i/f reset00000000 r/w r 7 6 5 4 3 2 1 0 bit rev_id (see programming notes below.) reset00010000 r/w r bit definitions pci revision id and class code (dev0:f0:0x08) bit name function 31?24 class_code class code indicates a bridge device. 23?16 sub- class_code sub-class code indicates a host/pci bridge. 15?8 prog_i/f program interface indicates a host/pci bridge. 7?0 rev_id revision identification identifies revision number of the device.
36 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information pci latency timer and header type dev0:f0:0x0c register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit header_type reset00000000 r/w r 15 14 13 12 11 10 9 8 bit lat_timer reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit reserved reset00000000 r/w r bit definitions pci latency timer and header type (dev0:f0:0x0c) bit name function 31?24 reserved reserved 23?16 header_type header type bit 23 is always 0, indicating that the AMD-761? system controller is a single function device. bits [22:16] are 0, indicating that type 00 configuration space header format is supported. 15?8 lat_timer latency timer this bit field defines the mini mum amount of time in pci clock cycles that the bus master can retain ownership of the bus. this action is mandatory for masters that are capable of performing a burst consisting of more than two data phases. 7?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 37 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information base address 0: agp virtual address space dev0:f0:0x10 register description this register is used by system bios memory mappin g software to allocate virtual address space for agp. 31 30 29 28 27 26 25 24 bit base_addr_high base- addr_low reset00000000 r/w r/w r 23 22 21 20 19 18 17 16 bit base_addr_low reset00000000 r/w r 15 14 13 12 11 10 9 8 bit base_addr_low reset00000000 r/w r 7 6 5 4 3 2 1 0 bit base_addr_low prefetchable type memory reset00001000 r/w r
38 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions base address 0: agp virtual address space (dev0:f0:0x10) bit name function 31?25 base_addr_high base address high this bit field forms the upper part of bar0. this field is loaded by bios software. note that when the gart enable bit in the agp virt ual address space size register is 0 (see ?dev0:f0:0xac? on page 84), these bits always return 0s to indicate no address space should be allocated to agp. note that a write to this register must occur before a read returns 0s with the gart enable bit cleared. this bit field corresponds to bits [3:1] of th e agp virtual address space size register. when bits [3:1] of that register are set, the r/w a ttributes in bits [30:25] in this register are automatically set. bios software writes all 1s to this bar register and then reads back the register to determine how much memo ry is required for agp as follows: 24?4 base_addr_low base address low this bit field is hardwired to return 0s to indicate that the minimum allocated memory size is 32 mbytes. 3 prefetchable prefetchable this bit is hardwired to 1 to indicate that this range is prefetchable. 2?1 type type this bit field is hardwired to indicate that th is base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. 0memory memory this bit is hardwired to 0 to indicate that this base address register maps into memory space. 31 30 29 28 27 26 25 memory rw rw rw rw rw rw rw 32 mbytes rw rw rw rw rw rw r 64 mbytes rw rw rw rw rw r r 128 mbytes rw rw rw rw r r r 256 mbytes rw rw rw r r r r 512 mbytes rwrwrrrrr1 gbyte rwrrrrrr2 gbytes
chapter 2 AMD-761? system controller programmer?s interface 39 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information base address 1: gart memory-mapped register base dev0:f0:0x14 register description this register provides the base address for the gart memory-mapped configuration register space (see ?memory- mapped register map? on page 140 for details). 31 30 29 28 27 26 25 24 bit base_addr_high reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit base_addr_high reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit base_addr_high base_addr_low reset00000000 r/w r/w r 7 6 5 4 3 2 1 0 bit base_addr_low prefetchable type memory reset00001000 r/w r
40 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions base address 1: gart memory-mapped register base (dev0:f0:0x14) bit name function 31?12 base_addr_high base address high this bit field forms the upper part of bar1. this field is loaded by bios software. 11?4 base_addr_low base address low this bit field is hardwired to return 0s to indicate that 4 kbytes are allocated to gart memory-mapped control registers and that the registers always reside in a 4-kbyte boundary per pci local bus specification , revision 2.2. 3 prefetchable prefetchable this bit is hardwired to 1 to indicate that this range is prefetchable 2?1 type type this bit field is hardwired to indicate that th is base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. 0memory memory this bit is hardwired to 0 to indicate that this base address register maps into memory space.
chapter 2 AMD-761? system controller programmer?s interface 41 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp/pci capabilities pointer dev0:f0:0x34 register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit cap_ptr reset10100000 r/w r bit definitions agp/pci capabilities pointer (dev0:0x34) bit name function 31?8 reserved reserved 7?0 cap_ptr capabilities pointer this field contains a byte offset into a device ?s configuration space containing the first item in the capabilities list. the first item in the capabilities list is the agp function. note that when the agp valid bit in the pci- to-pci bridge virtual ad dress space register is set to invalid, this capabilities pointer is set by the chipset to point to the next item in the linked list. if no next item exists, then it is set to null.
42 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information extended biu control dev0:f0:0x44 register description this register provides controls for the processor interface, in addition to the biu control register at dev 0:f0:0x60 for processor 0. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reserved p0_wrdatadly reset 0 0 0 sip stream r/w r 7 6 5 4 3 2 1 0 bit reserved reserved reserved reserved p0_2bitpf reset00000000 r/w r r r r/w r
chapter 2 AMD-761? system controller programmer?s interface 43 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions extended biu control (dev0:f0:0x44) bit name function 31?11 reserved reserved 15?14 reserved reserved 10?8 p0_wrdatadly write data delay p0_wrdatadly is the time in sysclk periods from the launch of a sysdc writedata command until the launch of the first data object by the processor. this value is a calculated part of the sip stream. this value is not provided in the biu sip register and is thus provided here. 7-4 reserved reserved 3 p0_2bitpf two bit times per frame enable this bit enables the use of the two bit time commands on the amd athlon? processor system bus. this bit must be set when connected to an amd athlon processor and disabled when connected to an alpha processor. for proper operation, bios must not clear this bit once it has been set. 0 = two-bit time commands disabled 1 = two-bit time commands enabled (amd athlon processor only) 2?0 reserved reserved these bits must be written with 0 (cleared) for normal operation.
44 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ecc mode/status dev0:f0:0x48 register description this register provides ecc mode control and status reporting for the dram system. note that some bits of this register are not initialized at reset time, and all bits must be initialized by bios for proper operation. this action should be done prior to attempting dram access. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit serr_enable reserved ecc_diag ecc_mode ecc_status resetxx0xxx00 r/w r/w r r/w r/w r/w1c 7 6 5 4 3 2 1 0 bit ecc_cs_med ecc_cs_sed reset00000000 r/w r r
chapter 2 AMD-761? system controller programmer?s interface 45 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions ecc mode/status (dev0:f0:0x48) bit name function 31?16 reserved reserved 15-14 serr_enable system error enable these bits control the AMD-761? system controller?s reporting of ecc errors to the system via the serr# pin on the pci bus. note that serr# assertion is still subject to the normal pci serr# enable (bit 8 in dev 0:f0:0x04). refer to table 7 on page 34 for details about serr# assertion and status. 00 = serr# assertion is disabled. x1 = multiple bit errors force serr# assertion. 1x = single bit errors force serr# assertion. 13 reserved reserved 12 ecc_diag error correcting code diagnostic mode enable 0 = ecc diagnostic mode disabled 1 = ecc diagnostic mode enabled when the ecc diagnostic mode is enabled, the AMD-761 system controller always writes 0x00 to the ecc byte to aid testing of the ecc logic. during partial writes, the rmw sequence still occurs, but the ecc bits are always written to 0x00. for reads, the ecc circuitry is unaffected by the ecc_diag bit. the ecc code returned from memory is checked, and errors are reported in the ecc_status bits as usual. correction is not performed in this mode. 11?10 ecc_mode error correcting code mode 00 = ecc disabled, no error detection or correction is performed. 01 = ec_hiperf mode enabled. error checking and status reporting is enabled. data destined for the pci/agp and memory (rmr) is not corrected. 10 = ecc_hiperf mode enabled. error checki ng and status reporting is enabled. data destined for the pci/agp and memory (rmr) is corrected. 11 = ecc_scrub mode enabled. error checking and status reporting is enabled. data destined for the pci/agp and memory (rmr) is corrected. the memory contents are corrected (scrubbed) after all reads with errors. 9?8 ecc_status error correcting code status this bit field indicates the status of the ecc detect logic as follows: 00 = no error x1 = med: multi-bit error detect 1x = sed: single-bit error detect the ecc status bits and corresponding failing ch ip-select indicators are set by the first error detected of each type (sed or med). the AMD-761 system controller does not log any new errors of each type or assert serr# until software clears the associated ecc_status bit by writing a 1.
46 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes system software is responsible for decoding the binary encoded, failing chip-select information and identifying a corresponding physical dimm location. some bits in this register are not initialized at reset. bios must initialize all bits in this register prior to attempting dram access. 7?4 ecc_cs_med multiple bit error chip select these bits provide the binary encoded chip select for the first multiple-bit error detected by the AMD-761? system controller. 3?0 ecc_cs_sed single bit error chip select these bits provide the binary encoded chip se lect for the first single-bit error detected by the AMD-761 system controller. bit definitions (continued) ecc mode/status (dev0:f0:0x48) bit name function
chapter 2 AMD-761? system controller programmer?s interface 47 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information pci control dev0:f0:0x4c register description this register controls various functions in the primary pci and agp interfaces. note: the wsc_dir configuration bit is implemented only in re vision b4 silicon and above. this bit is reserved and must be cleared in all previous silicon revisions. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reserved reserved reserved reset00000000 r/w r r r r 7 6 5 4 3 2 1 0 bit reserved reserved reserved wsc_dir (see note.) pci_dt_en pci_or_en func1_en reset00000 000 r/w r r r/w r/w r/w r/w
48 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes if the target latency bit is set (bit 23 of dev 0:f0:0x84), then the delayed transactions enable (bit 2) must be set when the front-side bus is clocked at 66 mhz. when enabling pci ordering rules compliance, it is recomme nded that delayed transactions be enabled simultaneously for optimal performance. refer to see chapter 5, ?pci bus interface? on page 195 for more information on the transaction options in the AMD-761 system controller. refer to see chapter 7, ?recommended bi os settings? on page 211 for the recommended bit settings for these bits. note that the wsc_dir pin is implemented only in silicon revi sions b4 and above and must be treated as reserved (write a 0) in all other silicon revisions. bit definitions pci control (dev0:f0:0x4c) bit name function 31?4 reserved reserved 3wsc_dir write snoop complete direction control this bit controls the direction and functi on of the write snoop complete (wsc#) pin. refer to the AMD-761? system controller datasheet , order# 24088, for a full description of the wsc# pin. 0 = bidirectional mode for use with southbridges that drive wsc# as an output and sample wsc# as an input (such as the amd-766? peripheral bus controller). in this mode, the wsc# pin of the AMD-761 system controller defaults as an input and is driven by the northbridge only after the pin is first asserted by the southbridge. 1 = unidirectional mode for use with southbridges that only sample wsc# as an input. in this mode, the wsc# pin is always driven by the AMD-761 system controller. note: this bit is implemented only in silicon revi sion b4 and above. it is reserved in all previous silicon revisions and must be cleared. 2 pci_dt_en delayed transactions enable (pci) 0 = delayed transactions disabled on the pci interface 1 = delayed transactions enabled on the pci interface 1pci_or_en ordering rules compliance enable (pci) this bit controls how the AMD-761 system controller pci bus interface orders transactions. 0 = pci ordering rules compliance disabled 1 = pci ordering rules compliance enabled 0 func1_en function 1 enable this bit controls access to device 0, func tion 1 configuration space (ddr pdl registers). refer to ?device 0, function 1: ddr pdl configuration registers? on page 97 for more information on the function 1 registers. 0 = device 0, function 1 disabled 1 = device 0, function 1 enabled
chapter 2 AMD-761? system controller programmer?s interface 49 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information amd athlon? processor system bus dynamic compensation dev0:f0:0x50 register description note that the default value of the byp, byp_p, and byp_n fiel ds of this register can be optionally controlled by sip bits when loading the sip stream from external rom. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit pval nval reset00000000 r/w r 15 14 13 12 11 10 9 8 bit byp_p byp_n reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit slewcntl byp reserved reset01100000 r/w r/w r/w r
50 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions amd athlon? system bus dynamic compensation (dev0:f0:0x50) bit name function 31?24 reserved reserved 23?20 pval p transistor strength value this field reflects the p transistor strength value that was automatically written to the amd athlon? processor system bus i/o pads by the auto-compensation circuit. in bypass mode (bit 4=1) this field returns the values in the byp_p field (bits [15:12]). the p values are active low. 19?16 nval n transistor strength value this field reflects the n transistor strength value that was automatically written to the amd athlon processor system bus i/o pads by the auto-compensation circuit. in bypass mode (bit 4=1) this field returns the values in the byp_n field (bits [11:8]). the n values are active high. 15?12 byp_p bypass values p driver bypass strength values for the p driver. the p values are active low. a value of 0 on bit 3 for instance signifies that (2^3 + 1) or 9 legs of the p driver are active. 11?8 byp_n bypass values n driver bypass strength values for the n driver. the n values are active high. a value of 1 on bit 3, for instance signifies that (2^3 + 1) or 9 legs of the n driver are active. 7?5 slewcntl slew rate control slew rate control for amd athlon processor system bus. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 (default) 100 = slew rate 4 101= slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 4byp bypass setting the bypass bit allows an external drive strength setting to be provided in the byp_p and byp_n fields. clearing this bit causes the drive strength to be provided by the compensation circuit. 3-0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 51 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information dram timing dev0:f0:0x54 register description this register defines the dram timing parameters for all bank s. bios software must set appropriate values in this register before setting the sdram_init bit (see ?bit definitions dram mode/status (dev0:f0:0x58)? on page 57) or attempting any dram accesses. note that this register is not initialized at reset time, and all bits must be initialized by bios for proper operation. this action should be done prior to attempting dram access. 31 30 29 28 27 26 25 24 bit sbpwaitstate addrtiming_a addrtiming_b rd_wait_state reg_dimm_en t wtr t wr resetxxxxxxxx r/w r/w 23 22 21 20 19 18 17 16 bit t rrd reserved idle_cyc_limit resetx0000xxx r/w r/w r r/w 15 14 13 12 11 10 9 8 bit ph_limit reserved t rc t rp resetxx00xxxx r/w r/w r r/w 7 6 5 4 3 2 1 0 bit t rp t ras t cl t rcd resetxxxxxxxx r/w r/w
52 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions dram timing (dev0:f0:0x54) bit name function 31 sbp_wait_state super bypass wait state this bit forces a wait state on all super bypa ss reads. this bit should be set when the bus speed is 133 mhz (refer to table 8 on page 55). 0 = no additional wait state on super bypass reads 1 = add wait state on super bypass reads 30 addrtiming_a address timing for copy-a this bit determines whether an extra delay is added to the address and command buses (maa[14:0], rasa#, casa#; wea#, ckea, cs[5:4, 1:0]#). this bit should be programmed depending on the loading presented to these pins. 0 = no extra delay 1 = xx ps delay 29 addrtiming_b address timing for copy-b this bit determines whether an extra delay is added to the address and command buses (mab[14:0], rasb#, casb#; web#, ckeb, cs[7:6, 3:2]#). this bit should be programmed depending on the loading presented to these pins. 0 = no extra delay 1 = xx ps delay 28 rd_wait_state read wait state this bit determines whether a wait state must be added before returning the read data from the memory to the requester. this bit should be programmed depending on the overall round-trip timing. note that this bit must be set for 100-mhz and 133-mhz operation, but it must not be set for 66-mhz operation (refer to table 8). 0 = no wait states 1 = one wait state 27 reg_dimm_en registered dimm enable this bit enables the use of registered dimms on the motherboard. AMD-761? system controller 0 = unbuffered dimms 1 = registered dimms 26 t wtr write data in to read command delay this bit controls the number of clock cycles that must occur between the last valid write operation and the next read command. 0 = t wtr duration is 1 clock cycle. 1 = t wtr duration is 2 clock cycles.
chapter 2 AMD-761? system controller programmer?s interface 53 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 25-24 t wr write recovery time this bit field controls the number of clock cycles that must occur from the last valid write operation to the earliest time a new precharge command can be asserted to the same bank. 00 = t wr duration is 1 clock cycle. 01 = reserved 10 = t wr duration is 2 clock cycles. 11 = t wr duration is 3 clock cycles. 23 t rrd activate bank a to activate bank b command delay this bit controls the number of clock cycles between successive activate commands to different banks. 0 = t rrd duration is 2 clock cycles. 1 = t rrd duration is 3 clock cycles. 22-19 reserved reserved 18?16 idle_cyc_limit idle cycle limit this bit field controls the number of idle cycl es to wait before precharging an idle bank. idle cycles are defined as cycles in which no valid requests are asserted. 111 = disable idle precharge 110 = 48 c ycles 101 = 32 cycles 100 = 24 cycles 011 = 16 cycles 010 = 12 cycles 001 = 8 cycles (recommended ?safe? configuration) 000 = 0 cycles 15?14 ph_limit page hit limit this bit field controls the number of consecutive page hit requests to allow before choosing a non-ph request. 00 = 1 cycle 01 = 4 cycle 10 = 8 cycles (recommended ?safe? configuration) 11 = 16 c ycles 13?12 reserved reserved bit definitions (continued) dram timing (dev0:f0:0x54) bit name function
54 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 11?9 t rc t rc this bit field indicates the t rc timing value (bank cycle time: minimum time from activate to activate of same bank). 111 = 10 cycles 110 = 9 c ycles 101 = 8 cycles (recommended ?safe? configuration) 100 = 7 cycles 011 = 6 c ycles 010 = 5 c ycles 001 = 4 cycles 000 = 3 cycles 8?7 t rp t rp this bit field indicates the t rp timing value (precharge time: time from precharge to activate on the same bank). 00 = 3 cycles (recommended ?safe? configuration) 01 = 2 cycles 10 = 1 cycles 11 = 4 cycles 6?4 t ras t ras this bit field indicates the t ras timing value (minimum bank ac tive time: time from activate to precharge of same bank). 111 = 9 c ycles 110 = 8 c ycles 101 = 7 cycles (recommended ?safe? configuration) 100 = 6 cycles 011 = 5 c ycles 010 = 4 c ycles 001 = 3 cycles 000 = 2 cycles 3?2 t cl cas latency of sdram 11 = reserved 10 = 2.5 cycles 01 = 2 cycles (recommended ?safe? configuration) 00 = 3 cycles bit definitions (continued) dram timing (dev0:f0:0x54) bit name function
chapter 2 AMD-761? system controller programmer?s interface 55 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes this register is not initialized at reset. bios must initialize all bits in this register prior to setting the sdram_init bit ( see ?bit definitions dram mode/status (dev0:f0:0x58)? on page 57) or attempting dram access for correct operation. the required settings for the wait state bits for sbp_wait_state and rd_wait_state are listed in table 8. 1?0 t rcd t rcd this bit field (t rcd ) is the timing value (ras to cas latency, delay from activate to rd/wr command). 11 = 4 cycles 10 = 3 cycles (recommended ?safe? configuration) 01 = 2 cycles 00 = 1 cycle table 8. wait state settings for dram timing register ddr interface frequency sbp_wait_state [bit 31] rd_wait_state [bit 28] 66 mhz 0 0 100 mhz 0 1 133 mhz 1 1 bit definitions (continued) dram timing (dev0:f0:0x54) bit name function
56 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information dram mode/status dev0:f0:0x58 register description this register provides general mode contro l and status reporting of the dram system. note that some bits of this register are not initialized at reset time, and all bits must be initialized by bios for proper operation. this action should be done prior to attempting dram access. 31 30 29 28 27 26 25 24 bit clk_dis5 clk_dis4 clk_dis3 clk_dis2 clk_dis1 clk_dis0 sdram_init reserved reset00000000 r/w r/w r/w1s r 23 22 21 20 19 18 17 16 bit mode_reg _ status str_control burst_ref_en ref_dis cyc_per_ref reset000xxxxx r/w r/w1s r/w 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit cs7_x4mode cs6_x4mode cs5_x4mode cs4_x4mode cs3_x4mode cs2_x4mode cs1_x4mode cs0_x4mode resetxxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w
chapter 2 AMD-761? system controller programmer?s interface 57 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions dram mode/status (dev0:f0:0x58) bit name function 31 clk_dis5 clock disable this bit controls the ddr clkout5/clkout5# differential clock pair: 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses. 30 clk_dis4 clock disable this bit controls the ddr clkout4/clkout4# differential clock pair. 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses. 29 clk_dis3 clock disable this bit controls the ddr clkout3/clkout3# differential clock pair. 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses. 28 clk_dis2 clock disable this bit controls the ddr clkout2/clkout2# differential clock pair. 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses. 27 clk_dis1 clock disable this bit controls the ddr clkout1/clkout1# differential clock pair. 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses. 26 clk_dis0 clock disable this bit controls the ddr clkout0/clkout0# differential clock pair. 0 = clock pair enabled 1 = clock pair disabled (three-stated) note: this bit is meant to disable the clock pair when it is not connected to anything. this bit should not be used for memory sizing or power management uses.
58 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 25 sdram_init sdram initialization this bit is used by the bios to tell the sdram controller to start the sdram initialization sequence. once set, this bit cannot be rese t. the bios should first program the sdram timing registers and set the output buffer drive strength. after that, it should set this bit. 24 reserved reserved 23 mode_reg_status mode register status 0 = off/done 1 = set when clear, the mode register write is disa bled and/or mode register write done. when set, the mode register write is enabled. configuration bits t cl must be set before this bit is asserted. bios software sets this bit for write to the sdram mode register. the memory controller clears this bit when it has issu ed the mode register write to the sdram. 22?21 str_control suspend to ram control these bits are used to allow the bios to communicate the power-up sequence to the AMD-761? system controller memory controller and power management logic, as follows: 00 = default. these bits are cleared to this state any time the reset# pin is asserted. the AMD-761 memory controller always drives the cke pins inactive (low) while these bits are low. 01 = bios sets this pattern after the system resumes from s4 (suspend to disk), s5 (soft off), or mechanical off states. this ac tion causes the AMD-761 memory controller to assert the cke pins and follow the normal sequence for ddr dram initialization after power-on. 1x = bios sets this pattern when the system is resuming from the s3 (suspend to ram) state. this action causes the AMD-761 memory controller to exit self-refresh while preserving all memory data. 20 burst_ref_en burst refresh enable 0 = AMD-761 system controller does not burst refreshes. 1 = AMD-761 system controller queues up to four refreshes before issuing. refreshes are only queued during long sequences of operations to the same memory device. 19 ref_dis refresh disable this bit is provided for system debug, and should be cleared for normal operation. 0 = refresh enabled (normal operation) 1 = refresh disabled (debug only) 18 reserved bit definitions (continued) dram mode/status (dev0:f0:0x58) bit name function
chapter 2 AMD-761? system controller programmer?s interface 59 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 17?16 cyc_per_ref cycles per refresh refresh counter defines period of refresh requests. the following table shows the relationship between the values in this field and the resultant refresh period for the different system clock frequencies: 15?8 reserved reserved 7 cs7_x4mode chip-select 7 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 6 cs6_x4mode chip-select 6 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 5 cs5_x4mode chip-select 5 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 4 cs4_x4mode chip-select 4 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 3 cs3_x4mode chip-select 3 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 2 cs2_x4mode chip-select 2 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 1 cs1_x4mode chip-select 1 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). 0 cs0_x4mode chip-select 0 x4mode enable 0 = this chip select consists of non-x4 devices (disabled). 1 = this chip select consists of x4 devices (enabled). bit definitions (continued) dram mode/status (dev0:f0:0x58) bit name function value 66 mhz 100 mhz 133 mhz 00 30.72 s 20.48 s 15.36 s 01 23.04 s15.36 s11.52 s 10 15.36 s10.24 s 7.68 s 11 7.68 s 7.68 s 3.84 s
60 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes note that some bits of this register are not initialized at reset time, and all bits must be initialized by bios for proper operation. this action should be done prior to attempting dram access. the clk_dis bits are cleared by reset#, and therefore all ddr dram interface cl ock pairs are enabled when exiting the advanced configuration and power interface (acpi) s3 sleep state (suspend to ram). bios should disable any clock pairs that are connected to unpopulated dimm slots upon exit of s3. when a chip select is programmed to operate in x4 dimm mo de, the dm[8:0] pins become dqs pins for that chip select. the pad configuration for the dm[8:0] pins is automatically controlled by the dqs_drive field (dev 0:f0:0x40) instead of the mdat_drive field, when any chip select is configured for x4 dimm mode.
chapter 2 AMD-761? system controller programmer?s interface 61 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information biu0 status/control dev0:f0:0x60 register description this register provides general status and control for the amd athlon? processor system bus interface. 31 30 29 28 27 26 25 24 bit prb_en reserved reserved reserved xca_prb_cnt xca_rd_cnt reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit xca_rd_cnt xca_wr_cnt halt_discon _en stp_grant _discon_en prb_limit reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit prb_limit ack_limit bypass_en sysdc_out _dly reset0000110pinstrapping r/w r/w r r/w r 7 6 5 4 3 2 1 0 bit sysdc_out _dly sysdc_in_dly wr2_rd rd2_wr reset pinstrapping r/w r
62 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions biu0 status/control (dev0:f0:0x60) bit name function 31 prb_en probe enable 0 = probes are not sent to this processor. 1 = probes are sent to this processor. 30 reserved this bit must be programmed to zero for normal operation. 29 reserved this bit must be programmed to zero for normal operation. 28 reserved this bit must be programmed to zero for normal operation. 27?25 xca_prb_cnt xca probe count this bit field represents the maximum number of consecutive amd athlon? processor system bus grants for probe data movement ty pes that are allowed before letting another type have the bus.bios must program this field to a non-zero value for proper operation. the recommended value to be loaded in this field by bios software is 0x2. 24?22 xca_rd_cnt xca read count this bit field represents the maximum num ber of consecutive amd athlon processor system bus grants for read data movement types that are allowed before letting another type have the bus.bios must program this field to a non-zero value for proper operation. the recommended value to be loaded in this field by bios software is 0x6. 21?19 xca_wr_cnt xca write count this bit field represents the maximum num ber of consecutive amd athlon processor system bus grants for write data movement types that are allowed before letting another type have the bus.bios must program this field to a non-zero value for proper operation. the recommended value to be loaded in this field by bios software is 0x6. 18 halt_discon_en halt disconnect enable 0 = no amd athlon system bus disconnect is performed following halt. 1 = amd athlon system bus disconnects after receiving a halt special cycle. 17 stp_grant_ discon_en stop grant disconnect enable 0 = no amd athlon processor system bus disc onnect is performed following stop/grant. 1 = amd athlon processor system bus disconnects after receiving a stop/grant special cycle. 16?14 prb_limit probe limit bios software initializes this field with the maximum number of outstanding probes that the given cpu can handle. the default is a single probe. encoding is as follows: 0b000 = 1 probe 0b001 = 2 probes ................................ 0b111 = 8 probes 13?10 ack_limit ack limit bios software reads this field to determine how many outstanding unacknowledged amd athlon processor system bus commands can be sent to the AMD-761? system controller. the AMD-761 system controller allows a maximum of four unacknowledged commands. encoding is as follows: 0b0000 = 1 unacknowledged command 0b0001 = 2 unacknowledged commands .......................................................... 0b1111 = 16 unacknowledged commands
chapter 2 AMD-761? system controller programmer?s interface 63 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes 9 bypass_en bypass enable when set, the AMD-761? system controller internally bypasses certain memory pipe stages for optimal performance. this bit may be set only if both of the following are true: 1. system is single processor or it is tw o processors and only cpu0 is present, and 2. cpu clock multiplier is 4 or greater. see ?config status? on page 74 to determine the clock multiplier (fid). 8?7 sysdc_out_dly sysdc out delay this bit field specifies the number of sysclk cycles from a return of read data type sysdc command and the start of the corresponding data. 0b00 = reserved 0b01 = 1 clock 0b10 = 2 clocks 0b11 = 3 clocks this field is initialized by pinstrapping during reset. 6?3 sysdc_in_dly sysdc in delay this bit field specifies the number of sysclk cycles from a write data type sysdc command and the start of the corresponding data. 0b0000 = 1 clock 0b0001 = 2 clocks ............................. 0b1111 = 16 clocks this field is initialized by pinstrapping during reset. 2wr2_rd wr2 read this field defines the number of sysclk cycles that are inserted between write data and read data cycles to allow the amd athlon? processor system bus data wires to turn around. this field is initialized by pinstrapping during reset. 1?0 rd2_wr rd2 write this field defines the number of sysclk cycles that are inserted between read data and write data cycles to allow the amd athlon processor system bus data wires to turn around. this field is initialized by pinstrapping during reset. bit definitions (continued) biu0 status/control (dev0:f0:0x60) bit name function
64 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information biu0 sip dev0:f0:0x64 register description this register provides visibility to th e serial initialization packet delivered to the amd athlon? processor during the amd athlon processor system bus connect protocol. 31 30 29 28 27 26 25 24 bit clk_fwd_offset data_init_cnt addr_init_cnt sys_data_even_clk_dly reset 0 pinstrapping r/w r/w r 23 22 21 20 19 18 17 16 bit sys_data_odd_clk_dly sys_data_even_dly sys_data_odd_dly sys_addr_dly reset pinstrapping r/w r 15 14 13 12 11 10 9 8 bit sys_addr_dly sysdc_dly sys_addr_clk_dly reset pinstrapping r/w r 7 6 5 4 3 2 1 0 bit sys_rst_clk_offset sys_data_rec_mux_preld sys_addr_rec_mux_preld reset 0 0 pinstrapping r/w r
chapter 2 AMD-761? system controller programmer?s interface 65 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions biu0 sip (dev0:f0:0x64) bit name function 31 clk_fwd_offset clock forward offset 0 = the AMD-761? system controller delays driving of the data and clock for amd athlon? processor system bus sysdata bits [31:16] and [63:48] by ~1000 ps. 1 = all amd athlon system bus clkfwd groups drive the same nominally sysclk edge. 30?29 data_init_cnt data initialization count this value specifies the number of sysclks from the launch of data by the processor until it can be read from the AMD-761 system controller receive fifo. 28?27 addr_init_cnt address initialization count this value specifies the number of sysclks from the launch of a command by the processor until it can be read from the AMD-761 system controller receive fifo. 26?24 sys_data_even _clk_dly system data even clock delay -- amd athlon processor sip[33:31] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the even clocks. 23?21 sys_data_odd _clk_dly system data odd clock delay -- amd athlon processor sip[30:28] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the odd clocks. 20?19 sys_data_even _dly system data even delay -- amd athlon processor sip[27:26] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the even data (sysdata bits [31:16] and [63:48]). 18?17 sys_data_odd _dly system data odd delay -- amd athlon processor sip[25:24] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the odd data (sdata bits [15:00] and [47:32]). 16?15 sys_addr_dly system address delay -- amd athlon processor sip[23:22] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the address (sysaddout). 14?11 sysdc_dly sysdc delay -- amd athlon processor sip[19:16] this value is an internal processor paramete r that is used to ca use sysdc commands and their associated data to arrive in the processor core at the correct relative times. 10?8 sys_addr_clk _dly system addr clock delay -- amd athlon processor sip[13:11] this value specifies the number of processor xiclk phases between the nominal start of bit time and the launch of the saddoutclk. 7?6 sys_rst_clk _offset system reset clock offset -- amd athlon processor sip[10:9] this value is an internal processor paramete r that is used to properly time amd athlon system bus data transfer. 5?3 sys_data_rec _mux_preld system data rec mux preld -- amd athlon processor sip[8:6] this value specifies the number of sysclk phases from the launch of data by the AMD-761 system controller until it can be read from the amd athlon receive fifo. 2?0 sys_addr_rec _mux_preld system address rec mux preld -- amd athlon processor sip[5:3] this value specifies the number of sysclk phases from the launch of address/command by the AMD-761 system controller until it can be read from the amd athlon receive fifo.
66 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information memory status/control dev0:f0:0x70 register description this register provides general status and control for the memory controller. note that the self_ref_en bit in this register is not initializ ed at reset time, but must be initialized by bios for proper operation. this action should be done prior to attempting dram access. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved self_ref_en reset00000x00 r/w r r/w 15 14 13 12 11 10 9 8 bit reserved pci_pipe_en pci_blk_wr _en reserved reset00000000 r/w r/w r r/w r 7 6 5 4 3 2 1 0 bit reserved reserved reserved reserved reserved reserved reset00000000 r/w r r r
chapter 2 AMD-761? system controller programmer?s interface 67 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes note that the self_ref_en bit in this register is not initializ ed at reset time but must be initialized by bios for proper operation. this action should be done prior to attempting dram access. dcstop# assertion (acpi s1/s3) must not be enabled if the self_ref_en bit is cleared. bit definitions memory status/control (dev0:f0:0x70) bit name function 31?19 reserved reserved 18 self_ref_en self-refresh enable this bit enables self-refresh when entering certain power management states. this bit should normally be set, but the option to disable this function is provided to accommodate specific dimms that do not correctly support the self-refresh feature. note that if this bit is not set, then dcstop# assertion (acpi sleep states) must be inhibited. 0 = self-refresh disabled 1 = self-refresh enabled 17?14 reserved 13 reserved 12?11 reserved reserved 10 pci_pipe_en pci pipe enable 0 = all pci transactions, from either the pci or agp interfaces, force the memory controller to check for outstanding read pr obes with a matching block address and stall until these probes are complete. 1 = memory controller pipelines pci transactions. setting this bit generally increases pci th roughput. this bit must be clear when the processor is allowed to issue cleanvictimblock commands. 9pci_blk_wr_en pci block write enable 0 = pci full-block writes do rid/inv probes, forcing the memory controller to wait for probe data movement. 1 = pci full-block writes do nop/inv probes. this bit must be clear when the amd athlon? processor is allowed to issue cleanvictimblock commands. 8?1 reserved reserved 0 reserved reserved
68 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information who am i (whami) dev0:f0:0x80 register description 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reserved reserved reserved biu0_present reset0000000from cpu r/w r 15 14 13 12 11 10 9 8 bit firstbusid reset00000000 r/w r 7 6 5 4 3 2 1 0 bit whami reset cpuid r/w r
chapter 2 AMD-761? system controller programmer?s interface 69 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions who am i (whami) (dev0:f0:0x80) bit name function 31-17 reserved reserved 16 biu0_present biu0 present this bit, when set, indicates that a proc essor is installed on the specified amd athlon? processor system bus port on the AMD-761? system controller and it has requested a connect sequence (procrdy assertion). 15?8 firstbusid first busid this field contains the amd athlon processor sy stem bus id of the first processor to read this register: 00h if cpu0 was the first to read whami after reset, 01h if cpu1 was the first to read whami after reset. 7?0 whami who am i this field returns the amd athlon processor system bus id (below) of the processor that accesses it: 00h for cpu0, 01h for cpu1.
70 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information pci arbitration control dev0:f0:0x84 register description this register provides general pci arbiter mode control. 31 30 29 28 27 26 25 24 bit agp_vga_bios reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit tgt_latency reserved reserved agp_chain_en pci_chain_en reset00000000 r/w r/w r r r/w r/w 15 14 13 12 11 10 9 8 bit mda_debug pci_wr_post _rtry agp_wr_post _rtry rd_data_err _dis agp_erly_prb _dis pci_erly_prb _dis agp_arb_pipe _dis sb_lock_dis reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit pm_reg_en 15m_hole 14m_hole ev6_mode tgt_lat_tim _dis agp_pref_en pci_pref_en park_pci reset00000000 r/w r/w
chapter 2 AMD-761? system controller programmer?s interface 71 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions pci arbitration control (dev0:f0:0x84) bit name function 31?24 agp_vga_bios agp vga bios these bits when set indicate that the corresponding (16-kbyte) segment should be mapped to the agp pci bus. bit 24 corresponds to the addresses 0xc0000?0xc3fff and bit 31 maps addresses 0xdc000?0xd ffff to the agp pci interface. set one or more of these bits if the agp graphics card has a rom bios. 23 tgt_latency target latency this bit is designed to ensure that the amd- 761? system controller is compliant to the pci maximum target latency rule. note that this compliance applies only to the pci bus and not the agp bus. 0 = amd-751? system controller-compatible, the AMD-761 system controller does not disconnect a master when it cannot service a read request within 32 pci clock periods (initial latency) or 8 clocks (subsequent data cycles). 1 = if the AMD-761 system controller cannot respond to a memory read within 32 clocks for the initial access, or 8 clocks for each subsequent access, it forces a retry. note: to prevent potential deadlocks, set this bit and clear bit 3 (tgt_lat_tim_dis) if the system has pci to agp traffic. 22?18 reserved reserved 17 agp_chain_en enable agp chaining when set, cpu writes to the agp bus are chained together. 16 pci_chain_en enable pci chaining when set, cpu writes to pci are chained together. 15 mda_debug mda debug this bit allows monochrome display adapters (mda) to be used simultaneously with agp cards for debug of agp device drivers. the behavior of the AMD-761 system controller display adapters is a function of this bit a nd the vga enable in (d1:0x3c[19]) as follows: mda address ranges: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b 8h, 3b9h, 3bah, 3bfh vga = 0, mda = 0: all mda and vga references go to pci vga = 0, mda = 1: operation undefined vga = 1, mda = 0: all vga references go to agp, mda only (i/o 3bfh) goes to pci vga = 1, mda = 1: all vga references go to agp, all mda (including memory) go to pci 14 pci_wr_post _rtry pci write post retry when set, this bit enables retries on pci if there are pending posted writes. 13 agp_wr_post _rtry agp write post retry when set, this bit enables retries on the agp bus if there are pending posted writes.
72 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 12 rd_data_err_ dis read data error disable whenever a cycle from a processor to the pc i or agp buses results in a master abort (except special cycles), the AMD-761? syst em controller returns a read data error indicator to the processor. when set, this bit causes data value of all 1s to be returned. when clear, an amd athlon? processor system bus read data error response is returned. the cpu response to read data error is determined by the settings of the machine check architecture registers in the processor. 11 agp_erly_prb_ dis agp early probe disable as soon as the AMD-761 system controller detects a pci write cycle to memory from an external agp master, it sends a ?probe only? request to the processor that is used to flush data from the processor cache. after one or more data phases, a write request is sent to the memory, which also results in a probe. when set, this bit disables the early probe from an agp master running a pci write cycle to memory. 10 pci_erly_prb_ dis pci early probe disable this bit is similar agp_erly_prb_dis and can disable early probe requests for write cycles from an external master on the standard pci bus. 9 agp_arb_pipe_ dis agp arbiter pipe disable when set, this bit disables the agp arbi ter from pipelining grants onto the bus. 8 sb_lock_dis southbridge lock disable when the southbridge makes a request for the pci bus, the AMD-761 system controller makes sure that all the previous posted re quests from the processors and pci are completed by the memory before granting the bus to the southbridge. when set, this bit disables this flushing of previous requests. 7 pm_reg_en power management register enable this bit, when set, enables reading from and writing to the power management register (at bar2). 615m_hole 15m memory hole when set, this bit creates a hole in memory fr om 15 mbytes to 16 mbytes. this register is used by the pci decode logic to know when to accept a cycle from an external pci master. when set, the pci decode logic does not assert a match for addresses falling in this range. 514m_hole 14m memory hole when set, this bit creates a hole in memory fr om 14 mbytes to 15 mbytes. this register is used by the pci decode logic to know when to accept a cycle from an external pci master. when set, the pci decode logic does not assert a match for addresses falling in this range. 4 ev6_mode ev6 mode when set, this bit indicates that the pci interfaces have to decode memory hits in the ev6 mode. there are no memory holes and dma ca n be done to any address that lies within the sdram map. bit definitions (continued) pci arbitration control (dev0:f0:0x84) bit name function
chapter 2 AMD-761? system controller programmer?s interface 73 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes to avoid potential deadlocks for systems th at use traffic from the pci bus to the pc i bus of the agp, clear the write target latency timer disable bit (bit 3, tgt_lat_tim_dis), and set the read target latency timer bit (bit 23, tgt_latency). refer to the programming notes for the pci control register (dev 0:f0:0x4c) for details on the recommended setting of the tgt_latency bit. 3 tgt_lat_tim_ dis target latency timer disable when the AMD-761? system controller acts as a pci target, it has a latency timer that retries the (write) cycle if it cannot respond wi thin 8 bus clocks (16 clocks for the first transfer). when set, this bit disables the am d-761 system controller?s target latency timer on both the standard pci and agp pci interfaces. note: to prevent potential deadlocks caused by pci to agp traffic on the system, this bit should be cleared and bit 23 (tgt_latency) must be set. note also that setting this bit disables the tgt_latency function controlled by bit 23. 2agp_pref_en agp prefetch enable when set, this bit enables the AMD-761 syst em controller to prefetch data from the sdram when a pci master on the standard agp bus reads from the main memory. 1pci_pref_en pci prefetch enable when set, this bit enables the AMD-761 syst em controller to prefetch data from the sdram when a pci master on the pci bus reads from the main memory. 0park_pci park pci when set, this bit enables parking on an exte rnal pci master. when clear, the pci arbiter only parks on processor accesses to pci. bit definitions (continued) pci arbitration control (dev0:f0:0x84) bit name function
74 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information config status dev0:f0:0x88 register description this register allows bios software to determine what syst em initialization states have been programmed by resistor pinstrappings on the motherboard. 31 30 29 28 27 26 25 24 bit agp_clk_mux sys_clk_mux type_det s2k_thresh reset x (from pci ad[14:12]) x (from pci ad[7:5]) x (from pci ad[20]) x (from pci ad[4]) r/w r 23 22 21 20 19 18 17 16 bit k7_pp_en ig_pp_en clk_speed reserved s2k0_bus_len reset x (from pci c/be[3]#) x (from pci c/be[2]#) x (from pci ad[31:30]) x (from pci ad[27:26]) x (from pci ad[11:10]) r/w r 15 14 13 12 11 10 9 8 bit tristate_en nand_en bypass_plls dis_divider reserved reset x (from pci ad[25]) x (from pci ad[23]) x (from pci ad[9]) x (from pci ad[29]) x (from pci ad[19:16]) r/w r 7 6 5 4 3 2 1 0 bit sip_rom_en gp_strap in_clk_en out_clk_en cpu0_divider reset x(from pci c/be[0]#) x (from pci ad[15]) x (from pci ad[24]) x (from pci ad[8]) x (from pci ad[3:0]) r/w r
chapter 2 AMD-761? system controller programmer?s interface 75 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions config status (dev0:f0:0x88) bit name function 31?29 agp_clk_mux agp clock mux for internal test only. 28?26 sys_clk_mux system clock mux for internal test only. 25 type_det type detect 0 = this installed card in the agp slot uses 1.5-v signalling. 1 = this installed card in the agp slot uses 3.3-v signalling. 24 s2k_thresh amd athlon? processor system bus threshold amd athlon? processor system bus threshold range select for amd athlon? system bus i/o cells. when low, these amd athlon processor system bus inputs sense input thresholds between 1.35 v and 1.9 v. when high, the inputs sense thresholds between 2.0 v and 2.2 v. 23 k7_pp_en amd athlon processor push-pull driver enable when set, this bit indicates that the amd a thlon processor push-pull drivers are enabled. 22 ig_pp_en AMD-761? system controller push-pull driver enable when set, this bit indicates that the AMD-761 system controller push-pull drivers are enabled. 21?20 clk_speed clock speed this bit field defines the speed of the sy stem clock received by the AMD-761 system controller: 00 = 100 mhz 01 = 66 m hz 10 = reserved 11 = 133 m hz 19?18 reserved reserved 17?16 s2k0_bus_len amd athlon processor system bus length this bit field indicates the relative length of the amd athlon processor system bus trace routing on the motherboard. 00 = short 01.............. 10............... 1 = long 15 tristate_en tristate enable for internal test only. 14 nand_en nand enable for internal test only.
76 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes 13 bypass_plls bypass plls this bit is set for test and debug of the AMD-761? system controller with the internal plls disabled. 0 = AMD-761 system controller plls enabled 1 = AMD-761 system controller plls bypassed; clocks driven from sysclk and agpclk pins directly to internal clock trees 12 dis_divider disable divider for internal test only. 11?8 reserved reserved 7 sip_rom_en sip rom enabled this bit indicates that the external sip rom is enabled and is read to create the sip stream to the amd athlon processor, instead of the internally generated sip table. 6gp_strap general-purpose strap this bit may be used as a general-purpose strap for communicating motherboard- specific information to bios. the AMD-761 system controller does not use this strap internally. 5in_clk_en inclk enable this bit indicates that the AMD-761 system controller delays the inclk to the amd athlon processor. when reset, the motherboard is expe cted to provide delay in the etch to center the inclk with the data. 4 out_clk_en outclk enable this bit indicates that the amd athlon processor delays the outclk to the AMD-761 system controller. when reset, the motherboard is expected to provide delay in the etch to center the outclk with the data. 3?0 cpu0_divider cpu divider this bit field contains the cpu clock multiplier field supplied by the processor. together with the clk_speed field and the s2k0_bus_len field, these fields allow the AMD-761 system controller to properly program the amd athlon? processor system bus initialization logic using the sip protocol. the clock multiplier field is also known as the frequency identification (fid) bits and the values are shown below. bit definitions (continued) config status (dev0:f0:0x88) bit name function fid value multiplier fid value multiplier fid value multiplier fid value multiplier 0000 11.0 0100 5.0 1000 7.0 1100 9.0 0001 11.5 0101 5.5 1001 7.5 1101 9.5 0010 12.0 0110 6.0 1010 8.0 1110 10.0 0011 12.5 0111 6.5 1011 8.5 1111 10.5
chapter 2 AMD-761? system controller programmer?s interface 77 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information pci top of memory dev0:f0:0x9c register description this register is used to define the top of main system memo ry. it is used to compare the memory addresses of an external pci master to determine if it is in the range of the amd-76 1? system controller dram. if the address compares, then the AMD-761 system controller responds to the bus master access with devsel# assertion. 31 30 29 28 27 26 25 24 bit pci_mem_top reset10000000 r/w r/w 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit reserved reset00000000 r/w r
78 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions pci top of memory (dev0:f0:0x9c) bit name function 31?24 pci_mem_top pci memory top this 8-bit field is compared to the incoming pci bus master address to determine if a memory cycle falls within the AMD-761? sy stem controller dram region, as follows: 31 30 29 28 27 26 25 24 pcimemtop field 31 30 29 28 27 26 25 24 pci address bios should write to this field following completion of the memory sizing algorithm, after it has determined the total size of the installed memory. 23?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 79 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp capability identifier dev0:f0:0xa0 register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit major_rev minor_rev reset00100000 r/w r 15 14 13 12 11 10 9 8 bit next_pointer reset00000000 r/w r 7 6 5 4 3 2 1 0 bit cap_id reset00000010 r/w r bit definitions agp capability identifier (dev0:f0:0xa0) bit name function 31?24 reserved reserved 23?20 major_rev major revision major revision of the agp interface specification conformed to by this device. 19?16 minor_rev minor revision minor revision of the agp interface specification conformed to by this device. 15?8 next_pointer next pointer pointer to the next item in the capabilities lis t. must be null for the final item on the list. 7?0 cap_id capid this value indicates that this list item pertains to agp registers.
80 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp status dev0:f0:0xa4 register description 31 30 29 28 27 26 25 24 bit max_reqq_depth reset00001111 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved sba reserved reset00000010 r/w r 7 6 5 4 3 2 1 0 bit reserved r4g fw reserved rates reset00000111 r/w r
chapter 2 AMD-761? system controller programmer?s interface 81 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes fast writes are disabled by default and are indicated in the st atus bit that reports this capability. setting the fw_enable bit in the agp 4x dynamic compensation register (dev 0:f0:0xb4, bi t 7) sets the fw bit in this register to indicate support of this feature. fast writes are enabled when both the fw_enable bit (in the agp 4x dynamic compensation register) and the fast_writes bit in the agp command register are set. agp 4x transfers are supported and the 4x status bit is set by de fault in this register. this bit can be overridden by setting the 4x_override bit in the agp 4x dynamic compensation register (dev 0:f0:0xb4, bit 6). bit definitions agp status (dev0:f0:0xa4) bit name function 31?24 max_reqq_ depth maximum command requests this field contains the maximum number of agp command requests that this node can manage. 23?10 reserved reserved 9sba sideband addressing this field is always 1, indicating that th e AMD-761? system controller supports sideband addressing. 8?6 reserved reserved 5r4g address limit this bit is always 0, indicating that th e AMD-761 system controller does not support addresses greater than 4 gbytes. 4fw fast write transfer this bit indicates supports of fast write transfers. 0 = fast writes not supported 1 = fast writes supported 3 reserved reserved 2?0 rates rate transfers this field indicates that the AMD-761 system c ontroller supports 1x (bit[0]), 2x (bit[1]), and 4x (bit[2]) transfers.
82 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp command dev0:f0:0xa8 register description 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved sba_en agp_en reset00000000 r/w r r/w 7 6 5 4 3 2 1 0 bit reserved r4g_en fast_writes reserved data_transfer_mode reset00000000 r/w r r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 83 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions agp command (dev0:f0:0xa8) bit name function 31?10 reserved reserved 9 sba_en sideband addressing enable when this bit is set, side band addressing is enabled. 8agp_en agp operations enable when this bit is set, the AMD-761? system controller accepts agp operations. when this bit is clear, the AMD-761 system controller ignores agp operations. 7?6 reserved reserved 5r4g_en 4gb address indicator this bit indicates that the AMD-761 system controller does not support addresses greater than 4 gbytes. the AMD-761 system cont roller supports only 32-bit addresses. 4 fast_writes fast writes 0 = fast writes disabled 1 = fast writes enabled when the fw_enable bit is also set in the agp 4x dynamic compensation register (dev 0:f0:0xb4, bit 7) 3 reserved reserved 2?0 data_transfer _mode data transfer mode only one bit must be set in this field to indicate the desired agp data transfer rate. 001 = 1x agp rate 010 = 2x agp rate 100 = 4x agp rate
84 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp virtual address space size dev0:f0:0xac register description 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved vga_ia_en reset00000000 r/w r r/w 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit reserved va_size gart_en reset00000000 r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 85 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions agp virtual address space size (dev0:f0:0xac) bit name function 31?17 reserved reserved 16 vga_ia_en isa address aliasing enable when set, this bit forces the AMD-761? system controller to alias isa addresses, which means that address bits [15:10] are not used in decoding. when clear, no isa aliasing is performed and address bits [15:10] are used for decoding. 15?4 reserved reserved 3?1 va_size virtual address size this field defines the virtual address space size to be allocated to gart by the system bios. prior to the execution of the system bios memory mapping software, system bios gets the amount of gart virtual address space required by the graphics controller. it sets these bits to the required value. changing these bits automatically changes bits [30:25] in the host-pci bridge (device 0) agp virtual address space register, offset 0x10 (see ?dev0:f0:0x10? on page 37). the size of gart virtual address space is al ways greater than or equal to the amount of physical system memory allocated to agp in non-contiguous 4-kbyte blocks. the amount of physical memory allocated to agp is determined by operating system software. [3] [2] [1] va_size 0 0 0 32 mbytes 0 0 1 64 mbytes 0 1 0 128 mbytes 0 1 1 256 mbytes 1 0 0 512 mbytes 1 0 1 1 gbytes 1 1 0 2 gbytes 0 gart_en gart enable when clear, gart is not valid in this system . system bios does not allocate virtual address space for gart because the host-pci bridge (d evice 0) agp virtual address space, offset 0x10 (see ?dev0:f0:0x10? on page 37) is set to 0. the pci-pci bridge (device 1) capabilities pointer is set to point to the next item in the linked list or null if there is no other item. this bit is set by bios pci enumeration routines. when set, gart is valid in this system. sy stem bios allocates virtual address space for gart based upon the value in bits [3:1] above.
86 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information gart/agp mode control dev0:f0:0xb0 register description this register provides bits to control specific featur es of the AMD-761? system controller agp implementation. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved nongart _snoop pdc_en lv1_index reset00000000 r/w r r/w 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit reserved reset00000000 r/w r
chapter 2 AMD-761? system controller programmer?s interface 87 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions gart/agp mode control (dev0:f0:0xb0) bit name function 31?21 reserved reserved 20 reserved 19 nongart_snoop nongart snoop when set, this bit forces agp accesses that are not in the gart range to cause amd athlon? processor system bus probes to the processor(s). when clear, agp addresses that fall outside of the gart range do not cause probes. 18 reserved 17 p d c _ e n gart page directory cache enable this bit is used only in the two-level gart mode. it has no effect in the one-level gart mode. the gart directory is enabled only when both this bit and the agp features control register (offset 02h of the memory-m apped features and capabilities register?see ?bar1 + 0x00? on page 141) bit 2, "gart cache enable", are 1s. 16 lv1_index level 1 index (gart index scheme control) when set to 1, this bit enables the one-level gart mode. when cleared to 0, two-level gart mode is enabled. 15?0 reserved reserved
88 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp 4x dynamic compensation dev0:f0:0xb4 register description 31 30 29 28 27 26 25 24 bit pval nval resetxxxxxxxx r/w r 23 22 21 20 19 18 17 16 bit reserved disstrb quantum_cnt reset00000001 r/w r r/w r/w 15 14 13 12 11 10 9 8 bit reserved reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit fw_enable 4x_override comp3.3 reserved pci always_ compensate do_ compensate reset00000000 r/w r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 89 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions agp 4x dynamic compensation (dev0:f0:0xb4) bit name function 31?28 pval p transistor strength value this field reflects the p transistor strength value that was written to the non-strobed agp i/o pads according to table 9 on page 90. 27?24 nval n transistor strength value this field reflects the n transistor strength value that was written to the non-strobed agp i/o pads according to table 9 on page 90. 23 reserved reserved 22 disstrb disable strobe this bit allows the complimentary strobes adstb[1:0]# to be disabled when the agp interface is operating in 2x mode. setting this bit causes these pins to be driven high. 21?16 quantum_cnt quantum count this field is used to determine the number of 100-ms intervals that elapse before a dynamic compensation event is performed wh en the alwayscompensate bit is set. the value allows for dynamic compensation time quantums to range from 100 ms to 6.4 s. 15?8 reserved reserved 7 fw_enable fast writes override 0 = fast writes disabled 1 = fast writes enabled (see below) agp fast writes are enabled by a combination of this bit and the fast_writes enable bit in the agp command register (dev 0:f0:0xa8, bit 4). the fast_writes status bit in the agp status register (dev 0:f0:0xa4, bit 4) is 0 by default, indicating that the AMD-761? system controller does not support this feature. setting this bit forces the status bit to a 1 to indicate support of fast writes. the fast writes feature is enabled only when this bit and the fast_writes bit in the agp command register (dev 0:f0:0xa8, bit 4) are set. 6 4x_override agp 4x override this bit can be set to override the value in the read-only agp status register (dev 0:fd0:0xa4). by default the rates field of th e agp status register report 4x capability, but setting this bit forces the 4x-capable bit to be 0, indicating a maximum of 2x support. 5 comp3.3 compensate for 3.3-v signalling this bit overrides the typedet# value to force an agp auto-compensation in a 3.3-v signalling environment. this bit may be se t in conjunction with the do_compensate bit to enable bios to determine which drive strength values the auto-compensation circuit selected for this motherboard. note: this bit must be set only while the agp interface is disabled . setting this bit while the agp interface is enabled results in unpredictable behavior. 4-3 reserved reserved 2pci pci as shown in table 9 on page 90, this bit, along with byp and agp2x bits, controls the drive strength of the output buffer and whether the input buffers are single-ended or differential.
90 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes when transitioning from bypass enabled to disabled via the agp compensation bypass register (dev 0:f0:0xb8), the do_compensate bit should be set. agp should not be subse quently enabled until the do_compensate bit is read back as a 0, indicating that the compensation cycle is complete. refer to the agp compensation bypass register (dev 0:f0:0xb8) for details of bypass mode. 1always_ compensate always compensate when set, dynamic compensation is pe rformed by agp on an ongoing basis at regular intervals. 0do_compensate do compensate this bit is used to initiate a dynamic compensation command on agp. this bit is cleared by the AMD-761? system controller when the compensation cycle is complete. see the programming note below on recommendation for exiting bypass mode. table 9. i/o pad drive strength and input type bypass typedet# pci agp mode output drive strength 0 0 x n/a compensated strength 0 1 0 n/a agp-1x strength 01 1 n/apci strength 1 x x n/a bypass, user configurable bypass typedet# pci agp mode input type x 0 x 4x differential x 0 x 1x/2x single-ended x 1 x 1x/2x single-ended x 1 x 1x/2x single-ended bit definitions (continued) agp 4x dynamic compensation (dev0:f0:0xb4) bit name function
chapter 2 AMD-761? system controller programmer?s interface 91 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp compensation bypass dev0:f0:0xb8 register description this register allows bios to bypa ss the agp auto-compensation to directly control the agp pad configuration. 31 30 29 28 27 26 25 24 bit byp_pdrvxfer byp_ndrvxfer reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit bypxfer reserved pslewxfer nslewxfer reset10000000 r/w r/w r r/w 15 14 13 12 11 10 9 8 bit byp_pdrvstrb byp_ndrvstrb reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit bypstrb reserved pslewstrb nslewstrb reset10000000 r/w r/w r r/w
92 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions agp compensation bypass (dev0:f0:0xb8) bit name function 31?28 byp_pdrvxfer p drive strength control this field is used to directly program the p transistor drive strength on all agp pins except the data strobes. a value of 0000 is the weakest, 1111 is the strongest. this value is written to the i/o pads only when bypxfer (bit 23) is set. 27?24 byp_ndrvxfer n drive strength control this field is used to directly program the n transistor drive strength on all agp signals except the data strobes. a value of 0000 is the weakest, 1111 is the strongest. this value is written to the i/o pads only when bypxfer (bit 23) is set. 23 bypxfer bypass enable this bit must be set to bypass the auto-compe nsation circuit for direct control of all agp pads except the strobe pins. when this bit is set, the values programmed in the drive strength fields are written directly to the pads. 22?20 reserved reserved 19?18 pslewxfer slew rate control this field is used to directly program the rise time in all agp signals except the data strobes. this field is not affected by the bypxfer bit. 00 = slew rate 0 (slowest) 01 = slew rate 1 10 = slew rate 2 11 = slew rate 3 (fastest) 17?16 nslewxfer slew rate control this field is used to directly program the fall time in all agp signals except the data strobes. this field is not affected by the bypxfer bit. 00 = slew rate 0 (slowest) 01 = slew rate 1 10 = slew rate 2 11 = slew rate 3 (fastest) 15?12 byp_pdrvstrb p drive strength control this field is used to directly program the p transistor drive strength on the agp data strobes (ad_stb[1:0], ad_stb[1:0]#). a valu e of 0000 is the weakest, 1111 is the strongest. this value is written to the i/ o pads only when bypstrb (bit 7) is set. 11?8 byp_ndrvstrb n drive strength control this field is used to directly program the n transistor drive strength on all agp data strobes (ad_stb[1:0], ad_stb[1:0]#). a valu e of 0000 is the weakest, 1111 is the strongest. this value is written to the i/ o pads only when bypstrb (bit 7) is set. 7bypstrb bypass enable this bit must be set to bypass the auto-compe nsation circuit for direct control of all agp strobe pins (ad_stb[1:0], ad_stb[1:0]#). when this bit is set, the values programmed in the drive strength fields are written directly to the pads. 6?4 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 93 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes there are three basic modes of bypass operation, as shown in the table below. note that compensation applies to 1.5-v signalling operation only. it is possible to configure the agp i/o pads such that th e non-strobed signals are auto-compensated while the strobes are in bypass mode, but not vice-versa, as shown in the table above. once the non-strobed signals are programmed in bypass mode , these programmed bypassed values are also written to the strobed signal i/o pads, until the strobed pads bypass values are also written. 3?2 pslewstrb slew rate control this field is used to directly program the rise time in all agp data strobes (ad_stb[1:0], ad_stb[1:0]#). this field is not affected by the bypstrb bit. 00 = slew rate 0 (slowest) 01 = slew rate 1 10 = slew rate 2 11 = slew rate 3 (fastest) 1?0 nslewstrb slew rate control this field is used to directly program the fall time in all agp data strobes (ad_stb[1:0], ad_stb[1:0]#). this field is not affected by the bypstrb bit. 00 = slew rate 0 (slowest) 01 = slew rate 1 10 = slew rate 2 11 = slew rate 3 (fastest) auto compensate bypass bypass modes non-strobe strobes non-strobed signals auto-compensated while strobe signals programmed manually in bypass mode. all signals all signals programmed manually in bypass mode. all signals all signals auto-compensated. bit definitions (continued) agp compensation bypass (dev0:f0:0xb8) bit name function
94 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information memory base address registers (dev0:f0:0xc0 to 0xdf) the AMD-761 system controller ddr memory controller can access up to eight banks of dram (four dimms, one bank per side). these banks are controlled by eight chip selects. these registers define how an incoming address is parsed to select only one out of the eight ch ip selects. bios software is responsible for correctly loadin g these registers based on data returned from the serial presence detect rom mechanism through the smbus implemente d in the southbridge. bios software must adhere to the fo llowing rules when configuring these registers: the largest banks are config ured first as the lowest addressed memory, increasing addresses with decreasing size of banks available. logically, a given chip-select n, is asserted when: (addr[31:23] & ~csmaskn) == (csbasen & ~csmaskn) the smallest bank suppo rted is 32 mbytes. see table 10 on page 95.
chapter 2 AMD-761? system controller programmer?s interface 95 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information register description note that these registers are not initialized at reset time, bu t must be initialized by bios for proper operation. this action should be done prior to attempting dram access. table 10. ddr memory base address register locations memory base address register 0 dev0:f0:0xc0 memory base address register 1 dev0:f0:0xc4 memory base address register 2 dev0:f0:0xc8 memory base address register 3 dev0:f0:0xcc memory base address register 4 dev0:f0:0xd0 memory base address register 5 dev0:f0:0xd4 memory base address register 6 dev0:f0:0xd8 memory base address register 7 dev0:f0:0xdc 31 30 29 28 27 26 25 24 bit cs_base resetxxxxxxxx r/w r/w 23 22 21 20 19 18 17 16 bit cs_base reserved resetx0000000 r/w r/w r 15 14 13 12 11 10 9 8 bit cs_mask resetxxxxxxxx r/w r/w 7 6 5 4 3 2 1 0 bit cs_mask reserved addr_mode cs_en resetx0000xxx r/w r/w r r/w
96 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes note that these registers are not initialized at reset time, bu t must be initialized by bios for proper operation. this action should be done prior to attempting dram access. table 11 shows dram addressing modes. bit definitions memory base address registers 0?7 (dev0:f0:0xc0?0xdf) bit name function 31?23 cs_base chip-select base this bit field defines which 8-mbyte boundary the given bank services. incoming addresses are compared against field, subj ect to the mask field in bits [15:7]. 22?16 reserved reserved 15?7 cs_mask chip-select mask this bit field defines what bits in the addr ess are ignored when incoming addresses are compared to the csbase in bits[31:23] above. if a given bit is set, the corresponding bit in the compare is ignored. 6?3 reserved reserved 2?1 addr_mode addressing mode this bit field determines the addressing m ode for this cs, based on the type of dimm installed, according to table 11. this addres sing applies to the physical addressing on the maa and mab address buses. note that modes 00 and 11 are reserved . 0 cs_en chip-select enable when set, this bank is eligible for selection by incoming addresses. when clear, this bank?s chip select is not asserted and the values in [31:23] and [15:7] are ignored. table 11. AMD-761? dram addressing modes mode pins14131211109876543210 mode 1 addr_mode = 01 64 mbyte x4/8/16 128 mbyte x4/8/16 row 12 11 24 23 22 21 20 19 18 17 16 15 14 13 col 1211 27pc2625109876543 bk bk mode 2 addr_mode = 10 256 mbyte x4/8/16 512 mby te x4/8/16 row 12 11 25 24 23 22 21 20 19 18 17 16 15 14 13 col 12112928pc2726109876543 bk bk
chapter 2 AMD-761? system controller programmer?s interface 97 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 2.4.4 device 0, function 1: ddr pdl configuration registers the registers defined in this section are required to implement double data rate (ddr) dram in the AMD-761 system controller northbridge. the func tion 1 registers control the 18 ddr programmable delay lines (pdl). in table 12, the column entitled offset consists of the register number specified in the configuration address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. table 12. device 0, function 1 configuration register map ddr pdl registers (device 0, function 1) offset reference reserved 0x00 to 0x3f ddr pdl calibration control 0x40 to 0x43 ?dev0:f1:0x40? on page 98 ddr pdl configuration 0 0x44 to 0x47 ?dev0:f1:0x44? on page 101 ddr pdl configuration 1 0x48 to 0x4b ddr pdl configuration 2 0x4c to 0x4f ddr pdl configuration 3 0x50 to 0x53 ddr pdl configuration 4 0x54 to 0x57 ddr pdl configuration 5 0x58 to 0x5b ddr pdl configuration 6 0x5c to 0x5f ddr pdl configuration 7 0x60 to 0x63 ddr pdl configuration 8 0x64 to 0x67 ddr pdl configuration 9 0x68 to 0x6b ddr pdl configuration 10 0x6c to 0x6f ddr pdl configuration 11 0x70 to 0x73 ddr pdl configuration 12 0x74 to 0x77 ddr pdl configuration 13 0x78 to 0x7b ddr pdl configuration 14 0x7c to 0x7f ddr pdl configuration 15 0x80 to 0x83 ddr pdl configuration 16 0x84 to 0x87 ddr pdl configuration 17 0x88 to 0x8b ddr mdat/dqs pad configuration 0x8c to 0x8f ?dev0:f1:0x8c? on page 104 ddr clk/cs pad configuration 0x90 to 0x93 ?dev0:f1:0x90? on page 108 ddr cmdb/cmda pad configuration 0x94 to 0x97 ?dev0:f1:0x94? on page 111 ddr mab/maa pad configuration 0x98 to 0x9b ?dev0:f1:0x98? on page 114 reserved 0x9c to 0xff
98 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr pdl calibration control dev0:f1:0x40 register description this register allows bios control of the calibration circui t for the AMD-761? system controller?s 18 programmable delay lines. note that this register is not initialized at reset time but must be initialized by bios for proper operation. this action should be done prior to attempting dram access. 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit sw_recal use_act_dly auto_cal_en act_dly_inh reserved auto_cal_period resetxxxx00xx r/w r/w w r/w r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 99 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions ddr pdl calibration control (dev0:f1:0x40) bit name function 31?8 reserved reserved 7sw_recal software recalibration software should write a 1 to this bit to ca use recalibration of the pdls. the hardware recomputes the cal_delay values for all pdls, based on the values of their sw_cal_dly fields. status of the recalibration that was initiated by writing a 1 to this bit is also indicated in this bit. after setting this bit, software should poll this bit until it becomes a 0 again. 0 = calibration complete (default) 1 = calibration not complete if auto_cal_en is set, writes to this bit are ignored. also refer to table 13, ?pdl calibration modes,? on page 100. note: this bit should not be set if the system clock frequency is 66 mhz. 6 use_act_dly use actual delay software should set this bit to indicate to the hardware that it has written to the act_dly fields and wants to update the pdls (all 18) with the newly written act_delay values. software only needs to change th e act_delay values that are not currently at their desired values (the other act_dly values are simply re-applied). this method should be used only when sw_recal and auto_cal_en bits are not set. if auto_cal_en is set, writes to this bit are ignored. also refer to table 13, ?pdl calibration modes,? on page 100. this bit always returns a 0 when read. 5 auto_cal_en auto calibration mode 0 = auto-calibration mode off (default) 1 = auto-calibration mode on when this bit is set, all of the cal_dly values are recomputed periodically (according to the setting of the auto_cal_period field) for all pdls, based on the values of their sw_cal_dly fields. if the act_dly_inh bit is not set, the cal_dly values are also applied to the act_dly. also refer to table 13, ?pdl calibration modes,? on page 100. note: once auto_cal_en is set to 1, clearing it makes the bit a 0, but the auto-calibration logic may perform one more update, depending on when the auto_cal_en bit is cleared. therefore, bios should at least wait for the amount of time specified by the auto_cal_period field after clearing the auto_cal_en bit before attempting to change any of the pdl parameters. note: this bit should not be set if the system clock frequency is 66 mhz.
100 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes note that this register is not initialized at reset time, but must be initialized by bios for proper operation. this action should be done prior to attempting dram access. see table 13 for pdl calibration modes. 4 act_dly_inh actual delay update inhibit this bit configures the hardware to either update the actual pdls (act_dly values) with new cal_delay values or not. the setting of this bit affects both auto-calibration and swcalibration but not the use_act_dly method. after an exit from power-on reset or self- refresh, the setting of this bit determines whether the act_dly value is updated or not. 0 = update all the pdls with new cal_dly values in hardware after recomputation is done (default). 1 = do not update the actual pdl delay values after recomputation of cal_dly is done. note: the internal logic tests this bit just prior to updating the act_dly, so the other bits in this register should be taken in to consideration when writing to this bit. 3?2 reserved reserved 1?0 auto_cal_period auto-calibration period this bit field defines how often auto-calibration is performed. 00 = 10000 system clocks 01 = 1000000 system clocks 10 = 10000000 system clocks 11 = reserved bios should configure this field before setting the auto_cal_en bit, and while auto_cal_en is set, do not write to this field. table 13. pdl calibration modes auto_cal_en use_act_delay sw_recal resultant operation 000no action. 0 0 1 sw_cal_dly values are applied. 0 1 0 act_dly values are applied. 0 1 1 illegal combination (do not use). 1xx sw_cal_dly values are applied according to the auto_cal_period setting. do not set the act_dly or sw_recal bits. bit definitions (continued) ddr pdl calibration control (dev0:f1:0x40) bit name function
chapter 2 AMD-761? system controller programmer?s interface 101 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information table 14. ddr pdl configuration register locations ddr pdl configuration register 0 dev0:f1:0x44 ddr pdl configuration register 1 dev0:f1:0x48 ddr pdl configuration register 2 dev0:f1:0x4c ddr pdl configuration register 3 dev0:f1:0x50 ddr pdl configuration register 4 dev0:f1:0x54 ddr pdl configuration register 5 dev0:f1:0x58 ddr pdl configuration register 6 dev0:f1:0x5c ddr pdl configuration register 7 dev0:f1:0x60 ddr pdl configuration register 8 dev0:f1:0x64 ddr pdl configuration register 9 dev0:f1:0x68 ddr pdl configuration register 10 dev0:f1:0x6c ddr pdl configuration register 11 dev0:f1:0x70 ddr pdl configuration register 12 dev0:f1:0x74 ddr pdl configuration register 13 dev0:f1:0x78 ddr pdl configuration register 14 dev0:f1:0x7c ddr pdl configuration register 15 dev0:f1:0x80 ddr pdl configuration register 16 dev0:f1:0x84 ddr pdl configuration register 17 dev0:f1:0x88
102 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr pdl configuration registers register description these registers allow configuration of programmable delay lines 0?17. there are a total of 18 pdls (one per ddr dqs pin in x4 mode). note that these registers are not initialized at reset time, but must be initialized by bios for proper operation. th is action should be done prior to attempting dram access, and a software initiated calibration should be forced. 31 30 29 28 27 26 25 24 bit clk_dly resetxxxxxxxx r/w r 23 22 21 20 19 18 17 16 bit sw_cal_dly resetxxxxxxxx r/w r/w 15 14 13 12 11 10 9 8 bit cal_dly resetxxxxxxxx r/w r 7 6 5 4 3 2 1 0 bit act_dly resetxxxxxxxx r/w r/w
chapter 2 AMD-761? system controller programmer?s interface 103 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes note that these registers are not initialized at reset time, bu t must be initialized by bios for proper operation. this action should be done prior to attempting dram access, and a software-initiated calibration should be forced. bit definitions ddr pdl configuration registers 0?17 (dev0:f1:0x44?0x8b) bit name function 31?24 clk_dly clock delay this field provides the number of buffers that amount to one half-period of the system clock. note: upon exit from self-refresh, this bit field is updated with the number of buffers required to equal one half-period of the sy stem clock. the value of this field depends on the operating pvt point. this field is also updated when a recalibration is done either due to auto_cal_en or sw_recal. 23?16 sw_cal_dly software calibration delay this bit field represents the amount of dela y that is required for the corresponding dqs. the typical value is 0x69 for 100-mhz ddr operation, or 0x6b for 133 mhz. this field is used to calculate the cal_dly value during ex it from self-refresh, auto-calibration, and software-initiated recalibration. this field mu st be configured before setting the sw_recal bit or the auto_cal_en bit, and while these bi ts are set, this field must not be written. bios writes a desired value into this field if the default dqs delays are not the desired dqs delays for any reason. the value written in this field should be 256 times the required delay as a percentage of the half-period of the system clock, and then rounded off to the nearest integer. for example, if the desired dqs delay is 43.5 pe rcent of the system clock?s half-period, the value written into this field should be 0.434 x 256 = 111 (0x6f). note: this bit field should not be used if the system clock frequency is 66 mhz. 15?8 cal_dly calibration delay this bit field provides the last cal_dly value in number of buffers. note: upon exit from self-refresh, this bit field is updated with the number of buffers required to equal the time specified by the sw_cal_dly field. the value of this field depends on the operating pvt point. this field is also updated when a recalibration is done either due to auto_cal_en or sw_recal. 7?0 act_dly actual delay this bit field provides the current act_dly value (in number of buffers) that is in effect for the corresponding pdl. software can read the current value of act_dly from this field. software can write the desired number of buffer delays into this field. software typically writes to this field only if auto-calibration is disabled. after writing to this field, software should also set the use_act_dly bit in the pdl calibration control register. upon writes to this field, the new value takes effect at the first available ?safe? time after the use_act_dly bit is set. note: upon exit from self-refresh, this bit field is updated with the number of buffers required to equal the time specified by the sw_cal_dly field. the value of this field depends on the operating pvt point. this field is also updated when a recalibration is done either due to auto_cal_en or sw_recal (unless the act_dly_inh bit in the pdl calibration register is set). note: values written directly by software to this field are not pvt-independent, so this field is primarily for lab and debug use.
104 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr dqs/mdat pad configuration dev0:f1:0x8c register description this register allows bios control of the ddr dqs and memory data pad drive strength and slew rate. 31 30 29 28 27 26 25 24 bit reserved pslewmdat nslewmdat reset00xxxxxx r/w r r/w 23 22 21 20 19 18 17 16 bit reserved pdrvmdat ndrvmdat reset0000xxxx r/w r r/w 15 14 13 12 11 10 9 8 bit reserved pslewdqs nslewdqs reset00xxxxxx r/w r r/w 7 6 5 4 3 2 1 0 bit reserved pdrvdqs ndrvdqs reset0000xxxx r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 105 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions ddr dqs/mdat pad configuration (dev0:f1:0x8c) bit name function 31?30 reserved reserved 29?27 pslewmdat mdat rising edge slew rate these bits control the rising edge slew rate of the mdat[63:0] and dm[8:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) note that the dm[8:0] pins are controlled by the pslewdqs field when any chip select is configured for x4 dimms in the dram mode/status register (dev 0:f0:0x58). 26?24 nslewmdat mdat falling edge slew rate these bits control the falling edge slew rate of the mdat[63:0] and dm[8:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) note that the dm[8:0] pins are controlled by the nslewdqs field when any chip select is configured for x4 dimms in the dram mode/status register (dev 0:f0:0x58). 23?20 reserved reserved 19?18 pdrvmdat mdat p transistor drive strength these bits control the p transistor drive strength of the mdat[63:0] and dm[8:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) note that the dm[8:0] pins are controlled by the pdrvdqs field when any chip select is configured for x4 dimms in the dram mode/status register (dev 0:f0:0x58).
106 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 17?16 ndrvmdat mdat n transistor drive strength these bits control the n transistor drive strength of the mdat[63:0] and dm[8:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) note that the dm[8:0] pins are controlled by the ndrvdqs field when any chip select is configured for x4 dimms in the dram mode/status register (dev 0:f0:0x58). 15?14 reserved reserved 13?11 pslewdqs dqs rising edge slew rate these bits control the rising edge slew rate of the dqs[8:0] pins (and dm[8:0] pins) when any chip select is configured for x4 di mms in the dram mode/status register at dev 0:f0:0x58). 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 10?8 nslewdqs dqs falling edge slew rate these bits control the falling edge slew rate of the dqs[8:0] pins (and dm[8:0] pins) when any chip select is configured for x4 di mms in the dram mode/status register at dev 0:f0:0x58). 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 7?4 reserved reserved bit definitions (continued) ddr dqs/mdat pad configuration (dev0:f1:0x8c) bit name function
chapter 2 AMD-761? system controller programmer?s interface 107 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes 3?2 pdrvdqs dqs p transistor drive strength these bits control the p transistor drive strength of the dqs[8:0] pins (and dm[8:0] pins) when any chip select is configured for x4 dimms in the dram mode/status register at dev 0:f0:0x58). 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 1?0 ndrvdqs dqs n transistor drive strength these bits control the n transistor drive stre ngth of the dqs[8:0] pins (and dm[8:0] pins) when any chip select is configured for x4 dimms in the dram mode/status register at dev 0:f0:0x58). 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) bit definitions (continued) ddr dqs/mdat pad configuration (dev0:f1:0x8c) bit name function
108 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr clk/cs pad configuration dev0:f1:0x90 register description this register allows bios control of the ddr clocks and chip-selects pad drive strength and slew rate. 31 30 29 28 27 26 25 24 bit reserved pslewclk nslewclk reset00xxxxxx r/w r r/w 23 22 21 20 19 18 17 16 bit reserved pdrvclk ndrvclk reset0000xxxx r/w r r/w 15 14 13 12 11 10 9 8 bit reserved pslewcs nslewcs reset00xxxxxx r/w r r/w 7 6 5 4 3 2 1 0 bit reserved pdrvcs ndrvcs reset0000xxxx r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 109 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions ddr clk/cs pad configuration (dev0:f1:0x90) bit name function 31?30 reserved reserved 29?27 pslewclk clocks rising edge slew rate these bits control the rising edge slew rate of the clkout[5:0] and clkout[5:0]# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 26?24 nslewclk clocks falling edge slew rate these bits control the falling edge slew rate of the clkout[5:0] and clkout[5:0]# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 23?20 reserved reserved 19?18 pdrvclk clocks p transistor drive strength these bits control the p transistor drive strength of the clkout[5:0] and clkout[5:0]# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 17?16 ndrvclk clocks n transistor drive strength these bits control the n transistor drive strength of the clkout[5:0] and clkout[5:0]# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 15?14 reserved reserved
110 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes 13?11 pslewcs cs rising edge slew rate these bits control the rising edge slew rate of the cs[7:0]# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 10?8 nslewcs cs falling edge slew rate these bits control the falling edge slew rate of the cs[7:0]# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 7?4 reserved reserved 3?2 pdrvcs cs p transistor drive strength these bits control the p transistor drive strength of the cs[7:0]# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 1?0 ndrvcs cs n transistor drive strength these bits control the n transistor dr ive strength of the cs[7:0]# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) bit definitions (continued) ddr clk/cs pad configuration (dev0:f1:0x90) bit name function
chapter 2 AMD-761? system controller programmer?s interface 111 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information ddr cmdb/cmda pad configuration dev0:f1:0x94 register description this register allows bios control of the ddr rasa#, rasb#, casa#, casb#, wea#, web#, ckea#, and ckeb# pad drive strength and slew rate. 31 30 29 28 27 26 25 24 bit reserved pslewcmdb nslewcmdb reset00xxxxxx r/w r r/w 23 22 21 20 19 18 17 16 bit reserved pdrvcmdb ndrvcmdb reset0000xxxx r/w r r/w 15 14 13 12 11 10 9 8 bit reserved pslewcmda nslewcmda reset00xxxxxx r/w r r/w 7 6 5 4 3 2 1 0 bit reserved pdrvcmda ndrvcmda reset0000xxxx r/w r r/w
112 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions ddr cmdb/cmda pad configuration (dev0:f1:0x94) bit name function 31?30 reserved reserved 29?27 pslewcmdb command b rising edge slew rate these bits control the rising edge slew rate of the rasb#, casb#, web#, and ckeb# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 26?24 nslewcmdb command b falling edge slew rate these bits control the falling edge slew rate of the rasb#, casb#, web#, and ckeb# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 23?20 reserved reserved 19?18 pdrvcmdb command b p transistor drive strength these bits control the p transistor drive strength of the rasb#, casb#, web#, and ckeb# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 17?16 ndrvcmdb command b n transistor drive strength these bits control the n transistor drive strength of the rasb#, casb#, web#, and ckeb# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 15?14 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 113 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes 13?11 pslewcmda command a rising edge slew rate these bits control the rising edge slew rate of the rasa#, casa#, wea#, and ckea# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 10?8 nslewcmda command a falling edge slew rate these bits control the falling edge slew rate of the rasa#, casa#, wea#, and ckea# pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 7?4 reserved reserved 3?2 pdrvcmda command a p transistor drive strength these bits control the p transistor drive strength of the rasa#, casa#, wea#, and ckea# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 1?0 ndrvcmda command a n transistor drive strength these bits control the n transistor drive strength of the rasa#, casa#, wea#, and ckea# pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) bit definitions (continued) ddr cmdb/cmda pad configuration (dev0:f1:0x94) bit name function
114 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information ddr mab/maa pad configuration dev0:f1:0x98 register description this register allows bios control of the ddr maa and mab address bus pad drive strength and slew rate. 31 30 29 28 27 26 25 24 bit reserved pslewmab nslewmab reset00xxxxxx r/w r r/w 23 22 21 20 19 18 17 16 bit reserved pdrvmab ndrvmab reset0000xxxx r/w r r/w 15 14 13 12 11 10 9 8 bit reserved pslewmaa nslewmaa reset00xxxxxx r/w r r/w 7 6 5 4 3 2 1 0 bit reserved pdrvmaa ndrvmaa reset0000xxxx r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 115 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions ddr mab/maa pad configuration (dev0:f1:0x98) bit name function 31?30 reserved reserved 29?27 pslewmab mab rising edge slew rate these bits control the rising edge slew rate of the mab[14:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 26?24 nslewmab mab falling edge slew rate these bits control the falling edge slew rate of the mab[14:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 23?20 reserved reserved 19?18 pdrvmab mab p transistor drive strength these bits control the p transistor dr ive strength of the mab[14:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 17?16 ndrvmab mab n transistor drive strength these bits control the n transistor drive strength of the mab[14:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 15?14 reserved reserved
116 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes 13?11 pslewmaa maa rising edge slew rate these bits control the rising edge slew rate of the maa[14:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 10?8 nslewmaa maa falling edge slew rate these bits control the falling edge slew rate of the maa[14:0] pins. 000 = slew rate 0 (slowest) 001 = slew rate 1 010 = slew rate 2 011 = slew rate 3 100 = slew rate 4 101 = slew rate 5 110 = slew rate 6 111 = slew rate 7 (fastest) 7?4 reserved reserved 3?2 pdrvmaa maa p transistor drive strength these bits control the p transistor dr ive strength of the maa[14:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) 1?0 ndrvmaa maa n transistor drive strength these bits control the n transistor drive strength of the maa[14:0] pins. 00 = drive strength 0 (weakest) 01 = drive strength 1 10 = drive strength 2 11 = drive strength 3 (strongest) bit definitions (continued) ddr mab/maa pad configuration (dev0:f1:0x98) bit name function
chapter 2 AMD-761? system controller programmer?s interface 117 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 2.4.5 device 1: pci-to-pci bridge configuration registers the registers defined in this section are required to implement the pci-to-pci bridge function (device 1) in the AMD-761 system controller northbridge. in table 15, the column entitled offset consists of the register number specified in the configuration address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. table 15. device 1 configuration register map pci-to-pci bridge (device 1) offset reference device id vendor id 0x00 ?dev1:0x00? on page 118 status command 0x04 ?dev1:0x04? on page 120 class code0x0600 revision id 0x08 ?dev1:0x08? on page 123 reserved header type primary latency timer reserved 0x0c ?dev1:0x0c? on page 124 reserved 0x10 to 0x17 seclatency time subordinate bus num secondary bus num primary bus num 0x18 ?dev1:0x18? on page 125 secondary status i/o limit i/o base 0x1c ?dev1:0x1c? on page 127 memory limit memory base 0x20 ?dev1:0x20? on page 130 prefetchable memory limit prefetchable memory base 0x24 ?dev1:0x24? on page 132 reserved 0x28 to 0x2f i/o limit upper 16 bits i/o base upper 16 bits 0x30 ?dev1:0x30? on page 134 reserved reserved 0x34 to 0x3b bridge control interrupt pin interrupt line 0x3c ?dev1:0x3c? on page 135 miscellaneous device 1 control 0x40 ?dev1:0x40? on page 137 reserved 0x44 to 0xff
118 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci id dev1:0x00 register description 31 30 29 28 27 26 25 24 bit dev_id reset01110000 r/w r 23 22 21 20 19 18 17 16 bit dev_id reset00001111 r/w r 15 14 13 12 11 10 9 8 bit vend_id reset00010000 r/w r 7 6 5 4 3 2 1 0 bit vend_id reset00100010 r/w r
chapter 2 AMD-761? system controller programmer?s interface 119 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions agp/pci id (dev1:0x00) bit name function 31?16 dev_id device identifier this 16-bit register is assigned by the de vice manufacturer and identifies the type of device. the current northbridge device id assignments are: AMD-761? system controller ? amd athlon? processor, 1p ddr 133 mhz 0x700e host to pci bridge 0x700f pci-to-pci bridge (4x agp) amd-762? system controller ? amd athlon processor, 2p ddr 133 mhz 0x700c host to pci bridge 0x700d pci-to-pci bridge (4x agp) amd-751? system controller ? amd athlon processor, 1p sdram-100 0x7006 host to pci bridge 0x7007 pci-to-pci bridge (1x/2x agp) 15?0 vend_id vendor identifier this 16-bit register identifies the manufacturer of the device.
120 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci command and status dev1:0x04 register description the agp/pci command and status register provides coar se control over the pci-pci bridge function within the AMD-761? system controller. this register controls the ab ility to generate and respond to pci cycles on both the agp bus and the pci bus. 31 30 29 28 27 26 25 24 bit perr_rcv serr_rcv mas_abrt trgt_abrt trgt_abrts _signaled devsel_timing data_perr reset00000010 r/w r r/w1c r 23 22 21 20 19 18 17 16 bit fast_b2b udf 66m cap_lst reserved reset00100000 r/w r 15 14 13 12 11 10 9 8 bit reserved fback serr reset00000000 r/w r r/w 7 6 5 4 3 2 1 0 bit step perr vga mwinv scyc mstr mem i/o reset00000000 r/w r r/w
chapter 2 AMD-761? system controller programmer?s interface 121 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions agp/pci command and status (dev1:0x04) bit name function 31 perr_rcv detected parity error this bit is always low because the AMD-761? system controller does not support parity checking. 30 serr_rcv signaled system error this bit is set whenever the AMD-761 system controller received agp serr# and subsequently asserted pci serr#. this bit is cleared by writing a 1. refer to table 7 on page 34 for details about serr# assertion and status. 29 mas_abrt received master abort this bit is always 0. 28 trgt_abrt receive target abort this bit is always 0. 27 trgt_abrts _signaled signaled target abort this bit is always 0. 26?25 devsel_timing devsel# timing this field is always 0b01, indicating that the AMD-761 system controller supports medium devsel# timing. 24 data_perr data perr# this bit is always 0 because the AMD-761 system controller does not report data parity errors. 23 fast_b2b fast back-to-back capable this bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. 22 udf user-definable features this bit is always 0, indicating that udf is not supported on the AMD-761 system controller. 21 66m 66-mhz capable this bit is always 1, indicating that the AMD-761 system controller supports 66 mhz on device 1. 20 cap_lst capabilities list this bit is always 0, indicating that the c onfiguration space of this device does not support a capabilities list. 19?10 reserved reserved 9fback fast back-to-back to different devices enable this bit is always 0, because the AMD-761 system controller does not allow generation of fast back-to-back transactions to different agents.
122 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes 8 serr system error enable when set, this bit enables the serr# out put. when clear, this bit disables the serr# output. the agp a_serr# is an input to the AMD-761? system controller. the AMD-761 system controller receives agp a_serr#, ors it with the normal pci serr#, and asserts it to the amd-766? peripheral bus controller for possible error interrupt generation. refer to table 7 on page 34 for details about serr# assertion and status. 7 step address stepping this bit is always 0 because the AMD-761 system controller does not perform address stepping. 6perr parity error response this bit is always 0 because the AMD-761 system controller does not report data parity errors. 5vga vga palette snoop enable this bit is always 0, indicating that the AMD-761 system controller does not snoop the vga palette address range. 4mwinv memory write and invalidate enable this bit is always 0 because the amd-76 1 system controller does not generate memory write and invalidate commands. 3scyc special cycle this bit is always 0 because the AMD-761 system controller ignores pci special cycles. 2 mstr bus master enable when this bit is set, the AMD-761 system controller accepts dma accesses from the agp interface. 1mem memory access enable when set, the AMD-761 system controller forwards amd athlon? processor system bus accesses that reference agp memory space onto the agp bus (see ?dev1:0x20? on page 130). 0i/o i/o access enable when set, the AMD-761 system controller forw ards cpu accesses that reference agp i/o space onto the agp bus (see ?dev1:0x1c? on page 127). bit definitions (continued) agp/pci command and status (dev1:0x04) bit name function
chapter 2 AMD-761? system controller programmer?s interface 123 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp/pci revision id and class code dev1:0x08 register description programming notes 31 30 29 28 27 26 25 24 bit class_code reset00000110 r/w r 23 22 21 20 19 18 17 16 bit sub-class_code reset00000100 r/w r 15 14 13 12 11 10 9 8 bit prog_i/f reset00000000 r/w r 7 6 5 4 3 2 1 0 bit rev_id reset00000000 r/w r bit definitions agp/pci revision id and class code (dev1:0x08) bit name function 31?24 class_code class code this field is always 06h, indicati ng that it is a bridge device. 23?16 sub-class_code sub-class code this field is always 04h for sub-class code and 00h for prog. i/f, indicating it is a pci/pci bridge. 15?8 prog_i/f program interface this field is always 00h, indicating that it is a pci-to-pci bridge. 7?0 rev_id revision id this field contains an 8-bit value identifying the revision number of the device.
124 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci header type dev1:0x0c register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit header_type reset00000001 r/w r 15 14 13 12 11 10 9 8 bit pri_lat_timer reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit reserved reset00000000 r/w r bit definitions agp/pci header type (dev1:0x0c) bit name function 31?24 reserved reserved 23?16 header_type header type bit 23 is always 0, indicating that the AMD-761? system controller is a single function device. bits 22:16 are 0x01, indicating that type 01 configuration space header format is supported (pci-to-pci bridge). 15?8 pri_lat_timer primary latency timer this latency timer is not used in the amd- 761 system controller because the primary bus of the pci-to-pci bridge is internal. this regi ster is read/write to maintain compliance with the pci specifications. 7?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 125 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp/pci sub bus number/secondary latency timer dev1:0x18 register description 31 30 29 28 27 26 25 24 bit secon_lat_timer reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit sub-bus_num reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit secon_bus_num reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit pri_bus_num reset00000000 r/w r/w
126 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes the agp bus is logically a sub-bus of the pci bus. th e pci bus normally enumerat es as bus 0 and the agp bus enumerates as bus 1. bit definitions agp/pci sub bus number/secondary latency timer (dev1:0x18) bit name function 31?24 secon_lat_timer secondary latency timer adheres to the definition of the latency timer in the pci local bus specification , revision 2.2, but only applies to the secondary interface of a pci-to-pci bridge. 23?16 sub-bus_num sub-bus number this bit field records the number of the highest numbered pci bus that is behind (or subordinate to) a bridge. the bridge uses th is number in conjunction with the secondary bus number register to determine when to respond to type 1 configuration transactions on the primary interface and to pass them on to the secondary interface. 15?8 secon_bus_num secondary bus number this bit field records the number of the pci bus that the secondary interface of the bridge is connected to. the bridge uses this number to determine when to respond to type 1 configuration transactions on the primary interface and to convert them to type 0 transactions on the secondary interface. 7?0 pri_bus_num primary bus number this bit field records the number of the pci bus that the primary interface of the bridge is connected to. the bridge uses this number to decode type 1 configuration transactions on the secondary interface that should be converted to special cycle transactions on the primary interface.
chapter 2 AMD-761? system controller programmer?s interface 127 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp/pci status, i/o base and limit dev1:0x1c register description the secondary status register reflects the conditions of the secondary pci-to-pci bridge interface (the agp bus). the i/o base register defines the bottom (inclusive) of an address ran ge that is used by the bridge to determine when to forward i/o transactions from one interface to the other. the i/o limi t register defines the top (inclusive) of an address range that is used by the bridge to determine when to forward i/o transactions from one interface to the other. 31 30 29 28 27 26 25 24 bit perr_rcv serr_rcv mas_abrt trgt_abrt trgt_abrts _signaled devsel_timing data_perr reset00000010 r/w r r/w1c r 23 22 21 20 19 18 17 16 bit fast_b2b udf 66m cap_lst reserved reset00100000 r/w r 15 14 13 12 11 10 9 8 bit io_lim[15:12] io_lim_r reset00000001 r/w r/w r 7 6 5 4 3 2 1 0 bit io_base[15:12] io_base_r reset00000001 r/w r/w r
128 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions agp/pci status, i/o base and limit (dev1:0x1c) bit name function 31 perr_rcv detected parity error this bit is always low because the am d-761? system controller does not support parity checking. 30 serr_rcv signaled system error this bit is set whenever the AMD-761 system controller received agp serr#. this bit is cleared by writing a 1. refer to table 7 on page 34 for details about serr# assertion and status. 29 mas_abrt received master abort this bit is set by the AMD-761 system c ontroller whenever a bus master transaction (except for a special cycle) is terminated due to a master abort. this bit is cleared by writing a 1. 28 trgt_abrt receive target abort this bit is set by the AMD-761 system controller whenever a bus master transaction (except for a special cycle) is terminated due to a target abort. this bit is cleared by writing a 1. 27 trgt_abrts _signaled signaled target abort this bit is always 0 because the AMD-761 system controller does not terminate transactions with target aborts. 26?25 devsel_timing devsel# timing this field is always 0x1, indicating that the AMD-761 system controller supports medium devsel# timing. 24 data_perr data perr# this bit is always 0 because the AMD-761 system controller does not report data parity errors. 23 fast_b2b fast back-to-back capable this bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. 22 udf user-definable features this bit is always 0, indicating that udf is not supported on the AMD-761 system controller. 21 66m 66-mhz capable this bit is always 1, indicating that the AMD-761 system controller supports 66 mhz on device 1. 20 cap_lst capabilities list this bit is always 0, indicating that the c onfiguration space of this device does not support a capabilities list. 19?16 reserved reserved 15?12 io_lim[15:12] i/o limit (write) this bit field indicates the upper writable 4 bi ts that define the top address of an address range that is used by the bridge to determin e when to forward i/o transactions from one interface to the other. 11?8 io_lim_r i/o limit (read) the lower read-only 4 bits define the top address of an address range that is used by the bridge to determine when to forward i/o transa ctions from one interface to the other. 0x1 indicates that 32-bit i/o address decoding is available.
chapter 2 AMD-761? system controller programmer?s interface 129 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes 7?4 io_base[15:12] i/o base (write) the upper writable 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward i/o transactions from one interface to the other. 3?0 io_base_r i/o base (read) the lower read-only 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward i/o tr ansactions from one interface to the other. 0x1 indicates that 32-bit i/o address decoding is available. bit definitions (continued) agp/pci status, i/o base and limit (dev1:0x1c) bit name function
130 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci memory limit and base dev1:0x20 register description 31 30 29 28 27 26 25 24 bit mlim[31:20] reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit mlim[31:20] reserved reset00000000 r/w r/w r 15 14 13 12 11 10 9 8 bit mbase[31:20] reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit mbase[31:20] reserved reset00000000 r/w r/w r
chapter 2 AMD-761? system controller programmer?s interface 131 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes bit definitions agp/pci memory limit and base (dev1:0x20) bit name function 31?20 mlim[31:20] memory limit address memory limit address defines the top addres s of the non-prefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. the lowe r 20 bits of address are assumed to be 0xfffff. the memory address range adheres to 1-mbyte alignment and granularity. 19?16 reserved reserved 15?4 mbase[31:20] memory base address memory base address defines the base addr ess of the non-prefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. bits [1 5:4] correspond to address bits [31:20]. the lower 20 bits of the address are assumed to be 0. the memory address range adheres to 1-mbyte alignment and granularity. 3?0 reserved reserved
132 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci prefetchable memory limit and base dev1:0x24 register description 31 30 29 28 27 26 25 24 bit prefet_mem_lim reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit prefet_mem_lim reserved reset00000000 r/w r/w r 15 14 13 12 11 10 9 8 bit prefet_mem_base reset00000000 r/w r/w 7 6 5 4 3 2 1 0 bit prefet_mem_base reserved reset00000000 r/w r/w r
chapter 2 AMD-761? system controller programmer?s interface 133 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information bit definitions programming notes bit definitions agp/pci prefetchable memory limit and base (dev1:0x24) bit name function 31?20 prefet_mem_lim prefetchable memory limit address prefetchable memory limit address defines th e top address of the prefetchable address range used by the agp target (graphics cont roller) where control registers and fifo-like communication interfaces are mapped. the lowe r 20 bits of address are assumed to be 0xfffff. the memory address range adheres to 1-mbyte alignment and granularity. 19?16 reserved reserved 15?4 prefet_mem_base prefetchable memory base address prefetchable memory base address defines th e base address of the prefetchable address range used by the agp target (graphics cont roller) where control registers and fifo-like communication interfaces are mapped. bits [1 5:4] correspond to address bits [31:20]. the lower 20 bits of the address are assumed to be 0. the memory address range adheres to 1-mbyte alignment and granularity. 3?0 reserved reserved
134 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information agp/pci i/o limit and base upper 16 bits dev1:0x30 register description this set of registers define the valid range of 32-bit i/o addr esses that are allowed to be forwarded from the host to the agp/pci. note that if this register is 0, 32 -bit addressing mode is effectively disabled. programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit i/o_lim[23:16] reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit i/o_base[23:16] reset00000000 r/w r/w bit definitions agp/pci i/o limit and base upper 16 bits (dev1:0x30) bit name function 31?24 reserved reserved 23?16 i/o_lim[23:16] i/o limit this field defines the upper limit (inclusive) of 24-bit i/o addresses that are passed to the agp/pci bus. 15?8 reserved reserved 7?0 i/o_base[23:16] i/o base this field defines the base (inclusive) of 24-bit i/o addresses that are passed to the agp/pci bus.
chapter 2 AMD-761? system controller programmer?s interface 135 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information agp/pci interrupt and bridge control dev1:0x3c register description 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit bridge_fast _b2b_en secon_bus _reset mas_abort _mode reserved vga_en isa_en serr_en par_resp_en reset00000000 r/w r r/w r 15 14 13 12 11 10 9 8 bit int_pin reset00000000 r/w r/w (see note) 7 6 5 4 3 2 1 0 bit int_line reset00000000 r/w r/w bit definitions agp/pci interrupt and bridge control (dev1:0x3c) bit name function 31?24 reserved reserved 23 bridge_fast_ b2b_en fast back-to-back capable this bit is always 0, indicating that the AMD-761? system controller as a master is not capable of generating fast back-to-back transactions to different agents on the secondary bus. 22 secon_bus_reset secondary bus reset this bit is always 0. reset for the secondary interface is done with the pcirst# output of the amd-766? peripheral bus controller. 21 mas_abort_mode master abort mode this bit is always 0. the response to a master abort is determined by the rd_data_err_dis bit, dev0:f0:0x84 bit 12.
136 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes 20 reserved reserved 19 vga_en vga enable affects the response by the bridge to compatible vga addresses. when it is set, the bridge decodes and forwards the following accesses on the primary interface to the secondary interface. memory accesses in the range: 0xa0000 to 0xbffff i/o address where ad[9:0] are in the ranges: 0x3b0 to 0x3bb and 0x3c0 to 0x3df (inclusive of isa address aliases ? ad[15:10] are not decoded) 18 isa_en isa enable modifies the response by the bridge to isa i/o addresses. this modification applies only to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kbytes of pci i/o address space (0000 0000h to 0000 ffffh). when set, the bridge blocks any forwarding from primary to seconda ry of i/o transactions addressing the last 768 bytes in each 1-kbyte block. in the opposite direction (secondary to primary), i/o transactions are forwarded if they address the last 768 bytes in each 1-kbyte block. 0 = forward all i/o addresses in the address range defined by the i/o base and i/o limit registers. 1 = block forwarding of isa i/o addresses in the address range defined by the i/o base & i/o limit registers that are in the first 64 kbytes of pci i/o address space (top 768 bytes of each 1-kbyte block). 17 serr_en serr enable forwards the secondary interface serr# assertions to the primary interface. this bit must be set, along with the serr enable bit (d ev 1:f0:0x04) to allow an agp serr# to be propagated to the AMD-761? system controller pci serr# pin. refer to table 7 on page 34 for details about serr# assertion and status. 16 par_resp_en parity response enable this bit is always 0. the AMD-761 system controller does not support parity. 15?8 int_pin interrupt pin indicates which interrupt pin the pci-to-pci bridge uses. note: this field is r/w depending on the value of the intpincntl bit (bit 0 of dev 1:0x40). refer to ?dev1:0x40? on page 137 for details. the ability to write this field is supported to allow bios to program to the required value. the AMD-761 system controller hardware does not use this field internally in any way. 7?0 int_line interrupt line communicates interrupt line routing information. this field is a simple r/w field to allow bios software to program to the required value. bit definitions (continued) agp/pci interrupt and bridge control (dev1:0x3c) bit name function
chapter 2 AMD-761? system controller programmer?s interface 137 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information miscellaneous device 1 control dev1:0x40 register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit reserved int_pin_cntl reset00000000 r/w r r/w bit definitions miscellaneous device 1 control (dev1:0x40) bit name function 31?1 reserved reserved 0 int_pin_cntl interrupt pin control this bit controls the intpin field in agp/pci interrupt and bridge control register (dev1:0x3c). 0 = intpin field is read-only. 1 = intpin field is read-writable for bios initialization.
138 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.5 memory-mapped registers the AMD-761 system controller implements a set of memory- mapped control registers as show n in section 2.5.2 on page 140. the base for these registers is defined in bar1 (see ?dev0:f0:0x14? on page 39). this address is determined and loaded by system bios. the registers in the space are used by the AMD-761 miniport driver to control the gart cache functionality during run time. 2.5.1 AMD-761? system controller gart cache overview this section provides a brief overview for programmers. the graphics address relocation table (gart) is a structure in memory that contains mappings from a virtual address generated by an agp master (or any other master in the system including pci masters and the cpu) and the actual physical address of a given request. the default mode used by the AMD-761 gart cache is a two-level directory/table indexing scheme that is very similar to the standard x86 virtual memory architecture. by using two levels of indexing, the gart structure does not need to be physically contiguous. figure 4 on page 139 illustrates the two-level indexing scheme.
chapter 2 AMD-761? system controller programmer?s interface 139 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information figure 4. two-level gart indexing physical memory gart directory directory entry 1 directory entry 2 1k table entries 1k table entries gart table directory cache table cache 16 entries fully associative 8 entries fully associative northbridge gart base address register points here (dev0:bar1: 0x04). AMD-761? system controller
140 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2.5.2 memory-mapped register map for registers that are accessed by the AMD-761 system controller miniport driver during run time, the AMD-761 system controller implements a set of memory-mapped registers for quick access. th ese are defined in table 16. bar1 initialization note that bios must program the base address 1:gart memory mapped register base register (dev 0:f0:0x14) prior to accessing the memory-mapped registers. refer to ?dev0:f0:0x14? on page 39 for details of this register. table 16. AMD-761? system controller memory-mapped registers gart memory-mapped control registers offset from bar1 reference feature status feature control capabilities revision id 0x00 ?bar1 + 0x00? on page 141 gart base address 0x04 ?bar1 + 0x04? on page 144 gart cache size 0x08 ?bar1 + 0x08? on page 145 gart cache control 0x0c ?bar1 + 0x0c? on page 146 gart cache entry control 0x10 ?bar1 + 0x10? on page 147
chapter 2 AMD-761? system controller programmer?s interface 141 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information features and capabilities bar1 + 0x00 register description 31 30 29 28 27 26 25 24 bit reserved valid_bit_err_id p2p_status gart_cache _status reserved valid_err reset00000000 r/w r r/w1c 23 22 21 20 19 18 17 16 bit reserved p2p_en tlb_en sb_stb_tog _det gar_valid_ err_en reset00000000 r/w r r/w 15 14 13 12 11 10 9 8 bit reserved hang_en p2p_cap link_cap valid_cap reset00000001 r/w r r/w r 7 6 5 4 3 2 1 0 bit rev_id reset00000001 r/w r
142 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information bit definitions features and capabilities (bar1 + 0x00) bit name function 31?30 reserved reserved 29?28 valid_bit_err_id valid bit error id these bits are used to determine the source of the valid bit error. the values are as follow: 00 = agp 01 = cpu 10 = pci/agp?s pci 11 = reserved 27 p2p_status p2p status this bit is hardwired to 0 to indicate that the AMD-761? system controller implements only those pci-to-pci bridge commands required to implement agp (the AMD-761 system controller does not implement a complete pci 2.1-compliant pci-to-pci bridge between pci and agp). 26 gart_cache _status gart cache status 0 = gart cache disabled 1 = gart cache enabled by software 25 reserved reserved 24 valid_err valid bit error when set, this bit indicates that a valid bit error has been detected and serr# has been asserted. refer to table 7 on page 34 for details about serr# assertion and status. this bit is cleared by writing a 1. 23?20 reserved reserved 19 p2p_en p2p enable this bit is hardwired to 0 to indicate that the AMD-761 system controller only implements those pci-to-pci bridge commands required to implement agp (the AMD-761 system controller does not implement a complete pci 2.1-compliant pci-to-pci bridge between pci and agp). 18 tlb_en tlb enable when set, this bit enables th e caching of gart tlb entries. 17 sb_stb_tog _det_dis sideband strobe toggle detect disable when set, this bit disables the agp sideband strobe toggle detect logic. 16 gar_valid_err _en gart valid error enable when set, the AMD-761 system controller asserts serr# when a graphics device attempts to access a page in agp memory that is not valid (valid bit error). a valid bit error causes the gart table walk state machine to hang. the processor can still access memory after that if it does not use gart address space. refer to table 7 on page 34 for details about serr# assertion and status. 15?12 reserved reserved 11 hang_en hang enable when set, illegal gart entries fetched by the gtw logic forces the AMD-761 system controller to hang.
chapter 2 AMD-761? system controller programmer?s interface 143 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information programming notes 10 p2p_cap p2pcap this bit is hardwired to 0 to indicate that the AMD-761? system controller implements only those pci-to-pci bridge commands required to implement agp (the AMD-761 system controller does not implement a complete pci 2.1-compliant pci-to-pci bridge between pci and agp). 9link_cap linkcap this bit is always low, indicating that gart entry multiple pages are not supported. 8 valid_cap valcap this bit is set to indicate that the AMD-761 system controller supports the detection of valid bit errors. 7?0 rev_id revision id this field contains the revision identification. bit definitions (continued) features and capabilities (bar1 + 0x00) bit name function
144 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information gart directory base address bar1 + 0x04 register description programming notes 31 30 29 28 27 26 25 24 bit gart_dir_base_addr reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit gart_dir_base_addr reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit gart_dir_base_addr reserved reset00000000 r/w r/w r 7 6 5 4 3 2 1 0 bit reserved reset00000000 r/w r bit definitions gart directory base address (bar1 + 0x04) bit name function 31?12 gart_dir_base _addr gart directory base address these bits define the base address of the gart directory that is located in physical system memory. these 20 bits correspond to the 20 most significant bits of the 32-bit gart directory base address that is aligned on a 4-kbyte page boundary. twenty bits provide 4-kbyte resolution, which is the minimum allowa ble size of the gart. a value other than 0 defines a valid base address. 11?0 reserved reserved
chapter 2 AMD-761? system controller programmer?s interface 145 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information gart cache size bar1 + 0x08 register description programming notes 31 30 29 28 27 26 25 24 bit gart_cache_size reset00000000 r/w r 23 22 21 20 19 18 17 16 bit gart_cache_size reset00000000 r/w r 15 14 13 12 11 10 9 8 bit gart_cache_size reset00000000 r/w r 7 6 5 4 3 2 1 0 bit gart_cache_size reset00010000 r/w r bit definitions gart cache size (bar1 + 0x08) bit name function 31?0 gart_cache_size gart cache size the AMD-761? system controller implements a gart table cache that contains 16 entries, organized as eight-way set associative.
146 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information gart cache control bar1 + 0x0c register description programming notes 31 30 29 28 27 26 25 24 bit reserved reset00000000 r/w r 23 22 21 20 19 18 17 16 bit reserved reset00000000 r/w r 15 14 13 12 11 10 9 8 bit reserved reset00000000 r/w r 7 6 5 4 3 2 1 0 bit reserved gart_cache _inval reset00010000 r/w r r/w1s bit definitions gart cache control (bar1 + 0x0c) bit name function 31?1 reserved reserved 0 gart_cache _inval gart cache invalidate this bit is written by the AMD-761? miniport driver. when set to 1, the AMD-761 system controller invalidates the entire gart directory and table cache. when the invalidate operation is completed, the AMD-761 system controller resets this bit to 0.
chapter 2 AMD-761? system controller programmer?s interface 147 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information gart table cache entry control bar1 + 0x10 register description this register must be written to with doubleword (32-bit or 4-byte) operands. 31 30 29 28 27 26 25 24 bit gart_tbl_entry_addr reset00000000 r/w r/w 23 22 21 20 19 18 17 16 bit gart_tbl_entry_addr reset00000000 r/w r/w 15 14 13 12 11 10 9 8 bit gart_tbl_entry_addr reserved reset00000000 r/w r/w r 7 6 5 4 3 2 1 0 bit reserved tbl_update tbl_inval _entry reset00000000 r/w r r/w1s
148 AMD-761? system controller programmer?s interface chapter 2 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information programming notes bit definitions gart table cache entry control (bar1 + 0x10) bit name function 31?12 gart_tbl_entry _addr gart table entry address these bits define the page address for the particular gart table entry to be invalidated or updated. when a page address is written to this register by the AMD-761? miniport driver, the referenced gart table cache entry is invalidated or updated based on the value in bits [1:0] as long as it is within the virtua l address space. if the page address is outside of the virtual address space, then the in validate/update instructions do nothing. 11?2 reserved reserved 1 tbl_update table update when set, this bit forces the AMD-761 system controller to update the gart table cache entry specified in bits [31:12] with the curren t entry in the gart table in system memory. the update function is performed immediately following the write to this register. when the update operation is completed, this bit is reset to 0. 0 tbl_inval_entry table invalidate entry when set, this bit forces the AMD-761 system controller to invalidate the gart table cache entry specified in bits [31:12] if it is pres ent in the gart cache. the invalidate function is performed immediately following the write to this register. when the invalidate operation is completed, this bit is reset to 0. note that this bit does not affect the gart directory cache.
chapter 3 ddr sdram interface 149 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 3 ddr sdram interface this chapter details bios configuration as it pertains to the AMD-761? system controller ddr sdram controller. the topics discussed in this chapter are entitled as follows: ddr dimms and ddr sdrams on page 150 ddr speed grades on page 150 ddr dimm data from serial presence detect (spd) device on page 151 memory space config uration on page 152 ddr memory dimm timings on page 157 additional memory controller settings on page 161 dram mode/status settings on page 165 ecc and memory scrubbing on page 169 programmable delay lines (pdl) on page 174 ddr i/o drive strength on page 182 3.1 overview to date, there are two types of ddr memory dimms? unbuffered and registered. the am d-761 system controller can be configured to support up to two unbuffered dimm slots with two banks each, or up to four registered dimm slots with two banks each. registered and unbuffered implementations cannot be intermixed. the AMD-761 system controller embeds the ddr sdram memory controller of the system. all programming registers that configure the memory controller reside in pci configuration space. this space is defined in bus 0, device 0, and exists in both function 0 and function 1. motherboard and northbridge characteristics are programmed from data provided by the respective designers and manufacturers. this data includes bus speed implementations, memory bus signal strengths and slew rates, and internal memory controller characteristics, etc.
150 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information dimm and memory device (memory chip) timing and configuration data exist in the serial presence detect (spd) eeprom on the dimm. 3.2 ddr dimms and ddr sdrams the following section discusses ddr dimms and ddr sdrams. 3.2.1 ddr speed grades ddr dimms adhere to an alternate naming convention associated with a corresponding data transfer rate. the data rate is a function of the clock speed of the memory subsystem, for example, 100-mhz clock or 133-mhz clock. two names, and their corresponding transfer rates, are currently defined and implemented: pc1600 pc2100 the pc1600 naming convention represents dimms with a data transfer rate of 1600 mbytes per second (1.6 gbytes per second). this data rate is calculated as follows: pc1600 data transfer rate = (100-mhz clock) x (2 data transfers/clock) x (8 bytes/transfer) pc1600 data transfer rate = 1600 mbytes per second similarly, the pc2100 designation represents dimms with a data rate of 2100 mbytes per second (2.1 gbytes per second). this data transfer rate is calculated as follows: pc2100 data transfer rate = (133-mhz clock) x (2 data transfers/clock) x (8 bytes/transfer) pc2100 data transfer rate = 2100 mbytes per second (rounded) note that the cas latency (cl) parameter of the device does not factor into the pc 1600 and pc2100 transfer rates calculated above. the cas latency setting is dependent on device frequency, which is used in the calculation of the transfer rates above. the cas latency values are ddr device-
chapter 3 ddr sdram interface 151 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information specific and based on the operating frequency of the device. the cas latency is specified as the initial latency (in clocks) required by the device before data is returned during a read access. in general, the higher the frequency, the larger the cas latency value. typical device cl parameters and their respective frequencies are shown in table 17. note: cas latency settings are valid only if an acceptable entry for the corresponding bus speed exists in spd byte 9 or 23. 3.2.2 ddr dimm data from serial presence detect (spd) device ddr memory systems implemented with the AMD-761 system controller require use of the serial presence detect (spd) data. this data describes configuration and speed characteristics of the ddr dimm and ddr sdram devices mounted on the dimm. the spd is a serial eeprom that physically exists on the di mm and is encoded by the dimm manufacturer. a description of this eeprom is usually provided on a data sheet for the dimm itself along with data describing the memory devices (chips) used. the data sheet should also contain the byte values for the dimm encoded in the spd on the dimm. the spd is accessed via the i 2 c bus implemented on the motherboard, normally via registers in a southbridge agent. su broutines to access spd data must be provided in the bios or other code that requires access. the i 2 c bus addresses the spd via a 7-bit address where convention dictates that memory dimms respond to an address range beginning with 0xa0. the second memory dimm responds to 0xa2 and so on. the i 2 c bus specification describes a 7-bit address. however, this scheme actually uses 8 bits. the 8th bit is actually bit 0. the scheme defines bit 0 as the read/write designation of the address. bit 0 equal to 0 means that the host is executing a write to the address. bit 0 equa l to 1 means that the host is executing a read from the address. reality then is that a1 addresses a read operation to dimm slot #0. a3 addresses a table 17. typical cl parameter settings for pc1600 and pc2100 designation cas latency (cl) setting ddr memory clock speed pc1600 2 100 mhz pc2100 2.5 133 m hz
152 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information read operation to dimm slot #1. a0 addresses a write operation to dimm slot #0. 3.3 memory space configuration a dimm may have one or two sides populated with ddr devices. the term bank refers to one logical side of the dimm memory. for the purpose of this document, each bank has a corresponding chip select. it is important to point out that double-sided dimms require two separate chip-select signals. therefore, for these types of dimms, two separate base address chip-select registers must be programmed. the size of each bank is read from spd, byte 31 . the number of banks on the dimm is read from spd byte 5. the AMD-761 system controller ddr sdram controller requires 21 bits of configuration information for each chip select?that is, each side of the dimm. these 21 bits are within a full 32-bit configuration register that contains 11 reserved bits. usage of the 32 bits is sh own in table 18 and explained in further detail below. as previously mentioned, a dimm socket may be single banked (containing one logical side of ddr sdram devices) or double banked (containing two logical sides of ddr sdram devices). the dimm socket may also be empty. if one bank is not present or if the socket is empty?that is, two banks not present?then their corresponding enable bit sh own in table 18 should be set to 0. it is important that the registers place the largest logical bank of memory in the lowest addr ess space and then progress in order to higher address space with the smaller sized banks. table 18. dimm bank address bit definition bit(s) bank n 0 1 = enable 0 = disable 2:1 address mode (modes 00 and 11 are reserved) 15:7 address mask ? size of this bank 31:23 base address ? starting address of this bank
chapter 3 ddr sdram interface 153 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information when the dimm socket sides ar e equally sized, the order of address space programming between them is not important. each side/row/bank of dram requires 4 bytes as previously stated. the patterns that satisfy the address mask and base address for various sizes of sides/rows/banks are shown in table 19 . the address mask and base address bits are presented as xxxx_xxxx_x to show correspondence with address lines. in practice, the 9 bits of address mask map to bank n, bits 15:7 and the 9 bits of base addres s map to bank n, bits 31:23. the minimum memory size or granularity for ddr is 32 mbytes. however, all base ad dress and address mask bits represent a granularity of 8 mbytes. the symmetry of the ddr device?that is, organization of storage elements rows and columns?dictates the addressing mode configuration. the specified addressing mode dictates the physical mapping of the memory address signals to the ddr device address signals. the addressing modes of the AMD-761 system controller memory controller map to industry- standard ddr device symmetries set forth by the joint electron device engineering co uncil (jedec). therefore, the addressing mode is set accord ing to the devices on the dimm. addr_mode => 01b for 64-mbit and 128-mbit drams addr_mode => 10b for 256-mbit and 512-mbit drams table 19. memory size addresses bank / row size address mask base address [address lines] [31:23] [31:23] 8 mbytes n/a 0000_0000_1 16 mbytes n/a 0000_0001_0 32 mbytes 0000_0001_1 0000_0010_0 64 mbytes 0000_0011_1 0000_0100_0 128 mbytes 0000_0111_1 0000_1000_0 256 mbytes 0000_1111_1 0001_0000_0 512 mbytes 0001_1111_1 0010_0000_0 1024 mbytes (1 gbyte) 0011_1111_1 0100_0000_0 2048 mbytes (2 gbytes) 0111_1111_1 1000_0000_0
154 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information note: modes 00b and 11b are reserved. to determine the size of the ddr sdram device from spd data, bios needs to read the size of the bank(s) in spd byte 31 and the device width in byte 13. ddr sdram widths are either 4, 8, or 16 for this im plementation. a 4-bit device width implies that 16 ddr sdram devices exist on a dimm for a 64-bit bus transfer. an 8-bit device width implies eight ddr sdram devices exist on a dimm for a 64-bit bus transfer, and a 16-bit width implies four ddr sdram devices exist on a dimm for the 64-bit bus transfer. the size of the bank can be deduced as: size of device(mbits) = size of bank x (sdram width) where the size of device is specified in mbits. dividing the size of device value by eight (8 ) yields the size of the bank in mbytes. if more than 4 gbytes of total memory are populated in the system, it is the responsibility of bios to configure and report only 4 gbytes to prevent a 4-gbyte wrap, which would result in aliasing. table 20 shows the total amount of memory with respect to ddr device density and width. note: this table assumes double sided dimms. note: total system maximum is 4 gbytes. note: shaded rows use x4 devices that are as registered dimms only. table 20. total memory width and density dimm 0dimm 1dimm 2dimm 3 x16 128 mbit 128 mbytes 256 mbytes 384 mbytes 512 mbytes x8 128 mbit 256 mbytes 512 mbytes 768 mbytes 1 gbytes x4 128 mbit 512 mby tes 1 gbytes 1.5 gbytes 2 gbytes x16 256 mbit 256 mbytes 512 mbytes 768 mbytes 1 gbytes x8 256 mbit 512 mbytes 1 gbytes 1 gbytes 2 gbytes x4 256 mbit 1 gbyte 2 gbytes 3 gbytes 4 gbytes x16 512 mbit 512 mbytes 1 gbytes 1.5 gbytes 2 gbytes x8 512 mbit 1 gbyte 2 gbytes 3 gbytes 4 gbytes x4 512 mbit 2 gbytes 4 gbytes
chapter 3 ddr sdram interface 155 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information this document assumes that b ios uses the spd to determine the total amount of memory in the system. this document does not specify a sizing algorithm other than utilizing the spd. base address chip select the base address chip select bits (dev 0:f0:0xc0, bits [31:23] through dev 0:f0:0xdf, bits [31:23]) specify the 8-mbytes boundary a given chip-s elect services. each of the eight chip selects [7:0] have an associated base address chip select register. incoming addresses are compared against the value programmed into the base address chip select register and also the address mask bits (dev 0:f0:0xc0, bits [15:7] through dev 0:f0:0xdf, bits [15:7]) of this register. address mask the address mask bits (dev 0:f0 :0xc0, bits [15:7] through dev 0:f0:0xdf, bits [15:7]) specif y which address bits to ignore when incoming addresses are compared to the base address chip select bits dev 0:f0:0xc 0, bits [31:23] through dev 0:f0:0xdf, bits [31:23]) defined in base address chip select. if a given bit is set in this register, its corresponding address bit in the address compare is ignored. address mode the address mode bits (dev 0:f0 :0xc0, bits [2:1] through dev 0:f0:0xdf, bits [2:1]) specify the memory address mapping. the address memory mapping is specific to the symmetry of the device and is shown in tabl e 21. as can be seen in this table, the maximum page width is 2 kbytes. this maximum width implies that a new internal bank is accessed on a 2-kbyte boundary. note that address mo des 00b and 11b are reserved, thus this field should never be specified. table 21. AMD-761? system controller ddr sdram addressing modes mode pins14 131211109876543210 mode 1 addr_mode=01 64mb x4/8/16 128mb x4/8/16 row 12 11 24 23 22 21 20 19 18 17 16 15 14 13 col 12 11 27pc2625109876543 bk bk mode 2 addr_mode=10 256mb x4/8/16 512mb x4/8/16 row 12 11 25 24 23 22 21 20 19 18 17 16 15 14 13 col 12 112928pc2726109876543 bk bk
156 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information chip select enable the chip select enable bit (dev 0:f0:0xc0, bit [0] through dev 0:f0:0xdf, bit [0]) specifies wh ether a bank of memory exists for that corresponding chip select. when enabled with a 1b, the incoming address is eligible to be compared with bits [31:23] and [15:7] for chip-select decode. a 0b in this field disables the associated chip select, thus the associated base address chip select and address mask fields are ignored. example: memory base address registers table 22 is an example of how to size the memory base register for a total of 128 mbytes using a two-bank dimm at 64 mbytes per bank. for the purpose of illustrating memory sizing, the bytes 0xc0? 0xdf are the relevant bytes. configuration bytes c0h, c1h, c2h, and c3h are for bank 0. byte c0h contains bits [7:0], c1h bits [15:8], etc. this example shows 64 mbytes in both banks 0. configuration bytes c4h, c5h, c6h, and c7h are for bank 1 bits c0h[7] and c1h[7:0] contain the address mask for 64 mbytes. bits c4h[7] and c5h[7: 0] contain the address mask for 64 mbytes. bit c0h[0] and bit c4h[0] signal bank enable. bit c2h[7] and bits c3h[7:0] set a base address of 0 mbyte for side/row/bank 0. bit c6h[7] and bits c7h[7:0] set a base address of 64 mbytes for side/row/bank 1. the total memory size is 128 mbytes . banks 2?7 are empty. the relevant bytes are set to 0. table 22. memory sizing example, 128 mbytes total registers ? bus:00 device:00 function:00 0123456789abcdef c 83030000830300040000000000000000 d00000000000000000000000000000000
chapter 3 ddr sdram interface 157 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information table 23 is an example on how to size the memory base register for a total of 320 mbytes using one-bank dimm at 64 mbytes per bank and a two-bank dimm at 128 mbytes per bank. 3.4 ddr memory dimm timings one of the most important changes from earlier sdram dimm technology is that conservative settings for cas latency (cl) are no longer valid?that is, when there is doubt that the dimm works using cl=2, falling ba ck to a setting of cl=3 is not an alternative as it was on single data rate devices. cas latency for a dimm must be set to a value described in the spd on the dimm. a dimm that is set to something other than a rated value in its spd cannot be expected to work and most likely will not work. industry standards for cl on ddr dimms are 1.5, 2.0, and 2.5. please notice that the amd-76 1 system controller supports cl=3.0 as the highest cl setting. some legacy ddr devices support cl=3.0, but most devices available today specify cl=2.5 as a maximum. the AMD-761 system controller does not support cl=1.5. 3.4.1 memory timings the AMD-761 system controller supports the following ddr device timing parameters: t cl , t rcd , t ras , t rp , t rc , t rrd , t wr , and t wtr . the t cl , t rcd , t ras , t rp , t rc , and t rrd timings are available from the spd. the data format of each byte is described in the application note published by ibm and other sources. matching this data to memory controller settings is a function of speed of the memory bus. examples of settings are developed for bus speeds of 100 mhz and 133 mhz. table 23. memory sizing example, 320 mbytes total registers ? bus:00 device:00 function:00 0123456789abcdef c 83030010000000008307000083070008 d00000000000000000000000000000000
158 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information cas latency cas latency values can occupy multiple bytes in the spd. cas latency is the only item governing dimm setup that has multiple values. table 24 shows cas latency settings. the two entries for supported cas latency(cl) represent different perfor mance potential. the smaller value for cl (2) would represent best performance. bios ca n choose from any legal cl that exists in the spd for the dimm. the AMD-761 system controller supports cl values of 2, 2.5, and 3. other timing values in the spd reflect minimum timings required, based on the correspo nding memory bus clock speed. bios must program the memory controller configuration with the correct timing values as specified by the ddr device. table 24. cas latency settings symbol name spd byte typical value description t cl cas latency 0x0x0x54[3:2] 9 max bus speed for cl=2.5 with AMD-761? system controller. 0 dimm does not support cl=2.5. 75h 75h equal 7.5 ns. this dimm can be used @ cl = 2.5 when bus speed is less than or equal to 133 mhz. a0h a0h equals 10 ns. this dimm can be used @ cl = 2.5 when bus speed is less than or equal to 100 mhz. 23 max bus speed for cl=2 with AMD-761? system controller. 0 dimm does not support cl=2. 75h 75h equal 7.5 ns. this dimm can be used @ cl = 2 when bus speed is less than or equal to 133 mhz. a0h a0h equals 10 ns. this dimm can be used @ cl = 2 when bus speed is less than or equal to 100 mhz. notes: 1. other values in byte 9 represent other maximum bus speeds for cl=2.5. should another speed occur, cl=2.5 cannot be used beyond its max for this dimm?that is, byte 9 = 80 means a maxi mum bus speed of 120 mhz. cl=2.5 can be used for a maximum bus speed of 100 mhz, but not for 133 mhz. 2. other values in byte 23 represent other maximum bus speeds for cl=2. should another speed occur, cl=2 cannot be used beyond its max for this dimm?that is, byte 23 = 80 means a maximu m bus speed of 120 mhz. cl=2 can be used for a maximum bus speed of 100 mhz, but not for 133 mhz.
chapter 3 ddr sdram interface 159 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information t rcd the ras to cas delay bits (dev 0:f0:0x54, bits [1:0]) specify the minimum amount of time required between the opening of a page within the ddr device (via an activate command) and the issuance of a read or write command to that same ddr device?s internal bank. this timing parameter is device- specific. byte 29 of the spd defines the t rcd timing parameter. refer to table 25 on page 160 for typical settings. t ras the row active bits (dev 0:f0:0x54, bits [6:4]) specify the minimum amount of time that a page within the ddr device (via an activate command) can remain opened within the same internal bank of the ddr device. this timing parameter is device-specific. byte 30 of the spd defines the t ras timing parameter. refer to table 25 on page 160 for typical settings. t rp the row precharge time bits (dev 0:f0:0x54, bits [8:7]) specify the minimum amount of time that the ddr device requires to precharge a row and is specified as the time between the precharge command and an activate command within the same internal bank of the ddr device. this timing parameter is ddr device-specific. byte 27 of the spd defines the t rp timing parameter. refer to table 25 on page 160 for typical settings. t rc the row cycle time bits (dev 0:f0:0x54, bits [11:9]) specify the minimum amount of time th at the ddr device requires between activate commands within the same internal bank of the ddr device. this timing parameter is ddr device- specific. in short, this requirement specifies the minimum amount of time that the same internal bank can recycle row accesses. byte 41 of the spd defines the t rc timing parameter. (note that t rc is new to the spd and vo ted in at th e september 2000 jedec meeting.) historically, t rc was defined as t ras + t rp , but this algorithm is not recommended when the spd information is available. refer to table 25 on page 160 for typical settings. t rrd the bank to bank activate time bit (dev 0:f0:0x54, bit [23]) specifies the minimum amount of time that the same ddr device can receive back-to-ba ck activate commands, even to different internal banks. this timing parameter is ddr device- specific. device manufacturers specify the t rrd parameter to limit current surges within the device, based on row activate activity, because row activates require a large amount of
160 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information current. byte 28 of the spd defines the t rrd timing parameter. refer to table 25 on page 160 for typical settings. write recovery the write recovery bits (dev 0:f0:0x54, bit [25:24]) specify the minimum amount of time that must occur from the last write command to a precharge command to the same internal bank of the ddr device. this device timing parameter is not specified in the spd, but the recommended setting is 10b and specifies two system clock cycles between a write command and a precharge command to the same internal bank. refer to table 25 on page 160 for typical settings. write to read the write to read bit (dev 0:f0:0x54, bit [26]) specifies the minimum amount of time that must occur between the last write command to a following read command to the same internal bank of the ddr device. this device timing parameter is not specified in the spd, but the recommended setting is 1b and specifies two system clock cycles. refer to table 25 on page 160 for typical settings. table 25. ddr device timing values symbol name spd byte typical value description t rcd minimum ras to cas delay 0x0x0x54[1:0] 29 50h has 2-bit fraction?see spd definitions. 50h = 20 ns. 2 cycles @100 mhz, 3 @ 133 mhz. t ras minimum active to precharge time 0x0x0x54[6:4] 30 32h integer value. 50-ns require- ment. 5 cycles @ 100 mhz, 7 @ 133 mhz. t rp minimum row precharge time 0x0x0x54[8:7] 27 50h has 2-bit fraction?see spd definitions. 50h = 20 ns. 2 cycles @100 mhz, 3 @ 133 mhz. t rc bank cycle time 0x0x0x54[11:9] 41 typically defined as t ras + t rp. spd entry available soon. 7 cycles @ 100 mhz, 10 @133 mhz. t rrd minimum row active to row active delay 0x0x0x54[23] 28 3ch has 2-bit fraction?see spd definitions. 3ch = 15 ns. 2 cycles @100 mhz and 133 m hz. t wr minimum write to precharge time n/a n/a t wtr minimum write to read time n/a n/a
chapter 3 ddr sdram interface 161 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information example configurations are shown in table 26. 3.5 additional memory controller settings this section discusses configurat ion features that are specific to the AMD-761 system controller ddr memory controller. the AMD-761 memory controller contains ddr memory controller settings starting at (dev 0:f0:0x54). these settings are page hit limit, idle cycle limit, registered dimm enable device control (used in this register to specify registered versus unbuffered dimm), read wait state timing control, selectable hold time for the ddr address and command buses (selectable per address and command bus a and b), and a selectable wait state for super bypass control. page hit limit the page hit limit bits (dev 0:f0:0x54, bits [15:14]) specify the number of consecutive page hit requests that are processed by the AMD-761 dram controller before choosing a non-page hit request. this fe ature is designed to reduce starvation (a pending request not fulfilled for an extended period of time) due to a flood of consecutive page hit requests. typically, consecutive page hits yield the best ddr dram page performance for those requesting devices (such as the cpu or pci device, etc.). however, starvation of a request because it is a non-page-hit request does not constitute a fair system memory access policy. when the number of consecutive page hits across all internal ddr device internal banks of a given chip select equals the value specified in these bits, the ddr controller arbiter gives priority to a ddr memory request that is not a page hit. it was determined that eight cons ecutive page hit accesses is table 26. dev 0:f0:0x54 bit examples cl dimm dev 0:f0:0x54 57 56 55 54 2 100 mhz unbuffered 16 01 88 b5 2 100 mhz registered 7e 01 88 b5 2.5 133 mhz unbuffered 96 01 8c 4a 2.5 133 mhz registered f6 01 8e 5a
162 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information adequate to give fair access to the memory sub-system. therefore, these bits should be set to 10b. a higher page hit limit allows the prioritization of a large amount of consecutive page hits, if available, whereas a lower page hit limit would allow for a greater chance of page interruption should there be an otherwise large amount of page hit requests. refer to table 27 on page 165 for typical settings. idle cycle limit the idle cycle limit bits (dev 0:f0:0x54, bits [18:16]) specify the number of system clocks before the memory controller issues a precharge all command to the currently active chip select. this feature is used to tune system performance by closing open pages during periods of memory request inactivity. the idle cycle limit logic does not have any logical indication of page conflicts or bank misses and simply counts the number of system clocks of memory request inactivity. this feature takes advantage of the lack of temporal locality, where a page left open for a specified amount of time is less likely to be accessed again. therefore, it is more advantageous to precharge the page and incur the page miss overhead rather than the overhead associated with a page conflict. analysis shows that eight idle clocks is an adequate amount of system clocks to wait for a following request to the memory sub-system. therefore, these bits should be set to 001b for best performance. a higher idle cycl e limit allows a greater chance for a following request to ac cess an open page. however, temporal locality states that the greater amount of time between accesses reduces the chance of a hit to the open page. a lower idle cycle limit decreases the window of following memory access to utilize an op en page. a lower idle cycle limit results in a greater chance of page interruption should there be an otherwise large amount of page hit requests. refer to table 27 on page 165 for typical settings. registered dimm enable the registered dimm enable bit (dev 0:f0:0x54, bits [27]) specifies whether the ddr dimm sockets are populated with registered or unbuffered dimm mo dules. this bit is set to 1b by bios if the dimm sockets are populated with ddr- registered dimm modules. the AMD-761 system controllerAMD-761 system controller memory controller does not support the mixing of registered and unbuffered ddr modules in the same system. the system must be populated
chapter 3 ddr sdram interface 163 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information with either all registered or all unbuffered ddr modules. refer to table 27 on page 165 for typical settings. read wait state the read wait state bit (dev 0:f0:0x54, bits [28]) specifies whether more time is needed in the ddr read data round trip loop. the read data round trip loop originates at the AMD-761 system controller ddr clk outp uts and terminates at the AMD-761 system controller intern al requester logic. because all ddr read data is returned with its corresponding dqs signal, read data is captured at the memory controller interface in the dqs clock domain. this data is then held and crosses into the core requester clock domain. however, because of the physical dimm placement on the motherboard, large round trip delays the response ti me of the ddr devices, and AMD-761 system controller internal delays may be long enough that an additional wait state must be added to compensate for the delay. when this bit is set to a 1b, the data captured in the dqs clock domain is transferred to a register array that is within the core logic clock domain and physically exists at the pads of the AMD-761 system controller ddr interface. when this bit is set to a 1b, the data is delayed to the requester by one additional system clock period. because the read wait state bit is related to the full read data round trip and may imply that the read data and dqs are being returned from a far dimm, when the read wait state bit is set to 1b, one additional clock cycle is placed between read followed by write cycles to prevent data and dqs overlap when accessing a far dimm for read data and followed immediately by a write cycle. because of motherboard timing analysis and AMD-761 system controller timing analysis, it is recommended that this bit be set for 100-mhz and 133-mhz operation. refer to table 27 on page 165 for typical settings. address timing for copy-b the address timing for copy-b bit (dev 0:f0:0x54, bit [29]) specifies additional hold time for the address and command bus b. when this bit is set to 1b, the memory address bus (mab[14:0]), rasb#, casb#, web#, ckeb, and cs[7:6 and 3:2]# is delayed an additional 350 ps (best case) and 600 ps (worst case) to provide additional hold time to the ddr device. this bit should be set by bios when registered dimms are installed and set to 0b when unbuffered dimms are installed.
164 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information this bit assumes a bus and b chip-select dimm socket mapping is such that the b bus uses chip select bit [7:6] and [3:2]. this motherboard mapping should be adhered to should bios want to control the a bus and b bus hold timing separately. refer to table 27 on page 165 for typical settings. address timing for copy-a the address timing for copy-a bit (dev 0:f0:0x54, bit [30]) specifies additional hold time for the address and command bus a. when this bit is set to 1b, the memory address bus (maa[14:0]), rasa#, casa#, wea#, ckea, and cs[5:4 and 1:0]# is delayed an additional 350 ps (best case) and 600 ps (worst case) to provide additional hold time to the ddr device. this bit should be set by bios when registered dimms are installed and set to 0b when unbuffered dimms are installed. this bit assumes a bus and b chip-select dimm socket mapping is such that the b bus uses chip select bit [5:4] and [1:0]. this motherboard mapping should be adhered to should bios want to control the a bus and b bus hold timing separately. refer to table 27 on page 165 for typical settings. super bypass wait state the super bypass wait state bit (dev 0:f0:0x54, bit [31]) specifies an additional one system clock wait state for super bypass requests, when set to 1b. a super bypass cycle is a low- latency request to ddr memory from the bus interface unit when all reordering queues are empty. this super bypass cycle allows direct access to ddr memory. for internal timing reasons, this bit must be set for 133-mhz operation. this bit should be set to 0b for 100-mhz operation or below. refer to table 27 for typical settings.
chapter 3 ddr sdram interface 165 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 3.6 dram mode/status settings the AMD-761 system controller memory controller contains additional ddr memory controll er settings starting at (dev 0:f0:0x58). these settings are: x4 ddr device symmetry configuration, refresh control (which includes refresh rate, refresh disable, and burst refresh enable), suspend to ram (str) control, ddr device initialization control, and AMD-761 system controller ddr clock output control. chip-select width the sdram chip-select width bits (dev 0:f0:0x58, bits [7:0]) are used to indicate ddr device data widths installed for the corresponding chip se lect. the AMD-761 system controller can differentiate between x4 or x8/x16 banks by bios setting a corresponding bit for the chip select in this register. a bit should be set to 1b to represent a x4 bank or set to 0b to represent a x8/x16 bank. the x8 and x16 devices use one dqs data strobe per byte, whereas a x4 device uses one dqs data strobe per nibble (4-bit). because the AMD-761 system controller dram controller uses the data mask (d m) signals as dqs data strobes during data transfers to x4 devices, the dram controller uses these bits to determine the func tion for the dm signals. the table 27. system related timings name 0x0x0x54 bit(s) typical setting description page hit limit 15:14 10b 8 cycles idle cycle limit 18:16 001b 8 cycles registered dimm enable 27 x 0 for unbuffered 1 for registered read wait state 28 1 always set address timing for copy-b 29 x 0 for unbuffered 1 for registered address timing for copy-a 30 x 0 for unbuffered 1 for registered super bypass wait state 31 x 0 < 133 mhz 1 @ 133 mhz
166 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information AMD-761 system controller provid es a data width selection for each chip select, although it is unlikely that a double banked dimm can support x4 devices on one side and x8/x16 devices on the other. however, this resolution is provided to allow chip- select signal routing flexibility on the motherb oard should the same dimm socket not use neighboring chip-select wiring. the spd byte 13 provides ddr device data width information and can be used to set these bits accordingly. sdram initialization the sdram initialization bit (d ev 0:f0:0x58, bit [25]), when written to a 1b, initiates the ddr device initialization sequence. however, as mentione d below, the suspend to ram bits (dev 0:f0:0x58, bits [22: 21]) must be written to a 01b in order for the initialization sequence to occur. the bios should first initialize the ddr timing control registers and drive strength registers prior to setting this bit. this bit remains set after the initialization sequenc e has completed. status as to the completion of the initialization sequence can be provided by polling the mode register st atus (dev 0:f0:0x58, bit [23]) but only after setting the mode register status bit. this procedure is described below. the sdram initialization bit is reset to 0b during a suspend to ram because a system reset is issued in this case. mode register status the mode register bit (dev 0:f0:0x58, bit [23]), when written with a 1b, is used to initiate a load mode register command to the ddr devices. the load mode register command programs the cas latency of the device, burst length, and burst order. the burst length and burst order are fixed to a burst of eight and the device is programmed for interleaved mode. however, the cas latency is configurable via the cas latency bit. bios must set the cas latency bit to its correct value (defined by ddr devices specification and operating frequency) before the mode register bit is set. this bit is then cleared by the AMD-761 system controller memory controller after the load mode register cycle is issued to the ddr devices. therefore, after setting this bit, bios shou ld poll this bit until it becomes 0b to verify that the load mode register command has been applied to the ddr device s before continuing. the recommended method is to set this bit (after already initializing the cas latency bit) when writing to this register to set bits [22:21] of this register to a 01b and bit 25 of this register to a 1b. because the ddr initialization has priority
chapter 3 ddr sdram interface 167 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information over the application of the load mode register command and the load mode register command is the last command applied in the ddr initialization, this bit can be polled to prove status as to when the entire ddr initialization is complete. suspend to ram control the suspend to ram bits (dev 0: f0:0x58, bits [22:21]) are used by bios to communicate the power-up sequence to the AMD-761 system controller. the bios usage of the suspen d to ram control bits are defined in the power management section (see section 4.4.1 on page 191). burst refresh enable the burst refresh bit (dev 0:f0:0x58, bit [20]) allows the AMD-761 system controller to sk ip refreshes that are queued, until the maximum number (four) is reached. burst refresh support is a performance enhancement that prevents refresh requests from interfering with memory requests. refresh requests that would have interfered with memory requests would normally stall the memory accesses or interfere with the open page policy by prematurely closing pages due to the refres h. when burst refresh is enabled and the burst queue is beginning to fill up, the dram controller treats the refresh queue requests as an urgent priority. refresh disable the refresh disable bit (dev 0:f0:0x58, bit [19]) allows the disabling of refresh cycles for debug purposes only. this bit is not reset during a system reset and it is therefore the responsibility of bios to write this bit to a 0 to enable refresh cycles. cycles per refresh the cycles per refresh bits (dev 0:f0:0x58, bits [17:16]) provide a setting to specify the ddr refresh rate. the refresh rate is tied directly to the clock frequency, thus it is important for bios to configure the refresh rate based on the AMD-761 system controller frequency. bios should first determine the AMD-761 system controller operating frequency by reading (dev 0:f0:0x58, bits [21:20]) a nd setting these bits according to table 28 below. the refresh rate should not be configured slower than that specified by any of the ddr devices installed. (each dimm installed may have a different refresh requirement, so it is important to choose the refresh rate that satisfies the least common denominator for all dimms.)
168 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information dimm clock disable the dimm clock disable bits (dev 0:f0:0x58, bits [31:26]) provide a way to individually disable the six differential ddr clock pairs provided for the ddr dimms. after bios memory sizing, these bits can be used to disable clocks to empty ddr dimm slots. the setting of a bit disables the corresponding clock pair. each clock pair is connected according to the motherboard layout for regist ered or unbuffered dimms. refer to the appropriate motherboard schematic to verify ddr clock dimm mapping to a particular dimm slot. with a system hard reset, these bits are cleared, thus enabling all clock pairs. because an AMD-761 system controller system reset is issued during a power-ma naged s3 state, all clocks are re-enabled following the exit from this state. therefore, bios should return to this register and restore the disabled clock pairs that it had previously disabled during post. note: ddr clocks are automatically disabled during the s3 power- managed state when unbuffered dimms are installed but continue running an additional six clocks when registered dimms are installed. table 28. refresh rate value 66 mhz 100 mhz 133 mhz 00 30.72 s 20.48 s 15.36 s 01 23.04 s 15.36 s11.52 s 10 15.36 s 10.24 s 7.68 s 11 7.68 s 7.68 s 3.84 s
chapter 3 ddr sdram interface 169 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 3.7 ecc and memory scrubbing the AMD-761 system controller ddr sdram controller supports error correcting code (ecc) and memory scrubbing. the error correction capability allows the correction of single- bit errors and the detection of multiple-bit errors in any memory quadword. data is only checked by the memory controller during a read access. a data error may be due to a faulted bit in the ddr device itself, or a faulted bit that occurred during data transmissions from the ddr devices to the AMD-761 system controller memory controller. to support the ecc function, dimms must s upport additional storage for the ecc check bits. when ecc is enabled, the system must have all ddr dimms that are 72 bits wide (also called ecc ddr dimms). the AMD-761 system controller ddr sdram controller provides five ecc modes. all ecc modes work correctly with either unbuffered or registered ddr dimms. the five modes supported are: ecc disabled high-performance ec mode (ec_hiperf mode)?error checking only, no correction, except to the amd athlon? processor high-performance ecc mode (ecc_hiperf mode)?error checking and correction ecc with scrubbing (ecc_scrub mode)?error checking and correction with scrubbing diagnostic ecc mode (ecc_diag) each mode is discussed below. the ecc check bits that are stored in the additional ddr devices on the dimm are generated by the memory controller (based on a hamming code algorithm) and written into the dimms check bit storage during a memory write operation when any ecc function is enabled. a single byte of check bits represents the associated quadword of data that is written into memory. when any ecc mode is enabled and a read access is performed, the memory controller internally generates check bits based on the data value r ead (for each quadword of data read) and compares it with the check bits read along with the
170 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information data from the check bit storage of the dimms. if the generated value does not match the check bit value, then both values are used to detect the number of bi ts that contain errors and the bit positions that contain errors. if only a single-bit error is detected, the generated check bits and the read check bits are used to correct the bit and pass the corrected data back to the requester that requested the read data. this single-bit error is signalled for system status. a read requester may be either the amd athlon? processor, pci, agp, apc, or gart. the detection of more than a single -bit error signals a multiple-bit system error and this data is not corrected. when any of the AMD-761 system controller ecc features are enabled, all ddr dimms installed must support ecc and all memory locations must be written to (initialized) prior to system operation to generate check bit values that match the data written for every location of memory. it is the responsibility of the bios to initialize all memory locations prior to any ecc function being enabled. the additional logic to support the ecc function is costly in both silicon real estate and sy stem timing. in the ecc modes that support data correction, one additional system clock must be used to generate the correc ted data. however, because the amd athlon processor checks for its own errors, data is passed directly through the AMD-761 system controller without an additional system clock delay. the detailed implementation of error detection and correction differs dependent on whether th e read or write is from the processor or pci, apc, agp, or gart and whether the write is a full quadword or less than a full quadword in size. the processor generates ecc for all full quadword writes and checks and corrects (if necessary) on all reads. for processor, pci, apc, agp, or gart partial quadword writes, the memory system performs a read-modify-write operation by reading the existing memory location, correcting the memory data if necessary, merging in the modified bytes, generating new ecc, and writing the new value to memory. a read-modify-write operation is used only for all partial quadword writes. the data read from memory during a read-modify-write operation is checked and corrected before the merge/write operation. a detailed operation is furt her described in table 29 on page 171.
chapter 3 ddr sdram interface 171 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information memory scrubbing not only corrects single-bit errors to the requesters and detects multiple-bit errors, but also writes the corrected single-bit error value back into memory when this feature is enabled. refer to ?ecc_mode? on page 172 for more information regarding the memory scrubbing feature and configuration. in addition to the status bits and chip-select identification, the AMD-761 system controller allows single-bit and/or multiple- bit errors to optionally asse rt serr# to allow monitoring, logging, and analysis of ecc errors by software. syseccen bit should be set in the amd ath lon processor when setting "report ecc syndrome case." syseccen has an msr address of msr c001_0010[15]. table 29. AMD-761? system controller ecc behavior (with ecc enabled) operation ecc generated by: ecc checked by: sbes 1 corrected by: amd athlon? processor system bus read dram AMD-761? sys- tem controller and amd athlon processor amd athlon processor amd athlon processor system bus full quadword writes amd athlon processor none none amd athlon processor system bus partial quadword writes AMD-761 system controller rmw on each qw AMD-761 system controller 2 AMD-761 system controller 2 pci/apci/gart 3 read dram AMD-761 system controller AMD-761 system controller pci/apci/gart 3 full quadword writes AMD-761 system controller none none pci/apci/gart 3 partial quadword writes AMD-761 system controller rmw on each qw AMD-761 system controller 2 AMD-761 system controller 2 notes: 1. single-bit error (sbe). 2. the data read from memory is checked and corrected before the merge/write. 3. apci =alternate pci on agp interface. 4. the scrubbing circuit detects, corrects read errors, and writes the corrected data to memory.
172 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 3.7.1 ecc and memory s crubbing configuration serr_enable the system error enable bits (dev 0:f0:0x48, bits [15:14]) control the AMD-761 system controller reporting of ecc errors to the system via the serr# pi n on the pci bus. note that serr# assertion is still subject to the normal pci serr# enable (dev 0:f0:0x04, bit [8]). error reporting options are as follow: 00 = serr# assertion disabled x1 = multiple bit errors force serr# assertion 1x = single bit errors force serr# assertion ecc_diag the error correcting code diagnostic mode enable (dev 0:f0:0x48, bit [12]) provides a way to purposely corrupt the ecc check bits. when this mode is enabled, the AMD-761 system controller always writes 0x00h to the ecc check bit byte. during partial writes, th e rmw sequence still occurs, but the ecc bits are always written to 0x00. this bit is useful for logic testing and ecc driver development. a check bit value of 0x00 is a valid check bit code, so care should be used to not corrupt a location where the user does not expect this valid check bit value to exist. in the ecc_diag mode, the AMD-761 system controller always writes 0x00 to the ecc byte to aid testing of the ecc logic. for reads, the ecc circuitry is unaffected by the ecc_diag bit. the ecc code returned from memory is checked, and errors are reported in the ecc_status bits as usual. correction is not performed in this mode to pci, agp, apc, or gart. however, as mentioned earlier, because the AMD-761 system controller simply passes ecc and read data information directly to the amd athlon processor, the processor may correct this data if this feature is enabled in the processor. ecc_mode the error correcting code mode bits enable a specific ecc mode. these fields can be us ed in the following cases: disable ecc checking. in this mode, ecc is neither generated nor maintained in the memory, and correction is not performed. this mode is intended for memory systems that are only 64 bits in width. enable ecc error checking mode only where data is still checked and errors are still reported, but data destined for the pci or apci/gart is not corrected. this approach
chapter 3 ddr sdram interface 17 3 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information provides the benefit of detectin g an error but does not incur the one clock penalty that is necessary for data correction for data destined for the pci or agp. data and ecc check bits are still passed from the ddr devices to the amd athlon processor, which pe rforms its own data error detection and correction. therefore, data correction to the amd athlon processor is not inhibited in this mode. this mode provides all the benefits of parity checking with little or no performance impact. it is useful in systems that desire status information but not the overhead that is associated with error correcting or scrubbing. a system can transition between the ec_hiperf mode, ecc_hiperf mode, and ecc_scrub mode dynamically, thereby getting the desired benefits of each mode as needed. enable ecc error checking and correction mode. data destined for the pci or apci/gart is corrected but at the expense of one clock cycle. as always, data and ecc check bits are still passed from the ddr devices to the amd athlon processor, which pe rforms its own data error detection. the AMD-761 system controller provides a high- performance ecc mode (ecc_hiperf) that provides all the data integrity benefits of ecc but without the overhead of scrubbing. in this mode, ecc is written into memory during writes (partial writes result in a rmw sequence), and correction is performed on reads. ecc checking is performed and the status indicators provide valid information regarding errors. this mode is useful in systems that need status information and data integr ity but not the overhead that is associated with scrubbing. a system can transition between the ec_hiperf mode, ecc_hiperf mode, and ecc_scrub mode dynamically, thereby attaining the desired benefits of each mode as needed. enable ecc_scrub mode wh ere error checking, data correction, and memory scrubbing are enabled. memory scrubbing corrects a detected single-bit error in the ddr memory. when a single-bit error is detected, additional cycle overhead is associated with correcting the single-bit error in memory. ecc with scrubbing (ecc_scrub) mode is the ecc mode of highest reliability. in ecc_scrub mode, ecc is written into memory during writes (partial writes result in a rmw sequence), an d corrected data is provided to the pci/apci/gart on reads. the AMD-761 system controller checks the ecc returned from memory and sets
174 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information the ecc status indicators. in addition, the controller also corrects any single-bit errors in memory. ecc_status the error correcting code status bits indicate the status of the ecc detect logic as follows: 00 = no error x1 = med: multi-bit error detect 1x = sed: single-bit error detect the ecc status bits and corr esponding failing chip-select indicators (see bits below) are set by the first error detected of each type (sed or med). the AMD-761 system controller does not log any new errors of each type or assert serr# until software clears the associated ecc_status bit by writing a 1. ecc_cs_med the multiple bit error chip select status provides the binary encoded chip select for the first multiple-bit error detected by the AMD-761 system controller. the failing ecc chip select is a binary encoded field and is valid only when the ecc_status bits indicate a multi-bit error was detected. ecc_cs_sed the single-bit error chip sele ct status provides the binary encoded chip select for the first single-bit error detected by the AMD-761 system controller. the failing ecc chip select is a binary encoded field and is valid only when the ecc_status bits indicate a single-b it error was detected. 3.8 programmable delay lines (pdl) this section describes the method used to create the delays necessary for proper dqs operation on the AMD-761 system controller ddr interface. the configuration registers used to control the delays are located in device 0:function 1. note that for most systems, the bios should simply set the values recommended in section 7 on page 211. the following sections provide a detailed description of the pdl operation and the options for bios configuration. for memory reads, the ddr devices drive the dqs pins edge- aligned with the data, and the AMD-761 system controller must ?adjust? the incoming dqs to ca pture the data. the adjusting of the incoming dqs requires delaying the dqs accordingly for each byte or nibble. because this timing is very tight, the
chapter 3 ddr sdram interface 17 5 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information AMD-761 system controller implements a programmable delay line (pdl) to adjust the incoming dqs. each pdl is composed of a selectable buffer chain that is used to delay the incoming dqs stro be for placing the dqs within the valid data window. a separa te pdl is implemented for each dqs pin (nine total in non-x4mode ) with additional pdls (for a total of 18 in x4mode) placed on the input of the data mask (dm) pins for use when accessing a x4 dimm. the pdl is only used for read data capture. because the propagation delay of an individual buffer of the pdl is a function of process, voltage and temperature (pvt), a mechanism is required to compensate for these three variables. this calibration mechanism determines the appr opriate delay to apply across pvt. a calibration mechanism is placed near every two pdls to accurately sense pvt near the ac tual pdls used to delay the incoming dqs strobes. each calibration mechanism is hand placed within the AMD-761 system controller to match gate for gate the actual pdl. this ap proach minimizes error between the calibration mechanism and the actual pdls. the range of each pdl is from 1 ns to 2.5 ns (worst case). the resolution of the pdl is equal to one buffer delay inside the AMD-761 system controller. that is, the value in the pdl register that controls the ?tap? point of the pdl delay chain represents the number of inte rnal buffer propagation delays. because the propagation delay of an internal buffer can vary over pvt, the number of buffers (and therefore the value in the pdl control register) can be different at different times (and different across the same AMD-761 system controller device or even different across selected AMD-761 system controller devices), but it can still represent the same delay value in time units. board effects (signal skews, cross talk, etc.) are incorporated in the timing budget analysis, and they combine to reduce the effective data-valid window width presented to the AMD-761 system controller. the pdl hardware assumes that the effects are symmetric?that is, they shrink the setup and hold times equally. if this symmetry is no t the case for the system, then the AMD-761 system controller allows the bios to compensate for these effects. the internally delayed dqs (outpu t of the pdl) is used inside the AMD-761 system controller to capture the corresponding
176 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information data byte (for x8 and x16 devices) or data nibble (for x4 devices) on a read cycle. the time value of the amount of delay to be applied to each dqs is fixed and is only dependent on the frequency of the system clock. therefore, the dqs delay required is known a priori and is listed in table 30. what is not known is how many internal buffer delays equal this required time value over pvt, which is the purpose of the pdl calibration mechanism. because the propagation delay of an individual buffer internal to the AMD-761 system controller is a function of pvt, a mechanism is required to compensate for these three variables. as previously mentioned, the delay value is known, but the number of buffers that provides this delay value is not known for a given pvt point. the calibration mechanism provides this piece of information. the mechanism used is a simple measurement of how many buffer delays are required to equal the system clock period. because the system clock is generated by a pll in the AMD-761 system controller, and it is already compensated for pvt, the system clock period is independent of pvt. therefore, the clock period can be assumed to be a constant and can be used to correlate the pdl values (cal_dly and act_dly) to units of time. each calibration mechanism inside the AMD-761 system controller measures the 2x sysc lk period in buffer delays. this measurement can take a few hundred clock cycles, therefore it is done off-line. the calibration mechanism computes a cal_dly value that is then transferred into the pdl control register (act_dly) at a time when the dqs pins are not active as inputs. the calibration is automatically performed once after reset and once after self-refresh exit, and the resultant value is transferred to each pdl. re-calibration can be initiated via software. the AMD-761 system controller also has a mode that enables periodic auto calibration. table 30. default dqs delay versus system clock frequency system clock frequency dqs delay (ns) dqs delay (% of cclk2x period) 100 mhz 2.0500 ns 41.0% 133 mhz 1.5625 ns 41.7%
chapter 3 ddr sdram interface 17 7 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information periodic auto-calibration mode re-computes the cal_dly values and transfers this value into the pdls. all nine (or 18) calibration mechanisms are enabled/disabled together for auto- calibration. this mode is usef ul in adjusting the delay values during operation. in effect, au to-calibration can adjust for voltage and temperature (vt) drifts during operation. note that the AMD-761 system controller also allows re-calibration to occur completely under software control when this (auto- calibration) mode is disabled. the auto-calibration period is configurable, and the possible periods are 10000, 1000000, 10000000 clock cycles (at 100 mhz, these periods are equal to 100 s, 10 ms, and 100 ms, while at 133 mhz it is somewhat faster). the setting of the auto- calibration period should be based on the actual characteristics of the system. software can control when calibr ation is done (except for the first computation at reset or an exit from self-refresh). it can either configure the AMD-761 system controller for auto- calibration (via the au to_cal_en bit), or it can initiate a single recomputation (via the sw_recal bit). if software initiates a single recomputation (v ia the sw_recal bit), it should also poll for this computat ion to be done. because auto-calibration registers are not initialized at reset, it is the responsibility of the bios to initialize the sw_cal_dly. the sw_cal_dly value that bios provides is based on a value provided after AMD-761 silicon characterization. the hardware computes the cal_dly value that is applied to the pdl based on the sw_cal_dly programmed. the sw_cal_dly bits are used by AMD-761 system controller to update the delay times in both auto-calibration mode as well as software-initiated calibrations. for example, if the delay required is 1.7 ns and the system clock frequency is 133 mhz, the following is the derivation of the sw_cal_dly value: the half-period of system clock = 3.75 ns. 1.7 ns = 45.33% of the half-period. the sw_cal_dly value is 0.4533 x 256 = 116 (rounded to nearest integer) = 0x74. the AMD-761 system controller allows software to optionally write to the act_dly bits that control each pdl. the value written to the act_dly bits is the number of buffer delays
178 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information required (rather than a percen tage of the clock period). to determine the number of buffer delays, software must first read the clk_dly bits and scale this value for the required act_dly. for example, if clk_dly is 75 buffer delays at 100 mhz, and the bios desires a delay of 2.1 ns, the following is the derivation of the act_dly value: 75 buffer delays = half-per iod of system clock = 5 ns 2.1 ns = 2.1 / 5 x 75 = 31.5 buffer delays the act_dly value is either 31 or 32 (depending on rounding desired) = 0x1f or 0x20. the AMD-761 system controller provides a configuration bit (act_dly_inh) that inhibits the auto calibration state machine from updating the act_dly valu es after the computation of clk_dly and cal_dly is completed. if this mode is used, the pdls (act_dly values) are not updated with new cal_dly values (whether auto-calibration is enabled or whether software initiates a re-calibration). however, the pdls are always updated at reset. upon exit from self-refresh, the act_dly_inh bit determines wh ether the pdls are updated or not. this feature can be us eful for diagnostic purposes. sw_recal the software re-calibration bit (dev 0:f1:0x40, bit [7]) provides a way for software to force a re-calibration cycle. this action is allowed only when the auto calibration feature is disabled . a re-calibration is forced when this bit is written to a 1b. this bit also provides stat us by being cleared when the calibration has complete d. bios may find it useful to be aware of the completion of the calibra tion, although from a functional perspective, the ddr memory co ntroller does not require it. when the re-calibration is co mplete, the hardware recomputes the cal_dly values for all pdls, based on the values of their sw_cal_dly fields. use_act_dly the use actual delay bit (dev 0:f1:0x40, bit [6]) provides a way for software to change the pdl setting manually, which is done by updating the act_dly field directly. bios should set this bit to indicate to the hardware that it has written to the act_dly fields and wants to upda te the pdls (all 18) with the newly written act_dly values. this method should be used only when sw_recal and auto_cal _en bits are not set. if auto_cal_en is set, writes to this bit are ignored.
chapter 3 ddr sdram interface 179 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information auto_cal_en the auto calibration enable bit (dev 0:f1:0x40, bit [5]) provides a way for bios to en able the pdl auto calibration function. when this bit is set, all of the cal_dly values are recomputed periodically (according to the setting of the auto_cal_period field) for all pdls, based on the values of their sw_cal_dly fields. if the act_dly_inh bit is not set, the cal_dly values are also applied to the act_dly. note: once auto_cal_en is set to 1, clearing it makes the bit a 0, but the auto-calibration logic may perform one more update, depending on when the auto_cal_en bit is cleared. therefore, bios should at least wait for the amount of time specified by the auto_cal_period field after clearing the auto_cal_en bit before attemp ting to change any of the pdl parameters. note: this bit should not be set if the system clock frequency is 66 mhz. act_dly_inh the actual delay update inhibit bit (dev 0:f1:0x40, bit [4]) provides a way for bios to inhibit an auto-calibration value from updating the pdls. the setting of this bit affects both auto-calibration and software-ini tiated calibration but not the use_act_dly method. after an exit from self-refresh, the setting of this bit determines whether the act_dly value is updated or not. note: the internal logic tests this bit just prior to updating the act_dly, so the other bits in this register should be taken into consideration when writing to this bit. auto_cal_period the auto-calibration period (dev 0:f1:0x40, bits [1:0]) bits specify how often an auto-calibration occurs. the auto- calibration periods are as follows: 00 = 10000 system clocks 01 = 1000000 system clocks 10 = 10000000 system clocks 11 = reserved bios should configure this field before setting the auto_cal_en bit. this field should not be altered while auto_cal_en is set. clk_dly the auto-calibrator?s clock delay (dev 0:f1:0x44, bit [31:24] through dev 0:f1:0x88, bits [3 1:24]) is read-only and provides
180 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information the number of pdl buffer delays required to make up a 2x sysclk period. this value is used to calculate the actual pdl value. the value returned from this field divided by the clock frequency is the average delay per tap of the pdl. sw_cal_dly the auto-calibrator?s software calibration delay (dev 0:f1:0x44, bits [23:16] through dev 0:f1:0x88, bits [23:16]) provides bios access to the overall percentage of the buffers required, based on the total number of buffer delays shown in the clk_dly field. this value is used to calculate the actual pdl value. this value should be: 69h at 100 mhz (2.0500 ns 41.0%) 6bh at 133 mhz (1.5625 ns 41.7%) cal_dly the auto-calibrator?s calculated delay (dev 0:f1:0x44, bits [15:8] through dev 0:f1:0x88, bits [15:8]) is read-only and provides the calculated delay based on the auto-calibrator?s finding of clk_dly and the bios-specified sw_cal_dly. this value is the final calibration va lue that is used for the pdl if the act_dly_inh bit (dev 0:f1:0x40 , bit [4]) is not set. if the act_dly_inh bit is set, this calculated value is not used to update the pdls. act_dly the auto-calibrator?s actual delay (dev 0:f1:0x44, bits [7:0] through dev 0:f1:0x88, bits [7:0]) directly specifies the number of pdl taps. bios can manually update the pdl by writing a pdl tap value into this register and writing a 1b to the use actual delay bit (dev 0:f1:0x40, bit [6]). this action should only be done when the auto-cal ibration logic is disabled by writing a 0b to (dev 0:f1:0x40, bit [5]). manually updating the pdl while the auto-calibration lo gic is enabled could result in unpredictable system operation. 3.8.1 manual pdl window detection the recommended value specified in the sw_cal_dly field (dev 0:f1:0x44, bits [23:16] through dev 0:f1:0x88, bits [23:16]) is based on calculated round trip timing assuming worst case AMD-761 system controller conditions, worst case ddr dimm device conditions, and board routing. the most critical timing relationship during a ddr dimm read is the round trip data delays and the dqs/data relationship relative to each other. many factors affect the dqs/data relationship. because of these factors, bios itself can determine a precise
chapter 3 ddr sdram interface 181 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information sw_cal_dly value by performing a manual window detection rather than using the specified values. manual window detection can be accomplished with the following steps: disable the pdl auto-calibration feature by setting dev 0:f1:0x40, bit [5] = 1b0. disabling auto-calibration prevents auto-calibration interference while bios manipulates this process manually. determine the operating range of each pdl by adjusting each pdl tap from minimum to maximum to determine the data window range. this dete rmination is accomplished by multiple iterative writes to alter the pdl and reading back "expect" data from ddr memory after each pdl tap is altered. for x8/x16 devices, this process is performed at the byte resolution. for x4 devices, this process is performed at the nibble resolution. the actual delay is adjusted via dev 0:f1:0x44, bits [7:0] through dev 0:f1:0x88, bits [7:0]. after the actual delay is configured, bios must write a 1b to the use actual delay bit (dev 0:f1:0x40, bit [6]) to apply the new actual delay value. once the operational range for each byte (for x8/x16 devices) or for each nibble (for x4 devices) is determined, the center point for this window can be determined by dividing these ranges by two, which yields the ?target window pdl tap.? the average pdl tap value must be determined for knowledge of the expected dela y per tap of the pdl. this value can be retrieved by pe rforming a software-initiated calibration. first set the actu al delay update inhibit dev 0:f1:0x40, bit [4] to a 1b to prevent a calibration update. initiate a calibration by writing a 1b to dev 0:f1:0x40, bit [7], and then polling this bit to become a 0b to determine when the calibration is comple te. the total number of pdl taps that make up 5 ns (for 100-mhz operation) or 3.75 ns (for 133-mhz operation) can be found in the clock delay field for each calibrator in dev 0:f1:0x44, bits [31:24], through dev 0:f1:0x88, bits [31:24]. by dividing the appropriate period (as applies to the frequency of the AMD-761 system controller) by the values found in the clock delay fields yields the ?average delay per pdl tap.?
182 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information once the appropriate pdl value is determined for each byte or nibble (as it applies), this value must be converted into a software calibration delay value for the auto- calibration logic. this value can be calculated by multiplying the ?target window pdl tap? (found above) by the ?average delay per pdl tap,? which yields the ?required pdl tap delay? as a function of time (ns). the software calibration delay is specified as a percentage. therefore, the software calibration delay = ((operating period/2) / required pdl tap delay) x 256). the value determined in this calculation must be applied to the software calibration delay field dev 0:f1:0x44, bits [23:16], through dev 0:f1:0x88, bits [23:16]. clear the actual delay update inhibit dev 0:f1:0x40, bit [4] to allow calibr ation updates and then enable the auto- calibration system by writing a 1b to dev 0:f1:0x40, bit [5]. 3.9 ddr i/o drive strength the ddr i/o pads are sstl-2 co mpatible. the ddr pads have configurable slew rate and drive strength control of n and p transistors, separately. it is the responsibility of bios to initialize the pad drive strength and slew rate before any memory accesses. the ddr i/o drive strength and slew controls exist at (dev 0:f1:0x8c) through (dev 0:f1:0x9b). drive strength and slew control are provided for both the p and n transistors to allow for a fi ne adjustment for proper ddr sstl-2 crossover points and rise/fall edge rates. separate drive strength and slew control is provided for the following: data strobes (dqs) note: if any chip select is configured to support a x4 dimm, the dm buses inherit the drive strength and slew setting specified for the data strobes (dqs). otherwise, the dm pins inherit the drive strength specified for the mdat pins. this inheritance occurs because a x4 dimm access uses the dm signals as data strobes (dqs) signals. data bus (mdat), ecc bus (mecc), and data mask bus (dm) (see preceding note.) device clock output (clkouth/l)
chapter 3 ddr sdram interface 183 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information note: the AMD-761 system controller provides differential clocks, clkouth and clkoutl, for the ddr dimms. this single clkout drive strength and slew setting applies for both polarities of clkout. device chip select (cs[7:0]#) command bus a (rasa#, casa#, wea#, and ckea#) command bus b (rasb#, casb#, web#, and ckeb#) memory address bus a (maa[14:0]) memory address bus b (mab[14:0]) signal integrity studies have sh own that p and n slew settings of 101b and a p drive strength setting of 11b and an n drive strength setting of 10b for all of the signal groups specified above provide adequate edge rates across various unbuffered and registered dimm devices and population. a proper drive strength and slew setting for (d ev 0:f1:0x8c, bits [31:0]) is 0e_2d_0e_2dh.
184 ddr sdram interface chapter 3 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information
chapter 4 power management 185 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 4 power management this chapter provides the bios requirements for the AMD-761? system controller?s various power management states. the AMD-761 system controller includes logic specifically for the support of the following advanced configuration and power in terface (acpi) states: c2 stop grant (probed) s1 power-on suspend s3 suspend to ram this chapter discusses the bios requirements for the AMD-761 system controller only, an d does not include special requirements for the processor, southbridge, or the operating system support of each power management state. note: to accommodate the s3 state, some of the AMD-761 system controller register bits are not initialized to a known value at power-on with the rese t# signal. the bios must initialize all of these bits for proper operation, especially when enabling power management features as described in this section. bios must also perform a save and restore of all relevant configuration bits in the processor and chipset to support the suspend to ram feature. table 31 on page 186 summarizes the various features required by the AMD-761 system controller to support the different power management states. note: acpi c3 state is not supported by the AMD-761 system controller , and the bios must not declare c3 support to the operating system through the fixed acpi description table. the bios should declare the following values: a value of 0 in the pm2_cnt_blk field in the fixed acpi description table (fadt) a value of 0 in the pm2_cnt_len field of the fadt a value of 0 in the x_pm2_cnt_blk field of the fadt if this acpi 2.0 extension is supported by the operating system.
186 power management chapter 4 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information each of the various power management features may be optionally enabled with specific configuration bits in the AMD-761 system controller?s host bridge configuration space as described in the following sections. 4.1 c1 halt state requirements the processor enters the c1 halt state after executing a halt instruction and generating a halt special cycle on the amd athlon? system bus. the AMD-761 system controller supports two options for the halt state: 1. forward the halt special cycle to the pci bus but otherwise continue normal operat ion (no power savings). 2. disconnect the processor and then forward the halt special cycle to the pci bus (processor enters very low-power state). table 31. AMD-761? system controller power ma nagement features for acpi support AMD-761 system controller power management feature acpi state c1 c2 s1 s3 disconnect processor when halt special cycle is detected on amd athlon? system bus. enabled by biu status/control (dev 0:f0:0x60, bit 18) x disconnect processor when stop grant special cycle is detected on amd athlon? processor system bus. enabled by biu status/control (dev 0:f0:0x60, bit 17 for cpu 0) xxx memory controller forces dram to self-refresh mode enabled by biu status/control (dev 0:f0:0x60) and mode/status register (dev 0:f0:0x70, bit 18) xxx dcstop# assertion by southbridge causes AMD-761 system control- ler to gate off clock trees and dram clocks for lower power enabled when the stp_grant_disc on_en bit is set in the biu status/control register (dev 0:f0:0x60, bit 17). xx reset# assertion in s3 state causes AMD-761 system controller to gate off i/o rings so power can be removed from agp, pci, and pro- cessor interfaces while vdd_core and ddr interface remains pow- ered. enabled when the stp_grant_disc on_en bit is set in the biu status/control register (dev 0:f0:0x60, bit 17). x
chapter 4 power management 187 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information the first option is the reco mmended mode and requires no special setup in the AMD-761 sy stem controller other than to write a 0 to the halt_discon_en bit in the biu status/control register (dev 0:f0:0x60, bit 18). this action causes the AMD-761 system controller to react to the halt special cycle on the amd athlon system bus by forwarding the cycle to the pci bus but not attempting any processor disconnect. there is no significant power savings in this mode. the second option requires that the halt_discon_en bit be set, which forces the AMD-761 system controller to initiate a processor disconnect for lower power using the procrdy/connect protocol on the amd athlon? system bus. the pci and agp arbitration remains enabled in this state, thus any dma cycles that require a probe of the processor?s cache causes the AMD-761 system controller to reconnect using the procrdy/connect protocol. there is some additional latency impose d when this mode is enabled, because each processor probe re quires a reconnect of the cpu. when the amd athlon system bus is disconnected, the processor enters a very low-power state. the amd-766? peripheral bus cont roller southbridge does not require any special initialization for either of the above two modes. 4.2 c2 stop grant state requirements the processor enters the c2 stop grant state and issues a stop grant special cycle on the amd athlon processor system bus in response to the assertion of th e stpclk# input signal by the southbridge. the AMD-761 syst em controller supports two options for the stop grant state: 1. wait for a stop grant special cycle from both installed processors and fforward the stop grant special cycle to the pci bus, but otherwise contin ue normal operation (no significant processor power savings). 2. disconnect the processor, enter self-refresh, and then forward the stop grant special cycle to the pci bus. this power management state provides a lower power clock
188 power management chapter 4 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information controlled state that allows snooping of the processor cache. if the amd athlon processor sy stem bus is disconnected, the processor enters a very low-power state. the first option requires no special setup in the AMD-761 system controller other than to write a 0 to the stp_grant_discon_en bit in th e biu status/control register (dev 0:f0:0x60, bit 17). this action causes the AMD-761 system controller to react to the st op grant special cycle on the amd athlon processor system bus simply by forwarding the cycle to the pci bus, but not attempting any processor disconnect. no significant power savings occur in this mode. when this option is selected , the bios should not declare support for the c2 state in th e fixed acpi description table. the second option requires that the following AMD-761 system controller configuration bits be initialized: the stp_grant_discon_en must be set in the biu status/control register. when this bit is set, the AMD-761 system controller flushes inte rnal queues after receiving the stop grant special cycle, force the ddr dram into self- refresh mode, and forward the stop grant special cycle to the pci bus to the southbridge. dram refresh must be enabled by writing a 0 to the ref_dis test bit in the dram mode/status register (dev 0:f0:0x58, bit 19). self-refresh must be enabled by writing a 1 to the self_ref_en bit in the status/control register (dev 0:f0:0x70, bit 18). dma cycles initiated from the pci bus or agp interface?s pci bus can be probed in the c2 st ate. when a cacheable access is initiated on these interfaces , the AMD-761 system controller initiates a connect sequence on the amd athlon system bus via the procrdy/connect protocol. this mode requires specific conf iguration registers in the to be initialized for proper generatio n of the stpclk# signal and resume events.
chapter 4 power management 189 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 4.3 s1 power-on suspend state requirements the acpi s1 state uses the southbridge dcstop# signal to gate off the AMD-761 system controller?s internal clock trees for a very low-power state. all voltages remain powered on in this mode. to the AMD-761 system controller, the configuration register initialization required for s1 support is the same as that required for c2 support as described in section 4.1 on page 186. the AMD-761 system controller requires the following bios/drivers for s1 support: the stp_grant_discon_en must be set in the biu status/control register. when this bit is set, the AMD-761 system controller flushes inte rnal queues after receiving the stop grant special cycle, forces the ddr dram into self-refresh mode, and forwards the stop grant special cycle to the pci bus to the southbridge. dram refresh must be enabled by writing a 0 to the ref_dis test bit in the dram mode/status register (dev 0:f0:0x58, bit 19). self-refresh must be enabled by writing a 1 to the self_ref_en bit in the status/control register (dev 0:f0:0x70, bit 18). to ensure that no probes are generated, all pci/agp traffic must be prevented by the peripheral software drivers before entering the s1 state when dcstop# is asserted. it is expected that the drivers have already placed each pci/agp peripheral into the d3 state prior to stpclk# assertion by the southbridge. the s1 state is supported by th e AMD-761 system controller for both unbuffered and registered ddr dimms. however, when registered dimms are installed in the system (according to the reg_dimm_en bit in the dram timing register in dev 0:f0:0x54), the dram clocks (clkout[5:0], clkout[5:0]#) continue to be driven active. this action is required because the registered dimms do not support removal of the clock input unless in reset. the s1 sleep state has a very low resume latency because the plls are already running. the amd- 761 system controller
190 power management chapter 4 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information simply enables its clock trees and reconnects the processor. because no power is removed from the system, and the reset# signal is not asserted, all AMD-761 system controller configuration registers retain their original value prior to entering the s1 state. the s1 sleep state requires specific configuration registers in the amd-768 peripheral bus cont roller or amd-766 peripheral bus controller to be initialized for proper generation of the stpclk# and dcstop# sign als and resume events. 4.4 s3 suspend to ram state requirements the acpi s3 state achieves maximum power savings and low- latency resume by shutting off most system power supplies while retaining system context in dram. this action requires that the AMD-761 system controller core voltage remain powered on along with the dram and part of the southbridge, while the remaining platform components are powered off. for any system enabling the s3 state, a number of core logic pci configuration registers and processor msrs must be saved or restored prior to suspending or restoring s3. also, certain hidden bits must be unmasked. these requirements apply to all platforms regardless of segment and whether or not amd powernow!? is used. to the AMD-761 system controller, the configuration register initialization required for s3 support is the same as that required for s1 support. the AMD-761 system controller requires the following of the bios/drivers for s3 support: the stp_grant_discon_en must be set in the biu status/control register. when this bit is set, the AMD-761 system controller flushes inte rnal queues after receiving the stop grant special cycle, force the ddr dram into self- refresh mode, and forward the stop grant special cycle to the pci bus to the southbridge. dram refresh must be enabled by writing a 0 to the ref_dis test bit in the dram mode/status register (dev 0:f0:0x58, bit 19).
chapter 4 power management 191 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information self-refresh must be enabled by writing a 1 to the self_ref_en bit in the status/control register (dev 0:f0:0x70, bit 18). to ensure that no probes are generated, all pci/agp traffic must be prevented by the peripheral software drivers before entering the s3 state when dcstop# is asserted. it is expected that the drivers have already placed each pci/agp peripheral into the d3 state prior to stpclk# assertion by the southbridge. the suspend to ram control bits (str_control[1:0]) in the dram mode/status register (dev 0:f0:0x58) must be properly controlled by bios to force the AMD-761 system controller to properly enter and exit the s3 state. refer to section 4.4.1 on page 191 for details. to accommodate s3 support, the AMD-761 system controller does not initialize most of the memory controller configuration registers to a known value when reset# is asserted. it is important that these registers be properly initialized by bios during the power-up configurat ion. once initialized, the AMD-761 system controller retains these values when resuming from the s3 state. 4.4.1 str bit control for s3 support the str_control bits are provided to allow bios to communicate state changes to the AMD-761 system controller?s power management logic. proper control of these bits is required to ensure that the co rrect sequence is followed when the AMD-761 system controller is entering and exiting the suspend to ram state. each of the three str_contro l modes are de scribed below. power-on reset (00) the AMD-761 system controller always sets the str_control bits to this value when the re set# pin is asserted?that is, when powering up from the s3 , s4, s5, and mechanical off states). the AMD-761 system controller memory controller always drives the dram cke pins low in this state, forcing the drams inactive, and the memory controller configuration registers retain the values they had prior to the reset# assertion.
192 power management chapter 4 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information normal resume (01) bios should write this value to the str_control bits when resuming from the s4 (suspend to disk), s5 (soft off), or mechanical off states. this action forces the AMD-761 memory controller to follow the normal dram initialization sequence as follows: assert cke pins to enable clocks at the dram dimms perform required dram initialization sequence, including writes to dram mode registers, etc. the bios should then follow th e normal initia lization sequence in this mode, including dr am configuration and memory sizing, etc. after a hard reset, bios should set these bits to 01b and bit 25 of this register (dram init) to a 1b within the same configuration write. if this regi ster is not set to a 01b, setting bit 25 of this register has no effect. this pattern is written by bios to inform the AMD-761 system controller memory controller that this is a powe r-on reset rather than a suspend to ram wakeup from reset. resume from s3 (1x) bios should write this value to the str_control bits when resuming from the s3 (suspend to ram) state. this action instructs the AMD-761 system controller memory controller to perform the proper ddr protocol to exit self-refresh but not attempt to re-initialize the ddr dram devices?that is, mode register writes, etc.). note th at this bit is ignored by the memory controller after it exits self-refresh, until the bit is cleared by reset#. problems are thus avoided when the AMD-761 system controller periodically enters and exits self- refresh for c2, s1 and clock throttling. as shown in figure 5 on page 193, when bios writes a 1x to the str_control field upon exiting the s3 state, the AMD-761 system controller simply takes the dram out of self-refresh mode. at this time all of the AMD-761 memory controller configuration registers retain their original values programmed prior to entry to the s3 state, thus allowing bios immediate access to memory for the restoration of all other system configuration registers and context restoration. refer to section 1.1.3 on page 4 for a list of the AMD-761 system controller configuration registers that are not set to a known value when the reset# pin is asserted.
chapter 4 power management 193 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information figure 5. suspend to ram (str_control) bits usage 4.5 clock throttling clock throttling is a power management mechanism that periodically causes the assertion of the stpclk# signal to the processor to achieve lower system power. clock throttling can be accomplished through a combination of hardware and software and can be performed at regula r intervals?that is, modulating the stpclk# pin or through a more sophisticated system such as implementing thermal sensors on the motherboard. the AMD-761 system controller supports clock throttling with the same hardware mechanisms that are used for c2 support and requires the following bios configuration register initialization. the stp_grant_discon_en must be set in the biu status/control register. when this bit is set, the AMD-761 system controller flushes inte rnal queues after receiving the stop grant special cycle, forces the ddr dram into str_control 00 str_control 01 str_control 1x resume from s4/s5 or mechanical off states, bios writes 01 resume from s3 state, bios writes 1x AMD-761? system controller asserts dram cke pins and exits self-refresh mode. the AMD-761 system controller retains the value of all memory controller configuration registers; all other registers are cleared to their power-up values. bios disables any unused ddr clocks. bios can now begin restoring all other configuration registers from dram. resume from s3/s4/s5 or mechanical off states, reset# asserted, forces 00 dram cke pins are asserted by the AMD-761 system controller. bios initiates the AMD-761 system controller to start dram. power-up initialization process, including disabling any unused ddr clocks, writing to dram mode registers, etc. bios continues normal system initialization and post process. dram cke pins are low, all dram clkout pins are enabled powerdown or enter s3 state, str_control bits reset to 00 by assertion of reset# pin
194 power management chapter 4 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information self-refresh mode, and forwards the stop grant special cycle to the pci bus to the southbridge. dram refresh must be enabled by writing a 0 to the ref_dis test bit in the dram mode/status regi ster (dev 0:f0:0x58, bit 19). self-refresh must be enabled by writing a 1 to the self_ref_en bit in the status/control register (dev 0:f0:0x70, bit 18). dma cycles initiated from the pci bus or agp interface pci bus can be probed while in the stop grant state during clock throttling. when a cacheable access is initiated on these interfaces, the AMD-761 system controller initiates a connect sequence on the amd ath lon system bus via the procrdy/connect protocol. note that when using clock thro ttling, the southbridge must be programmed to wait for the stop grant special cycle before changing the state of the stpclk# signal. 4.6 ddr dram clock enables the AMD-761 system controller is designed to provide bios the ability to disable any unused ddr dram clock pairs to reduce power and system noise. these clock pairs are controlled by the clk_dis[5:0] field in the dram mode/status register (dev 0:f0:0x58). the AMD-761 system controller provides six differential clock pairs to suppo rt up to two unbuffered dimms or four registered dimms. the usage of these clocks is motherboard- specific (i.e., which clock pairs connect to which dimm clock inputs). the clk_dis bits are initialized to 0 when reset# is asserted, thus guaranteeing that all dram clock pairs are enabled when exiting the s3 state. it is recommended that clock pairs that are connected to unused dimm slots be disabled by bios. note that because the values programmed by bios during power-on initialization are not maintained when entering the s3 state, bios is required to write to the clk_dis field when restoring the AMD-761 system controller configur ation registers.
chapter 5 pci bus interface 195 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 5 pci bus interface this chapter provides additional details of some of the AMD-761? system controller pci interface options that affect system performance an d compliance to the pci local bus specification , revision 2.2, as well as some recommended settings for the AMD-761 system controller configuration register bits. the features and options discussed are as follows: pci delayed transactions and target latency pci transaction ordering special arbitration options for southbridges with legacy dma requirements performance enhancement option s, including read prefetch- ing and pci chaining 5.1 delayed transactions and ordering rules usage the AMD-761 system controller provides three transaction operating modes for the pci bus host bridge interface as listed in table 32 on page 196. bios should program the bits listed in table 32 to only one of these combinations for best results.
196 pci bus interface chapter 5 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information the effects of the settings described in table 32 above are described further in th e following sections. 5.1.1 delayed transactio ns and target latency delayed transactions and read target latency should be enabled and disabled together in the AMD-761 system controller, such that both bits are either set or cleared. setting the read target latency bit (tgt_latency) forces the AMD-761 system controller to disconnect the current pci memory read cycle in progress when the defined maximum allowable latency has expired. th is latency is defined in the pci local bus specification, revision 2.2, as 16 pci clocks (32 pci clocks for host bridges that must snoop processor caches). when the read target latency is reached, the AMD-761 system controller asserts the stop# signal, thus disconnecting the pci master (retry). the master is then obligated by protocol to retry the same cycle after re- arbitration, in anticipation that the read has completed in the memory subsystem, thus the next read cycle falls within the maximum target latency. setting the delayed transaction enable (pci_dt_en) causes the AMD-761 system controller to latch the address and read command that was initiated by the external master table 32. AMD-761? processor system controller pci read transaction options pci_dt_en dev 0:f0:0x4c, bit 2 pci_or_en dev 0:f0:0x4c, bit 1 tgt_latency dev 0:f0:0x84, bit 23 description 0 disabled 0 disabled 0 disabled no pci transaction ordering or target latency rules are enforced. delayed transactions are disabled, but masters are not retried by the AMD-761? system controller during memory reads (unless the pci_wr_post_rty bit is set in the pci arbitration register at dev 0:f0:0x84). this mode is not fully pci 2.2-compliant because the AMD-761 system controller host bridge may consume greater than 32 pci bus clocks during memory read transactions, and transaction ordering is not strictly enforced. 1 enabled 0 disabled 1 enabled delayed transactions are enabled and target latency rules are enforced. this mode is not fully pci 2.2-compliant because transaction ordering rules are not strictly enforced. 1 enabled 1 enabled 1 enabled delayed transactions are enabled, target latency and transaction ordering rules are enforced. this mode provides full pci 2.2-compliance.
chapter 5 pci bus interface 197 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information when the read target latency timer expires, thus allowing the pci target and memory controller logic to independently complete the read so that the next time the original master retries the read, the data is ready to return immediately (assumes the pci_wr_post_rty bit is not set in the pci arbitration register (dev 0:f0:0x84, bit 14). there are two reasons delayed transactions may be enabled: 1. for systems that must meet the target latency requirement, delayed transactions are bett er because the memory read cycle is queued in the amd-7 61 system controller memory controller after the pci master is disconnected and while it is re-arbitrating for the pci bus. this action provides a higher likelihood that when the master retries the transaction, the read data is immediately available. 2. delayed transactions free up the pci bus during the time that the memory subsystem is retrieving the read data, for peer-to-peer pci traffic between other pci masters and agents. unfortunately, this type of traffic is rare in most systems. it should be noted that the AMD-761 system controller supports only a single-level del ayed transaction queue, thus the performance benefit may be minimal and may actually be worse with delayed transa ctions enabled under some conditions. the following sections provide examples of pci read transactions with delayed transactions enabled and disabled. note that in both examples th e read target latency feature enable is set the same as the delayed transaction feature enable. delayed transactions and target latency disabled this example assumes that a memory read transaction is initiated by a pci master and that the AMD-761? system controller is unable to return data within the specified 32 pci clock latency. 1. the AMD-761 system controller initiates a memory read to the memory controller and simultaneously issues a probe to the processor. the memory s ubsystem is unable to return the data within 32 pci clocks, so it continues to hold the bus (devsel# active, stop#, and trdy# inactive).
198 pci bus interface chapter 5 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 2. a second pci master request s the bus to access main memory, and it receives a bus grant from the AMD-761 system controller pci arbiter, but it must wait until the memory read cycle initiated by the previous master is completed. if this master?s cycle was targeted to another pci agent, it still could not begin the transaction because the bus is tied up by the prev ious master and the AMD-761 system controller. 3. some number of pci clocks later, the memory subsystem returns read data to the master completing the transaction. the bus goes idle, so the next master begins its transaction. delayed transactions and target latency enabled this example assumes that a memory read transaction is initiated by a pci master and that the AMD-761 system controller is unable to return data within the specified 32 pci clock latency. 1. the AMD-761 system controller latches the memory read command and the address, and initiates a memory read to the memory controller and simultaneously issues a probe to the processor. the memory s ubsystem is unable to return the data within 32 pci clocks, so it asserts the stop# signal while trdy# remains inactive. this action causes the master that originated the cycle to disconnect, and it must re-arbitrate for the bus. meanwhile, the AMD-761 system controller memory controller continues to process the enqueued memory read transaction. 2. a second pci master?s bus request is now granted. if the request is a read from main memory, the AMD-761 system controller retries th e cycle but does not queue the transaction because it already has an outstanding delayed transaction in progress. if the request is to a peer pci agent, then the transaction can continue in parallel to the memory cycle being completed by the AMD-761 system controller. 3. the original master wins bus arbitration and retries its read command, and the AMD-761 system controller now responds with the read data within the specified maximum target read latency. in summary, if compliance to the target latency rules is desired, then it is recommended that delayed transactions enable and the target latency bits are enabled.
chapter 5 pci bus interface 199 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 5.1.2 transaction ordering rules the pci local bus specification , revision 2.2, defines various transaction ordering rules to accommodate the producer- consumer model and to prevent deadlock conditions on the bus under certain conditions. the AMD-761 system controller provides the ability to optionally disable strict adhere nce to the transaction ordering rules if desired. the ordering rules are defined such that data and its associated flags are visible by any agent on any segment of the pci bus. in typical systems, however, this visibility is not necessary, as both da ta and flags typically reside in main system memory. it may be possi ble to achieve slightly better pci bus performance when or dering rules compliance is disabled, because pci masters attempting to read main memory are not disconnected to force the flushing of posted write fifos in the AMD-761 system controller. figure 6 on page 201 illu strates an example system implementation with data and associated flags stored in different locations. in this exam ple, the flag is stored in main memory (dram) and the data is stored in the pci agent. the sections that follow describe the behavior in a system with and without ordering rules compliance. with ordering rules enabled using figure 6 as an example, the following case describes the behavior of the AMD-761 system controller when ordering rules are followed. 1. the processor writes data (memory write) destined to an agent on the pci bus, and the data is posted in the AMD-761 system controller pci posting buffer. 2. the processor then sets a flag in memory, informing the pci agent that the data is written. 3. the pci master reads the flag, but this action causes the data previously written by th e processor to be flushed from the AMD-761 system controller posted write buffer. the pci master is disconnected by the AMD-761 system controller (stop# active with trdy# inactive) to allow the AMD-761 system controller to write the data to the pci agent.
200 pci bus interface chapter 5 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 4. the pci master regains bus ow nership and atte mpts to read the flag again. this time it successfully reads the flag and the previously posted write da ta has already been written to the master?s target interface. it should be noted that this configuration is rare, as most systems place the data and the flag in main memory. with ordering rules disabled using figure 6 as an example, the following case describes the behavior of the AMD-761 system controller when ordering rules are not followed. 1. the processor writes data (memory write) destined to an agent on the pci bus, and the data is posted in the AMD-761 system controller pci posting buffer. 2. the processor then sets a flag in memory, informing the pci agent that the data is written. 3. the pci master reads the flag, but the associated data (previously written by the proc essor) has not been flushed from the AMD-761 system controller posted write buffer. this situation results in a data incoherency. again, as in the case when ordering rules are enabled, note that this configuration is rare , as most systems place the data and the flag in main memory. the AMD-761 system controller provides the ordering rules feature for compliance to the pci local bus specification , revision 2.2.
chapter 5 pci bus interface 201 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information figure 6. example of system with flag and data stored across pci bus domain 5.1.3 special arbitration considerations for the southbridge to accommodate legacy dma as is support ed in the amd-766? peripheral bus controller (the devices connected to the AMD-761 system controller?s sbreq# and sbgnt# pins), the AMD-761 system controller makes special exceptions in the arbitration for the southbridge. the southbridge is not preempte d or disconnected when it gains access to the pci bus as a master. this design prevents potential deadlock conditions that can occur with legacy dma. there are no bios requirements to enable or disable this functionality. before winning bus arbitr ation, the AMD-761 system controller?s internal memory read and write queues can optionally be locked and flushe d. this option is controlled by the sb_lock_dis bit in the pci arbitration control register (dev 0:f0:0x84, bit 8). this bit is cleared for normal operation. cpu producer pci agent consumer northbridge dram flag data pci bus producer (cpu) writes data to the agent (consumer), data is posted in the bridge posting buffer. producer sets flag in memory. consumer reads flag, causing the posting buffer to be auto- matically flushed with ordering rules compliance enabled. data posted in northbridge
202 pci bus interface chapter 5 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information by default, the AMD-761 system controller does not allow the sbreq# pci request to be pr eempted by requests on the normal req#[6:0] pins, and it does not disconnect the southbridge once it has started a transfer. 5.2 pci performance optimization options in addition to transaction level options as listed in section 5.1 on page 195, the AMD-761 system controller pci bus interface provides various system level op tions that can be used to tune the system performance. each of these options are described in the following sections. 5.2.1 read prefetching when the AMD-761 system controller is the target of pci memory read accesses to system memory, the AMD-761 system controller?s pci target interface initiates a probe of the amd athlon? processor?s cache and a read of eight quadwords (a single cache line) from memo ry. setting the read prefetching bit (pci_pref_en, dev 0:f0:0x84, bit 1) causes the AMD-761 system controller to prefetch another eight quadwords from memory, speculating that the pci master will request another cache line at the next cache-aligned address. the obvious advantage to read prefetching is that masters that are reading multiple contiguous cache lines of data can stream this data more effectively on the pci bus. the disadvantage is that it could result in wasted bandwidth of the memory subsystem of the prefetched data that is purged because it was not needed by the pci master.
chapter 5 pci bus interface 203 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 5.2.2 pci chaining pci chaining is a feature designed to optimize memory writes from the processor to the pc i bus. chaining simply causes write combining at the pci interf ace, such that four quadword cpu memory writes to contiguous addresses are chained together, resulting in a sing le pci burst-write instead of separate nonburst writes. pci chaining is enabled by th e pci_chain_en bit in the pci arbitration control register (dev 0:f0:0x84). it is recommended that this bit always be set for optimal performance. 5.2.3 pci bus parking the pci local bus specification , revision 2.2, requires that a default bus owner be designated that always drives the bus to a known value to prevent the bus from floating for long idle periods. the AMD-761 system controller provides two options for bus parking: park on the AMD-761 system controller?that is, cpu accesses to pci agents park on the last mast er that had bus tenure arbitration latency on an idle bus for the agent that has default ownership (bus is parked on that agent) is zero pci clocks, whereas it is two pci clocks for all other masters. pci bus parking is controlled by the park_pci bit in the pci arbitration control register (dev 0:f0:0x84). it is recommended that this bit be cl eared to 0 to force parking the bus on the AMD-761 system controller.
204 pci bus interface chapter 5 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information
chapter 6 agp interface 205 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 6 agp interface this chapter details some of th e specific bios requirements for programming the AMD-761? system controller?s agp interface. 6.1 agp dynamic compensation requirements to accommodate the high-speed requirements of 4x agp rates, the AMD-761 system controller provides circuitry designed to automatically compensate for motherboard impedance on the agp interface over the range of temperature and voltage, by dynamically adjusting the drive strength of the AMD-761 system controller i/o pads when 1.5-v signalling is selected by the agp card. this action requires proper initialization by bios as described in this section. two separate 32-bit configuration registers are used to control agp i/o characteristics: 1. agp dynamic compensation register, dev 0:f0:0xb4 2. agp compensation bypass register, dev 0:f0:0xb8 two modes are provided in the agp compensation circuitry: automatically compensate once or at regular intervals by adjusting the drive strengths of the agp interface i/o cells. in this case, bios is not required to program the drive strength values. bypass the compensation and allow bios to write drive strength values directly to the i/o cells. the AMD-761 system controller allows the agp strobe signals (adstb[1:0], adstb[1:0]#) to be controlle d independently from all other agp signals, including the ability to bypass compensation for one set of signals while the other set is compensated and vice-versa. the slew rate for the agp interface pins is also programmable by bios but is not changed by the autocompensation logic.
206 agp interface chapter 6 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information additional compensation details are provided in the following sections, and specific prog ramming recommendations are listed in section 6.3 on page 209. 6.1.1 the agp 4x dynamic compensation register agp compensation is controll ed by the agp 4x dynamic compensation register (dev 0:f0 :0xb4). this register contains additional fields that are not directly related to compensation but control various attributes of the AMD-761 system controller agp interface. this section provides additional details about the fields related to compensation. pval, nval the pval and nval are read-onl y fields that can be used to determine the drive strength values being automatically written to the agp i/o pads by the compensation logic. these apply only to the signals used for data transfer and status/control?that is, not the agp strobes. typically the values read back allow bios to determine if the correct compensation resistors are in stalled on the motherboard. quantum_cnt, always_compensate these fields are used to enable 1.5-v signalling compensation at regular intervals, which is the suggested method for all 4x agp non-strobe signals. the quantum_cnt field can be programmed for the maximum valu e (6.4 seconds), because it is not expected that a more freque nt adjustment is required. the compensation is scheduled by the AMD-761 system controller such that changing the drive stre ngth values does not interfere with agp traffic. if compensation bypass is select ed for both the data transfer and strobe pins (both the bypxfer and bypstrb bits are set in the compensation bypass register) then these fields are ignored. do_compensate, comp3.3 these bits can be used in two cases: to force a normal, single compensation cycle in 1.5-v signalling mode to update the agp i/o drive strengths, and to prevent any further updates. in this case, the do_compensate bit may be set (comp3.3 should be cleared), and the agp interfac e must not be enabled until this bit is read back as a 0, indicating that the compensation cycle is complete.
chapter 6 agp interface 207 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information to force a single compensation cycle in 3.3-v signalling mode (typically used for debug on ly). in this case, both the do_compensate and the comp3.3 bits should be set, and the agp interface must not be enabled until this bit is read back as a 0, indicating that the compensation cycle is complete. if compensation bypass is select ed for both the data transfer and strobe pins (both the bypxfer and bypstrb bits are set in the compensation bypass register) then these fields are ignored. 6.1.2 selection of 1.5- or 3.3-v agp signalling the selection of the agp signalling type (1.5 v versus 3.3 v) is done by the agp card via the typedet# pin when it is installed in the agp slot. agp cards operating in 3.3-v signalling mode have their typdet# pin unconnected. cards operating in 1.5-v signalling mo de have the pin connected to vss, forcing it to 0. the AMD-761 system controller latches the value of the typedet# pin at reset, and bios can read this value in the configuration status register (dev 0:f0:0x88, bit 25). the allowable rates at each signalling level are shown in table 33 as listed in the accelerated graphics port interface specification , revision 2.0. section 6.3 on page 209 describes the recommended initialization sequence for readin g this value and configuring various AMD-761 system controller parameters accordingly. table 33. allowable agp rate versus signalling level agp rate 1.5-v signalling 3.3-v signalling 1x supported supported 2x supported supported 4x supported not supported
208 agp interface chapter 6 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 6.2 feature override bits for agp cards the AMD-761 system controller supports 1x, 2x, and 4x agp rates as well as fast writes. the capability to support these features is normally reported to the operating system via the agp status register (dev 0:f0:0xa4) as defined by the accelerated graphics port interface specification , revision 2.0. the operating system is thus ab le to determine and select the highest rate supported by both the agp card and the AMD-761 system controller. the agp interface of the AMD-761 system controller includes two configuration bits that can be used to override the agp status register and to prevent reporting 4x and fast write capability. these bits are required to allow operation with agp cards that operate with 3.3-v signalling, but still report 4x capability to the operating syst em. the problem thus created is because the operating system at tempts to place the card and the AMD-761 system controller into 4x mode, but this speed is not supported when 3.3-v signalli ng is selected. the solution is for the AMD-761 system controlle r to report capability of a maximum of 2x agp speed in this configuration. the two override bits are de scribed below, and specific programming recommendations are listed in section 6.3. 4x_override this bit is used to force the 4x rate bit to 0 in the agp status register (dev 0:f0:0xa4, bit 2). after reset, the rate field in the agp status register is set to all 1s, indicating support for a maximum of 4x agp speed. setting the 4x_override bit automatically forces this field to 011, indicating a maximum of 2x support. this override mech anism is required because the agp status register is defined as a read-only register in the agp specification. fw_enable this bit indirectly enables fa st write support in the AMD-761 system controller. fast write support is reported to the operating system through the agp status register as described above for the rate field, but the fw status bit in the agp status register defaults to 0 (not supported) in the AMD-761 system controller. the fw_enable bit should be set if this feature is desired. section 6.3 provides guidelines for setting these bits.
chapter 6 agp interface 209 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 6.3 bios initialization requirements this section lists the steps in an algorithm recommended to properly configure the AMD-761 system controller agp fast write and rate features, as well as the compensation and slew rate values. this bios algorithm must properly detect the agp card?s signalling type (1.5 v or 3.3 v) and enable the appropriate features as listed in the steps below. note that these steps are require before the agp interface is enabled. 1. detect the signalling level (1.5 v or 3.3 v) by reading the value of the typedet# pin that was latched by the AMD-761 system controller at reset. this value can be read in the configuration status re gister, dev 0:f0:0x88, bit 25. if 0, then 1.5-v signalling is selected by the agp card. if 1, then 3.3-v signalling is used. 2. configure the override bits according to the signalling level as listed in table 34 on page 210 and the following notes. if 1.5 v, then the 4x_override bit should be cleared, and the fw_enable bit should be set in the agp 4x dynamic compensation register (dev 0:f0:0xb4, bits 6 and 7, respectively). this action causes the agp status register (dev 0:f0:0xa4) to report 4x and fast write capability to the operating system. if 3.3 v, then the 4x_override bit should be set, and the fw_enable bit should be cleared in the agp 4x dynamic compensation register (dev 0:f0:0xb4, bits 6 and 7, respectively). this action causes the agp status register (dev 0:f0:0xa4) to report a maximum rate of 2x, and no fast write capability to the operating system. 3. program the appropriate compensation, drive strength, bypass, and slew rates to the agp i/o pads in the agp 4x dynamic compensation and agp compensation bypass register according to table 34 below.
210 agp interface chapter 6 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 6.4 agp miniport driver requirements amd has found that some early generation 4x agp cards were not consistently implemented using published 4x agp guidelines for agp signal impedance and routing. these agp cards do not work reliably with the default agp drive-strengths of the AMD-761 system controller. as a result, amd has developed a mini-port solution to adjust the AMD-761 system controller agp drive strengths to the optimal levels for these early generation agp cards as id entified by the vendor and device id in pci configuration space. amd does not plan for any current or future generation agp cards to experience any incompatibilities with the amd-7 61 system controller. if a card is identified that requires a drive strength change, the amd mini-port or the agp card is updated to allow compatibility. table 34. agp i/o settings for 1.5- and 3.3-v signalling register bit/field name bits 1.5-v value typedet# = 0 3.3-v value typedet# = 1 dev 0:f0:0xb4 fw_enable [7] 1 0 4x_override [6] 0 1 comp3.3 [5] 0 0 pci [2] 0 0 always_compensate [1] 1 0 do_compensate [0] 0 0 dev 0:f0:0xb8 byp_pdrvxfer [31:28] don?t care don?t care byp_ndrvxfer [27:24] don?t care don?t care bypxfer [23] 0 0 pslewxfer [19:18] 11 11 nslewxfer [17:16] 11 11 byp_pdrvstrb [15:12] 1111 don?t care byp_ndrvstrb [11:8] 1111 don?t care bypstrb [7] 1 0 pslewstrb [3:2] 11 11 nslewstrb [1:0] 11 11
chapter 7 recommended bios settings 211 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 7 recommended bios settings this chapter provides the recommended bios settings for the initialization of some of the key AMD-761? system controller configuration registers. registers that change based on the system implementation, such as memory space and sizing, agp gart region, ddr dimm timing, etc., are not included here because they are very platform-specific. the following notes apply to the recommended settings tables in this section: all items keyed as bold capitals should be set or controlled by bios. this is mandatory . no setting can be assumed by default. refer to the actual configurat ion register descriptions for details of each bit. these can be found in ?AMD-761? system controller programmer?s interface? on page 9 of this document. the final and precise definition of bits in the spd of a ddr dimm can be found in jedec reference materials and specifications. values that are shown as x..xh or x..xb must be set by bios. numerical values shown with h or b are preferred settings. for any system enabling the s3 state, a number of core logic pci configuration registers and processor msrs must be saved or restored prior to suspending or restoring s3. also, certain hidden bits must be unmasked. these requirements apply to all platforms regardless of segment and whether or not amd powernow!? is used.
212 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 7.1 pci bus 0, device 0, function 0 registers pci bus 0, device 0, contains configuration registers that are mostly specific to the AMD-761 system controller and its processor, ddr sdram, agp, and pci bus interfaces. the bus 0, device 0 space contains two separate functions as follows: function 0 contains standa rd pci configuration space, timing and arbitration contro l for each interface, and memory decode registers. function 1 contains ddr drive strength control and calibration control for the programmable delay lines (pdls) of the dram interface.
chapter 7 recommended bios settings 213 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits register bit name initialized/ required value actual value key fcn( ) notes 0x0x0x00h pci id 31:16 device id 700eh r single-processor ddr northbridge 15:0 vendor id 1022h r amd 0x0x0x04h pci command and status 31 perr 0b r not supported 30 serr sent yb c r/w/1c, from AMD-761? system controller 29 master abrt yb u r/w/1c, from bus master 28 target abrt yb u r/w/1c, from bus master target 27 target abrts signaled 0b r not supported 26:25 devsel_timing 01b r 24 data_perr 0b r 23 fastb2b 0b r 22 udf 0b r 21 66m 0b r 20 cap_lst 1b r 19:10 reserved 000h r 9fback 0b 8 serr, system error enable yb u 0 = disable, 1 = enable 7step 0b r 6perr 0b r 5 vga palette snoop 0b r 4mwinv 0b r 3scyc 0b r 2 mstr 1b r 1 mem 1b b pci memory access enable 0 io 0b r io access disable on pci bus 0x0x0x08h pci rev id and class code 31:24 class code 06h r bridge device 23:16 sub_class code 00h r host/pci bridge 15:8 prog. i/f 00h r host/pci bridge 7:0 revision id 1yh r rev b1 = 11h, b2=12h, b3=13h key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
214 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x0ch pci latency timer and header type 31:24 reserved 00h r 23:16 header_type 00h r 15:8 lat_timer 20h b 7:0 reserved 00h r 0x0x0x10h bar0:agp virtual address space 31:25 agp base address register 0 gart agp aperture address xxxx_xxxb a 24:4 base address low 0b 00_000h r always 0 = 32 mbytes minimum 3 flags bar0 mem as prefetchable 1b r pci specification 2:1 bar0 type mem as 32 bits 00b r pci specification 0 flags bar0 as memory address space 0b r pci specification 0x0x0x14h bar1:gart memory mapped register base 31:12 gart memory mapped base address register settable portion of address xxxx_xh a 11:4 gart memory mapped base address register low, hardwired to force 4 kbytes 00h r 3 bar1 mem prefetchable 1b r pci specification 2:1 bar1 type mem as 32 bits 00b r pci specification 0 flags bar1 as memory 0b r pci specification key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 215 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x34h agp/pci capabilities pointer 31:8 reserved 000000h r 7:0 capabilities pointer a0h r agp function pointer first item in agp capabilities list 0x0x0x44h extended biu control 31:11 reserved 000h r 10:8 p0_wrdatadly yyyb r 7:4 reserved 0b r 3 p0_2bitpf 1b b must be set for amd athlon? processor 2:0 reserved 0b b must be set by bios 0x0x0x48h ecc mode/status 31:16 reserved 0000h r 15:14 serr_enable xxb b 00b = ecc/serr disabled 1xb = serr on multi_bit errors x1b = serr on single bit errors see serr# 0x0x0x4[8] 13 reserved 0b r 12 ecc_diag 0b b 0 = disable, 1= enable 11:10 ecc_mode spd # 11 xxb b spd 00b = no ecc or ecc disabled 01b = data errors reported 10b = data errors corrected for memory and pci /agp 11b = data errors corrected and memory scrubbed 9:8 ecc_status 00b b 00b = no error x1b =med multi bit error detect 1xb =sed single bit error detect r/w/1c 7:4 ecc_cs_med yh c cs of first med 3:0 ecc_cs_sed yh c cs of first sed key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
216 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x4ch pci control 31:04 reserved 0000h r 4:3 reserved 00b b must be set by bios 2 pci_dt_en 0b b 0= disable delayed transactions 1= enable delayed transactions 1pci_or_en 0b b 0= disable ordering rules compliance 1 = enable pci ordering rules compliance 0 func1_en 0b b 1= enable 0x0x1xrr access 0x0x0x50h amd athlon? system bus dynamic compensation 31:24 reserved 00h r 23:20 pval yh c p transistor value in use 19:16 nval yh c n transistor value in use 15:12 byp_p 0h b p transistor value used if byp = 1 11:8 byp_n 0h b n transistor value used if byp = 1 7:5 slewcntl 011b b 4byp 0b b 1 = enable byp_p and byp_n 3:0 reserved 0h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 217 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x54h sdram timing 31 spbwaitstate xb b fsb 0 @ 100-mhz fsb 1 @ 133-mhz fsb 30 addrtiming_a spd # 21 xb b spd 0 @ unbuffered dimm 1 @ registered dimm 29 addrtiming_b spd # 21 xb b spd 0 @ unbuffered 1 @ registered 28 rd_wait_state 1b b must = 1 27 reg_dimm_en spd # 21 xb b spd 0 @ unbuffered dimm 1 @ registered dimm 26 t wtr = write data in to read command delay 1b b 0 = 1 clock 1 = 2 clocks 25:24 t wr = write recovery time 10b b 00b=1 clock, 01b=reserved 10b=2 clocks, 11b=3 clocks 23 t rrd = active bank a to active b a n k c o m m a n d d e l a y spd # 28 xb b spd 0 = 2 clocks 1 = 3 clocks 22:19 reserved 000_0b r 18:16 idle cycle to wait before pre-charging the idle bank include bit 24 above 001b b 000 = 0 cyc, 001 = 8 cyc (safe) 010 = 12 c yc, 011 = 16 cyc 100 = 24 cyc, 101 = 32 cyc 110 = 48 cyc, 111 = disable 15:14 page hit request before a nonpage hit 10b b 00 = 1 cyc, 01 = 4 cyc 10 = 8 cyc (safe), 11 = 16 cyc 13:12 reserved 00b r 11:9 t rc = bank cycle time t ras + t rp or spd# 41(new, not yet implemented) xxxb b fsb and spd 000 = 3 cyc, 001 = 4 cyc 010 = 5 cyc, 011 = 6 cyc 100 = 7 cyc, 101 = 8 cyc (safe) 110 = 9 cyc, 111 = 10 c yc 8:7 t rp = precharge time spd # 27 xxb b fsb spd 00 = 3 cyc (safe), 01 = 2 cyc 10 = 1 cyc, 11 = 4 cyc key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
218 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 7.1.1 example settings for memory timing the table below provides example bios settings for the dram timing register, for both 100-mhz and 133-mhz bus speeds. note some register bits change based on the dimm type: u for unbuffered dimms r for registered dimms note also that spd values observ ed to date are from production dimms. future additions and changes to the spd bytes should be expected. registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x54h sdram timing 6:4 t ras = minimum bank active time spd # 30 xxxb b fsb and spd 000 = 2 cyc, 001 = 3 cyc 010 = 4 cyc, 011 = 5 cyc 100 = 6 cyc 101 = 7 cyc (safe) 110 = 8 cyc, 111 = 9 cyc 3:2 t cl = cas latency spd # 25 or # 23 or # 9 xxb b fsb and spd 00 = 3 cyc (optional on dimm, not recommended) 01 = 2 cyc, recommended 10 = 2.5 cyc, 11-reserved 1:0 t rcd ? ras to cas latency spd # 29 xxb b fsb and spd 00 = 1 cyc, 01 = 2 cyc 10 = 3 cyc (safe), 11 = 4 cyc key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 219 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information 0x0x0x54h sdram timing 100 mhz 133 mhz spd ns urur 31 spbwaitstate 0b 1b 0 @ 100 mhz , 1 @ 133 mhz fsb 30 addrtiming_a spd # 21 0b 1b 0b 1b 0 @ unbuff, 1 @ reg dimm 29 addrtiming_b, spd # 21 0b 1b 0b 1b 0 @ unbuff, 1 @ reg dimm 28 rd_wait_state 1b 1b must = 1 27 reg_dimm_en, spd # 21 0b 1b 0b 1b 0 @ unbuff, 1 @ reg dimm 26 t wtr = write data in to read cmd 1b 1b 0 = 1 clock, 1 = 2 clocks 25:24 t wr = write recovery time 10b 10b 00b=1 clock, 01b=reserved 10b=2 clocks, 11b=3 clocks 23 t rrd = a c t b n k a t o a c t b n k c m d spd # 28 0b 0b 3ch 15 0 = 2 clocks, 1 = 3 clocks 22:19 0000b 0000b 18:16 idle cycle to wait before precharging the idle bank 001b 001b 000 = 0 cyc, 001 = 8 cyc (safe) 010 = 12 cyc, 011 = 16 c yc 100 = 24 cyc, 101 = 32 cyc 110 = 48 cyc, 111 = disable 15:14 page hit request before a nonpage hit 10b 10b 00 = 1 cyc, 01 = 4 cyc 10 = 8 cyc, (safe) 11 = 16 cyc 13:12 00b 00b 11:9 t rc = bank cycle time t ras + t rp or spd# 41(new, not yet implemented) 100b 110b to 111b 41h to 46h 65 to 70 000 = 3 cyc, 001 = 4 cyc 010 = 5 cyc, 011 = 6 cyc 100 = 7 cyc, 101 = 8 cyc (safe) 110 = 9 cyc, 111 = 10 cyc 8:7 t rp = precharge time spd # 27 01b 00b 50h 20 00 = 3 cyc (safe), 01 = 2 cyc 10 = 1 cyc, 11 = 4 cyc 6:4 t ras = minimum bank active time spd # 30 011b 100b to 101b 2dh to 32h 45 to 50 000 = 2 cyc, 001 = 3 cyc 010 = 4 cyc, 011 = 5 cyc 100 = 6 cyc, 101 = 7 cyc (safe) 110 = 8 cyc, 111 = 9 cyc 3:2 t cl = cas latency spd # 25 (not available) # 23 # 9 ---- 01b 01b 10b 10b ---- ---- 01b --00b-- 10b a0h 75h a0h 75h 00 = 3 cyc (optional on dimm, not recommended) 01 = 2 cyc, recommended 10 = 2.5 cyc 11 = reserved (see 00 above.) 1:0 t rcd ? ras to cas latency spd # 29 01b 10b 50h 20 00 = 1 cyc, 01 = 2 cyc 10 = 3 cyc (safe), 11 = 4 cyc
220 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x58h sdram mode/status 31 clk_dis5 ? dimm clock 5 xb e mb 0=enable, 1=disable 30 clk_dis4 ? dimm clock 4 xb e mb 0=enable, 1=disable 29 clk_dis3 ? dimm clock 3 xb e mb 0=enable, 1=disable 28 clk_dis2 ? dimm clock 2 xb e mb 0=enable, 1=disable 27 clk_dis1 ? dimm clock 1 xb e mb 0=enable, 1=disable 26 clk_dis0 ? dimm clock 0 xb e mb 0=enable, 1=disable 25 sdram init 1b b set to start memory controller. all other memory config bits should be set before setting this bit. stays set, can be reset but not to 0. 24 reserved 0b r 23 mode register status xb b to be set before or with sdram init. causes writing of the memory mode register when sdram init is set. after setting, drops to 0 when function complete. cannot be set to 0. 22:21 str_control = suspend to ram control xxb b set <---> last power state 01b <---> moff, s4 or s5 10b <---> s3 refer to ?s3 suspend to ram state requirements? on page 190 for details. 20 burst refresh enable 0b b 0-disable, 1-enable 19 ref_dis = refresh disable 0b b 1 = disable refresh = debug bit 18 reserved 0b b 17 : 16 cycles per (between) refresh spd # 12 xxb b fsb and spd @100 mhz fsb: 00 = 2k cyc, 01 = 1.5k cyc 10 = 1k cyc, 11 = 0.75k cyc @133-mhz fsb: 00=1.5k cyc, 01=1.1k cyc 10=0.75k cyc, 11=0.37k c yc 15:8 0_0h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 221 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 7 cs7_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 6 cs6_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 5 cs5_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 4 cs4_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 3 cs3_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 2 cs2_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 1 cs1_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices 0 cs0_x4mode chip-select x4 enable spd # 13 xb b spd 0=x8/x16, 1=x4 dimm devices key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
222 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x60h biu0 status/control 31 probe enable for cpu0 1b b 0=disable, 1=enable 30:28 reserved 000b b 27:25 xca_probe_cnt 010b b 24:22 xca_rd_cnt 110b b 21:19 xca_wr_cnt 110b b 18 amd athlon system bus halt disconnect enable 0b b 0=disable 1=enable refer to ?power management? on page 185 for details. 17 amd athlon system bus stop grant disconnect enable 1b b 0=disable, 1=enable refer to ?power management? on page 185 for details. 16:14 probe limit 110b b 0-7 = 1 to 8 probes 110b = 7 recommended 13:10 ack limit 0000 = 1 un-acked command 0001 = 2....... 0011b r this field should be used to set up sysacklimit in amd athlon? (+1 to this value) (syscfg) 9 bypass_ en super bypass enable 1b b 0=disable, 1=enable 8:7 sysdc_out_ delay yyb r from init logic 6:3 sysdc_in_ delay yyyyb r from init logic 2 wr2_rd yb r from init logic 1:0 rd2_wr yyb r from init logic 0x0x0x64h biu0 sip 31 clkfwd offset 0b b 0=delay groups 1 and 3 1=no delays 30:0 ro from init/sip logic yyyb yy_yyyyh r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 223 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x70h mro status/control 31:19 reserved 0b r 18 self_ref_en 1b b enable memory self refresh for s1/s3 states. 17:11 reserved 0000000b b 10 pci pipe enable 1b b 0 = mro checks outstanding read probe before pci transactions 1 = mro pipelines pci transactions 9 pci block write enable 1b b 0 = biu does rid/inv probes, forcing mro mwq to wait for data movement 1 = biu does nop/inv probes for pci full-block writes 8:0 reserved 000h b 0x0x0x80h who am i 31:17 reserved 00b 000h r 16 biu0 present 1b c 15:8 first amd athlon system bus id 00h c 7:0 who am i 00h c key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
224 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn() notes 0x0x0x84h pci arbitration control 31:24 agp vga bios address decode 0fh a system config dependent bit 31: 0d_c000 = 0d_ ffff bit 30: 0d_8000 = 0d_bfff ? bit 24: 0c_0000 = 0c_3fff one or more of these bits should be set if an agp card has a rom bios. 23 tgt_latency 0b b 0x0x0 x84[3] 0=amd-751? system controller-compatible 1=pci maximum target latency rule. when =1, 0x0x0x84[3] must = 0. 22:18 reserved 000_00b r 17 agp chaining 1b b enabled = 1, when set cpu writes to agp are chained 16 pci chaining 1b b enabled = 1, when set cpu writes to pci are chained 15 mda support 0b a enabled = 1, allows monochrome adapter for agp device driver debug. normally 0. see AMD-761? system controller data sheet , order# 24088, for information. 14 pci write-post retry 1b b 1 = enables retry on pci if there are pending posted writes 13 agp write post retry 1b b 1 = enables retry on agp if there are pending posted writes 12 dis rd data err 1b b 0 = returns read data error to processor on master abort or target abort 1 = AMD-761? system controller returns all 1s on data read error key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 225 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 11 dis agp early probe 0b a 1 = disable early snoop from agp master running a pci cycle to memory 10 dis pci early probe 0b b 1 = disable early probe request for write cycles from an external pci master 9 dis agp arbiter pipelining 0b a 1 = disable agp arbiter from pipelining grants onto bus 8 southbridge lock disable 0b b 1 = disable flushing function performed before granting bus to the southbridge 7 pm register enable xb p 1 = enables r/w accesses to pm register at 0:0x18 bar2 ? agp power management 6 15-mbytes hole enable xb b 1 = enable a memory hole at 15-16 mbytes 5 14-mbytes hole enable xb b 1 = enable a memory hole at 14-15 mbytes 4 ev6 mode 1b b 1 = enable pci decoding in ev6 mode. used for opening buffers in 640k to 1-mbyte memory address space. legacy usb/scsi devices sometimes need this capability. 3 target latency timer disable 1b b 0x0x 0x84 [23] 1 = disable amd-751? system controller target latency timer on both pci and agp?s pci interfaces 2 apcpreen 0b b 1 = disables amd-751 system controller to prefetch data from sdram when a pci master on agp bus reads from main memory 1 pcipreen 0b b 1 = enables amd-751 system controller to prefetch data from sdram when a pci master on pci bus reads from main memory 0parkpci 0b b 0 = pci arbiter parks on processor accesses to pci 1 = enables parking on an external pci master key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
226 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ---- bits description initialized/ required value actual value key fcn( ) notes 0x0x0x88h config status 31:29 agp_clk_mux yyyb r 28:26 sys_clk_mux yyyb r 25 type_det yb r 0=1.5-v agp card signalling 1=3.3-v agp card signalling 24 s2k_thresh yb r 23 k7_pp_en 1b r 22 ig_pp_en 1b r 21:20 clk_speed yyb r fsb speed: 00b=100 mhz 01b=66 mhz 10b= reserved 11b=133 mhz 19:18 reserved yyb r 17:16 s2k_bus_len yyb r 15 tristate_en yb r 14 nand_en yb r 13 bypass_plls yb r 12 dis_divider yb r 11:8 reserved yh r 7sip_rom yb r 6 reg_dimm_en yb r 0=unbuffered, 1=registered 5 in_clk_en yb r 4out_clk_en yb r 3:0 cpu0_divider yh r 0x0x0x9ch pci top of memory 31:24 pci memory top xxh b actual memory size ad[31:24] 23:0 reserved 000_0000h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 227 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ---- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xa0h agp capability identifier 31:24 reserved 00h r 23:20 major_rev 2h r 19:16 minor_rev 0h r 15:8 next_pointer 00h r null = final item on list 7:0 cap_id 02h r 02h = agp 0x0x0xa4h agp status register 31:24 max_reqq_depth 0fh r max # agp command requests 23:10 reserved 00b 000h r 9sba 1b r side band addressing supported 8:6 reserved 000b r 5 r4g 0b r fixed at 4 gbytes maximum 4fw yb r 0x0x 0b4 [7] 1 = fast write support 0 = fast write not supported 3 reserved 0b r 2:0 rates 111b r AMD-761 system controller supports 1x/2x/4x 0x0x0xa8h agp command register 31:10 reserved 0000_0h 00b r 9 sba_ena sideband addressing enable yb o set by operating system agent, not bios. 0 = disable, 1 = enable 8 agp_ena agp operation enable yb o set by operating system agent, not bios. 0 = disable, 1 = enable 7:6 reserved 0b r 5 greater than 4g address support 0b r 0 = disable, 1 = enable 4 fast_writes yb o 0x0x0 b4[7] 0=disabled, 1=enabled 3 reserved 0b r 2:0 agp data transfer mode yyyb o 001b=1x, 010b=2x,100b=4x key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
228 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xach agp virtual address space size register 31:17 reserved yyyb 000h r 16 vga_ia_en xb b 0 = no isa aliasing on address [15:0] 1 = force amd-751? system controller to alias isa address [15:0] 15:4 reserved 000h r 3:1 va_size agp aperture size xxxb a 000 = 32 mbytes 001 = 64 mbytes 010 = 128 mbytes 011 = 256 mbytes 100 = 512 mbytes 101 = 1 gbyte 110 = 2 gbytes 128 mbytes recommended 0 gartena agp aperture base address enable xb a 0 = disable register 1 = enable register 0:0x10 (bar0) and start gart 0x0x0xb0h gart/agp mode control 31:21 reserved 00h 000b r 20 reserved 0b b 19 nongart snoop 0b b debug/performance register 0 = disable probes 1 = enable probes 18 reserved 0b b 17 gart page directory cache enable 0b b debug/performance register 0 = disable, 1 = enable 16 gart index scheme control yb o 0 = 2-level, 1 = 1-level mode 15:0 reserved 00h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 229 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xb4h agp 4x dynamic compensation 31:28 p val yh c p transistor strength, xfer i/o pads 27:24 nval yh c n transistor strength, xfer i/o pad 23 reserved 0b r 22 disstrb 0b a 1=disable adstb[1:0}# 21:16 quantum_cnt 000001b a 100-ms intervals for always_compensate 15:8 reserved 00h r 7 fw_enable xb a b4/bf 0=disable, 1=enable controls 0x0x0xa4h[4] and 0x0x0xa8h[4] refer to ?feature override bits for agp cards? on page 208 for details. 6 4x_override xb a b4/bf 0=disabled, 1=enabled -> forces 0x0x0xa4h[0]->010b->2x agp refer to ?feature override bits for agp cards? on page 208 for details. 5 comp3.3 0b a do_compensate=1 shows pval and nval when comp3.3 =1 with 3.3-v agp cards 4:3 reserved 0b r 2pci drive strength 0b a normally = 0 1 always_compensate xb a b4/bb 0=disable, 1=enable refer to ?agp interface? on page 205 for details. 0do_compensate 0b a set to init dynamic compensation clears when finished key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
230 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xb8h agp compensation bypass 31:28 byp_pdrvxfer xh a b4/bb p drive bypass value for data refer to ?bios initialization requirements? on page 209 for details. 27:24 byp_ndrvxfer xh a b4/bb n drive bypass value for data refer to ?bios initialization requirements? on page 209 for details. 23 bypxfer xb a b4/bb 1=enable drive bypass for data refer to ?bios initialization requirements? on page 209 for details. 22:20 reserved 000b r 19:18 byp_pslewxfer xxb a b4/bb p slew rate value for data refer to ?bios initialization requirements? on page 209 for details. 17:16 byp_nslewxfer xxb a b4/bb n slew rate value for data refer to ?bios initialization requirements? on page 209 for details. 15:12 byp_pdrvstrb xh a b4/bb p drive bypass value for strobes refer to ?bios initialization requirements? on page 209 for details. 11:8 byp_ndrvstrb xh a b4/bb n drive bypass value for strobes refer to ?bios initialization requirements? on page 209 for details. key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 231 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 7bypstrb xb a b4/bb 1=enable drive bypass for strobes refer to ?bios initialization requirements? on page 209 for details. 6:4 reserved 000b r 3:2 byp_pslewstrb xxb a b4/bb p slew rate value for strobes refer to ?bios initialization requirements? on page 209 for details. 1:0 byp_nslewstrb xxb a b4/bb n slew rate value for strobes refer to ?bios initialization requirements? on page 209 for details. key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
232 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 7.1.2 examples: agp compensation register settings (0xb4-0xbb) typedet# 0x0x0x88[25] type_det = 1 indicates that a card in the agp slot is a 3.3-v signalling card, which supports 2x agp maximum. a 3.3-v signalling card cannot run above 2x agp. type_det = 0 indicates that a card in the agp slot is a 1.5-v signalling card, which supports 4x agp maximum. a 1.5-v signalling card can run at 1x, 2x, or 4x agp rates. refer to ?agp interface? on page 205 for details on how the value of the type_det bit and the settings of the agp compensation register affect the settings in agp compensation bypass register. type_det = 1 2x agp maximum type_det =1 == 3.3-v card in agp slot 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh no option 48h 00h 01h c5h 0fh ffh 0fh c5h type_det = 0 4x agp maximum, reduced to 2x agp with 4x_override 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 1 4ah 00h 01h d8h 8fh ffh 04h d8h 4x_override and always_compensate 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 2 48h 00h 01h d8h 8fh ffh 84h d8h 4x_override and bypass type_det = 0 4xagp maximum, options of always compensate, bypass and fast writes 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 1 02h 00h 01h d8h 8fh ffh 04h d8h always_compensate 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 2 82h 00h 01h d8h 8fh ffh 04h d8h always compensate and fast writes 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 3 00h 00h 01h d8h 8fh ffh 84h d8h bypass 0x0x0x.. b4h b5h b6h b7h b8h b9h bah bbh option 4 80h 00h 01h d8h 8fh ffh 84h d8h bypass and fast writes
chapter 7 recommended bios settings 233 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xc0h memory base address register 0 31:23 cs_base chip-select base 0 bank 0 base address starting address of the bank map to ad[31:23] xxh xb b set by memory sizing routines 0000_0000_0b = 0 0000_0001_0b = 16 mbytes 0000_0010_0b = 32 mbytes 0000_0011_0b = 48 mbytes 0000_1000_0b = 128 mbytes 0001_0000_0b = 256 mbytes 0010_0000_0b = 512 mbytes, etc. 22:16 reserved 000b 0h r 15:7 cs_mask chip-select mask 0 bank 0 address mask sizes the bank map to ad[31:23] xxh xb b set by memory sizing routines 0000_0000_1b = 16 mbytes 0000_0001_1b = 32 mbytes 0000_0011_1b = 64 mbytes 0000_0111_1b = 128 mbytes 0000_1111_1b = 256 mbytes 0001_1111_1b = 512 mbytes 0011_1111_1b = 1 gbyte 0111_1111_1b = 1 gbyte 6:3 reserved 0h r 2:1 addr_mode size of device = size of bank x (primary sdram width /8) xxb b spd # 31 and 13 01b=sdram device <256 mbits 10b=sdram device >128 mbits 00b and 11b are reserved 0 enable/disable bank 1 xb b 0=disable cs, 1=enable cs 0x0x0xc4h memory base address register 1 31:23 chip-select base 1 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 1 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 1 xb b as 0x0x0xc0h above key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
234 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information memory rules 1. memory must be organized so that the largest banks occupy the lowest addresses. 2. all memory registers must be initialized, even when they are 0 memory registers do not default to 0. 3. unbuffered memories can be configured two deep, registered memories can be configured four deep. in all cases, unused memory registers must be zeroed. registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xc8h memory base address register 2 31:23 chip-select base 2 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 2 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 2 xb b as 0x0x0xc0h above 0x0x0xcch memory base address register 3 31:23 chip-select base 3 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 3 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 3 xb b as 0x0x0xc0h above key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 235 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x0xd0h memory base address register 4 31:23 chip-select base 4 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 4 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 4 xb b as 0x0x0xc0h above 0x0x0xd4h memory base address register 5 31:23 chip-select base 5 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 5 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 5 xb b as 0x0x0xc0h above 0x0x0xd8h memory base address register 6 31:23 chip-select base 6 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 6 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 6 xb b as 0x0x0xc0h above 0x0x0xdch memory base address register 7 31:23 chip-select base 7 xxh xb b as 0x0x0xc0h above 22:16 reserved 000b 0h r as 0x0x0xc0h above 15:7 chip-select mask 7 xxh xb b as 0x0x0xc0h above 6:3 reserved 0h r as 0x0x0xc0h above 2:1 addr_mode xxb b as 0x0x0xc0h above 0 enable/disable bank 7 xb b as 0x0x0xc0h above key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
236 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 7.1.3 pci bus 0, device 0, function 1 registers the device 0, function 1 registers are used for the purpose of controlling the ddr sdram interface drive strengths, and calibration of the programmable delay lines (pdls). all function 1 register bits are defaulted to an unknown value as required for the AMD-761 syst em controller to support the advanced configuration and power interface (acpi) s3 (suspend to ram) state. for proper operation, it is absolutely necessary that bios initialize all function 1 register bits. please obtain the AMD-761? system controller revision guide , order# 23613, for the most current information for each silicon revision.
chapter 7 recommended bios settings 237 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x40h ddr pdl calibration control 31:8 reserved 0000_000h r 7 sw_recal set after setting sw_cal_dly 0b b write 1=>calibration 0=calibration complete 1=calibration not complete 6 use_act_dly use actual delay 0b b 0=disable, 1=enable sw_recal and auto_cal_en must = 0 when use_act_dly = 1 5 auto_cal_en auto calibration mode 1b b 0=disable 1=enable refer to AMD-761? system controller revision guide , order# 23613, for special instructions for revision b2 silicon. 4 act_dly_inh actual delay update inhibit 0b b 0=disable 1=enable refer to AMD-761? system controller revision guide , order# 23613, for special instructions for revision b2 silicon. 3:2 reserved 00b r 1:0 auto_cal_period auto-calibration period 01b b 00=10000 system clocks 01=1000000 system clocks 10=10000000 system clocks 11=reserved 0x0x1x44h ddr pdl configuration register 0 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
238 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x48h ddr pdl configuration register 1 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x4ch ddr pdl configuration register 2 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x50h ddr pdl configuration register 3 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x54h ddr pdl configuration register 4 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x58h ddr pdl configuration register 5 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 239 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x5ch ddr pdl configuration register 6 31:24 clk_dly yyh c half period of the sys. clk. 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x60h ddr pdl configuration register 7 31:24 clk_dly yyh c half period of the sys. clk. 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x64h ddr pdl configuration register 8 31:24 clk_dly yyh c half period of the sys. clk. 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x68h ddr pdl configuration register 9 31:24 clk_dly yyh c half period of the sys. clk. 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x6ch ddr pdl configuration register 10 31:24 clk_dly yyh c half period of the sys. clk. 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
240 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x70h ddr pdl config register 11 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x74h ddr pdl config register 12 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x78h ddr pdl config register 13 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x7ch ddr pdl config register 14 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 241 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x8h ddr pdl config register 15 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x8h ddr pdl config register 16 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write 0x0x1x8h ddr pdl config register 17 31:24 clk_dly yyh c half period of the system clock 23:16 sw_cal_dly xxh b fsb delay for dqs: 100 mhz = 69h 133 mhz = 6bh 15:8 cal_dly yyh c sw_cal_dly in # of buffers 7:0 act_dly xxh c from sw_recal or direct write key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
242 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x8ch ddr dqs/mdat pad config 31:30 reserved 00b r 29:27 pslewm dat 101b b slowest 000b <-> 111b fastest mdat rising edge slew rate 26:24 nslewmdat 101b b slowest 000b <-> 111b fastest mdat falling edge slew rate 23:20 reserved 0h r 19:18 pdrvm dat 11b b weakest 00b<->11b strongest mdat p transistor drv strength 17 : 16 n d r v m d at 10 b b weakest 00b<->11b strongest mdat n transistor drv strength 15:14 reserved 00b r 13:11 pslewdqs 101b b slowest 000b <-> 111b fastest dqs rising edge slew rate 10:8 nslewdqs 101b b slowest 000b <-> 111b fastest dqs falling edge slew rate 7:4 reserved 0h r 3:2 pdrvdqs 11b b weakest 00b<->11b strongest dqs p transistor drv strength 1:0 ndrvdqs 10b b weakest 00b<->11b strongest dqs n transistor drv strength key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 243 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x90h ddr clk/cs pad configuration 31:30 reserved 00b r 29:27 pslewclk 101b b slowest 000b <-> 111b fastest clk rising edge slew rate 26:24 nslewclk 101b b slowest 000b <-> 111b fastest clk falling edge slew rate 23:20 reserved 0h r 19:18 pdrvclk 11b b weakest 00b<->11b strongest clk p transistor drv strength 17 : 16 n d r v c l k 10 b b weakest 00b<->11b strongest clk n transistor drv strength 15:14 reserved 00b r 13:11 pslewcs 101b b slowest 000b <-> 111b fastest cs rising edge slew rate 10:8 nslewcs 101b b slowest 000b <-> 111b fastest cs falling edge slew rate 7:4 reserved 0h r 3:2 pdrvcs 11b b weakest 00b<->11b strongest cs p transistor drv strength 1:0 ndrvcs 10b b weakest 00b<->11b strongest cs n transistor drv strength key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
244 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x94h ddr cmdb/cmda pad configuration 31:30 reserved 00b r 29:27 pslewcmdb 101b b slowest 000b <-> 111b fastest cmdb rising edge slew rate 26:24 nslewcmdb 101b b slowest 000b <-> 111b fastest cmdb falling edge slew rate 23:20 reserved 0h r 19:18 pdrvcmdb 11b b weakest 00b<->11b strongest cmdb p transistor drv strength 17 : 16 n d r v c m d b 10 b b weakest 00b<->11b strongest cmdb n transistor drv strength 15:14 reserved 00b r 13:11 pslewcmda 101b b slowest 000b <-> 111b fastest cmda rising edge slew rate 10:8 nslewcmda 101b b slowest 000b <-> 111b fastest cmda falling edge slew rate 7:4 reserved 0h r 3:2 pdrvcmda 11b b weakest 00b<->11b strongest cmda p transistor drv strength 1:0 ndrvcmda 10b b weakest 00b<->11b strongest cmda n transistor drv strength key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 245 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x0x1x98h ddr maa/mab pad configuration 31:30 reserved 00b r 29:27 pslewmab 101b b slowest 000b <-> 111b fastest mab rising edge slew rate 26:24 nslewmab 101b b slowest 000b <-> 111b fastest mab falling edge slew rate 23:20 reserved 0h r 19:18 pdrvmab 11b b weakest 00b<->11b strongest mab p transistor drv strength 17 : 16 n d r v m a b 10 b b weakest 00b<->11b strongest mab n transistor drv strength 15:14 reserved 00b r 13:11 pslewma a 101b b slowest 000b <-> 111b fastest maa rising edge slew rate 10:8 nslewma a 101b b slowest 000b <-> 111b fastest maa falling edge slew rate 7:4 reserved 0h r 3:2 pdrvmaa 11b b weakest 00b<->11b strongest maa p transistor drv strength 1:0 ndrvmaa 10b b weakest 00b<->11b strongest maa n transistor drv strength key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
246 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information 7.2 pci bus 0, device 1, function 0 registers device 1 registers provide the necessary controls for the AMD-761 system controller?s internal pci-to-pci bridge and agp controller functions. the pci to pci bridge functions as a logical bridge between the host pci bus and the agp interface and contains the normal pci configuration registers for su ch a device. most of these bits are read-only.
chapter 7 recommended bios settings 247 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x1x0x00h pci id 31:16 device id 700fh r AMD-761? system controller 15:0 vendor id 1022h r amd 0x1x0x04h pci command and status 31 perr_rcv 0b r not supported 30 serr sent yb u r/w/1c, from AMD-761 system controller 29 master abrt 0b r r/w/1c, from bus master 28 target abrt 0b r r/w/1c, from bus master target 27 target abrts signaled 0b r not supported 26:25 devsel_timing 01b r 24 data_perr 0b r 23 fastb2b 0b r 22 udf 0b r 21 66m 1b r support 66 mhz on device 1 20 cap_lst 0b r 19:10 reserved 00b 00h r 9fback 0b 8 serr, system error enable yb u 0 = disable, 1 = enable 7step 0b r 6perr 0b r 5 vga palette snoop 0b r 4mwinv 0b r 3scyc 0b r 2 mstr 1b b dma enabled on apci 1mem 1b b memory access enable on apci 0io 1b b io access enabled on apci 0x1x0x08h pci rev id and class code 31:24 class code 06h r bridge device 23:16 sub_class code 04h r host/pci bridge 15:8 prog. i/f 00h r host/pci bridge 7:0 revision id 00h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
248 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x1x0x0ch agp/pci header type 31:24 reserved 00h r 23:16 header_type 01h r 15:8 pri_lat_timer 40h b 7:0 reserved 00h r 0x1x0x18h agp/pci sub bus num/ secondary latency timer 31:24 secon_lat_timer 40h b 23:16 sub_bus_num 01h b 15:8 secon_bus_num 01h b 7:0 pri_bus_num 00h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 249 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x1x0x1ch pci command and status 31 perr_rcv 0b r not supported 30 serr_rcv yb u r/w/1c from AMD-761? system controller 29 master abrt yb u r/w/1c from bus master 28 target abrt yb u r/w/1c from bus master target 27 target abrts signaled 0b r not supported 26:25 devsel_timing 01b r 24 data_perr 0b r 23 fastb2b 0b r 22 udf 0b r 21 66m 1b r 20 cap_lst 0b r 19:16 reserved 0h r 15:12 io_lim[15:12] xh b upper 4 bits defining top address that is used by the bridge to forward i/o transactions from one interface to another. 11:8 iolimit_r 1h r lower 4 bits defining top address that is used by the bridge to forward i/o transactions from one interface to another. 0x1 indicates that 32 bit i/o address decoding is available 7:4 iobase [15:12] xh b writable 4 bits that defines bottom address that is used by the bridge to forward i/o transactions from one interface to another. 3:0 iobase_r 1h r lower 4 bits defining bottom address that is used by the bridge to forward i/o transactions from one interface to another. 0x1 indicates that 32 bit i/o address decoding is available. key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
250 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x1x0x20h agp/pci memory limit and base 31:20 mlim[31:20] xxxh b memory limit address defining top address to be used by agp target graphics controller for control registers and buffers. the lower 20 bits are 0xfffff for 1-mbyte granularity. 19:16 reserved 0h r 15:4 mbase[31:20] xxxh b memory limit address defining lower address to be used by agp target graphics controller for control registers and buffers. the lower 20 bits are 0xfffff for 1-mbyte granularity. 3:0 reserved 0h r 0x1x0x24h agp/pci prefetchable memory limit and base 31:20 mlim [31:20] xxxh b prefetchable memory limit address defining top address to be used by agp target graphics controller for control registers and buffers. the lower 20 bits are 0xfffff for 1-mbyte granularity. 19:16 0h r 15:4 mbase [31:20] xxxh b prefetchable memory base address defining lower address to be used by agp target graphics controller for control registers and buffers. the lower 20 bits are 0xfffff for 1-mbyte granularity. 3:0 reserved 0h r key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
chapter 7 recommended bios settings 251 24081d?february 2002 AMD-761? system controller software/bios design guide preliminary information registers ----- bits description initialized/ required value actual value key fcn( ) notes 0x1x0x30h agp/pci i/o limit and base 31:24 reserved 00h r 23:16 io_ lim [23:16] xxh b this field defines the upper limit (inclusive) of the 24bit i/o addresses passed to the agp/pci bus. 15:8 reserved 00h r 7:0 io_ base [23:16] xxh b this field defines the base (inclusive) of the 24bit i/o addresses passed to the agp/pci bus. 0x1x0x3ch agp/pci interrupt and bridge control 31:24 reserved 00h r 23 bridge_fast_b2b_en 0b r 22 secon_bus_ reset 0b r 21 mas_abort_mode 0b r 20 reserved 0b r 19 vga_en 1b b 18 isa_en 0b b 17 serr_en yb u 16 par_resp_en 0b r 15:8 int_pin xxh b enabled by 0x1x0x40[0] 7:0 int_line xxh b 0x1x0x40h miscellaneous device 1 control 31:1 reserved 000b 0000000h r 0 int_pin_cntl xb b 1=enable 0x1x0x3c[15:8] key: b= mandatory bios function a= agp setup by bios c = calculated/set by AMD-761? internal logic p= power management setup by bios o = setup by os or os driver f = performance enhancement set by bios r = hardcoded and reserved u = pci operational user interface e = elective bios function
252 recommended bios settings chapter 7 AMD-761? system controller software/bios design guide 24081d?february 2002 preliminary information

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