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| data sheet music semiconductors, the music logo, and the phrase "music semiconductors" are january 9, 2001 rev. 3 registered trademarks of music semiconductors. music is a trademark of music semiconductors. application benefits ? high performance mac address processor for multiport switches and routers (up to 48 10/100 or 4 gigabit ethernet at wire speed) ? layer 4 flow recognition for quality of service up to 16.7 million packets per second ? arp cache manager/ip address caching at 12.5 million packets per second ? synchronous interfaces and programmable priority between ports for simplicity of design ? learn, age, and auto-age functions with virtual queues, keeping track of aged and learned entries ? transparent cascade of up to four 2k devices without external logic, software setup, or performance hit distinctive characteristics ? 2k and 8k x 80-bit partitionable cam/ram data field in address database ? 32-bit synchronous port with separate inputs and outputs; optional 16-bit configuration ? 32-bit bi-directional processor port; optional 16-bit configuration ? pipelined operation ? operations performed from the synchronous port or processor port; all flags independently available to both ports ? 9-bit internal time stamp ? 50 mhz clock ? 388-pin pbga (8k) and 160-pin pqfp (2k) packages. ? 3.3 volt core with 3.3 volt/5 volt tolerant io buffers. ? ieee 1149.1 (jtag) compliant figure 1: block diagram -- b i t 79 -- ------- ------- b i t 0--- 80-bit la tch 80-bit la tch 80 to 32/16-bit mux 80 to 32/16-bit mux 80-bit latch 80-bit 2 to 1 mux 16/32 to 80-bit mux control jtag sync port dout(31:0) processor port din(31:0) op(3:0) /dine dinready /oe /doute /doutvalid tdi tms tck trst 16/32 to 80-bit mux tdo procd(31:0) proca(5:0) /pcs r/w procready int /reset clk sync port din(31:0) /ff /mf chain chainup chaindn /chaincs processor port dout(31:0) address data base flag and chain logic 80-bit latch muaa routing coprocessor (rcp) family muaa routing coprocessor (rcp) family muaa routing coprocessor (rcp) family muaa routing coprocessor (rcp) family
muaa routing coprocessor (rcp) family general description 2 rev. 3 general description the music muaa routing coprocessor (rcp) family consists of 80-bit wide content-addressable memories (cams), available in depths of 2k and 8k words. the cam/ram associated data partition is programmable from 32 bits of cam and 48 bits of associated data, to 80 bits of cam and 0 bits of ram. the muaa rcp can perform normal routing functions such as search, insert, and delete on single entries and can age multiple entries simultaneously. in addition, there is a learn instruction, particularly useful in networking applications. for maximum flexibility all the operations may be performed either through the processor port or through the synchronous port. operations may occur on both ports simultaneously; the port with the highest priority will gain access first if both ports require a read or write into the cam array simultaneously. the synchronous interface consists of 32-bit wide input and output ports, both of which may be configured as 16 bits. the data is multiplexed into and out of the cam and ram associated data field. where input or output data is wider than the port, it is loaded or unloaded in multiple cycles starting with the least significant word. internally the device is pipelined; once an operation is started on the synchronous port the next operation may be loaded and the results of the previous operation unloaded, thus maximizing device throughput. multiple 2k muaa rcps may be chained transparently to provide deeper memory. no software configuration is necessary. each muaa rcp detects where it is in the chain from the chaining pins on the previous device. a register is provided to inform the host of the total available cam memory and the number of cams chained. all operations to the chained cam are totally transparent. no individual device selection or addressing is required. the music muaa rcp has aging, auto-aging, and learning functions. all entries have a 9-bit time stamp and may be marked as static to prevent the aging function from deleting them. when auto aging is enabled it may be configured to have higher or lower priority access than the ports. two internal virtual queues of learned and aged entries are available. as entries are learned or aged out they are tagged as such and may be read from the device through either of the ports. this feature enables simple host management of aged out and learned entries. ieee standard. 1149.1 (jtag) testability is implemented providing bypass, sample/preload, extest, clamp, and high-z functions. pin descriptions muaa routing coprocessor (rcp) family rev. 3 3 pin descriptions note: signal names that start with a slash (/) are active low. all signals are 3.3 volt cmos level. all input and bi-directional pi ns are 5-volt tolerant, except for clk. never leave inputs floating except where indicated. the cam architecture draws large curre nts during search operations, mandating the use of good layout and bypassing techniques. refer to the electrical characteristics se ction for more information. see table 1 for the 388-pin balls and the packages section for the chip illustrations. figure 2: 160-pin pqfp (top view) din[31:0] (input) din[31:0] are synchronous port data input pins. data is loaded into the muaa rcp right aligned, least significant word first. /dine (input) din is sampled by the rising edge of clk when /dine is asserted. refer to table 1 for slave connections. op[3:0] (input) op[3:0] is a synchronous port operation to be performed on the data applied to the din pins. op is sampled by the rising edge of clk when /dine is asserted. when loading the cam/ram words to din, op is set to load except for the last word. op for the last word is set to the desired operation. dinready (output) when dinready is high, the synchronous port accepted the current operation. this is affected by the priority set for the din port and the processor port. note, dinready may be low for up to 800 clk periods after /reset is taken high. the jtag interface is able to set dinready to high-z. active high. dout[31:0] (3-state output) dout[31:0] is the synchronous port data output. data is read out right aligned, least significant word first. the address index (bits 25C0), swex flag (bit 26), pwex flag (bit 27), lqueue flag (bit 28), aqueue flag (bit 29), sync port match flag (bit 30), and full flag (bit 31) may also be read from this port before or after operation data depending on configuration. 160-pin pqfp 160 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 81 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 gn d vcc dout0 gn d din 30 din 29 din 28 din 27 gn d din 26 din 25 din 24 din 21 vcc din 20 din 19 din 17 din 16 din 15 din 14 din 13 din 12 din 11 din 10 di n9 di n8 di n7 vcc di n6 di n5 di n4 di n3 di n2 di n1 di n0 vcc vcc clk gn d /mf /f f /dou tval id din re ad y in t procr eady tdo gn d tdi tms tck /trst /oe /dout e /d in e op0 op1 op2 op3 vcc proca0 proca1 proca2 proca3 proca4 proca5 r/w /pcs /reset gn d procd0 procd1 procd2 procd3 procd4 gn d gn d dout1 dout2 dout3 dout4 dout5 dout6 dout7 gn d dout8 dout9 dout10 dout11 vcc dout12 dout13 dout14 dout15 gn d dout16 dout17 dout18 dout19 vcc dout20 dout21 dout22 dout23 gn d dout24 dout25 dout26 dout27 vcc dout28 dout29 dout30 dout31 gn d vcc cha ind n cha inup gn d cha in3 cha in2 cha in1 cha in0 procd31 gn d procd30 procd29 procd28 procd27 procd26 procd25 procd24 vcc procd23 procd22 procd21 procd20 procd19 procd18 gn d procd17 procd16 procd15 procd14 procd13 procd12 vcc procd11 procd10 procd9 procd8 procd7 procd6 gn d din 18 din 22 din 23 din 31 vcc procd5 chai ncs muaa routing coprocessor (rcp) family pin descriptions 4 rev. 3 /doutvalid (output) /doutvalid indicates when new data is available at the synchronous output port. /doutvalid is active low for one clk cycle. /doutvalid may be configured to become active on the same clock as new dout becomes valid or the clk before. the jtag interface is able to set /doutvalid to high-z. /oe (input) /oe is the dout high impedance control. /doute (input) /doute is the dout enable control. when the dout data word is configured to be wider than the output port then this strobe enables the next word(s) of the dout data onto the dout pins. procd[31:0] (bi-directional) the bi-directional processor data port provides the processor interface to the device. on write cycles all devices respond in parallel. on read cycles the appropriate device responds without additional intervention from the processor. proca[5:0] (input) processor port address bus. selects which device register is accessed. bit 0 is only used when the port is set to 16-bit mode, otherwise it should be held at a valid logic level. r/w (input) r/w is the processor port read/write control pin. this pin is high for reads, low for writes. /pcs (input) /pcs is the processor port chip select pin. when low this pin indicates a cycle to the processor port. on write cycles data must be set up to the rising edge of /pcs. on read cycles /pcs controls the output enable of the procd bus. note that /pcs may be asynchronous to clk. refer to table 1 for slave connections. procready (output) when procready is high, indicates the processor read data is available or the processor write data is accepted. priority may be set between the din port and the processor port. note procready may be low for up to 800 clk periods after /reset is taken high. the jtag interface is able to set procready to high-z. int (output) int interrupt. indicates the aged or learned queue has at least one entry or a write exception occurred. the service routine should either check the aqueue, lqueue, and wex registers, or bits 26C29 of the address index register, to determine the cause. the interrupt is cleared after the appropriate flag register has been read and will not be reasserted until either the queue(s) are emptied and then get at least one entry again, or another write exception occurs. the jtag interface is able to set int to high-z. /reset (input) the /reset input is used to reset the muaa rcp. /reset must be asserted for at least 3 clk periods. clk (input) the rising edge of clk input is the device clock. /ff (full flag, output) /ff is active when the device (or chain of devices) is full. /ff becomes inactive when any one device has two open entries. the jtag interface is able to set /ff to high-z. chain[3:0 (input) when two or more devices are chained they communicate among themselves using the chain[3:0] signals. see chaining section. internally pulled-up. refer to table 1 for slave connections. chainup (output) when two or more devices are chained they communicate among themselves using the chainup signals. see chaining section. the jtag interface is able to set chainup to high-z. refer to table 1 for slave connections. chaindn (output) when two or more devices are chained they communicate among themselves using the chaindn signals. see chaining section. the jtag interface is able to set chaindown to high-z. refer to table 1 for slave connections. chaincs (bi-directional) when two or more devices are chained they communicate among themselves using the chaincs signals. see chaining section. internally pulled up. refer to table 1 for slave connections. /mf (match flag, output) the /mf output indicates whether a match was found. the jtag interface is able to set /mf to high-z. /trst (jtag reset, input) the /trst is the test reset pin. internally pulled up with 25k minimum. must be tied to /reset or tied low when not in use. /tclk (jtag test clock, input) the /tclk input is the test clock input. must be tied at a valid logic level when not in use. tms (jtag test mode select, input) the tms input is the test mode select input. internally pulled up with 25k minimum. pin descriptions muaa routing coprocessor (rcp) family rev. 3 5 tdi (jtag test data input, input) the tdi input is the test data input. internally pulled up with 25k minimum. refer to table 1 for slave connections. tdo (jtag test data output, output) the tdo output is the test data output. refer to table 1 for slave connections. vcc, gnd these pins are the power supply connection to the muaa rcp. vcc must meet the voltage supply requirements in the operating conditions section relative to the gnd pins, which are at 0 volts (system reference potential), for correct operation of the device. all the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. ball descriptions table 1: ball descriptions functional group ball name(s) function type pbga ball(s) synchronous input port din[31:0] synchronous port data input. input 5v tol b0:aa26, b1:aa25, b2:y26, b3:y25, b4:w26, b5:w25, b6:v26, b7:v25, b8:u26, b9:u25, b10:t26, b11:t25, b12:r26, b13:r25, b14:p26, b15:p25, b16:n26, b17:n25, b18:m26, b19:m25, b20:l26, b21:l25, b22:k26, b23:k25, b24:j26, b25:j25, b26:h26, b27:h25, b28:g26, b29:g25, b30:f26, b31:f25 /dine when asserted, din is sampled by the rising edge of clk. connect to t2, r2, and p2. input 5v tol t1 /dine-s1 slave 1. connect to t1, /dine. input 5v tol t2 /dine-s2 slave 2. connect to t1, /dine. input 5v tol r2 /dine-s3 slave 3. connect to t1, /dine. input 5v tol p2 op[3:0] synchronous port operation performed on data applied to din pins. input 5v tol b0:u1, b1:u2, b2:u3, b3:t3 dinready when high, indicates the synchronous port accepted the current operation. output h1 clk rising edge is the device clock. input 3.3v only d1 synchronous output port dout[31:0] synchronous port data output. output b0:a21, b1:b21, b2:a20, b3:b20, b4:a19, b5:b19, b6:a18, b7:b18, b8:a17, b9:b17, b10:a16, b11:b16, b12:a15, b13:b15, b14:a14, b15:b14, b16:a13, b17:b13, b18:a12, b19:b12, b20:a11, b21:b11, b22:a10, b23:b10, b24:a9, b25:b9, b26:a8, b27:b8, b28:a7, b29:b7, b30:a6, b31:b6 /doutvalid indicates when new data is available at the synchronous output port. output g1 /oe dout high impedance control. input 5v tol p1 /doute dout enable control. input 5v tol r1 /mf match flag. indicates if a match was found. output e1 muaa routing coprocessor (rcp) family pin descriptions 6 rev. 3 processor port procd[31:0] processor port data. bidir 5v tol b0:ab1, b1:ab2, b2:ac1, b3:ac2, b4:af3, b5:ae3, b6:af4, b7:ae4, b8:af5, b9:ae5, b10:af6, b11:ae6, b12:af7, b13:ae7, b14:af8, b15:ae8, b16:af9, b17:ae9, b18:af10, b19:ae10, b20:af11, b21:ae11, b22:af12, b23:ae12, b24:af13, b25:ae13, b26:af14, b27:ae14, b28:af15, b29:ae15, b30:af16, b31:ae16 proca[5:0] processor port address bus. input 5v tol b0:w1, b1:w2, b2:w3, b3:y1, b4:y2, b5:y3 r/w processor port read/write control input 5v tol v2 /pcs processor port chip select. connect to aa2, aa3, and ab3. input 5v tol aa1 /pcs-s1 slave 1. connect to aa1, /pcs. input 5v tol aa2 /pcs-s2 slave 2. connect to aa1, /pcs. input 5v tol aa3 /pcs-s3 slave 3. connect to aa1, /pcs. input 5v tol ab3 procready when high, indicates the processor read data is available or the processor write data is accepted. output k1 int int interrupt. indicates the aged or learned queue has at least one entry or a write exception occurred. output j1 /reset resets the muaa rcp. input 5v tol v1 /ff full flag. active when the device (or chain of devices) is full output f1 table 1: ball descriptions (continued) functional group ball name(s) function type pbga ball(s) pin descriptions muaa routing coprocessor (rcp) family rev. 3 7 cascade chain0 nc. for music production test only. input af18 chain1 internal chaining. connect to ae19, chainup-s1. input af19 chain2 internal chaining. connect to ae20, chainup-s2. input af20 chain3 internal chaining. connect to ae21, chainup-s3. input af21 chain0d internal chaining. connect to af23, chaindn. input ae22 chain1d internal chaining. connect to ae23, chaindn-s1. input ad22 chain2d internal chaining. connect to ad23, chaindn-s2. input ac22 chainup nc. for music production test only. output af22 chainup-s1 internal chaining. connect to af19, chain1. output ae19 chainup-s2 internal chaining. connect to af20, chain2. output ae20 chainup-s3 internal chaining. connect to af21, chain3. output ae21 chaindn internal chaining. connect to ae22, chain0d. output af23 chaindn-s1 internal chaining. connect to ad22, chain1d. output ae23 chaindn-s2 internal chaining. connect to ac22, chain2d. output ad23 chaind-s3 nc. for music production test only. output ac23 chaincs internal chaining. connect to ae17, ad17, and ac17. bidir af17 chaincs-s1 internal chaining. connect to af17. bidir ae17 chaincs-s2 internal chaining. connect to af17. bidir ad17 chaincs-s3 internal chaining. connect to af17. bidir ac17 chain1x nc. for music production test only. input ae18 chain2x nc. for music production test only. input ad18 chain3x nc. for music production test only. input ac18 jtag /trst test reset. input n3 tclk test clock input. input n2 tms test mode select. input n1 tdi test data input. input m1 tdi-a internal jtag chain. connect to l2, tdo-a. input m2 tdi-b internal jtag chain. connect to l3, tdo-b. input m3 tdi-c internal jtag chain. connect to l3, tdo-c. input m4 tdo test data output. output l1 tdo-a internal jtag chain. connect to m2, tdi-a. output l2 tdo-b internal jtag chain. connect to m3, tdi-a. output l3 tdo-c internal jtag chain. connect to m4, tdi-a. output l4 power 3.3v device power, 3.3 volts. n/a ad7, ad8, ad13, ad14, ad19, ad20, ac7, ac8, ac13, ac14, ac19, ac20, y4, y23, y24, w4, w23, w24, r3, r4, r12, r13, r14, r15, p3, p4 p12, p15, p23, p24, n12, n15, n23, n24, m12, m13, m14, m15, h23, h24, g23, g24, d6, d7, d10, d11, d15, d16, d20, d21, c6, c7, c10, c11, c15, c16, c20, c21 table 1: ball descriptions (continued) functional group ball name(s) function type pbga ball(s) muaa routing coprocessor (rcp) family operational characteristics 8 rev. 3 operational characteristics loading and unloading in order to keep data alignment simple, the number of words to be loaded and unloaded for each operation is kept consistent for each cam/ram partition configuration and the width of the port. tables 2 and 3 show the cycle sequence and cam/ram bit mappings for 32- and 16-bit bus modes. the bus may be selected for each port independently. table 4 shows whether cam, ram or both types of segments are used on input or output cycles for each operation. loads always start right aligned from the least significant word, cam partition first, followed by ram if necessary. most instructions do not require the entire 80 bits to be loaded. cam data is required as an input for all operations except read lqueue and read aqueue. the use of ram data is optional (i.e., it is not necessary to perform all ram cycles when inputting data). however, the user must be aware that insert and learn operations will over-write ram data. therefore, the application should remain consistent in the number of ram bits used for these operations. all cam and ram segment writes except the last use the load instruction. the last segment of data uses the instruction for the desired operation. depending on the operation, unloads either start from the right aligned, least significant word of cam followed by the right aligned, least significant word of ram or just from the right aligned, least significant word of ram. for instance, a queue read returns cam then ram, whereas a search just returns ram. where the cam/ram partition does not lie on a port width boundary the last word of the read may contain undefined data in the most significant bits. the number of unload cycles actually completed is optional. the dout register stores the results of operations from the asynchronous processor port. search results are obtained by repeated reads of dout until all ram data is read. when performed from the processor port, read lqueue and read aqueue return the first segment of cam data on the cycle that requests the operation; additional cam and ram segments are obtained by repeated reads of the dout register. loading is flow controlled on the synchronous din port with the dinready signal, which is high when data is accepted by the din port. on the processor port the procready signal is high when the current write cycle may complete. ground gnd device ground. n/a af1, af2, af24, af25, af26 ae1, ae2, ae24, ae25, ae26 ad1?ad6, ad9? ad12, ad15, ad16, ad21, ad24, ad25, ad26, ac3?ac6, ac9?ac12 ac15, ac16, ac21, ac24?ac26, ab4, ab23?ab26, aa4, aa23, aa24, v3, v4, v23, v24, u4, u23, u24, t4, t11?t16, t23, t24, r11, r16, r23, r24, p11, p13, p14, p16, n4, n11, n13, n14, n16, m11, m16, m23, m24, l11?l16, l23, l24, k23, k24 j23, j24, f23, f24, e23?e26, d2?d5, d8, d9, d12?d14, d17?d19, d22?d26, c1?c5, c8, c9, c12?c14, c17?c19, c22? c26, b1?b5, b22?b26, a1?a5, a22?a26 table 1: ball descriptions (continued) functional group ball name(s) function type pbga ball(s) operational characteristics muaa routing coprocessor (rcp) family rev. 3 9 operations on the synchronous port, operations are started on the clk cycle in which the requested op-code is written. on the processor port operations are started when the chosen operation register is written. the user should use the flow control mechanisms to determine when results are available. on the synchronous port the /doutvalid signal is asserted for one clk cycle when new data is written to the dout port. the processor port will assert its procready signal on the clk edge that data is available. note that there is no internal flow control from the sync dout port back to the sync din port. the dout data is overwritten if it is not unloaded. note: *bus bits [15:0] contain data. bus bits [31:16] are undefined. device chaining up to four muaa 2k rcps may be chained with no external logic. figure 3 shows the interconnection. unused chain[3:0] pins should be left unconnected. the /mf, /ff, int, doutvalid, dinready, and procready signals should only be used on the master device and left disconnected on the slave devices. the master device is the one with no connection to the chainup pin. where device pins are paralleled, attention should be paid to signal integrity, in particular to signals used for clocking, i.e., clk, /pcs. pcb layout techniques such as daisy chaining and driver to track impedance matching should be observed. the scheme in figure 3 allows devices to be designed in but not fitted. the fit order would be master, slave1, slave2, slave3. table 2: 32-bit bus mode cam/ram cycles by partition configuration cycle no ram 79:0 cam 79:64 ram 63:0 cam 79:48 ram 47:0 cam 79:32 ram 31:0 cam 1 cam[31:0] cam[31:0] cam[31:0] cam[31:0] 2 cam[63:32] cam[63:32] cam[47:32]* ram[63:32] 3 cam[79:64]* ram[79:64]* ram[79:48] ram[79:64]* table 3: 16-bit bus mode cam/ram cycles by partition configuration cycle no ram 79:0 cam 79:64 ram 63:0 cam 79:48 ram 47:0 cam 79:32 ram 31:0 cam 1 cam[15:0] cam[15:0] cam[15:0] cam[15:0] 2 cam[31:16] cam[31:16] cam[31:16] cam[31:16] 3 cam[47:32] cam[47:32] cam[47:32] ram[47:32] 4 cam[63:48] cam[63:48] ram[63:48] ram[63:48] 5 cam[79:64] ram[79:64] ram[79:64] ram[79:64] table 4: input and output cam/ram cycles by operation operation din, procd (write) dout, procd (read) insert cam & ram n/a search cam only ram only searcha cam only ram only learn cam & ram n/a delete cam only n/a read lqueue n/a cam & ram read aqueue n/a cam & ram muaa routing coprocessor (rcp) family operational characteristics 10 rev. 3 figure 3: device chaining (2k only) slave 1 slave 2 master slave 3 dinready /doutvalid din(31:0) dine op(3:0) dout(31:0) /oe /doute procd(31:0) proca(5:0) r/w procready int clk /reset din(31:0) dine op(3:0) dout(31:0) /oe /doute procd(31:0) proca(5:0) r/w clk /reset din(31:0) dine op(3:0) dout(31:0) /oe /doute procd(31:0) proca(5:0) r/w clk /reset din(31:0) dine op(3:0) dout(31:0) /oe /doute procd(31:0) proca(5:0) r/w /pcs clk /reset /ff /mf chaindn chaindn chainup chain(0) chain(1) chain(2) chain(3) chain(0) chain(1) chain(2) chain(3) chain(0) chain(1) chain(2) chain(3) chain(0) chain(1) chain(2) chain(3) chaindn chainup chainup chainup chaindn chaincs chaincs chaincs chaincs /pcs /pcs /pcs operational characteristics muaa routing coprocessor (rcp) family rev. 3 11 interrupts there are four sources of interrupts that will cause the int pin to be asserted: aqueue, lqueue, swex, and pwex. the appropriate enables must be set in the configuration register to enable the interrupts. the interrupt service routine should read the appropriate flag registers to determine the interrupt cause. the flags are available individually or from the address index register. the appropriate individual flag register must be read in order to acknowledge the interrupt. lqueue and aqueue aqueue and lqueue interrupts are set by an entry being written into one or another of the queues. when the flag register is read the interrupt is acknowledged. the processor may read the lqueue and aqueue flags to determine when all the entries are read from the appropriate queue. the interrupt will not be reasserted until a queue has been emptied and then gets another entry. note that it is possible for learned entries to be aged and aged entries to be learned. if this occurs the aqueue and lqueue flags may be set for an entry that has changed status. the user may qualify reads from aqueue and lqueue with the appropriate ports match flag that will be asserted if the data is valid. swex and pwex swex and pwex interrupts are set when a write exception condition occurs. this occurs when two write cycles are pending in the device and there is only one space left. the swex and pwex flags indicate which port caused the exception and which are available individually to the processor. both processor write exceptions are available in the processor address index port and the dout port address index word. jtag please refer to ieee standard 1149.1 for information on using the jtag functions. see table 5 for jtag functions. a bsdl file is available; check the music semiconductors website or contact music technical support. typical example this typical example shows the cycles that the muaa rcp would perform in a multiport switch. the cam/ram partition is set to 48 bits cam, 32 bits ram. both the processor port and the synchronous port are 32 bits wide. the index and flags are programmed to be the last word out of the dout port. the synchronous port has priority. the lqueue and aqueue are enabled. the cam partition is used to store 48-bit mac addresses and the ram partition used to store associated data to the mac address such as switch port and vlan numbers. sync port cycle 1 is a search to lookup the port associated with a frame da (destination address). at clk1 the first word (32 bits) of cam search word is loaded. at clk2 the last 16 bits of cam search word is loaded and the instruction search given. the most significant 16 bits of the second word are discarded as the cam partition is 48 bits wide. the results from the da search will not be available until clk6 because the operation takes three clk periods to complete. due to the internal design of the muaa rcp, pipelining is possible; therefore, further operations can be performed while the da search is being done internally. sync port cycle2 is a learn on a frame sa (source address). at clk3 the first word of cam is loaded, at clk4 the second word is loaded (most significant 16 bits discarded). at clk5 the learn instruction is given along with the word of ram data that would contain the port id and other data associated with the sa. at clk6 the results of the search instruction issued in cycle1 are available at the dout bus of the synchronous port, as indicated by /doutvalid going active for a clk. the result of this cycle was a no-match condition as /mf was not asserted low. because the cycle was a da search and there was a no-match result, there will be no data available on the dout bus. typically in this situation a switch would forward the frame to all ports or all ports on the same vlan. table 5: jtag functions id jtag codes binary 0011 1010 1010 0000 0010 0001 0011 0011 ext test 0000 hex 3aa02133 bypass1111 description version muaa 2k manuf id sample 0001 id code 0010 clamp 0100 high-z 0011 muaa routing coprocessor (rcp) family operational characteristics 12 rev. 3 sync port cycle3 starts at clk8, which is the da search of the next frame. at clk 10 the results of the cycle2 learn operation are available. /mf was not asserted low; therefore the 48-bit cam partition data was not found during the compare. the muaa rcp automatically writes the 80-bit cam/ram word into the next free location of the memory array along with the most up to date time stamp or entry life. the address index is available from the dout bus to indicate where in the memory array the data was placed. this can be used to implement further associated data in software or hardware. furthermore, the int output is asserted to indicate that the learned word was entered into the lqueue. sync port cycle4, which is the sa learn of the same frame as sync port cycle3, is initiated at clk10. the processor can also be used to access the muaa rcp for general housekeeping duties. the lqueue contains the contents of the virtual learned queue. a processor cycle is started around clk12 to read the lqueue register. this cycle is unable to be completed because the cam core is busy servicing the synchronous port. procready remains inactive to inform the processor of the delay. the cycle is therefore extended and will complete when the muaa rcp asserts procready high. /mf is asserted low to indicate a match result on the cam partition compare. at this point dout will be used to transfer the associated data and the address index of the matching condition. the associated data is available first (ram partition) and would normally contain the port id in a typical switch. the ram partition is configured as 32 bits wide and can therefore be transferred in one clk period. /doute is asserted by the user to transfer the next word of data on the next clock period. as the ram takes only one cycle, the address index is available after the associated data. the result of cycle4, which was a sa learn, is available at clk17. the learn instruction produced a match result. there was no need to overwrite the cam/ram partitions, but the muaa rcp automatically updated the time stamp or entry life of the matching entry. the address index of the entry becomes available at the dout port. the processor cycle data requested earlier, can now become available at clk21. procready is asserted high by the device to indicate that the cycle may be completed. the first 32-bit word is available on the procd bus and can be read by the processor. the two remaining 32-bit words that complete the lqueue entry are read by the subsequent processor cycles. these cycles do not require access to the cam core, hence the procready signal is asserted immediately once the cycle is initiated. the processor may use the lqueue data to maintain a management database of mac addresses and associated port ids. back to back da searches are shown from clk25 onward. this is to demonstrate how the synchronous port handshaking works using the /dinready output. sync port cycle5 and cycle6 are completed normally but at clk29 /dinready goes low to indicate that the muaa rcp cannot accept the load operation of sync cycle7. therefore the host must hold the din, op, and dine signals active until /dinready goes high. at this point the muaa rcp will return /dinready to high to indicate that it has accepted the din and op information. operational characteristics muaa routing coprocessor (rcp) family rev. 3 13 figure 4: example sequence clk /dine din(31:0) op(3:0) dinready /mf dout(31:0) /doutvalid /doute /oe int /pcs procd(31:0) proca(5:1) r/w procready cam1 cam1 cam2 cam2 ram2 cam3 cam3 cam4 cam4 cam4 cam5 cam5 cam6 cam6 cam7 cam7 cam8 cam8 load1 search1 load2 load2 learn2 load3 search3 l oad4 load4 learn4 load5 search 5 load6 search 6 load7 search 7 load8 search 8 no match 1 no match 2 match 3 match 4 match 5 no match 6 no match 7 lqueue cam2 lqueue ram2 lqueue addr lqueue addr lqueue addr 1 2 3 5 6 7 14 15 16 17 8 9 10 12 13 11 18 20 21 22 24 25 27 26 28 29 30 32 33 34 35 37 4 23 31 36 index2 ram3 index3 index4 ram5 index5 valid1 valid2 valid3 valid4 valid5 valid6 valid7 learn 2 in queue cam2 lqueue muaa routing coprocessor (rcp) family instruction set descriptions 14 rev. 3 instruction set descriptions mnemonic: noop binary op-code: 0 clks: 3 function: no operation. mnemonic: load instruction set descriptions muaa routing coprocessor (rcp) family rev. 3 15 processor port registers table 6: processor port registers register/instruction proca[5:0] bit(s) function noop 0x00 31:0 w noop operation load muaa routing coprocessor (rcp) family instruction set descriptions 16 rev. 3 address index 0x26 25:0 r once an operation has been performed on the processor port the address index is available here. useful as an index for associated tables in software. 26 r swex flag 27 r pwex flag 28 r lqueue flag 29 r aqueue flag 30 r processor port match flag; 1 = match 31 r full flag; 1 = full lqueue flag 0x28 0 r indicates the lqueue has at least one entry. note this bit is available even if the int pin is disabled. a read clears the interrupt. aqueue flag 0x2a 0 r indicates the aqueue has at least one entry. note this bit is available even if the int pin is disabled. a read clears the interrupt. pwex flag 0x2c 0 r indicates a write exception condition has occurred on the processor port. a read clears the interrupt. swex flag 0x2e 0 r indicates a write exception condition has occurred on the syncport. a read clears the interrupt. auto-age interval 0x30 31:0 r/w when auto-aging is enabled the clk is divided by the value in this reg- ister to provide the auto-age interval. resets to 02faf080h = 1 second with 50 mhz clk. learned entry life 0x32 8:0 r/w this register sets the life of a learned entry in units of the auto-age interval register. resets to 012ch = 300. info 0x34 1:0 r number of cascaded devices 2 r read 0 31:3 r device id. 1 = muaa rcp. size 0x36 31:0 r chain size. multiples of 0.25k revision 0x38 3:0 r master device rev. 7:4 r slave 1 rev. 11:8 r slave 2 rev. 15:12 r slave 3 rev. 31:16 r read 0 table 6: processor port registers (continued) register/instruction proca[5:0] bit(s) function electrical muaa routing coprocessor (rcp) family rev. 3 17 electrical absolute maximum ratings supply voltage -0.5 to 4.6 volts stresses exceeding those listed under absolute maximum ratings may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. all voltages referenced to gnd. voltage on all other pins -0.5 to vcc+0.5 volts (-2.0 volts for 10 ns, measured at the 50% point) temperature -40 c to 85 c storage temperature -55 c to 125 c dc output current 20 ma (per output, one at a time, one second duration) operating conditions symbol parameter min. typical max. units notes v cc operating supply voltage 3.0 3.3 3.6 volts v ih input voltage logic 1 2.0 5.5 volts all other pins 2.4 v dd + 0.3 volts clk v il input voltage logic 0 -0.3 0.8 volts t a ambient operating temperature 0 70 cstill air electrical characteristics symbol parameter min. typical max. units notes i cc average power supply current 310 400 ma muaa2k 1.25 1.6 a muaa8k i cc(sb) stand-by power supply current 2 7 ma v oh output voltage logic 1 2.4 volts i oh = -8.0 ma v ol output voltage logic 0 0.4 volts i ol = 8.0 ma i iz input leakage current -2 2 av ss v in v cc i oz output leakage current -10 10 av ss v out v cc i rp input pull-up resistors muaa2k 25 k ? /trst, tms, tdi muaa8k 6.25 k ? capacitance symbol parameter max. units notes c in input capacitance muaa2k 6 pf f = 1 mhz, v in = 0v muaa8k 45 pf c out output capacitance muaa2k 7 pf f = 1 mhz, v out = 0v muaa8k 45 pf muaa routing coprocessor (rcp) family timing diagrams 18 rev. 3 timing diagrams figure 5: sync port cycle t15 t15 t5 t5 t7 t6 t11 t10 t4 t14 t3 t3 t9 t8 t13 t16 t16 t12 t16b t16b t16a t16a t2 t1 data data data data op op load load clk /dine din(31:0) op(3:0) dinready /ff /mf dout(31:0) /doutvalid /doute /oe read1 readn table 7: sync port cycle - 20 - 30 no. name min. max. min. max. comment t1 tdvch 5 7 din(31:0), op(3:0) setup to clk high t2 tchdx 3 4 clk high to din(31:0), op(3:0) hold t3 tchdrv 16 18 clk high to dinready valid t4 tchmv 10 12 clk high to /mf valid t5 tchqv 15 18 clk high to do valid t6 tchqz 0.5 2.5 0.5 4 clk high to do hi-z t7 tchqx 3 4 clk high to do active t8 tqevch 5 7 /doute setup to clk high t9 tchqex 3 4 clk high to /doute hold t10 tghqz 0.5 3 0.5 4 /oe to do hi-z t11 tglqx 3 4 /oe to do active t12 tdevch 5 7 /dine setup to clk high t13 tchdex 3 4 clk high to dine hold t14 tchfv 10 12 clk high to /ff valid t15 tchqvv 10 12 clk high to /doutvalid t16 tchch 20 30 clk period t16a tchcl 8 12 clk high time t16b tclch 8 12 clk low time timing diagrams muaa routing coprocessor (rcp) family rev. 3 19 figure 6: processor port cycle notes: * n = 3 for all write operations n = 6 for all register read operations n = 10 for read lqueue operations n = 11 for read aqueue operations assumes no sync port activity to core on previous processor port core operation pending completion. depending on sync port acti vity (auto-age events and processor port priority setting), processor port operations may be extended. t25 t19 t22 t18 t24 t23 t27 t26 t21 t20 /pcs procd(31:0) (read) proca(5:0) r/w (read) procready procd(31:0) (write) r/w (write) clk t29 t29 t28 table 8: processor port cycle - 20 - 30 no. name min. max. min. max. comment t18 tsldqx t16 t16 /pcs low to procd active t19 tshdqz 8 12 /pcs high to procd hi-z t20 trwvsl 3 4 r/w setup to /pcs low t21 tslrwx 3 4 /pcs low to r/w hold t22 tchdqv 15 18 clk to procd valid (read) t23 tdqvsh 5 8 procd setup to /pcs high (write) t24 tshdqx 3 5 /pcs high to procd hold (write) t25 tchprh 10 12 clk high to procready valid t26 tavsl 5 7 proca setup to /pcs low t27 tslax 3 4 /pcs low to proca hold t28 tslprh nxt16* nxt16* /pcs low to procready high t29 tshprl 4xt16* 4xt16* /pcs high to procready low t30 tchiv 10 12 clk high to int valid muaa routing coprocessor (rcp) family notes 20 rev. 3 notes notes muaa routing coprocessor (rcp) family rev. 3 21 notes muaa routing coprocessor (rcp) family packages 22 rev. 3 packages 388-pin pbga af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a e f 2625242322212019181716151413121110987654321 pin # 1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a e e1 d1 d 4.00 * 45 o (4x) a1 seating plane a l b l1 388-pin pbga dimensions dim. a dim. a1 dim. b dim. d d1 dim. e e1 dim. e dim. f dim. l l1 min. 0.50 34.80 34.80 2.20 nom. 1.17 1.73 35.00 30.00 35.00 32.00 1.27 31.75 2.33 30 max. o.70 35.20 35.20 2.46 packages muaa routing coprocessor (rcp) family rev. 3 23 160-pin pqfp 160-pin pqfp dimensions dim. a dim. a1 dim. a2 dim. b c dim. d d1 d2 dim. e e1 e2 dim. e dim. l min. 0.25 3.20 0.22 0.11 nom. 3.32 0.30 0.15 31.20 28.00 25.35 31.20 28.00 25.35 0.65 1.60 max. 4.10 3.60 0.38 0.23 d d1 d2 e e1 e2 e b 160-pin pqfp a a2 a2 l c muaa routing coprocessor (rcp) family ordering information 24 rev. 3 ordering information part number cycle time package temperature vol tag e muaa2k80-20qgc MUAA2K80-30QGI muaa8k80m-20b388c 20 ns 30 ns 20 ns 160-pin pqfp 160-pin pqfp 388-pin pbga 0?70 c -40?85 c 0?70 c 3.3 0.3 3.3 0.3 3.3 0.3 music semiconductors? agent or distributor: music semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability or reliability. information furnished by music is believed to be accurate, but no responsibility is assumed by music semiconductors for the use of said information, nor for any infringements of patents or of other third-party rights which may result from said use. no license is granted by implication or otherwise under any patent or patent rights of any music company. ? copyright 2000, music semiconductors http://www.music-ic.com email: info@music-ic.com worldwide headquarters music semiconductors 2290 n. first st., suite 201 san jose, ca 95131 usa tel: 408 232-9060 fax: 408 232-9201 usa only: 800 933-1550 tech support 888 226-6874 product info asian headquarters music semiconductors special export processing zone carmelray industrial park canlubang, calamba, laguna philippines tel: +63 49 549-1480 fax: +63 49 549-1024 sales tel/fax: +632 723-6215 european headquarters music semiconductors p. o. box 184 6470 ed eygelshoven the netherlands tel: +31 43 455-2675 fax: +31 43 455-1573 |
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