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?001 fairchild semiconductor corporation huf76113dk8 rev. b huf76113dk8 6a, 30v, 0.032 ohm, dual n-channel, logic level ultrafet power mosfet this n-channel power mosfet is manufactured using the innovative ultrafet process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?iency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery- operated products. formerly developmental type ta76113. features logic level gate drive 6a, 30v ultra low on-resistance, r ds(on) = 0.032 ? temperature compensating pspice model temperature compensating saber model thermal impedance spice model thermal impedance saber model peak current vs pulse width curve uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards symbol packaging jedec ms-012aa ordering information part number package brand huf76113dk8 ms-012aa 76113dk8 note: when ordering, use the entire part number. add the suf? t to obtain the variant in tape and reel, e.g., HUF76113DK8T. g1(2) d1(8) s1(1) d1(7) d2(6) d2(5) s2(3) g2(4) branding dash 1 2 3 4 5 data sheet december 2001
?001 fairchild semiconductor corporation huf76113dk8 rev. b absolute maximum ratings t a = 25 o c, unless otherwise speci?d huf76113dk8 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current continuous (t a = 25 o c, v gs = 10v) (figure 2) (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = 5v) (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = 4.5v) (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 6 1.8 1.7 figure 4 a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figure 6 power dissipation (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 0.02 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. t j = 25 o c to 125 o c. 2. 50oc/w measured using fr-4 board at 1 second. 3. 228 o c/w measured using fr-4 board with 0.006 in 2 footprint at 1000 seconds. electrical speci?ations t a = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 30 - - v zero gate voltage drain current i dss v ds = 25v, v gs = 0v - - 1 a v ds = 25v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds(on) i d = 6a, v gs = 10v (figures 9, 10) - 0.026 0.032 ? i d = 1.8a, v gs = 5v (figure 9) - 0.033 0.041 ? i d = 1.7a, v gs = 4.5v (figure 9) - 0.035 0.043 ? thermal specifications thermal resistance junction to ambient r ja pad area = 0.76 in 2 (note 2) - - 50 o c/w pad area = 0.027 in 2 (see tb377) - - 191 o c/w pad area = 0.006 in 2 (see tb377) - - 228 o c/w switching specifications (v gs = 4.5v) turn-on time t on v dd = 15v, i d ? 1.7a, r l = 8.8 ? , v gs = 4.5v, r gs = 18 ?, (figure 15) - - 110 ns turn-on delay time t d(on) -17-ns rise time t r -57-ns turn-off delay time t d(off) -32-ns fall time t f -38-ns turn-off time t off - - 105 ns huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b switching specifications (v gs = 10v) turn-on time t on v dd = 15v, i d ? 6a, r l = 2.5 ? , v gs = 10v, r gs = 18 ? (figure 16) - - 60 ns turn-on delay time t d(on) - 6.5 - ns rise time t r -33-ns turn-off delay time t d(off) -50-ns fall time t f - 40 - ns turn-off time t off - - 135 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 15v, i d ? 1.8a, r l = 8.3 ? i g(ref) = 1.0ma (figure 14) - 16.0 19.2 nc gate charge at 5v q g(5) v gs = 0v to 5v - 8.4 10.2 nc threshold gate charge q g(th) v gs = 0v to 1v - 0.55 0.66 nc gate to source gate charge q gs - 1.50 - nc gate to drain ?iller?charge q gd - 3.90 - nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 605 - pf output capacitance c oss - 275 - pf reverse transfer capacitance c rss -40-pf electrical speci?ations t a = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 6a - - 1.25 v i sd = 1.8a 1.00 v reverse recovery time t rr i sd = 1.8a, di sd /dt = 100a/ s--40ns reverse recovered charge q rr i sd = 1.8a, di sd /dt = 100a/ s--42nc typical performance curves figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs ambient temperature t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 1 2 3 4 5 7 25 50 75 100 125 150 i d , drain current (a) t a , ambient temperature ( o c) v gs = 4.5v, r ja = 228 o c/w v gs = 10v, r ja = 50 o c/w 6 huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b figure 3. normalized maximum transient thermal impedance figure 4. peak current capability figure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability typical performance curves (continued) 0.001 0.01 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t, rectangular pulse duration (s) z ja , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 r ja = 228 o c/w 2 1 10 100 500 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 i dm , peak current (a) t, pulse width (s) v gs = 5v r ja = 228 o c/w v gs = 10v transconductance may limit current in this region t c = 25 o c i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: t j = max rated t a = 25 o c 100 s 10ms 1ms v dss(max) = 30v 10 100 1 v ds , drain to source voltage (v) 1 100 500 10 i d , drain current (a) limited by r ds(on) area may be operation in this 1 10 100 50 1 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c 0.1 10 t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature typical performance curves (continued) 0 345 2 0 5 10 15 20 i d , drain current (a) v gs , gate to source voltage (v) 150 o c -55 o c 25 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v 30 1 25 0 5 10 15 0 12345 20 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 80 s t a = 25 o c 25 v gs = 5v v gs = 10v v gs = 4.5v v gs = 3v 30 v gs = 3.5v v gs = 4v duty cycle = 0.5% max i d = 1.8a 0 50 100 150 200 246810 v gs , gate to source voltage (v) i d = 6a pulse duration = 80 s r ds(on) , drain to source on resistance (m ? ) 0 duty cycle = 0.5% max 0.6 0.8 1.0 1.2 1.6 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 80 s 1.4 v gs = 10v, i d = 6a duty cycle = 0.5% max -80 -40 0 40 80 120 160 0.6 0.7 0.8 0.9 1.2 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 1.0 1.1 1.2 1.1 1.0 0.9 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance figure 16. switching time vs gate resistance typical performance curves (continued) 1000 600 0 0 5 10152025 c, capacitance (pf) 800 v ds , drain to source voltage (v) 400 c iss c oss c rss 30 200 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss = c ds + c gd 0 2 4 6 8 10 0 5 10 15 20 v gs , gate to source voltage (v) v dd = 15v q g , gate charge (nc) i d = 6a i d = 1.8a waveforms in descending order: 30 20 30 40 50 0 120 90 60 0 10 switching time (ns) r gs , gate to source resistance ( ? ) t d(off) t d(on) t r t f v gs = 4.5v, v dd = 15v, i d = 1.7a, r l = 8.8 ? 60 20 30 40 50 0 150 120 90 0 10 switching time (ns) r gs , gate to source resistance ( ? ) t d(off) t d(on) t r t f v gs = 10v, v dd = 15v, i d = 6a, r l = 2.5 ? 30 test circuits and waveforms figure 17. unclamped energy test circuit figure 18. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the ther- mal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the applications ambient tempera- ture, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the sop-8 package, the environment in which it is applied will have a signi?ant in?ence on the parts current and maximum power dissipa- tion ratings. precise determination of p dm is complex and in?enced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air ?w and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designers preliminary application evaluation. figure 23 de?es the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air ?w. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja values listed in the electrical speci?ations table. the points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, p dm . figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10 v ds v gs i g(ref) 0 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 (eq. 1) p dm t jm t a C () z ja ------------------------------ - = huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b thermal resistances corresponding to other copper areas can be obtained from figure 23 or by calculation using equation 2. r ja is de?ed as the natural log of the area times a cof?ient added to a constant. the area, in square inches is the top copper area including the gate and source pads. while equation 2 describes the thermal resistance of a single die, several of the new ultrafets are offered with two die in the sop-8 package. the dual die sop-8 package introduces an additional thermal component, thermal coupling resistance, r ? . equation 3 describes r ? as a function of the top copper mounting pad area. the thermal coupling resistance vs. copper area is also graphically depicted in figure 23. it is important to note the thermal resistance (r ja ) and thermal coupling resistance ( r ? ) are equivalent for both die. for example at 0.1 square inches of copper: r ja1 = r ja2 = 159 o c/w r ? 1 = r ? 2 = 97 o c/w t j1 and t j2 de?e the junction temerature of the respective die. similarly, p 1 and p 2 de?e the power dissipated in each die. the steady state junction temperature can be calculated using equation 4 for die 1and equation 5 for die 2. example: to calculate the junction temperature of each die when die 2 is dissipating 0.5 watts and die 1 is dissipating 0 watts. the ambient temperature is 70?c and the package is mounted to a top copper area of 0.1 square inches per die. use equation 4 to calulate t j1 and and equation 5 to calulate t j2 .. t j1 = (0 watts)(159?c/w) + (0.5 watts)(97?c/w) + 70?c t j1 = 119?c t j2 = (0.5 watts)(159 o c/w) + (0 watts)(97 o c/w) + 70 o c t j2 = 150 o c the transient thermal impedance (z ja ) is also effected by varied top copper board area. figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. each trace represents a copper pad area in square inches corresponding to the descending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. for pulse widths less than 100ms the transient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and rtherm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. (eq. 2) r ja 103.2 24.3 area () ln C = 0 50 100 150 200 250 300 0.001 0.01 0.1 1 r ? , r ja ( o c/w) area, top copper area (in 2 ) per die 191 o c/w - 0.027in 2 228 o c/w - 0.006in 2 figure 23. thermal resistance vs mounting pad are a r ja = 103.2 - 24.3 * ln (area) r ? = 46.4 - 21.7 * ln (area) (eq. 3) r ? 46.4 21.7 area () ln C = (eq. 4) t j1 p 1 r ja p 2 r ? t a ++ = (eq. 5) t j2 p 2 r ja p 1 r ? t a ++ = 0 40 80 120 160 10 -1 10 0 10 1 10 2 10 3 figure 24. thermal resistance vs mounting pad area t, rectangular pulse duration (s) z ja , thermal impedance ( o c/w) copper board area - descending order 0.020 in 2 0.140 in 2 0.257 in 2 0.380 in 2 0.493 in 2 huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b pspice electrical model .subckt huf76113 2 1 3 ; rev july 1998 ca 12 8 8.50e-10 cb 15 14 8.05e-10 cin 6 8 5.71e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 38.7 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 9.67e-10 lsource 3 7 3.27e-10 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 3.04e-3 rgate 9 20 2.65 rldrain 2 5 10 rlgate 1 9 9.67 rlsource 3 7 3.27 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 25.0e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*256),2))} .model dbodymod d (is = 8.35e-13 rs = 1.39e-2 trs1 = 1.03e-3 trs2 = 6.85e-6 cjo = 9.11e-10 tt = 2.14e-8 m = 0.42) .model dbreakmod d (rs = 8.21e-2 trs1 = 2.25e-3 trs2 = 4.14e-5) .model dplcapmod d (cjo = 3.76e-10 is = 1e-30 n = 10 m = 0.68) .model mmedmod nmos (vto = 2.03 kp = 3.75 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.65) .model mstromod nmos (vto = 2.36 kp = 50 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.77 kp = 0.10 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 26.5 rs = 0.1) .model rbreakmod res (tc1 = 1e-3 tc2 = 1e-7) .model rdrainmod res (tc1 = 3.67e-2 tc2 = 4.11e-5) .model rslcmod res (tc1 = 2.26e-3 tc2 = 1.23e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc = -2.97e-3 tc2 = -5.91e-6) .model rvtempmod res (tc1 = -7.41e-4 tc2 = 9.41e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -6.05 voff= -2.00) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.00 voff= -6.05) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.00 voff= 0.60) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.60 voff= 0.00) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b saber electrical model rev july 1998 template huf76113 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 8.35e-13, cjo = 9.11e-10, tt = 2.14e-8, m = 0.42) d..model dbreakmod = () d..model dplcapmod = (cjo = 3.76e-10, is = 1e-30, n = 10, m = 0.68) m..model mmedmod = (type=_n, vto = 2.03, kp = 3.75, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.36, kp = 50, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.77, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.05, voff = -2) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.05) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.6) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = 0) c.ca n12 n8 = 8.5e-10 c.cb n15 n14 = 8.05e-10 c.cin n6 n8 = 5.71e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 9.67e-10 l.lsource n3 n7 = 3.27e-10 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = 1e-7 res.rdbody n71 n5 = 1.39e-2, tc1 = 1.03e-3, tc2 = 6.85e-6 res.rdbreak n72 n5 = 8.21e-2, tc1 = 2.25e-3, tc2 = 4.14e-5 res.rdrain n50 n16 = 3.04e-3, tc1 = 3.67e-2, tc2 = 4.11e-5 res.rgate n9 n20 = 2.65 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 9.67 res.rlsource n3 n7 = 3.27 res.rslc1 n5 n51 = 1e-6, tc1 = 2.26e-3, tc2 = 1.23e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 25e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -7.41e-4, tc2 = 9.41e-7 res.rvthres n22 n8 = 1, tc1 = -2.97e-3, tc2 = -5.91e-6 spe.ebreak n11 n7 n17 n18 = 38.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/256))** 2)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf76113dk8
?001 fairchild semiconductor corporation huf76113dk8 rev. b spice thermal model rev june 1998 huf76113dk8 copper area = 0.02 in 2 ctherm1 th 8 8.5e-4 ctherm2 8 7 1.8e-3 ctherm3 7 6 5.0e-3 ctherm4 6 5 1.3e-2 ctherm5 5 4 4.0e-2 ctherm6 4 3 9.0e-2 ctherm7 3 2 4.0e-1 ctherm8 2 tl 1.4 rtherm1 th 8 3.5e-2 rtherm2 8 7 6.0e-1 rtherm3 7 6 2 rtherm4 6 5 8 rtherm5 5 4 18 rtherm6 4 3 39 rtherm7 3 2 42 rtherm8 2 tl 48 saber thermal model copper area = 0.02 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 9.0e-2 ctherm.ctherm7 3 2 = 4.0e-1 ctherm.ctherm8 2 tl = 1.4 rtherm.rtherm1 th 8 = 3.0e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 3.8 rtherm.rtherm4 6 5 = 9.5 rtherm.rtherm5 5 4 = 25 rtherm.rtherm6 4 3 = 38 rtherm.rtherm7 3 2 = 25 rtherm.rtherm8 2 tl = 38 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8 table 1. thermal models componant 0.02 in 2 0.14 in 2 0.25 in 2 0.38 in 2 0.50 in 2 ctherm6 9.0e-2 1.3e-1 1.5e-1 1.5e-1 1.5e-1 ctherm7 4.0e-1 6.0e-1 4.5e-1 6.5e-1 7.5e-1 ctherm8 1.4 2.5 2.2 3 3 rtherm6 39 26 20 20 20 rtherm7 42 32 31 29 23 rtherm8 48 35 38 31 25 huf76113dk8
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?

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