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e preliminary december 1998 order number: 290621-005 n low-cost linear flash card ? intel ? strataflash tm memory technology n high-performance writes ? 6 m s typical byte write n fast read performance ? 200 ns max access time n low-cost linear flash card n 32 byte write buffer ? frees cpu to perform other tasks n single supply operation ? 5 v read/write n x16 data interface n automated write and erase algorithms ? cfi and scs compliant n enhanced automated suspend options ? block erase suspend to write ? block erase suspend to read n enhanced data protection features ? flexible block locking n 100,000 erase cycles per block n 128-kbyte erase blocks n compact form factor ? type 1 pc card the intel ? 5 volt series 200 flash memory cards deliver the benefits of intel ? strataflash? memory to users of portable electronic systems. intel strataflash memory benefits include: more density in less space, lowest cost-per-bit nor devices, support for code and data storage, and easy migration to future devices. providing 2x the bits in 1x the space, intel strataflash memory devices are the first to bring reliable, two-bit- per-cell storage technology to the flash memory market. using the same nor-based etox? technology as intels one-bit-per-cell products, intel strataflash memory devices take advantage of 400 million units of manufacturing experience since 1988. manufactured on intels 0.4 micron etox v process technology, intel strataflash memory provides the highest levels of quality and reliability. as a result, intel strataflash components are ideal for code or data applications where high density and low cost are required. examples include networking, telecommunications, audio recording, and digital imaging. intel strataflash memory components provide a new generation of forward-compatible software support built upon the intel ? flashfile? memory architecture. by using the common flash interface (cfi) and the scaleable command set (scs), customers can take advantage of density upgrades and optimized write capabilities of future intel strataflash memory devices. 5 volt value series 200 flash memory cards, based on the pcmcia pc card specification, employ intel strataflash components to provide the ultimate in convenient, low-cost data storage for users of portable electronics systems. the flash memory card provides the lowest cost, highest performance nonvolatile read/write solution for solid-state storage applications. these applications are enhanced further with the products symmetrically-blocked architecture, extended mtbf, and 5 volt operation. card memory is organized as a x16 linear array of flash memory devices. host-based filing system software, such as flash translation layer (ftl) eliminates the need for expensive card-based microcontrollers and asics. the cards offer the pc card industry-standard pinout in the most compact pc card form factor (type 1), a removable linear flash memory medium, the ability to upgrade system memory software without board layout changes, and compatibility over a wide range of ms-dos* and windows* 95-based pcs systems. note: this document formerly known as value series 200 flash memory card 8 64 megabytes. 5 volt value series 200 flash memory card imc008flsg, IMC016FLSG, imc024flsg imc032flsg, imc048flsg, imc064flsg
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the imc008flsg, IMC016FLSG, imc024flsg, imc032flsg, imc048flsg, imc064flsg may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1998 cg-041493 *third-part y brands and names are the propert y of their respective owners
e imc008/016/024/032/048/064flsg 3 preliminary contents page page 1.0 scope of document ................................ 5 2.0 product overview .................................. 5 3.0 card architecture................................. 5 3.1 card signal description ............................... 5 4.0 memory control logic ......................... 9 4.1 bus operations............................................ 9 4.2 decode logic............................................. 12 5.0 command definition .............................. 13 5.1 basic command set .................................. 13 5.2 scaleable command set ........................... 19 6.0 card attribute information............. 21 6.1 pc card information structure................... 21 6.2 cis data.................................................... 21 7.0 system design considerations ........ 24 7.1 power supply decoupling .......................... 24 7.2 power-up/down protection........................ 24 7.3 rdy/bsy# and write/block erase status polling....................................................... 24 8.0 electrical specifications ................. 25 8.1 absolute maximum ratings ....................... 25 8.2 operating conditions ................................. 25 8.3 capacitance............................................... 25 8.4 dc characteristics ..................................... 26 8.5 ac characteristics ..................................... 28 8.6 block erase, write, and lock-bit configuration performance ....................... 33 9.0 packaging................................................. 34 10.0 ordering information ....................... 35 11.0 additional information..................... 35 revision history date of revision version description 12/01/97 -001 original version 4/01/98 -002 updated front cover sheet highlights: eliminated 40- and 56-mbyte density offerings; changed write speed to 7 m s; changed number of erase cycles per block to 100,000 in third paragraph of legal statement on page 2, eliminated imc040flsg and imc056flsg references in paragraph 2.0, product overview, reworded the first sentence of the first paragraph to eliminate the implied availability of all multiples of 8-mbytes for memory densities offered in the range from 8- to 64-mbytes in table 3, card signal values for the card's bus operations and modes, changed conditions for word read, word write and standby operations in first sentence of paragraph 4.1.3, standby , re-defined standby mode entry conditions in table 10, value series 200 card tuples, eliminated entries not related to products actually offered: eliminated 40- and 56-mbyte references and 150 ns speed references in paragraph 7.2, power-up/down protection , reworded the second sentence of the third paragraph for the requirement that we# must be low and ce 1 # or ce 2 # must be low for a command write
imc008/016/024/032/048/064flsg e 4 preliminary revision history (continued) 4/01/98 -002 in paragraph 8.4, dc characteristics , changed the minimum limit for v ih to 0.7 v cc (from 2.0) in paragraph 8.4, dc characteristics , eliminated i ccs and i ccd entries for 40- and 56-mbyte cards in note 1 of paragraph 8.5.2, write operations , restated the ce# deasserted conditions to be both ce#s (cel# and ceh#) instead of either one of the ces (cel# or ceh#) in paragraph 8.6, block erase, write, and lock-bit configuration performance , changed the typ entries for first 3 parameters (pertaining to write time) to increase write times by 16.67%; added note 6 to describe expected write time performance relative to the specified maximum and typical values, and to suggest use of rdy/bsy# to maximize system performance. in paragraph 10.0, ordering information, deleted density codes for 40- and 56- mbytes 05/01/98 -003 updated front cover sheet highlights: changed write speed to 6.3 m s 05/15/98 -004 updated front cover sheet highlights: changed write speed to 12 m s in table 8.5.1, read operations ? common memory , changed ieee symbol t ghqz to t ehqz in paragraph 8.6 block erase, write, and lock-bit configuration performance, changed typical values for the following parameters: write buffer word write time, word write time (using word write command), and block write time (using write to buffer command) 12/22/98 -005 8-,16-,24-, and 32-mbyte cards use 28f320j5 components updated i ccs and i ccd specifications updated table 8.6, block erase, write and lock-bit configuration performance name of document changed from value series 200 flash memory card 8 64 megabytes.
e imc008/016/024/032/048/064flsg 5 preliminary 1.0 scope of document this datasheet describes an intel strataflash? memory card architecture, ac and dc characteristics and command definitions. refer to the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet, order number 290606. 2.0 product overview the intel 5 volt value series 200 family of flash memory pc cards offers a lowest cost selection of memory card products ranging in memory density from 8- to 64-mbytes. each card contains a flash memory array made up of intel strataflash memory components. the 8-, 16-, 24-, or 32- mbyte cards consist of between two and eight 4-mbyte components (intel ? 28f320j5) configured for x16 (word-wide) operation. the 48- or 64- mbyte cards consist of multiple 8-mbyte components (intel ? 28f640j5) also configured for x16 (word-wide) operation. intel strataflash memory can store more than one bit per flash memory cell, reducing the size and cost of large flash memory arrays. figure 1 presents a 8-mbyte card block diagram as an example illustration of the functional layout and user interface of a 5 volt value series 200 card. a command user interface (cui) serves as the interface between the system processor and internal operation of the cards memory device(s). a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, write, and lock-bit configuration operations. each intel strataflash memory device incorporates a 16-word (32-byte) write buffer. this dramatically improves write performance by optimizing a flash memory devices programming algorithm, thereby freeing the cpu from writing data and polling status on a word-by-word basis. the 32-byte buffer can be loaded at full bus speed; then a single command can be issued to transfer the buffer into the flash memory array. while the write state machine (wsm) is handling all of the flash memory programming details for a memory write operation, the host cpu is free to perform other tasks. the 28f640j5 or e28f320j5 components forming a cards memory array each contain 64/32 separate 128-kbyte erase blo cks. the number of erase blocks on a card r ange from 64 erase blocks for a 8-mbyte card to 512 erase blo cks for a 64- mbyte card. a block erase operation erases one of the 128-kbyte blo cks typically within one second independent of other blo cks. each block can be independently erased 10,000 times. block erase suspend mode allows system software to sus pend block erase to read data from or write data to any other block. 3.0 card architecture the 5 volt value series 200 flash memory pc card implements the functionality of the pcmcia pc card specification with x16 (word-wide) data transfers. the card does not support individual 8- bit (byte) wide memory data transfers as the cards memory devices(s) and data bus interface are structured word-wide. various information about the card is contained in a card information structure (cis) as defined in the pcmcia pc card specification. the cis is stored in block 0 of the cards memory array. the high byte of the cis is always ffh, the low byte contains the actual cis data. the card information structure (cis) for the 5 volt value series 200 card is stored in block 0 of the flash memory to reduce the attribute memory cost overhead of an eeprom or asic. in embedded applications, a cis may not be required by the system and the entire memory array can be used by the system. the cis is stored in block 0 of the flash memory to reduce the attribute memory cost overhead of an eeprom or asic. in embedded applications, a cis may not be required by the system and the entire memory array can be used by the system. 3.1 card signal description the signals for the 5 volt value series 200 flash memory pc card are listed in table 1. they comply with the pc card specification .
imc008/016/024/032/048/064flsg e 6 preliminary decoder busy# cel# ceh# a[25:21] 28f320j5 sts ce 2 ce 1 ce 0 28f320j5 sts ce 2 ce 1 ce 0 2 d[15:0] oe# we# reset# a[20:0] d[15:0] a 0 oe# we# rp# a[21:1] d[15:0] a 0 oe# we# rp# a[21:1] and v cc v ccq v pen gnd v cc v ccq v pen gnd v cc gnd v cc wait# bvd 1 bvd 2 wp cd 1 cd 2 0621_01 figure 1. 8-mbyte flash memory card block diagram showing major functional elements
e imc008/016/024/032/048/064flsg 7 preliminary table 1. 5 volt value series 200 flash memory pc card definitions pin signal i/o function active pin signal i/o function active 1 gnd ground 27 a 2 i address bit 2 2dq 3 i/o data bit 3 28 a 1 i address bit 1 3dq 4 i/o data bit 4 29 a 0 i address bit 0 4dq 5 i/o data bit 5 30 dq 0 i/o data bit 0 5dq 6 i/o data bit 6 31 dq 1 i/o data bit 1 6dq 7 i/o data bit 7 32 dq 2 i/o data bit 2 7ce 1 # i card enable 1 low 33 wp o write protect high 8a 10 i address bit 10 34 gnd ground 9 oe# i output enable low 35 gnd ground 10 a 11 i address bit 11 36 cd 1 # o card detect 1 low 11 a 9 i address bit 9 37 dq 11 i/o data bit 11 12 a 8 i address bit 8 38 dq 12 i/o data bit 12 13 a 13 i address bit 13 39 dq 13 i/o data bit 13 14 a 14 i address bit 14 40 dq 14 i/o data bit 14 15 we# i write enable low 41 dq 15 i/o data bit 15 16 rdy/bsy# o ready/busy low 42 ce 2 # i card enable 2 low 17 v cc supply voltage 43 vs 1 o voltage sense 1 n.c. 18 v pp1 supply voltage n.c. 44 rfu reserved 19 a 16 i address bit 16 45 rfu reserved 20 a 15 i address bit 15 46 a 17 i address bit 17 21 a 12 i address bit 12 47 a 18 i address bit 18 22 a 7 i address bit 7 48 a 19 i address bit 19 23 a 6 i address bit 6 49 a 20 i address bit 20 24 a 5 i address bit 5 50 a 21 i address bit 21 25 a 4 i address bit 4 51 v cc supply voltage 26 a 3 i address bit 3 52 v pp2 supply voltage n.c.
imc008/016/024/032/048/064flsg e 8 preliminary table 1. 5 volt value series 200 flash memory pc card definitions (continued) pin signal i/o function active pin signal i/o function active 53 a 22 i address bit 22 61 reg# i attribute memory select 54 a 2 3 i address bit 23 62 bvd 2 o battery voltage detect 2 55 a 24 i address bit 24 63 bvd 1 o battery voltage detect 1 56 a 25 i address bit 25 n.c. 64 dq 8 i/o data bit 8 57 vs 2 o voltage sense 2 n.c. 65 dq 9 i/o data bit 9 58 rst i reset high 66 dq 10 i/o data bit 10 59 wait# o extend bus cycle low 67 cd 2 # o card detect 2 low 60 rfu reserved 68 gnd ground table 2. 5 volt value series 200 flash memory pc card interface signal description symbol type name and function a 0 Ca 25 input address inputs: a 0 through a 25 enable direct addressing of up to 64 mb of memory on the card. signal a 0 is not decoded since the card is x16 only. the memory will wrap at the card density boundary. the system should not try to access memory beyond the cards density, since the upper addresses are not decoded. dq 0 Cdq 15 input/ output data input/output: dq 0 through dq 15 constitute the bi-directional data bus. dq 15 is the most significant bit. ce 1 #, ce 2 # input card enable 1 & 2: ce 1 # enables accesses on the low byte of the data bus d 0 C7 . ce 2 # enables accesses on the high byte of the data bus d 8C15 . both ce 1 # and ce 2 # are active low signals. a host is expected to assert both ce 1 # and ce 2 # as the cards memory provides for word-wide data transfers but not byte-wide data transfers. oe# input output enable: active low signal enabling read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# output ready/busy output: indicates status of internally timed erase or write activities. a high output indicates the memory card is ready to accept accesses. cd 1 #, cd 2 # output card detect 1 & 2: these signals provide for card insertion detection. the signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins.
e imc008/016/024/032/048/064flsg 9 preliminary table 2. 5 volt value series 200 flash memory pc card interface signal description (continued) symbol type name and function wp output write protect: this signal is pulled low for pc card standard compatibility. the flash memory card has no wp signal functionality. v pp1 ,v pp2 n.c. program/erase power supply: these power signals are not connected on the card as the cards memory devices use v cc for program (write) and erase power. v cc card power supply: 5.0 v for all internal circuitry. gnd ground for all internal circuitry. reg# input register select: the memory card has no separate attribute memory. the cis is located in common memory. reg# is unconnected on the card. rst input reset: active high signal for placing card in power-on default state. reset can be used as a power-down signal for the memory array. wait# output wait: (extended bus cycle) this signal is pulled high for pc card standard compatibility. the flash memory card has no wait# signal functionality. bvd 1 , bvd 2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs 1 , vs 2 output voltage sense: notifies the host socket of the cards v cc requirements. vs 1 and vs 2 are open to indicate a 5 v v cc card has been inserted. rfu reserved for future use n.c. no internal connection to card pin may be driven or left floating. 4.0 memory control logic 4.1 bus operations the host executes memory read, write and erase operations by issuing the appropriate command to the flash memorys command user interface (cui). the cui, which supports the command set of the cards memory devices, serves as the interface between the host processor and internal operation of a flash device. commands can be issued to the cui using standard microprocessor bus cycles. table 3 lists the pc cards bus operations and modes. for each listed bus operation or mode the table defines the value of the cards relevant bus and control signals.
imc008/016/024/032/048/064flsg e 10 preliminary 4.1.1 read array the host enables reads from the card by writing the appropriate read command to the cui. the memory devices automatically reset to read array mode upon initial card power-up or after card reset. ce 1 #, ce 2 #, and oe# must be logically active to obtain 16 data bits at the outputs. the card enable (ce 1 # and ce 2 #) inputs together with the cards address inputs are used to select the addressed devices. output enable (oe#) is the data input/output (d 0 C d 15 ) direction control, and when active, drives data from the selected memory onto the data bus. we# must be driven to v ih (inactive) during a read access. 4.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. outputs (d 0 Cd 15 ) are placed in a high-impedance state. table 3. card signal values for the card's bus operations and modes bus operation/mode reset# ce 1 #ce 2 # oe# we# a 1 d 8 C15 d 0C7 notes word read v ih v il v il v il v ih x high low 1, 2, 3 v ih v ih v il v il v ih x high low 1, 2, 3, 4 v ih v il v ih v il v ih x high low 1, 2, 3, 4 word write v ih v il v il v ih v il x high low 1, 2, 3 v ih v ih v il v ih v il x high low 1, 2, 3, 5 v ih v il v ih v ih v il x high low 1, 2, 3, 5 manufacturer id v ih v il v il v il v ih v il 00h 89h device id v ih v il v il v il v ih v ih 00h 14h 00h 15h standby v ih v ih v ih x x x high-z high-z output disable v ih xxv ih v ih x high-z high-z reset/power-down v il x x x x x high-z high-z notes: 1. x can be v il or v ih for control signals and address. 2. busy# is v ol when the wsm is executing internal write or block erase algorithms. it is v oh when the wsm is not busy, in erase suspend mode, or deep power-down mode. 3. high indicates high byte data, low indicates low byte data. 4. both memory bytes will be read from memory as the cards memory component data bus is word-wide and does not provide for individual byte access. the bus operation is non-compliant with the pcmcia pc card standard as the pc card standard specifies a byte read operation instead of a word read operation for the listed signal conditions. 5. both memory bytes will be written to memory as the cards memory component data bus is word-wide and does not provide for individual byte access. the bus operation is non-compliant with the pcmcia pc card standard as the pc card standard specifies a byte write operation instead of a word write operation for the listed signal conditions. if a host system desires a byte write operation instead of a word write operation, then the host system must write v ih to the unwanted active byte (which should be inactive according the pc card standard ) in order to prevent the unwanted active byte from being written to card memory.
e imc008/016/024/032/048/064flsg 11 preliminary 4.1.3 standby if both ce 1 # and ce 2 # are at a logic-high level (v ih ), the card enters standby mode. standby operation disables much of the cards circuitry and substantially reduces device power consumption. the outputs (d 0 Cd 15 ) are placed in a high- impedance state independent of the status of oe#. if the host deselects the card during a write or erase, the card continues to function and consume normal active power until the operation completes. 4.1.4 reset/power-down reset# at v il initiates the reset/power-down mode. in read modes, reset#-low deselects the cards memory, places output drivers in a high-impedance state, and turns off numerous internal memory circuits. reset# must be held low for a minimum of t w . time t su is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and all memory device status registers are set to 80h. during block erase, write, or lock-bit configuration modes, reset#-low will abort the operation busy# transitions low and remains low for a maximum time of t w + t su until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a write operation or partially altered after an erase or lock-bit configuration operation. time t su is required after reset# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert reset# during system reset. w hen the system comes out of reset, it expects to r ead data from the flash memory. automated flash memories provide status information when accessed during block erase, write, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper initialization following a system reset thr ough the use of the reset# input. in this application, reset# is controlled by the same signal that resets the system cpu. 4.1.5 read identifier codes the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 2). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting.
imc008/016/024/032/048/064flsg e 12 preliminary reserved for future implementation reserved for future implementation (blocks 32 through 62) reserved for future implementation reserved for future implementation (blocks 2 through 30) reserved for future implementation reserved for future implementation block 63 block 31 block 1 block 0 lock configuration reserved for future implementation block 0 master lock configuration manufacturer code device code 3fffff 3f0003 3f0002 3f0000 3effff 1effff 1f0003 1f0002 1f0000 01ffff 010003 010002 010000 00ffff 000004 000003 000002 000001 000000 32 mbit 64 mbit word address a[22-1]: 64 mbit a[21-1]: 32 mbit block 31 lock configuration block 63 lock configuration block 1 lock configuration 0606_06 notes: 1. data is always given on the low byte (upper byte contains 00h). 2. memory shown is accessed by the read identifier codes command only and is physically distinct from the cards flash memory array. 3. master lock function of the cards underlying memory devices is not a card function. the master lock configuration information identified in the above memory map is shown only for the sake of consistency between the illustrated memory map and a corresponding memory map shown in the datasheet for the memory devices. figure 2. device identifier code memory map 4.1.6 write writing commands to the cui enables reading of device data, query, identifier codes, inspection and clearing of the status register, as well as block erasure, writing of data and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word write command requires the command and address of the location to be written. the write to buffer command requires the command, starting address of the memory region to be written and the number of words to be written to the write buffer. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is part of each memory device and is written when the device is enabled and we# is active. the address and data needed to execute a command are latched on the rising edge of we# or the first edge of ce 1 # or ce 2 # that disables the device. write cycle timing is specified in section 8.5.2, write operations . 4.2 decode logic the cards decode logic enables the appropriate memory component during a read or write access of card memory. unused upper addresses for the 5 volt value series 200 flash memory pc card will not be decoded. the address decoding will wrap around at the cards density.
e imc008/016/024/032/048/064flsg 13 preliminary 5.0 command definition the operations of the cards memory device(s) are selected by the writing of specific commands into the cui. the 5 volt value series 200 flash memory pc card implements two command sets: the basic command set and the scaleable command set. the basic command set is backward compatible with value series 100 flash memory pc card with the exception that write (program) suspend is not supported in the series 200. the scaleable command set adds three capabilities to the pc card in addition to the basic command set: 1. common flash interface (cfi); 2. buffered writes which employ a 32-byte write buffer to allow higher performance writes than available with the basic command set; and 3. a configurable busy# output. 5.1 basic command set table 4 presents the 5 volt value series 200 pc cards basic command set. the table indicates that the commands require one or more bus cycles to implement. the table and notes following the table describe each bus cycle. complete descriptions of the individual commands follow in subsections of the current document section. 5.1.1 read array command upon initial device power-up and after exit from reset/power-down mode, the cards memory devices default to read array mode. this operation is also initiated by writing the read array command to a memory device. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, write, or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend command. table 4. basic command set definitions (9) command bus cycles req'd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read array 1 write x xxffh read identifier codes 3 2 5 write x xx90h read ia id read status register 2 write x xx70h read x srd clear status register 1 write x xx50h word write 2 6, 7 write x xx40h or xx10h write wa wd block erase 2 7 write x xx20h write ba xxd0h block erase suspend 1 7 write x xxb0h block erase resume 1 7 write x xxd0h set block lock-bit 2 write x xx60h write ba xx01h clear block lock-bits 2 8 write x xx60h write x xxd0h
imc008/016/024/032/048/064flsg e 14 preliminary notes: 1. card signal values for the identified bus operations are defined intable 3. 2. x = any valid address within the device. ia = identifier code address: ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. wd = data to be written at location wa. data is latched on the rising edge of we#. id = data read from identifier codes. 4. the upper byte of the data bus during command writes is a dont care (x). 5. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see read identifier section for read identifier code data. 6. either xx40h or xx10h are recognized by the wsm as the word-write command setup. 7. the issue of a block erase or write-word command to a locked block will fail. 8. the clear block lock-bits operation simultaneously clears all block lock-bits. 9. commands other than those shown above are reserved by intel for future device implementations and should not be used. 5.1.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command to a memory device. following the command write, read cycles from addresses shown in figure 2 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see table 5 for identifier code values). to terminate the operation, write another valid command. the read identifier codes command is valid only when the wsm is off or the device is suspended. following the read identifier codes command, the following information can be read: table 5. identifier codes (1) code addr (1) data manufacture code 00000 (00) 89 device code (28f640j5) 00001 (00) 15 device code (28f320j5) 00001 (00) 14 block lock configuration x 0002 (2) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 1 C7 master lock configuration (3) 00003 device is unlocked dq 0 = 0 device is locked dq 0 = 1 reserved for future use dq 1C7 notes: 1. data is always presented on the low byte (upper byte contains 00h). 2. x selects the specific blocks lock configuration code. see figure 2 for the device identifier code memory map. 3. see the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet for a description of master lock configuration information. for 5 volt value series 200 flash memory pc cards the master lock configuration byte should indicate that the device is unlocked (dq 0 = 0).
e imc008/016/024/032/048/064flsg 15 preliminary 5.1.3 read status register command the status register may be read to determine when a block erase, write, or lock-bit configuration operation is complete and whether the operation completed successfully. table 6 defines the content and format of the status register. the register may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or the first edge of ce 1 # and ce 2 # that enables the device (see table 3, card signal values for the cards bus operations and modes ). oe# must toggle to v ih or the device enter standby mode (see table 3) before further reads to update the status register latch. during a word write, write to buffer, block erase, set lock-bit, or clear lock-bit command sequence, only sr.7 is valid until the write state machine completes or suspends the operation. device i/o pins dq 0 Cdq 6 and dq 8 Cdq 15 are placed in a high- impedance state. when the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read. 5.1.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking of multiple blocks or writing of several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. the clear status register command is only valid when the wsm is off or the device is suspended.
imc008/016/024/032/048/064flsg e 16 preliminary table 6. status register definitions (1) wsms ess eclbs pslbs vpens r dps r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high z when busy? status register bits notes: no yes yes yes yes yes yes yes sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = write and set lock-bit status 1 = error in write operation or set master/block lock-bit 0 = successful write operation or set master/block lock bit sr.3 = programming voltage status 1 = low programming voltage detected, write operation aborted 0 = programming voltage ok sr.2 = reserved for future enhancements sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or reset# (rp#) lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements check busy# or sr.7 to determine block erase, write (program), or lock-bit configuration completion. sr.6 Csr.0 are not driven while sr.7 = 0. if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous memory device (write) programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, word write, write to buffer, set block/master lock-bit, or clear block lock-bits command sequences. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and reset# (rp#) only after block erase, write word, write to buffer or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or reset# (rp#) is not v hh . read the block lock and master lock configuration codes using the read identifier codes command to determine master and block lock-bit status. sr.2 and sr.0 are reserved for future use and should be masked when polling the status register. note: 1. see the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet for a description of the master lock-bit. for 5 volt value series 200 flash memory pc cards the master lock-bit should always be = 0 and should not interfere with any of the cards write or erase operations. the bit is referenced in the table for consistency of definition between the card and card memory device datasheets as the card status register information is actually provided by whatever memory device receives the read status register command.
e imc008/016/024/032/048/064flsg 17 preliminary table 7. extended status register definitions wbs reserved bit 7 bits 6 C0 high z when busy? status register bits notes: no yes xsr.7 = write buffer status 1 = write buffer available 0 = write buffer not available xsr.6 Cxsr.0 = reserved for future enhancements after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. sr.6Csr.0 are reserved for future use and should be masked when polling the status register. 5.1.5 block erase command erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup is first written, followed by an block erase confirm. this command sequence requires an appropriate address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase s equence is written, the device automatically outputs status register data when read. the cpu can detect block erase completion by analyzing the logic level of the sts pin or status register bit sr.7. toggle oe#, ce 1 # or ce 2 # to update the status register. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. successful block erase requires that the corresponding block lock-bit be cleared. if block erase is attempted when the corresponding block lock-bit is set, sr.1 and sr.5 will be set to 1. 5.1.6 block erase suspend command the block erase suspend command allows block- erase interruption to read or write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bit sr.7 then sr.6 can determine when the block erase operation has been suspended (both will be set to 1). the busy# output will also transition to v oh . specification t whrh defines the block erase suspend latency. at this point, a read array command can be written in order to read data from blo cks other t han that which is suspended. a word-write or write-to-buffer command sequence can also be issued during erase suspend to write data in other blo cks. during a write operation with block erase suspended, status register bit sr.7 will return to 0 and the busy# output will transition to v ol . the only other valid commands while block erase is suspended are read query, read status register, clear status register, configure, and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and the busy# output will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read. block erase cannot resume until write operations initiated during block erase suspend have completed.
imc008/016/024/032/048/064flsg e 18 preliminary 5.1.7 word-write command word-write commands are executed in a two- cycle command sequence. word-write command setup (standard 40h or alternate 10h) is written in the first cycle and then followed in the next cycle by a second write that specifies the address and data (latched on the rising edge of we#) to be written in memory. the wsm then takes over, controlling the word-write and word-write verify algorithms internally. after the word-write command sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the write event by analyzing the logic state of the busy# output or status register bit sr.7. when the word-write operation is complete, status register bit sr.4 should be checked. if a write error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. successful write operations require that the corresponding block lock-bit be cleared. if a word write operation is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set to 1. 5.1.8 set block lock-bit command a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. the block lock-bits gate memory write and erase operations. individual block lock-bits can be set using the set block lock-bit command. set block lock-bit commands are invalid while the wsm is running or the device is suspended. set block lock-bit commands are executed by a two-cycle s equence. the set block lock-bit setup along with appropriate block or device address is written followed by the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by analyzing the logic state of the busy# pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. 5.1.9 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. this command is invalid while the wsm is running or the device is suspended. clear block lock-bits command is executed by a two-cycle s equence. a clear block lock-bits setup is first written followed by the clear block lock-bits confirm. the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing the logic state of the busy# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock- bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. if a clear block lock-bits operation is aborted due to v cc transitioning out of valid range or reset# active transition, block lock-bit values are left in an undetermined state. a repeat of the clear block lock-bits command is then required to initialize block lock-bit contents to known values.
e imc008/016/024/032/048/064flsg 19 preliminary 5.2 scaleable command set table 8 presents the 5 volt value series 200 pc cards scaleable command set definitions . the table indicates that the commands require one or more bus cycles to implement. the table and notes following the table describe each bus cycle. complete descriptions of the individual commands follow in subsections of the current document section. table 8. scaleable command set definitions (10) command bus cycles req'd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read query 3 2 write x xx98h read qa qd write to buffer > 2 5, 6, 7, 8, 9 write ba xxe8h write ba n ? confirm 1 6, 7 write x xxd0h configuration 9 notes: 1. card signal values for the identified bus operations are defined in table 3. 2. x = any valid address within the device. qa = query database address. ba = block address. 3. qd = data read from query database. cc = configuration code. 4. the upper byte of the data bus during command writes is a dont care. 5. after the first bus cycle of the write to buffer command, check the extended status register to make sure the write buffer i s available for writing. if the buffer is available for writing, proceed with the second bus cycle; otherwise, continue repeating the first bus cycle and checking the extended status register in turn until the buffer becomes available; when the buffer becomes available, proceed with the second bus cycle of the write to buffer command. 6. the number of words to be written to the write buffer = n + 1, where n = word count argument. the word count range on this device is n = 0000h to n = 000fh. writing a word count outside the buffer boundary causes unexpected results and should be avoided. the third and consecutive bus cycles of a write to buffer command sequence, as determined by n, are for writing data into the write buffer. in the third bus cycle a device start address is given along with the write buffer data. subsequent write cycles provide additional device addresses and data. all subsequent addresses must lie within the start address plus the count. the confirm command (xxd0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see memory component data sheet for additional information on the wirte to buffer command. 7. the write buffer operation does not begin until a confirm command is issued. 8. the issue of a write to buffer command to a locked block will fail. 9. the configuration command is not supported on the 5 volt value series 200 flash memory pc card. the configuration command serves to program the configurable status output (sts output pin) of a memory device. to satisfy the pcmcia pc card specification the sts output pin for all card memory devices must be configured as a ry/by# pin to generate the cards busy# output signal. at card power-up the sts output for all devices defaults to ry/by# pin operation; thereafter, host software shall not issue the configuration command. 10. commands other than those shown above are reserved for future use and should not be used.
imc008/016/024/032/048/064flsg e 20 preliminary 5.2.1 block write command to write to the flash device write buffer, a write to buffer command sequence is initiated. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. first, the write to buffer setup command is issued along with the block address of the memory device erase block to which the buffer content will be written. at this point, the extended status register (xsr) information (reference table 7) is loaded into the register and xsr.7 reverts to reflecting buffer available status. whenever the memory device is read immediately after receiving a write to buffer command, the xsr content will be presented by the memory. if xsr.7 = 0, the write buffer is not available for writing. when xsr.7 = 1, the memory device will allow data to be written to the write buffer. to determine when the write buffer can be written, continue to monitor xsr.7 until xsr.7 = 1 by repeating the sequence of first issuing the write to buffer setup command along with the appropriate block address, and then reading the extended status register. when the write buffer becomes available for writing, a word count (n) is given to the memory device with the block address of the memory device erase block to which the buffer content will be written. on the next write, a device start address is given along with the write buffer data. for maximum programming performance and lower power, align the start address at the beginning of a write buffer boundary. subsequent writes provide additional device addresses and data. all subsequent addresses must lie within the start address plus the count. after the final buffer data is given, a write confirm command is issued. this initiates the wsm (write state machine) to begin copying the buffer data to the flash memory. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr.5 and sr.4 will be set to a 1. for additional buffer writes, issue another write to buffer setup command and check xsr.7. the write buffers can be loaded while the wsm is busy as long as xsr.7 indicates that a buffer is available. if an error occurs while a device is writing data to memory, the device will stop writing, and status register bit sr.4 will be set to a 1 to indicate a write operation failure. any time a media failure occurs during a write or an erase (for which sr.4 or sr.5 is set, respectively), the device will not except any more buffered write commands. additionally, if the user attempts to write past an erase block boundary with a write to buffer command, the device will abort the write. this will generate an invalid command/sequence error (botch) and status register bits sr.5 and sr.4 will be set to a 1. to clear sr.4 and/or sr.5 issue a clear status register command. successful writing to an erase block requires that the blocks associated block lock-bit bit be reset. if the block lock-bit is set, the erase block is locked. a write to buffer command which attempts to write data to the locked block will fail and result in sr.1 and sr.4 being set to 1. 5.2.2 configuration command the configuration command is not supported on the 5 volt value series 200 pc card. the configuration command serves to program the configurable status output (sts output pin) of a memory device. to satisfy the pcmcia pc card specification the sts output pin for all card memory devices must be configured as a ry/by# pin to generate the cards busy# output signal. at card power-up the sts output for all devices defaults to ry/by# pin operation; thereafter, host software shall not issue the configuration command. 5.2.3 read query command the scs (scaleable command set) read query command causes the flash component to display the common flash interface (cfi) query structure or database. the common flash interface provides a standard means for a flash memory to tell a host system about the memory's architecture, algorithms and characteristics. see ap-646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. writing the read query command to the memory puts it in read query mode. while in read query mode, the memory responds to read bus operations with data from a rom instead of data from the flash array data. the data in the rom describes the memory component to which the ready query command is addressed. as the definition of cfi data presented by a card memory device is quite extensive, the definition is not repeated as part of the current document. refer
e imc008/016/024/032/048/064flsg 21 preliminary to the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 (order number 290606) for a complete definition of the card memorys cfi data and the read query command by which the data is accessed. 6.0 card attribute information 6.1 pc card information structure the card information structure (cis) begins at address 00000000h of the cards common memory plane and resides sequentially in memory locations with even byte memory addresses. it contains a variable length chain of data blo cks (tuples) that conform to the basic format described in table 9. the cis of the 5 volt value series 200 flash memory pc card is found in table 10. caution: the cis data in block 0 is not write protected and should not be erased by the system software if the cis is needed for card recognition. table 9. pc card tuple format bytes data 0 tuple code: cistpl_xxx. the tuple code 0ffh indicates no more tuples in the list. 1 tuple link: tpl_link. link to the next tuple in the list. this can be viewed as the number of additional bytes in tuple, excluding this byte. a link field of zero indicates an empty tuple body. a link field containing 0ffh indicates the last tuple in the list. 2-n bytes specific to this tuple. 6.2 cis data cis data is located in memory and describes the 5 volt value series 200 flash memory pc card as illustrated in table 10. table 10. 5 volt value series 200 card tuples address value description 00h 01h cistpl_device 02h 03h tpl_link 04h 52h type/speed flash / 200 ns 06h 1eh 3eh 5eh 7eh beh feh card size: 8 mb 16 mb 24 mb 32 mb 48 mb 64 mb 08h ffh end of device 0ah 1eh cistpl devicegeo 0ch 06h tpl_link 0eh 02h dgtpl_bus 10h 11h dgtpl_ebs 12h 01h dgtpl_rbs 14h 01h dgtpl_wbs 16h 01h dgtpl_part = 1 18h 01h flash device interleave 1ah 20h cistpl_manfid 1ch 04h tpl_link (04h) 1eh 89h tplmid_manf: lsb 20h 00h tplmid_manf: msb 22h 21h 31h 81h 51h 61h 91h 8mb - 200 ns 16 mb - 200 ns 24 mb - 200 ns 32 mb - 200 ns 48 mb - 200 ns 64 mb - 200 ns 24h 86h tplmid_card msb value series 200 card
imc008/016/024/032/048/064flsg e 22 preliminary table 10. 5 volt value series 200 card tuples address value description 26h 21h cistpl_funcid 28h 02h tpl_link 2ah 01h tplfid_function : memory 2ch 00h tplfid_sysinit 2eh 12h cistpl_longlink_c 30h 04h tpl_link 32h 00h lowest byte 34h 00h 36h 02h 38h 00h highest byte 3ah 15h cistpl_vers1 3ch 40h tpl_link 3eh 05h tpllv1_major 40h 00h tpllv1_minor 42h 69h tpllv1_info i 44h 6eh n 46h 74h t 48h 65h e 4ah 6ch l 4ch 00h end text 4eh 56h v 50h 41h a 52h 4ch l 54h 55h u 56h 45h e 58h 20h space 5ah 53h s 5ch 45h e 5eh 52h r table 10. 5 volt value series 200 card tuples address value description 60h 49h i 62h 45h e 64h 53h s 66h 20h space 68h 32h 2 6ah 30h 0 6ch 30h 0 6eh 20h space 70h 00h end text 72h 30h 31h 32h 33h 34h 36h 8 mb 16 mb 24 mb 32 mb 48 mb 64 mb 74h 38h 36h 34h 32h 38h 34h 8 mb 16 mb 24 mb 32 mb 48 mb 64 mb 76h 20h space 78h 00h end text 7ah 43h c 7ch 4fh o 7eh 50h p 80h 59h y 82h 52h r 84h 49h i 86h 47h g 88h 48h h 8ah 54h t 8ch 20h space 8eh 49h i 90h 4eh n
e imc008/016/024/032/048/064flsg 23 preliminary table 10. 5 volt value series 200 card tuples address value description 92h 54h t 94h 45h e 96h 4ch l 98h 20h space 9ah 43h c 9ch 4fh o 9eh 52h r a0h 50h p a2h 4fh o a4h 52h r a6h 41h a a8h 54h t aah 49h i ach 4fh o aeh 4eh n b0h 20h space b2h 31h 1 b4h 39h 9 b6h 39h 9 b8h 37h 7 table 10. 5 volt value series 200 card tuples address value description bah 00h end text bch ffh end of list beh 18h cistpl_jedec_c c0h 02h tpl_link c2h 89h manufacturer id c4h 15h jedec id for memory devices c6h ffh cistpl_end c8h 00h invalid address
imc008/016/024/032/048/064flsg e 24 preliminary 7.0 system design considerations 7.1 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby, active and transient current peaks which are produced by rising and falling edges of ce 1 # and ce 2 #. the capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks. three-line control and proper decoupling capacitor selection suppress transient voltage peaks. the 5 volt value series 200 cards contain on-card ceramic decoupling capacitors connected between v cc and gnd. the card connector should also have a 4.7 f electrolytic capacitor between v cc and gnd. the bulk capacitors overcome voltage slumps caused by printed-circuit-board trace inductance, and supply charge to the smaller capacitors as needed. 7.2 power-up/down protection the pcmcia/jeida-specified socket properly sequences the power supplies to the flash memory card via shorter and longer pins. each device in the memory card is designed to offer protection against accidental erasure or writing, caused by spurious system-level si gnals that may exist during power transitions. the card will power-up into the read state. a system desi gner must guard against active writes for v cc voltages above v lko (0.7 v cc ). since we# must be low and ce 1 # or ce 2 # must be low for a command write, driving either we# to v ih or both ce 1 # and ce 2 # to v ih will inhibit writes. with its control register architecture, alteration of device contents only occurs after successful completion of the two-step command sequences. 7.3 rdy/bsy# and write/block erase status polling rdy/bsy# is a full cmos output that provides a hardware method of detecting write and block erase completion. it transitions low time t whrl after a write or erase command sequence is written to a 28f640j5 memory device, and returns to v oh when all the wsm has finished executing the internal algorithm. rdy/bsy# can be connected to the interrupt input of the system cpu or controller. it is active at all times. rdy/bsy# is also v oh when the device is in erase suspend or deep power-down modes.
e imc008/016/024/032/048/064flsg 25 preliminary 8.0 electrical specifications 8.1 absolute maximum ratings* operating temperature during read, block erase, write, and lock-bit configuration ..... 0 c to +70 c (1) temperature under bias ........ C10 c to +80 c storage temperature................. C65 c to +125 c voltage on any pin ................... C2.0 v to +7.0 v (2) output short circuit current.....................100 ma (3) notice: this datasheet contains preliminary information on new products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc pin. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 8.2 operating conditions temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature 0 +70 c ambient temperature v cc v cc supply voltage (5 v 10%) 4.75 5.25 v 8.3 capacitance (1) t a = +25 c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested.
imc008/016/024/032/048/064flsg e 26 preliminary 8.4 dc characteristics test symbol parameter notes typ max unit conditions i li input load current 1,4 20 m a v cc = v cc max, v in = v cc or gnd i lo output leakage current 120 m a v cc = v cc max, v in = v cc or gnd i ccs v cc standby current m a v cc = v cc max 8-mbyte card 1,3 180 320 ce 1 # = ce 2 # = v cc 0.2v 16-mbyte card 1,3 340 620 cmos inputs 24-mbyte card 1,3 500 920 32-mbyte card 1,3 660 1220 48-mbyte card 1,3 500 920 64-mbyte card 1,3 660 1220 i ccd v cc deep power- down current m a reset, control signals = 8-mbyte card 1 180 220 v cc 0.2 v 16-mbyte card 1 340 520 i out (ready) = 0 ma 24-mbyte card 1 500 770 32-mbyte card 1 660 1020 48-mbyte card 1 500 770 64-mbyte card 1 660 1020 i ccr v cc read current 1 35 55 ma v cc = v cc max, ce 1 #/ ce 2 # = gnd, f = 5 mhz, i out = 0 ma i ccw v cc word write or set lock-bit current 1,3 35 60 ma cmos inputs i cce v cc block erase or clear lock-bits current 1,3 35 70 ma cmos inputs i cces v cc block erase suspend current 1,2 10 ma ce 1 # = ce 2 # = v ih
e imc008/016/024/032/048/064flsg 27 preliminary 8.4 dc characteristics (continued) test sym parameter notes min max unit conditions v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min, i ol = 5.8 ma v oh output high voltage 0.85 v cc v v cc = v cc min, i oh = C2.5 ma v cc C 0.4 v cc = v cc min, i oh = C100 a v lko v cc lockout voltage 3.25 v notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (speeds). contact intels application support hotline or your local sales office for information about typical specifications. 2. i cces is specified with the cards memory de-selected. if read or word write occurs while in erase suspend mode, the cards current draw is the sum of i cces and either i ccr (read) or i ccw (write). 3. cmos inputs are either v cc 0.2 v or gnd 0.2 v. 4. exceptions: with v in = gnd, the leakage current on ce 1 #, ce 2 # will be < 50 m a each due to internal pull-up resistors. test points input output 1.5 3.0 0.0 1.5 0581_06 note: 1. ac test inputs are driven at 3.0v for a logic 1 and 0.0 v for a logic 0. input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. figure 3. transient input/output reference waveform for v cc = 5 v 5% (standard test configuration) device under test out r l = 3.3 k w 1n914 1.3v c l note: c l includes jig capacitance figure 4. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v cc = 5.0 v 5% 100
imc008/016/024/032/048/064flsg e 28 preliminary 8.5 ac characteristics ac timing diagrams and characteristics are designed to meet or exceed pcmcia 2.1 specifications. no delay occurs when switching between the common and attribute memory planes. 8.5.1 read operations common memory (1) symbol 8 C 64-mb cards ieee pcmcia parameter min max unit t avav t c r read cycle time 200 ns t avqv t a (a) address access time 200 ns t elqv t a (ce) ce# access time 200 ns t glqv t a (oe) oe# access time 100 ns t ehqz t dis (ce) output disable time from ce# inactive 90 ns t ghqz t dis (oe) output disable time from oe# inactive 90 ns t glqx t en (oe) output enable time from oe# active (1) ns t elqx t en (ce) output enable time from ce# active (1) ns t axqx data hold from address, ce#, or oe# change (whichever occurs first) ns t elgl ce# setup time to oe# active ns t avgl address setup time to oe# active ns t phqv rdy/bsy# high to output delay 210 ns note: 1. sampled, not 100% tested
e imc008/016/024/032/048/064flsg 29 preliminary a4533-01 device and address selection outputs enabled power-up standby valid output address stable note 1 note 1 data valid standby v cc v cc power- down t ghqz t ehqz t avav t glqv t axqx high z high z v ih v il v ih v il v ih v il addresses(a) ce#(c) oe#(g) v ih v il we#(w) v oh v ol data(d/q) t elqv t elqx t avqv t glqx note 1: the filled area may be either high or low note 1 note 1 049102 figure 5. ac waveforms for read operations
imc008/016/024/032/048/064flsg e 30 preliminary 8.5.2 write operations (1, 2) symbol 8 C 64-mb cards jedec pcmcia parameter min max unit t avav t c w write cycle time 200 ns t wlwh t w (we) we# pulse width 120 ns t avwl t su (a) address setup time to we# active 20 ns t avwh t su (a-weh) address setup time for we# 140 ns t elwh t su (ceweh) card enable setup time for we# 140 ns t dvwh t su (d-weh) data setup time for we# inactive 60 ns t whdx t h (d) data hold time from we# inactive 30 ns t whax t rec (we) write recovery time 30 ns t whgl t h (oe-we) output enable hold from we# 10 ns t whrl we# (ce#) inactive time to rdy/bsy# active 90 ns notes: 1. these timings apply only if both ce#s (ce 1 # and ce 2 #) are deasserted prior to we# asserted. 2. read timing characteristics during erase and write operations are the same as during read-only operations. refer to ac characteristics for read-only operations.
e imc008/016/024/032/048/064flsg 31 preliminary addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# ih v il v ih v il v ih v il v ih v il v il v in d in a in a valid srd in d whrl t high z whdx t ih v il v v (v) pp 12 3 4 6 5 pph v ih v ppl v avav t avwh t whax t dvwh t wlwh t qvvl t vpwh t in d avwl t whgl t whqv1,2 t elwh t phwl t rdy/bsy# (r) il v ih v oh v ol v 0491_03 notes: 1. v cc power-up and standby 2. write program or erase setup command 3. write valid address and program or erase confirm command 4. automated program or erase delay 5. read status register data 6. write read array command figure 6. ac waveforms for write operations
imc008/016/024/032/048/064flsg e 32 preliminary 8.5.3 power-up timing (1, 2) symbol parameter notes min max units pcmcia v i (ce) ce# signal level (0.0 v < v cc < 2.0 v) 1 0 v imax v ce# signal level (2.0 v < v cc < v ih )1v cc C 0.1 v imax v ce# signal level (v ih < v cc )1v ih v imax v t su (v cc ) ce# setup time 20 ms t su (reset) ce# setup time 20 ms t rec (v cc ) ce# recover time 1.0 s t pr v cc rising time 2 0.1 300 ms t pf v cc falling time 2 3.0 300 ms t w (reset) reset width 10 s t h (hi-z reset) reset width 3 36 s t s (hi-z reset) reset width 0 ms notes: 1. v imax means absolute maximum voltage for input in the period of 0.0 v < v cc < 2.0 v, v i (ce#) is only 0.00 v ~ v imax. 2. the t pr and t pf are defined as linear waveforms in the period of 10% to 90%, or vice-versa. even if the waveform is not a linear waveform, its rising and falling time must meet this specification. 3. if reset# is asserted while a block erase, write, or lock-bit configuration operation is not executing, then the minimum required reset# pulse low time is 1 s. 4. a rest time, t phqv (reference section 8.5.1) is required from busy# or reset# going high until outputs are valid.
e imc008/016/024/032/048/064flsg 33 preliminary 049105 figure 7. power-up timing for systems supporting reset# 8.6 block erase, write, and lock-bit configuration performance (3,4) sym parameter notes min typ (1) max units t whqv1 t ehqv1 write buffer word write time 2, 5, 6 tbd 6 tbd s t whqv2 t ehqv2 word write time (using word write command) 2, 6 tbd 180 tbd s ? block write time (using write to buffer command) 2, 6 tbd 0.8 tbd sec t whqv4 t ehqv4 block erase time 2 tbd 0.7 tbd sec t whqv5 t ehqv5 set lock-bit time 2 tbd 32 tbd s t whqv6 t ehqv6 clear block lock-bits time 2 tbd 0.3 tbd sec t whrh t ehrh erase suspend latency time to read 26 35 s notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. these values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. the maximum write time is the absolute maximum time it takes the write algorithm to complete. the overwhelming majority of the bits are written within the typical value specified. to maximize system performance, the rdy/bsy# signal should be polled to determine the completion of a write operation.
imc008/016/024/032/048/064flsg e 34 preliminary 9.0 packaging all 5 volt value series 200 flash memory pc cards have the pcmcia type 1 form factor. this figure shows the outside dimensions of a card. for complete mechanical drawings refer to the pcmcia pc card specification . a4495-01 w l c connector surface a surface b surface a x 2x s x x #34 #68 y #1 #35 2x t p 1 1 1 2 2 polarization key length 3 millimeters are in parenthesis () interconnect area tolerance = 0.002 substrate area tolerance = 0.004 c min 0.294 (10.0) l 0.008 3.370 (85.60) w 0.004 2.126 (54.0) p min 0.394 (10.0) s min 0.118 (3.0) t 0.065 (1.65) x 0.002 0.039 (1.00) y 0.002 0.063 (1.60) substrate area interconnect area
e imc008/016/024/032/048/064flsg 35 preliminary 10.0 ordering information imc008flsg, sbxxxxx where: i = intel mc = memory card 008 = density in megabytes (008, 016, 024, 032, 048, 064 available) fl = flash technology s = blocked architecture g = revision sbxxxxx = customer identifier 11.0 additional information order number document 210830 flash memory databook 290621 5 volt value series 200 flash memory card specification update 290606 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet 292205 ap-647 5 volt intel ? strataflash? memory design guide 292204 ap-646 common flash interface (cfi) and command sets 292203 ap-644 migration guide to intel ? strataflash? memory note 3 ap-374 flash memory write protection techniques note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. these documents can be located at the intel world wide web support site, http://www.intel.com/support/flash/memory

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