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? s14024.b LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller technical manual april 2001 version 2.2
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000101-02, fourth edition (april 2001) this document describes the lsi logic LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. ultra scsi is the term used by the scsi trade association (sta) to describe fast-20 scsi, as documented in the scsi-3 fast-20 parallel interface standard, x3.277-199x. ultra2 scsi is the term used by the scsi trade association (sta) to describe fast-40 scsi, as documented in the scsi parallel interfaceC2 standard, (spiC2) x3t10/1142d. copyright ? 1998C2001 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, sdms, scripts, symplicity, and lvdlink are registered trademarks or trademarks of lsi logic corporation. arm is a registered trademark of advanced risc machines limited, used under license. all other brand and product names may be trademarks of their respective companies. sr
preface iii preface this book is the primary reference and technical manual for the lsi logic corporation LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller. it contains a complete functional description for the product and includes complete physical and electrical speci?cations. this technical manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided in the related publications list. audience this document was prepared for system designers and programmers who are using this device to design an ultra2 scsi port for pci-based personal computers, workstations, servers or embedded applications. organization this document has the following chapters and appendix: chapter 1, introduction , provides a general overview about the LSI53C1510. chapter 2, functional description , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. chapter 3, software description , describes the software features, ?rmware features, and hardware requirements. chapter 4, signal descriptions , contains the pin con?guration signal de?nitions.
iv preface chapter 5, registers (nonintelligent mode) , describes the pci and host interface registers that are visible to the host in nonintelligent mode. chapter 6, registers (intelligent mode) , describes the pci and host interface registers that are visible to the host in intelligent mode. chapter 7, speci?cations , contains the electrical characteristics and ac timing diagrams. appendix a, register summary , is a register summary. related publications for background please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface
preface v lsi logic world wide web home page www.lsil.com pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 i 2 o (intelligent input/output) sig web site http:\\www.i2osig.org LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller programming guide scsi scripts processors programming guide, order number s14044.a lsi53c896 pci to dual channel ultra2 scsi multifunction controller technical manual , order number s14015.b conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111.
vi preface revision record revision date remarks 0.1 3/98 first draft. 0.2 4/98 second draft. 1.0 5/98 preliminary. 1.1 5/98 preliminary. change bars mark all changes. in chapter 7, all gpio0_fetch/ and gpio1_master/ items were deleted. 2.0 1/00 final version. 2.1 11/00 updated table 7.2 operating conditions. all product names changed from sym to lsi. 2.2 4/01 updated dc electrical speci?cations and test conditions.
contents vii contents chapter 1 introduction 1.1 general description 1-1 1.1.1 block diagram 1-2 1.2 module overviews 1-3 1.2.1 pci interface 1-3 1.2.2 memory controller 1-3 1.2.3 i2o message unit 1-3 1.2.4 arm7tdmi risc processor 1-4 1.2.5 raid parity assist engine (pae) 1-4 1.2.6 scsi cores 1-4 1.3 LSI53C1510 features 1-4 1.3.1 features list 1-5 1.4 LSI53C1510 bene?ts 1-5 1.4.1 ultra2 scsi bene?ts 1-5 1.4.2 lvdlink? bene?ts 1-6 1.4.3 tolerant ? technology bene?ts 1-6 1.4.4 i2o bene?ts 1-7 1.4.5 pae bene?ts 1-7 1.4.6 arm7tdmi risc processor bene?ts 1-8 1.5 LSI53C1510 bene?ts summary 1-8 1.5.1 pci performance 1-8 1.5.2 scsi performance 1-8 1.5.3 raid performance 1-9 1.5.4 testability 1-9 1.5.5 integration 1-10 1.5.6 reliability 1-10 1.6 applications 1-11 1.6.1 embedded motherboard application 1-11 1.6.2 host adapter board application 1-12
viii contents chapter 2 functional description 2.1 modes of operation 2-2 2.1.1 LSI53C1510 overview 2-3 2.1.2 con?guration and initialization 2-4 2.1.3 i2o overview 2-6 2.1.4 i2o conceptual overview 2-6 2.1.5 i2o bene?ts 2-7 2.1.6 the i2o communications model 2-8 2.1.7 operational overview 2-8 2.1.8 system interface 2-8 2.2 the host interface 2-11 2.2.1 messages 2-11 2.2.2 message transport 2-11 2.2.3 request message 2-12 2.2.4 reply message 2-14 2.3 LSI53C1510 protocol engine 2-16 2.3.1 random block storage class 2-16 2.4 support components 2-18 2.4.1 dram memory 2-19 2.4.2 flash rom 2-19 2.4.3 serial eeprom 2-19 chapter 3 software description 3.1 pci raid software solutions 3-1 3.1.1 pci raid 3-1 3.1.2 symplicity storage manager 3-2 3.1.3 wind river systems ixworks rtos 3-3 3.2 management software features 3-3 3.3 raid firmware features 3-3 3.3.1 raid levels 0, 1, 3, 5, and 10 3-4 3.3.2 caching 3-5 3.3.3 runs in optimal and degraded mode 3-5 3.3.4 hardware assisted parity calculation 3-6 3.3.5 tagged command queuing 3-6 3.3.6 global hot spare drives 3-6 3.3.7 hot swap drive with automatic, transparent reconstruction 3-7
contents ix 3.3.8 variable stripe size 3-7 3.3.9 online dynamic capacity expansion 3-7 3.3.10 online raid level migration/recon?guration 3-7 3.3.11 battery backup support and cache recovery 3-8 3.3.12 supports saf-te 3-8 3.4 sdms software 3-8 3.5 memory requirements 3-8 chapter 4 signal descriptions 4.1 signal groupings 4-2 4.2 pci interface signals 4-4 4.2.1 system signals 4-4 4.2.2 address and data signals 4-5 4.2.3 interface control signals 4-6 4.2.4 arbitration signals 4-7 4.2.5 interrupt signals 4-7 4.2.6 arm signal 4-8 4.2.7 error recording signals 4-8 4.2.8 power management signal 4-8 4.2.9 gpio interface signals 4-9 4.3 scsi interface signals 4-10 4.3.1 scsi clock signal 4-10 4.3.2 scsi a-channel interface signals 4-10 4.3.3 scsi b-channel interface signals 4-13 4.4 memory interface signals 4-15 4.4.1 rom/sram interface signals 4-15 4.4.2 scan signals 4-16 4.4.3 dram interface signals 4-17 4.5 miscellaneous interface signals 4-18 4.5.1 uart interface signals 4-18 4.5.2 jtag interface signals 4-18 4.5.3 arm debug interface signals 4-19 4.5.4 raid interface signal 4-19 4.5.5 power and ground signals 4-20
x contents chapter 5 registers (nonintelligent mode) 5.1 pci functional description (nonintelligent mode) 5-3 5.1.1 pci addressing 5-3 5.1.2 pci bus commands and functions supported 5-5 5.1.3 internal arbiter 5-9 5.1.4 pci cache mode 5-9 5.2 pci con?guration registers (nonintelligent mode) 5-10 5.3 differences from the lsi53c895 and the lsi53c896 5-26 chapter 6 registers (intelligent mode) 6.1 programming models 6-3 6.1.1 system programming model 6-3 6.1.2 local programming model 6-3 6.2 pci con?guration registers (intelligent mode) 6-4 6.3 host interface registers (intelligent mode) 6-19 6.4 shared memory 6-27 chapter 7 speci?cations 7.1 dc characteristics 7-1 7.2 tolerant technology electrical characteristics 7-7 7.3 ac characteristics 7-11 7.4 pci and external memory interface timing diagrams 7-14 7.4.1 target timing 7-14 7.4.2 initiator timing 7-20 7.4.3 external memory timing 7-31 7.5 scsi timing diagrams 7-36 7.6 pinouts and packaging 7-43 appendix a register summary index customer feedback
contents xi figures 1.1 LSI53C1510 block diagram 1-2 1.2 typical LSI53C1510 mainboard applications 1-11 1.3 typical LSI53C1510 host adapter board application 1-12 2.1 LSI53C1510 block diagram 2-3 2.2 example of LSI53C1510 physical con?gurations 2-7 2.3 hardware messaging unit 2-10 2.4 LSI53C1510 request message transport 2-14 2.5 LSI53C1510 reply message transport 2-15 2.6 typical implementations 2-18 4.1 LSI53C1510 functional signal groupings 4-3 5.1 LSI53C1510 block diagram in nonintelligent mode 5-2 6.1 LSI53C1510 block diagram in intelligent mode 6-2 6.2 shared memory address translation 6-27 7.1 lvd driver 7-3 7.2 lvd receiver 7-4 7.3 rise and fall time test condition 7-8 7.4 scsi input filtering 7-8 7.5 hysteresis of scsi receivers 7-9 7.6 input current as a function of input voltage 7-9 7.7 output current as a function of output voltage 7-10 7.8 external clock 7-11 7.9 reset input 7-12 7.10 interrupt output 7-13 7.11 pci con?guration register read 7-15 7.12 pci con?guration register write 7-16 7.13 operating registers/scripts ram read, 32-bit 7-17 7.14 operating registers/scripts ram write, 32-bit 7-18 7.15 nonburst opcode fetch, 32-bit address and data 7-21 7.16 burst opcode fetch, 32-bit address and data 7-23 7.17 back-to-back read, 32-bit address and data 7-25 7.18 back-to-back write, 32-bit address and data 7-27 7.19 burst read, 32-bit address and data 7-29 7.20 burst write, 32-bit address and data 7-31 7.21 edo dram burst read 7-33 7.22 flash rom normal read only mode 7-34 7.23 flash rom program/verify mode 7-35
xii contents 7.24 initiator asynchronous send 7-36 7.25 initiator asynchronous receive 7-37 7.26 target asynchronous send 7-38 7.27 target asynchronous receive 7-38 7.28 initiator and target synchronous transfer 7-42 7.29 left half of the LSI53C1510 388 bga chip - top view 7-44 7.30 LSI53C1510 388 ball grid array 7-48 7.31 388 pbga (ii) mechanical drawing 7-49 tables 2.1 LSI53C1510 modes 2-2 2.2 rom size con?gurations 2-5 2.3 con?guration options 2-5 2.4 supported random block storage messages 2-17 4.1 pin type description 4-1 4.2 system signals 4-4 4.3 address and data signals 4-5 4.4 interface control signals 4-6 4.5 arbitration signals 4-7 4.6 interrupt signals 4-7 4.7 arm signal 4-8 4.8 error recording signals 4-8 4.9 power management signal 4-8 4.10 gpio interface signals 4-9 4.11 scsi clock signal 4-10 4.12 scsi a-channel interface signals 4-10 4.13 scsi b-channel interface signals 4-13 4.14 rom/sram interface signals 4-15 4.15 scan signals 4-16 4.16 dram interface signals 4-17 4.17 uart interface signals 4-18 4.18 jtag interface signals 4-18 4.19 arm debug interface signals 4-19 4.20 raid interface signal 4-19 4.21 power and ground signals 4-20 5.1 pci bus commands encoding 5-5 5.2 pci con?guration register map 5-10
contents xiii 6.1 pci con?guration register map 6-4 6.2 LSI53C1510 host interface register map 6-19 7.1 absolute maximum stress ratings 7-2 7.2 operating conditions 7-2 7.3 lvd driver scsi signalssd[15:0]+, sdp[1:0]/, sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 7-3 7.4 lvd receiver scsi signalssd[15:0]/, sdp[1:0]/, sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 7-3 7.5 diffsens scsi signal 7-4 7.6 rbias scsi signal 7-4 7.7 input capacitance 7-4 7.8 bidirectional signalsgpio0, gpio1, gpio2, gpio3, gpio4 7-5 7.9 output signalsmce/, moe/_testout, mwe/, tdo 7-5 7.10 bidirectional signalsad[31:0], c_be[7:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par 7-5 7.11 input signalsclk, gnt/, idsel, rst/, sclk, tck, tdi, test_hsc, test_rstn, tms 7-6 7.12 output signalsinta, intb 7-6 7.13 output signalserr/ 7-6 7.14 tolerant technology electrical characteristics for se scsi signals 7-7 7.15 external clock 7-11 7.16 reset input 7-12 7.17 interrupt output 7-13 7.18 pci con?guration register read 7-15 7.19 pci con?guration register write 7-16 7.20 operating registers/scripts ram read, 32-bit 7-17 7.21 operating registers/scripts ram write, 32-bit 7-18 7.22 nonburst opcode fetch, 32-bit address and data 7-20 7.23 burst opcode fetch, 32-bit address and data 7-22 7.24 back-to-back read, 32-bit address and data 7-24 7.25 back-to-back write, 32-bit address and data 7-26 7.26 burst read, 32-bit address and data 7-28 7.27 burst write, 32-bit address and data 7-30
xiv contents 7.28 dram timing parameters (using 50 ns extended data out mode) 7-32 7.29 initiator asynchronous send 7-36 7.30 initiator asynchronous receive 7-37 7.31 target asynchronous send 7-38 7.32 target asynchronous receive 7-38 7.33 scsi-1 transfers (se 5.0 mbytes) 7-39 7.34 scsi-1 transfers (differential 4.17 mbytes) 7-39 7.35 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock 7-40 7.36 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 50 mhz clock 7-40 7.37 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 7-41 7.38 ultra scsi hvd transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) 80 mhz clock 7-41 7.39 ultra2 scsi transfers 40.0 mbytes (8-bit transfers) or 80.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 7-42 7.40 signal names and bga position 7-46 7.41 signal names by bga position 7-47 a.1 LSI53C1510 pci registers (nonintelligent mode) register map a-1 a.2 LSI53C1510 pci registers (intelligent mode) register map a-2 a.3 LSI53C1510 host interface registers (intelligent mode) a-4
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 1-1 chapter 1 introduction this chapter provides a general overview of the LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller. the chapter contains the following sections: section 1.1, general description, page 1-1 section 1.2, module overviews, page 1-3 section 1.3, LSI53C1510 features, page 1-4 section 1.4, LSI53C1510 bene?ts, page 1-5 section 1.5, LSI53C1510 bene?ts summary, page 1-8 section 1.6, applications, page 1-11 1.1 general description the LSI53C1510 is a single chip i 2 o-ready pci raid ultra2 scsi controller. the LSI53C1510 contains a 32-bit risc arm7tdmi processor and a raid parity assist engine (pae). the risc processor frees the host cpu from the burden of processing i/o requests and reduces the number of i/o interrupts, thus improving system performance. the risc processor and associated ?rmware contain the ability to manage an i/o from start to ?nish without host intervention. the risc processor manages the intelligent input/output (i 2 o) message passing interface.
1-2 introduction the LSI53C1510 has two modes of operation: intelligent or nonintelligent mode. in intelligent mode, the LSI53C1510 functions as an embedded raid controller on a motherboard or as an add-in raid host adapter board. in nonintelligent mode the LSI53C1510 functions as a pci to scsi dual channel wide ultra2 controller. the LSI53C1510 is sold as a package with lsi logic i 2 o raid software to provide a raid solution. therefore, this manual describes the hardware and software only in enough detail for system intergrators to design the LSI53C1510 onto a motherboard or a host adapter board. the i 2 o raid software consists of the lsi logic i 2 o raid device driver module (ddm), symplicity? storage manager, and wind river systems ixworks rtos. the LSI53C1510 is a combination of many tried and proven modules. these modules have been proven in single and multimodule con?gurations. the following block diagram illustrates the major modules of the LSI53C1510. 1.1.1 block diagram the LSI53C1510 is a multifunction device composed of many modules. figure 1.1 is a block diagram of the LSI53C1510. figure 1.1 LSI53C1510 block diagram 32-bit, 33 mhz pci bus 132 mbytes dram dram 160 mbytes, memory interface 80 mbytes wide ultra2 scsi bus 80 mbytes scsi core scsi core i 2 o message unit 32-bit risc arm7tdmi processor raid parity assist engine pci interface 32-bit memory controller
module overviews 1-3 1.2 module overviews this section provides an overview of the six major LSI53C1510 modules, which consist of the pci interface, memory controller, i 2 o messaging unit, arm7tdmi risc processor, raid pae and scsi cores. chapter 2, functional description, provides a detailed description of the functions of each module. 1.2.1 pci interface the pci interface is a 32-bit, 33 mhz host pci bus. the pci interface supports dual address cycle (dac), pci power management, and subsystem vendor id. the pci interface also contains a pci master and slave control block, pci con?guration registers, and dma channel arbitration. this chip supports 64-bit addressing as a pci master and supports 32-bit addressing as a pci slave. 1.2.2 memory controller the memory controller provides access to flash rom, sram, and 32-bit edo dram with parity (50 ns access time). it supports two 64 mbytes (maximum con?guration of 128 mbytes) banks of dram. to support the rom and sram, there is a general purpose 8-bit expansion memory bus that supports up to 4 mbytes flash rom. it also supports up to 2 mbytes of sram and is designed to interface ef?ciently to an external 8 k x 8 battery backed up sram. 1.2.3 i 2 o message unit the messaging interface ef?ciently passes messages between the LSI53C1510 and other i/o agents in an i 2 o enabled system. the i 2 o message unit consists of the following four hardware fifos for the message queuing lists: request free, request post, reply free, and reply post. the LSI53C1510 provides control logic for the i 2 o message unit and external local memory provides storage for the messages.
1-4 introduction 1.2.4 arm7tdmi risc processor the LSI53C1510 uses an optimized 32-bit arm7 risc processor core to control all raid functionality. this frees the host cpu for other processing activity and improves i/o performance. the risc processor and associated ?rmware contain the ability to manage an i/o from start to ?nish without host intervention. the risc processor also manages the i 2 o message passing i/o interface. 1.2.5 raid parity assist engine (pae) the hardware pae of?oads the parity generation and checking from the host. it allows multiple parity operations to be queued for maximum ef?ciency. 1.2.6 scsi cores the integrated scsi cores are high-performance dual wide ultra2 scsi channels supporting either single-ended (se) or low voltage differential (lvd) scsi. the cores are based on the popular lsi53c8xx controllers and are capable of up to ultra2 transfer rates for each channel. 1.3 LSI53C1510 features the LSI53C1510 integrates a pci bus master dma core, two high-performance scsi cores, and two lsi logic scsi scripts? processors to meet the broad requirements of wide ultra2 scsi standards. it is designed to implement multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent controller designs. in nonintelligent mode, the LSI53C1510 is fully supported by the storage device management system (sdms?), a software package that supports the advanced scsi protocol interface (aspi). sdms software provides bios and driver support for hard disk, tape, removable media products, and cd-rom under the major pc operating systems.
LSI53C1510 bene?ts 1-5 in intelligent mode, the LSI53C1510 is a complete, single chip raid solution for the motherboardjust add memory. the raid product solution consists of a raid symplicity storage manager, symplicity i 2 o raid ?rmware with wind river system ixworks, and hardware. 1.3.1 features list highly integrated single chip raid controller i 2 o messaging unit raid pae 32-bit/33 mhz host pci bus Cdac C pci power management C pci cache commands (mrl, mrm, mwi) two wide ultra2 scsi channels C se or lvd scsi C based upon the popular lsi53c8xx controller 32-bit risc arm7tdmi processor 32-bit memory controller C up to two banks of 64 mbytes edo (50 ns access time) dram general purpose 8-bit expansion bus C supports up to 4 mbytes rom C chip enable to support an external 8 k x 8 battery backed sram 1.4 LSI53C1510 bene?ts this section provides a description of the major LSI53C1510 bene?ts. 1.4.1 ultra2 scsi bene?ts ultra2 scsi is an extension of the spi-2 draft standard that allows faster synchronous scsi transfer rates and de?nes a new physical layer, lvd scsi, that provides an incremental evolution from scsi-2 and ultra scsi. when enabled, ultra2 scsi (8-bit) performs transfers of
1-6 introduction 40 mbytes/s, which results in approximately double the synchronous transfer rate of ultra scsi. the LSI53C1510 can perform 16-bit (wide), ultra2 scsi synchronous transfers as fast as 80 mbytes/s. this advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing. an advantage of ultra2 scsi is that it signi?cantly improves scsi bandwidth while preserving existing hardware and software investments. 1.4.2 lvdlink? bene?ts the LSI53C1510 supports lvd scsi, a signaling technology that increases the reliability of scsi data transfers over longer distances than supported by se scsi. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high voltage differential (hvd) scsi without the added cost of external differential transceivers. ultra2 scsi with lvd allows a longer scsi cable and more devices on the bus, with the same cables de?ned in the scsi-3 parallel interface standard for fast-20 (ultra scsi). lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. for backward compatibility to existing se devices, the LSI53C1510 features universal lvdlink transceivers that can switch between lvd scsi and se modes. the lvdlink technology also supports high power differential signaling in legacy systems, when external transceivers are connected to the LSI53C1510. this allows the LSI53C1510 to be used in both legacy and ultra2 scsi applications. 1.4.3 tolerant ? technology bene?ts the LSI53C1510 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. through active negation, the scsi request, acknowledge, data, and parity signals are actively driven high rather than passively pulled up by terminators. active negation is enabled by setting bit 7 in the stest3 register. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices are subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input
LSI53C1510 bene?ts 1-7 ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. tolerant input signal ?ltering is a built-in feature of the LSI53C1510 and all lsi logic fast scsi, ultra scsi, and ultra2 scsi devices. the bene?ts of tolerant technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved ultra2 scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. 1.4.4 i 2 o bene?ts the i 2 o-ready design of the LSI53C1510 improves system performance by reducing interrupts to the host cpu and minimizing pci bandwidth through the packetized mailbox interface. these features are particularly important in high-performance symmetric multiprocessing servers and clustered computing systems. the bene?ts of the i 2 o architecture fully compliment those of scsi and include reduced host cpu i/o overhead for better system performance, improved scalability, reduced time to market for new i/o technology, reduced cost of integration and support for i/o. 1.4.5 pae bene?ts when the LSI53C1510 is in intelligent mode, the embedded pae works with raid applications to perform parity generation or checking as requested. the pae writes any generated parity data block back into local memory. the hardware pae of?oads the parity generation and checking from the host and it generates parity faster than software applications. the pae allows multiple parity operations to be queued for maximum ef?ciency. this frees the host cpu for other processing activity and improves i/o performance.
1-8 introduction 1.4.6 arm7tdmi risc processor bene?ts the arm processor manages the i 2 o message passing i/o interface. the embedded risc processor (arm7tdmi) improves system performance by reducing interrupts to the host cpu and minimizing pci bandwidth. the arm processor and associated software contain the ability to manage an i/o from start to ?nish without host intervention. this frees the host cpu for other processing activity and improves i/o performance. 1.5 LSI53C1510 bene?ts summary this section provides a summary of the pci, scsi, and raid performance bene?ts. it also provides a summary of the testability, integration, and reliability bene?ts. 1.5.1 pci performance fully pci 2.1 speci?cation compliant true multifunction device as de?ned in pci 2.1 speci?cation in nonintelligent mode and it presents only one load to the pci bus supports 32-bit word data bursts with variable burst lengths of 2, 4, 8, 16, 32, 64 or 128 dwords across the pci bus prefetches up to 8 dwords of scsi scripts performs zero wait-state bus master data bursts at 132 mbytes/s (@ 33 mhz) supports pci cache line size register supports pci memory write and invalidate, memory read line, and memory read multiple commands 1.5.2 scsi performance includes 4 kbytes internal ram on each scsi channel for scripts instruction storage, thus reducing pci bus utilization wide ultra scsi se interface performs wide ultra2 scsi synchronous transfers as fast as 80 mbytes/s with lvd
LSI53C1510 bene?ts summary 1-9 816-byte dma fifo for more effective pci and scsi bus utilization scsi synchronous offset of 31 levels for maximum performance in long cable situations supports variable block size and scatter/gather data transfers minimizes scsi i/o start latency performs complex bus sequences without interrupts, including restore data pointers reduces isr overhead through a unique interrupt status reporting method load/store scripts instruction increases performance of data transfers to and from chip registers supports target disconnect and later reconnect with no interrupt to the system processor supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching expanded register move instruction support software (drivers and scripts) compatible with lsi53c8xx integrated clock quadrupler enables ultra2 scsi with 40 mhz scsi clock input 1.5.3 raid performance maximum transfer rate: 80 mbytes/s with wide ultra2 scsi number of drives: 30 maximum (10 to 15 drives in typical application) supports raid levels 0, 1, 3, 5, 10 and jbod 1.5.4 testability access to all scsi signals through programmed i/o scsi loopback diagnostics scsi bus signal continuity checking single-step mode operation
1-10 introduction 1.5.5 integration dual channel scsi multifunction controller 3.3 v/5 v pci interface full 32-bit pci dma bus master high-performance scsi cores integrated scsi scripts processors arm7tdmi 32-bit risc processor raid pae i 2 o message unit 1.5.6 reliability 2 kv esd protection on scsi signals typical 300 mv scsi bus hysteresis protection against bus re?ections due to impedance mismatches controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certi?cation) latch-up protection greater than 150 ma voltage feed-through protection (minimum leakage current through scsi pads) power and ground isolation of i/o pads and internal chip logic tolerant technology provides: C active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates C input signal ?ltering on scsi receivers improves data integrity, even in noisy cabling environments
applications 1-11 1.6 applications there are many different applications and con?gurations for the LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller. figure 1.2 illustrates a typical LSI53C1510 embedded motherboard application. figure 1.3 illustrates a typical LSI53C1510 host adapter board application. figure 1.2 typical LSI53C1510 mainboard applications 1.6.1 embedded motherboard application the LSI53C1510 is ideally suited for embedded motherboard raid applications. the amount of motherboard space required to implement such an application is critical. the limited space available on the motherboard dictates a highly integrated solution like the LSI53C1510. all of the major functional blocks of raid controller including processor, memory controller, xor engine, and scsi controllers are integrated into the LSI53C1510. this greatly reduces the amount of board space 32-bit, 33 mhz primary pci bus edo dram w/parity (8C128 mbyte) flash (up to 4 mbyte) 8 kbyte battery backed sram w/rtc scsi b scsi a ultra2 scsi bus LSI53C1510 pci to scsi i 2 o-ready raid controller host pci bridge
1-12 introduction required to implement a raid controller. not only does this make raid on the motherboard a viable solution, it also greatly reduces the cost of implementing it. because the LSI53C1510 supports both raid and non-raid operational modes, it gives the motherboard designer the option of building a base motherboard that uses the LSI53C1510 as a dual channel ultra2 scsi controller. the additional memory and real time clock required for raid operation can then be provided on an optional raid upgrade card that plugs into a connector mounted on the motherboard. figure 1.3 typical LSI53C1510 host adapter board application 1.6.2 host adapter board application the LSI53C1510 single chip raid solution can be designed on an add-in host adapter card. this provides a highly scalable solution where additional storage and/or performance can be obtained by adding additional host adapter cards. LSI53C1510 pci to scsi i 2 o-ready raid controller flash (2 to 4 mbyte) battery backed sram (8 k x 8) w/rtc edo dram w/parity (8 to 128 mbyte) vhdci 68-pin high density ultra2 scsi bus clock nvram ultra2 scsi bus 68-pin high density memory back-up vhdci auto te r m auto te r m 32-bit, 33 mhz pci bus
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 2-1 chapter 2 functional description the chapter contains the following sections: section 2.1, modes of operation, page 2-2 section 2.2, the host interface, page 2-11 section 2.3, LSI53C1510 protocol engine, page 2-16 section 2.4, support components, page 2-18 the LSI53C1510 contains an arm7 32-bit risc processor, a raid pae, and a dma engine. the risc processor frees the host cpu for other processing activity and improves performance. the risc processor and associated software contain the ability to manage an i/o from start to ?nish without host intervention. the risc processor also manages the i 2 o message passing i/o interface. the dma engine moves blocks of data between system memory and the LSI53C1510 local memory. the LSI53C1510 uses a 32-bit pci interface for communication with the host cpus and system memory. the host interface to the LSI53C1510 is designed to minimize the amount of pci bandwidth required to support i/o requests. a packetized message passing i/o interface is used to reduce the number of single cycle pci bus cycles. all data traf?c across the pci bus occurs with zero wait-state bursts. the intelligent LSI53C1510 architecture allows the host to specify i/os at a very high level. complete scsi functionality is provided in the LSI53C1510, relieving the host cpu(s) from managing i/os.
2-2 functional description 2.1 modes of operation the LSI53C1510 has two modes of operation: intelligent or nonintelligent mode. in intelligent mode, the LSI53C1510 functions as an embedded raid controller on a motherboard or as an add-in raid host adapter board. in nonintelligent mode the LSI53C1510 functions as a pci to scsi dual channel wide ultra2 controller. these modes are entered during the initialization of the LSI53C1510 on power-up. the presence or absence of external memory determines which mode is entered. in intelligent mode, the LSI53C1510 uses its built-in arm processor. in nonintelligent mode, the arm processor is disabled. table 2.1 shows the LSI53C1510 modes of operation. table 2.1 LSI53C1510 modes modes external memory con?gurations intelligent i 2 o raid controller yes raid nonintelligent dual channel controller no dual channel wide ultra2 scsi controller
modes of operation 2-3 2.1.1 LSI53C1510 overview figure 2.1 LSI53C1510 block diagram figure 2.1 illustrates the major components of the LSI53C1510 controller. a dual channel pci interface function block provides slave access steering between the two scsi cores when operating in nonintelligent mode. the slave access and messaging unit utilizes a fifo for fast host system service and for speed matching between the 33 mhz domain of the pci bus and the 40 mhz clock domain of the memory controller. the dma unit contains a single data fifo for both read and write operations. the scsi cores each contain control registers and 4 kbytes scripts ram. when operating in nonintelligent mode, these are mapped pci master and slave control block, pci con?guration registers (1/2 sets), and dma channel arbitration 4 kbyte scripts ram 8 dword scripts ultra2 scsi controller host pci bus (32-bit, 33 mhz) prefetch buffer 816 byte dma fifo operating registers scsi scripts processor scsi fifo and scsi control block lvdlink drivers and receivers eeprom and auto- con?guration serial 8 kbyte arm instruction/ data buffer jtag parity assist engine dram engine memory control flash rom buffer buffer i 2 o msg unit slave dma internal module bus arm risc processor 4 kbyte scripts ram 8 dword scripts ultra2 scsi controller wide ultra2 scsi bus prefetch buffer 816 byte dma fifo operating registers scsi scripts processor scsi fifo and scsi control block lvdlink drivers and receivers external wide ultra2 scsi bus (a channel) 2-wire serial eeprom bus jtag arm debug flash rom/dram memory bus interrupt pin (b channel)
2-4 functional description according to the memory 0 and memory 1 base address registers. when in intelligent mode, the control registers are mapped into memory 0 base address registers. the pae accesses data and parity in the LSI53C1510 local memory and performs xor operations to generate parity and data blocks. multiple sources can be speci?ed for each operation and multiple operations can be queued within the unit. the memory controller includes a 32-bit with parity edo dram interface, plus an 8-bit utility interface supporting sram, flash rom, plus user-de?ned external components. 2.1.2 con?guration and initialization the LSI53C1510 initializes as a nonintelligent dual channel scsi controller, or as an intelligent i/o processor (iop). external pins are sensed at power-on and either nonintelligent mode or intelligent mode is selected. the power-on mode also determines which set of pci con?guration register values will be used. when in nonintelligent mode, the LSI53C1510 is a dual function pci device with two sets of con?guration registers. when in intelligent mode, the LSI53C1510 is a single function device with a single set of pci con?guration registers. the mem_addr bus is used to determine power-on con?guration. during power-on, internal 25 m a pull-downs are activated. if desired, these pull-downs can be overridden using 10 k w external pull-up resistors. this will change the default power-up conditions of the part. table 2.2 shows the rom size con?gurations the eight mem_addr lines generate. the eight mem_addr lines control the following con?guration options. options shown in table 2.3 are enabled using pull-up resistors.
modes of operation 2-5 table 2.2 rom size con?gurations mem_addr [3:0] options 0000 16 kbytes rom size (no external pull-ups) 0001 32 kbytes rom size 0010 64 kbytes rom size 0011 128 kbytes rom size 0100 256 kbytes rom size 0101 512 kbytes rom size 0110 1024 kbytes rom size 0111 2048 kbytes rom size 1000 4096 kbytes rom size 1001C1110 reserved 1111 no rom present table 2.3 con?guration options mem_addr [4:9] options bit 4 disable boot bit 5 raid_mode, based on simm/memory population bit 6 disables scsi scripts ram bit 7 disables eeprom downloads bit 8 reserved bit 9 channel b uses inta instead of intb
2-6 functional description 2.1.3 i 2 o overview when the LSI53C1510 is in intelligent mode, the risc processor manages the i 2 o message passing i/o interface. i 2 o de?nes a standard architecture for intelligent i/o, where low level interrupts are of?oaded from the host cpu to the arm iop designed speci?cally to handle i/o. with support for message passing between multiple independent processors, the i 2 o architecture relieves the host of interrupt intensive i/o tasks, greatly improving i/o performance in high bandwidth applications such as raid. i 2 o imposes no restrictions on where layered modules execute, providing support for single processor, multiprocessor and clustered systems. the i 2 o speci?cation also de?nes a split driver model for creating drivers that are portable across multiple oss and host platforms. through the split driver model, i 2 o signi?cantly decreases the number of drivers required. os vendors write a single i 2 o-ready driver for each class of device, such as scsi peripheral class or random block storage class. device manufacturers, like lsi logic, write a single i 2 o software program for each device, such as the LSI53C1510, which works for any os that supports i 2 o. 2.1.4 i 2 o conceptual overview the split i 2 o drivers are composed of two parts: the operating system services module (osm), that resides on and interfaces to the host os; and the hardware device module (hdm), that resides on and interfaces with the LSI53C1510 adapter to be managed by the driver. the hdm and the intermediate service module (ism) are often referred to collectively as ddms. the ism is a driver an independent software vendor can supply to add value or a specialized function to the LSI53C1510. these modules interface with each other through a communication system comprised of two layers: a message layer that sets up a communication session, and a transport layer that de?nes how information will be shared. much like a standard communications protocol, the message layer resides on top of the transport layer.
modes of operation 2-7 2.1.5 i 2 o bene?ts the i 2 o operating environment of the LSI53C1510 provides two main advantages. first, it enables the system vendor, lsi logic, to create an i/o platform that can support a number of intelligent con?gurations. the second advantage is the capability of stacked drivers, that enable a third party software vendor to provide value added expansion capability, independent of both the os and the hardware. figure 2.2 illustrates various ways the LSI53C1510 can be con?gured. figure 2.2 example of LSI53C1510 physical con?gurations host system system bus system memory scsi channel b scsi channel a risc processor other modules iop memory (shared memory) disk drive disk drive scsi bus a disk drive disk drive disk drive disk drive LSI53C1510 disk drive scsi bus b disk drive disk drive
2-8 functional description 2.1.6 the i 2 o communications model the communications model for the i 2 o architecture is a message passing system. the communication model de?nes how two entities exchange messages by using the message layer to set up a connection and exchange data and control. when the osm is presented with a request from the host os, it translates the request into an i 2 o message and dispatches it to the LSI53C1510 for processing. upon completion of the request, the LSI53C1510 dispatches the result back to the osm by sending a message through the i 2 o message layer. to the host os, the osm appears just like any other device driver. see section 2.2.1, messages, later in this chapter for more detail. 2.1.7 operational overview after power-on, the LSI53C1510 is con?gured as either a nonintelligent or intelligent controller. in intelligent mode, the LSI53C1510 initializes from local rom and then issues and responds to i 2 o messages exchanged with the host system. messages are decoded into local actions, usually involving the transfer of data. data may be moved between the host system and the LSI53C1510 local memory through the LSI53C1510s dma controller, or by the host system. the two scsi cores transfer data between disk and local memory or between disk and host system memory. 2.1.8 system interface the LSI53C1510 architecture features a generic, message passing i/o interface. the LSI53C1510 protocol engine provides a set of four hardware fifos for message queuing between the LSI53C1510 and the primary host (or other hosts and peers). the four fifos are: request free list request post list reply free list reply post list these fifos are used to manage how/where messages are sent and received.
modes of operation 2-9 control logic for the four hardware fifos is provided within the protocol engine. storage for the fifo entries is provided in external local memory. each element within each of these fifos contains a message frame address (mfa). the mfa is the offset from the ?rst memory base address register (memory 0 base address) where a message frame is located (push model). the number of fifo elements is con?gurable. supported fifo depths are powers of two between 256 and 4096. in addition to the hardware fifos, a region of shared memory is provided (the LSI53C1510 local memory mapped to system addresses) for the host to write request message frames into. this is the default method (push model) for request message frame transport, where the host itself copies the request message frame into the LSI53C1510 local memory. to support shared memory access (read/write), the LSI53C1510 protocol engine includes a slave burst fifo (depth of 128 bytes), slave burst logic including address capture and increment, and address translation between system and local memory addresses. reply message frames are always pushed from the LSI53C1510 protocol engine to system memory; the protocol engine includes a dma channel for transferring reply message frames. this dma channel may also be used for other purposes such as downloading software or uploading trace information. also present within the protocol engine is a system read/write interface which provides the arm processor the ability to read/write a single arbitrary dword from system memory. see figure 2.3 for an illustration of the fifos and memory in the protocol engine and external memory. 2.1.8.1 LSI53C1510 protocol engine overview the LSI53C1510 protocol engine contains an arm processor core, a local bus and controller, an 8 kbytes instruction cache, an 8 kbyte instruction/data buffer, an external memory controller, an instruction prefetch unit, a write buffer, an interface to the host system, and a timer/control block. the LSI53C1510 protocol engine functions as an intelligent iop. it receives request messages from the host cpu, processes them, and sends reply messages back to the host. processing of request messages typically involves an i/o transaction; the protocol engine and associated software together contain the ability to manage an i/o from start to ?nish without host intervention.
2-10 functional description figure 2.3 hardware messaging unit pci interface request free list fifo control request post list fifo control reply free list fifo control reply post list fifo control protocol engine slave burst fifo master burst fifo request free list fifo data request post list fifo data reply free list fifo data reply post list fifo data external memory shared memory (request message frames) private memory (code + data)
the host interface 2-11 2.2 the host interface the LSI53C1510 host interface is compliant with the i 2 o speci?cation, revision 1.5. this host interface is a high-performance, packetized, mailbox architecture which leverages intelligence in the LSI53C1510 to minimize traf?c on pci. see http:\\www.i2osig.org on the i 2 o special interest group (sig) web site for more information. symplicity is the lsi logic implementation of i 2 o architecture. there are two basic constructs in i 2 o. the ?rst construct, the message, is used to communicate between the host and the LSI53C1510. messages are moved between the host(s) and the LSI53C1510 using the second construct, a transport mechanism. 2.2.1 messages the LSI53C1510 uses request and reply messages to communicate with the host. request messages are created by the host to request an action by the LSI53C1510. reply messages are used by the LSI53C1510 to send status information back to the host. request message data structures are 128 bytes in length. the message includes a message header and a payload. the header includes information to uniquely identify the message. the message header information is sophisticated enough to support multiple hosts and targets. the payload may be any one of three different mechanisms to communicate scatter/gather information to the LSI53C1510. 2.2.2 message transport request and reply messages reside in preallocated message frames. message frames may reside in pci shared memory local to the LSI53C1510 or in host memory. the host selects where the request and reply messages are located during the LSI53C1510 initialization. the default, power-up con?guration, places request messages in pci shared memory local to the LSI53C1510. as an option, the request messages can reside in host memory. the reply messages, however, always reside in host memory.
2-12 functional description pointers that point to the request and reply messages are called mfas. the LSI53C1510 is responsible for the initialization and management of the mfas in the default model. the LSI53C1510 includes a set of four fifos which are used to track the request and reply mfas. the four fifos are: request free list request post list reply free list reply post list each element within the fifos contains the 32-bit mfas. the free list fifo contains mfas to memory locations which are free to be used for new messages. the LSI53C1510 ?rst enters these mfas into the request free list fifo at initialization. the host initializes the reply free list by writing the mfas for the reply messages into the reply register. the act of writing to this register pushes the mfa into the fifo. the post list fifos contain pointers to memory locations which contain new messages. the presence of a mfa in the post fifo indicates to the host or to the LSI53C1510 that a message is pending. the depth of the fifos determines the number of outstanding request messages which may be pending. the total number of outstanding or open i/os is limited by the number of request messages. therefore, the maximum number of open i/os is determined by the size or depth of the fifos. the depth of the fifos in the LSI53C1510 is software con?gurable, from 256 to 4096, in powers of two. the storage elements for the fifo are in the local dram external to the chip. therefore, the size of the fifos will have an impact on the total amount of dram required. see section 2.4.1, dram memory, later in the chapter for more information regarding local dram requirements. 2.2.3 request message the LSI53C1510 maintains a list of pointers to memory structures. the pool of pointers (mfas) are stored in the LSI53C1510 free fifo. the top fifo entry is provided to the host driver by reading the LSI53C1510 request register. in the default operation, the LSI53C1510 provides mfas to the LSI53C1510 local memory, mapped as shared memory. the
the host interface 2-13 process of the host writing to shared memory local to the LSI53C1510 is analogous to pushing messages down the pci hierarchy to the LSI53C1510. this process may be referred to as the push model. alternatively, the LSI53C1510 may be con?gured to provide mfas to memory located on the host. once con?gured as such, the LSI53C1510 will pull the messages to memory local to the LSI53C1510 using pci bus master cycles. this process may be referred to as the pull model. the lsi logic i 2 o raid software uses the push model. 2.2.3.1 to send a request message figure 2.4 illustrates the LSI53C1510 request message transport. 1. the host driver reads the LSI53C1510 request register to retrieve a pointer to the next available message structure. if the message structure resides in pci shared memory local to the LSI53C1510 (the default), the host reads the offset of the message structure with shared memory. device drivers may be written to request several pointers through a series of fast back-to-back pci slave read cycles. if there are no available message structures, request register reads return the value of ffffC0xffff. 2. the host driver then builds the request message(s) and writes the contents to the available message structure(s). 3. when the request message is built, the host driver writes the mfa(s) back to the LSI53C1510 request register. this action creates a queued entry in the LSI53C1510 post fifo. host drivers may post several mfas during fast back-to-back pci write cycles. 4. the LSI53C1510 protocol engine is interrupted on the ?rst post creating a request post fifo not empty condition. 5. the LSI53C1510 removes all of the mfas from the post fifo. 6. if the LSI53C1510 is operating under the pull model, then the LSI53C1510 arbitrates for the pci bus with the intent to copy the request message(s) in host memory using burst read cycles to memory local to the LSI53C1510. the LSI53C1510 will immediately start operating on request message(s) already written to local pci shared memory, if it is operating in the push model.
2-14 functional description 7. finally, the LSI53C1510 frees the memory associated with the message request by placing the mfa back in the request free fifo. if the operation requested by the request message requires a reply message from the LSI53C1510 to the host, then a similar message transfer process is initiated (see section 2.2.4, reply message ). the host driver may choose to poll the reply messages or have the LSI53C1510 interrupt on exception conditions. figure 2.4 LSI53C1510 request message transport 2.2.4 reply message the reply queue provided by the LSI53C1510 is managed similarly, except the LSI53C1510 generates the reply messages. the host has the responsibility to allocate the reply message pool, and post the mfa of each message frame to the reply register. 2.2.4.1 to send a reply message figure 2.5 illustrates the LSI53C1510 reply message transport. 1. the LSI53C1510 retrieves a mfa to the next free message frame from the reply message free fifo. 2. the LSI53C1510 then writes the message to the reply message frame queue. 1 host driver 3 request register 1 3 mfa_1 mfa_2 mfa_n post fifo mfa_1 mfa_2 mfa_n 4 LSI53C1510 7 5 mf_1 mf_2 mf_n 6 free fifo mf_3 request message frames 2
the host interface 2-15 3. when the reply message is written into the queue, the LSI53C1510 writes the pointer into the LSI53C1510 post fifo. 4. the LSI53C1510 protocol engine causes an interrupt to the host when the reply message is posted. 5. the host driver reads the reply register to retrieve the reply message pointer from the post fifo. if there are no posted messages when the host reads the reply register, the host receives the value ffffC0xffff. 6. the host driver then retrieves the reply message. 7. finally, the host driver writes the mfa (now a free message frame) to the reply register. figure 2.5 LSI53C1510 reply message transport 2.2.4.2 the push model the push model for the data transfer de?nes the hosts push of request messages down to the pci shared memory local to the LSI53C1510. the location to which the host writes is provided by the request free list. 7 host driver 5 reply register post fifo LSI53C1510 mfa_1 mfa_2 mfa_n 1 free fifo 7 mfa_1 mfa_2 mfa_n mf_1 mf_2 mf_n mf_3 reply message frames 2 3 5 4 6
2-16 functional description 2.3 LSI53C1510 protocol engine the LSI53C1510 provides a protocol engine to manage the execution of various i 2 o protocols. the protocol engine of?oads the host processor from management of the i 2 o protocol by providing a higher level of abstraction for the scsi protocols. this abstraction allows multiple scsi protocols to operate simultaneously, with no coordination required between the host-based drivers. each of the abstracted classes of service has well de?ned request and reply message protocols. the symplicity i 2 o raid software supports the random block storage class. this class provides a high level abstraction for random access block-oriented storage devices. 2.3.1 random block storage class the random block storage class provides a high level abstraction for random access block-oriented storage media. the class de?nition abstracts normal i/o operation using a message that consists of the starting logical block address, the number of bytes, the data buffer, the operation code, and the device handle on which to operate. the LSI53C1510 optimizes the request processing by attempting to sort and concatenate different requests, thereby reducing seek and latency time on the drives, and overall command overhead per request. each request is managed as a single exchange and appropriate error recovery and reporting is provided. table 2.4 lists the base messages that comprise the random block storage class message protocol.
LSI53C1510 protocol engine 2-17 in addition to the base messages for each class, the class de?nitions also provide utility messages to allow for management and con?guration of devices. a generic user interface scripting language is used to allow for building generic con?guration and management applications. table 2.4 supported random block storage messages function description bsablockread read from device to memory bsablockreassign reassign block addresses bsablockwrite write to device from memory bsablockwriteverify write to device from memory then verify bsacacheflush write dirty cache to media bsadevicereset reset the device bsamediaformat not de?ned at this time bsamediaverify verify accessibility of data bsapowermgt power management bsastatuscheck check device status
2-18 functional description 2.4 support components the memory controller block within the LSI53C1510 provides access to external local memory resources. external memory devices supported include flash rom, dram, and sram. the sections below provide guidance in choosing the support components necessary for a fully functional implementation using the LSI53C1510. a LSI53C1510 typical implementation diagram is shown below in figure 2.6 for reference. figure 2.6 typical implementations LSI53C1510 pci to scsi i 2 o-ready raid controller flash (2 to 4 mbyte) battery backed sram (8 k x 8) w/rtc edo dram w/parity (8 to 128 mbyte) vhdci 68-pin high density ultra2 scsi bus clock nvram ultra2 scsi bus 68-pin high density memory backup vhdci auto te r m auto te r m 32-bit, 33 mhz pci bus
support components 2-19 2.4.1 dram memory the dram memory stores a run time image of the LSI53C1510 software. this memory also provides a data cache for raid operations. the LSI53C1510 uses a 32-bit demultiplexed memory bus to access the dram. this memory bus has the capability to address up to 128 mbytes of edo dram. the memory controller managing this bus has the ?exibility to support variable dram access speeds. the speed of the drams will have a dramatic impact on the performance of the LSI53C1510 and 50 ns edo dram is required. the LSI53C1510 memory controller also supports optional byte-wide parity error detection. 2.4.2 flash rom the memory controller in the LSI53C1510 manages an optional flash rom. if present, the flash rom is used to store the software for the LSI53C1510 protocol engine and int 0x13 boot software. if the flash rom is not used, then the host platform is responsible for downloading the protocol engine software to the LSI53C1510 through the pci interface. the LSI53C1510 supports a diagnostic interface that is enabled through a sequence of commands issued to the wrseq register in the host interface register set. software may be directly written to the LSI53C1510 internal memory and external dram through the diagnostic interface. details of this implementation are not currently de?ned; therefore, lsi logic recommends using flash rom for software storage. the flash rom is accessed using the lower 8 bits of the dram memory interface. 2.4.3 serial eeprom the serial eeprom is primarily used during nonintelligent mode operations. it can be programmed using the host interface of the LSI53C1510.
2-20 functional description
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 3-1 chapter 3 software description this chapter describes the software features, ?rmware features, and memory requirements for the LSI53C1510 in the following sections: section 3.1, pci raid software solutions, page 3-1 section 3.2, management software features, page 3-3 section 3.3, raid firmware features, page 3-3 section 3.4, sdms software, page 3-8 section 3.5, memory requirements, page 3-8 3.1 pci raid software solutions the LSI53C1510 is the ?rst in high-integration raid processor. lsi logic offers a full pci raid software solution consisting of the lsi logic raid ddm, symplicity storage manager utility, and wind river systems ixworks rtos. these applications run in the LSI53C1510 intelligent mode. 3.1.1 pci raid operating in intelligent mode, the LSI53C1510 can use the lsi logic pci raid software package. leveraging third generation software from the lsi logic established and successful bridge controllers and subsystems, the lsi logic raid software for the LSI53C1510 provides an extremely stable, feature rich, high availability platform.
3-2 software description 3.1.2 symplicity storage manager symplicity storage manager provides host-based, transparent management of disk array controllers and the following features. common features C obtaining a raid module pro?le C naming a raid module (user-de?ned) C locating a raid module con?guration C lun creation, deletion using gui or command line C easy default con?gurations or detailed parameter options available C manages multiple raid modules C hot spare creation/deletion C dynamic recon?guration features status C event logging in system log or storage manager (speci?c log) C scriptable error noti?cation_snmp, email, etc. C lun reconstruction progress and in-progress tuning C performance monitor gui displays key statistics for a card and its logical units command line interface captures full set of detailed data recovery C health check for immediate report of component failures C lead-through recovery steps from single or multiple failures maintenance/tuning C cache management C parity check and repair C set lun reconstruction rates
management software features 3-3 3.1.3 wind river systems ixworks rtos wind river systems has ported ixworks to the LSI53C1510. this version of ixworks has been tuned for optimal performance. 3.2 management software features management software has the following features: supported by symplicity storage manager client/server model (windows nt/win95 client with windows nt, netware, or unixware server) compatible with microsoft cluster server (wolfpack) online maintenance and event noti?cation bbu support with utility level software remote diagnostic capability con?gurable drive rebuild rate recovery guru 3.3 raid firmware features raid ?rmware has the following features: raid levels 0, 1, 3, 5, and 10 caching C caching (read-ahead, write through, or write back) C cache memory options of 8 mbyte to 128 mbyte runs in optimal and degraded mode hardware assisted parity calculation variable stripe size tagged command queuing global hot spare drives drive hot swap with automatic, transparent reconstruction
3-4 software description online dynamic capacity expansion online raid level migration/recon?guration battery backup support and cache recovery supports scsi accessed fault-tolerant enclosure (saf-te) 3.3.1 raid levels 0, 1, 3, 5, and 10 this section describes raid and the different raid levels. 3.3.1.1 raid (redundant array of independent disks) a disk array in which part of the storage capacity is used to store redundant information about user data stored on the remainder of the storage capacity. the redundant information enables regeneration of user data if one of the disk drives in the drive group fails. 3.3.1.2 raid level indicates the way the controller reads and writes data and array parity on the drives. the LSI53C1510 controller can create raid level 0, 1, 3, and 5 logical units. these levels do not indicate any certain hierarchy or preference. 3.3.1.3 raid level 0 raid level 0 is a nonredundant raid level where data, without parity, is striped across a drive group/lun. all drives are available for storing user data. any single drive failure causes data loss and a logical unit status of dead. 3.3.1.4 raid level 1 raid level 1 or disk mirroring, protects data against disk failure by replicating all data stored on the virtual disk at least once. for some i/o intensive applications, a raid level 1 can improve performance signi?cantly over a single disk. as implemented by lsi logic, raid 1 combines both striping and mirroring. the striping and mirroring combination is also referred to as raid 0+1 or raid 10.
raid firmware features 3-5 3.3.1.5 raid level 3 raid level 3 adds parity to a striped array, permitting user data to be regenerated in the event of a failure. raid level 3 arrays use normal disk mechanisms for failure detection and the parity for data regeneration in the event of a failure. raid level 3 relies on close coordination of member disk activities. 3.3.1.6 raid level 5 raid level 5 is another independent access raid level. it is functionally equivalent to raid level 4, using a single parity strip to protect data stored on several data strips in the same stripe. it differs from raid level 4 in that its parity strips are distributed across multiple array members rather than being concentrated on a dedicated parity disk. this provides some relief from the write bottleneck that characterizes raid level 4, and is the reason that raid 5 is most often implemented in independent access raid array products rather than raid level 4. 3.3.2 caching cache memory is an area on the controller used for intermediate storage of read and write data. by using cache, you can increase system performance because the data for a read or write operation from the host may already be in the cache from a previous operation (thus the need to access the drive itself is eliminated), or the write operation is considered complete once it is written to the cache. the following caching options are supported. caching (read-ahead, write through, or write back) cache memory options of 8 mbyte to 128 mbyte 3.3.3 runs in optimal and degraded mode the software permits your raid system to produce optimal performance. if a failure occurs, the system can run in a degraded mode until replacement of the failed unit occurs.
3-6 software description 3.3.4 hardware assisted parity calculation raid ?rmware uses the hardware pae in the LSI53C1510 to of?oad parity generation and checking from the host. the pae calculates the parity for write operations much faster than what can be done in software/?rmware. it also allows multiple parity operations to be queued for maximum ef?ciency. 3.3.5 tagged command queuing tagged command queuing provides the capability for the host to issue multiple commands to a logical unit. this capability is essential for an array logical unit that is made up of multiple devices. without tagged queuing, the controller can only execute one operation on the logical unit at a time, even though there are multiple drives available for overlapped operations. the maximum number of commands which can be queued in the controller (the sum of all logical units) is 256. this is the number of available structures the controller has for operations received from the host. if the host attempts to issue more commands to the controller than it has structures available for, a queue full status will be returned. the controller maintains a queue for each logical unit and a queue for each drive in the logical unit. how a command moves from queue to queue is dependent on the type of queue tag received with the command. 3.3.6 global hot spare drives this drive contains no valid data but if a failure occurs, the controller can automatically reconstruct and use the global hot spare drive to replace a failed drive. hot spare drive allows full performance and data redundancy to be restored without user intervention. the user simply replaces the failed drive at a later time. this is an important feature because it can signi?cantly reduce mean time to data loss. a global hot spare drive can replace a failed drive of the same or smaller capacity anywhere on the disk array.
raid firmware features 3-7 3.3.7 hot swap drive with automatic, transparent reconstruction this disk drive replaces a failed drive. hot swap technology makes it possible to remove and replace an array component while power is applied and data activity to and from the system continues. the controller automatically reconstructs data on the new drive, or initiates copying back the data from the global hot spare drive that is standing in for the failed drive. this data reconstruction is transparent to the user and allows full performance and data redundancy to be restored. 3.3.8 variable stripe size the dynamic segment sizing (dss) feature provides the ability to change the segment size for a lun. changing the segment size causes the lun to be recon?gured such that the data is mapped according to the new segment size. this feature is provided while allowing full user data availability and accessibility. the raid ?rmware allows variable stripe size. a striped array is also known as a raid level 0 array. 3.3.9 online dynamic capacity expansion the dynamic capacity expansion feature provides the ability to add drives to a drive group. adding drives to a drive group causes the luns on that drive group to be recon?gured such that the data is spread onto the additional drives. after recon?guration, the additional capacity may be used to create additional luns on the drive group. this feature is provided while allowing full user data availability and accessibility. 3.3.10 online raid level migration/recon?guration the dynamic raid migration (drm) feature provides the ability to change the raid level for a drive group. changing the raid level causes the luns in the drive group to be recon?gured such that the data is mapped according to the de?nition of the new raid level. this feature is provided while allowing full user data availability and accessibility. valid raid level migrations are: 0>1, 0>3, 0>5, 1>0, 1>3, 1>5, 3>0, 3>1, 3>5, 5>0, 5>1, and 5>3.
3-8 software description 3.3.11 battery backup support and cache recovery the battery backup feature allows data in cache memory to be saved and then recovered following a power failure. 3.3.12 supports saf-te saf-te support has been added to the destination (drive) side of the controller. this allows attachment of drive enclosures that support saf-te. 3.4 sdms software operating in nonintelligent mode, the LSI53C1510 can use the sdms software package. sdms software is a complete software package that solves the increasingly complex problem of managing system i/o. it seamlessly addresses hardware and software interfaces by supporting the lsi logic family of scsi processors and controllers, and a wide range of scsi peripheral devices, while offering interoperability across application programs, operating systems, and host platforms. sdms software consists of a resident scsi bios that manages all scsi controller or processor speci?c functions, and a series of scsi device drivers that provide operating system and peripheral speci?c support. sdms software provides a standard method to interface scsi i/o subsystems with devices, operating systems, and application software. it also enhances system capabilities already provided by scsi controllers and processors by facilitating multithreaded i/o support, system wide scsi device access, and the creation of new applications. 3.5 memory requirements to run the LSI53C1510 in intelligent mode, with the pci raid software solutions (lsi logic raid ddm, symplicity storage manager utility, and wind river systems ixworks rtos), your memory should meet the following requirements.
memory requirements 3-9 edo dram (with parity) - 8 mbytes to 128 mbytes flash rom - minimum of 2 mbytes nvram (with real time clock) - 8 kbytes (equivalent to sgs-thomson mk48t18) to run the LSI53C1510 in nonintelligent mode, with lsi logic the sdms software package, your memory should meet the following requirements. two serial eeprom - 2 kbytes flash rom - 128 kbytes
3-10 software description
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 4-1 chapter 4 signal descriptions this chapter presents the LSI53C1510 pin con?guration and signal de?nitions using tables and illustrations. figure 4.1 is the functional signal grouping. the signal descriptions are organized into functional groups: section 4.1, signal groupings, page 4-2 section 4.2, pci interface signals, page 4-4 section 4.3, scsi interface signals, page 4-10 section 4.4, memory interface signals, page 4-15 section 4.5, miscellaneous interface signals, page 4-18 a slash (/) at the end of a signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage. all signals/pins described in this chapter are identi?ed by a pin type described in table 4.1 . table 4.1 pin type description type description i input, a standard input only signal o totem pole output, a standard output driver i/o input and output (bidirectional) t/s 3-state, a bidirectional, 3-state input/output signal s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time
4-2 signal descriptions 4.1 signal groupings the LSI53C1510 signals fall into the following groups. these groups are illustrated in figure 4.1 . pci interface signals C system signals C address and data signals C interface control signals C arbitration signals C interrupt signals C error reporting signals C power management event signals scsi interface signals C a-channel C b-channel memory interface signals C rom/sram signals C edo dram signals miscellaneous interface signals C scsi gpio function signals C uart signals C jtag signals C arm debug signals C arm C raid mode power and ground signals
signal groupings 4-3 figure 4.1 LSI53C1510 functional signal groupings clk rst/ pci_ad[31:0] c_be[3:0]/ pa r frame/ req/ gnt/ inta/ intb/ mce2_rd/ mce2_wr/ mem_ce[2:0] mem_we/ moe/_testout scanmode scan_en scan_ram_en scan_rst_en scan_test_clk_en dram_casfb_a dram_casfb_b dram_we/ dram_oe/ dram_addr[12:0] dram_data[31:0] a_sd[15:0] / b_sdp[1:0] / b_sd[15:0] / arm_tms arm_tdo arm_trst/ b_sc_d / LSI53C1510 scsi lvd channel a scsi gpio functions system address and data interface control arbitration interrupt rom sram signals edo dram signals pci bus interface a_sctrl/ a_gpio[4:0] error reporting pme/ mem_addr[12:0] trdy/ irdy/ stop/ devsel/ idsel/ serr/ perr/ mem_data[7:0] test_hsc test_dramclk testin dram_par[3:0] dram_ras/[3:0] dram_cas/[7:0] a_sdp[1:0] / a_sc_d / a_si_o / a_smsg / a_sreq / a_sack / a_sbsy / a_satn / a_srst / a_ssel / 32-bit 33 mhz memory interface a_diffsens a_rbias sclk b_si_o / b_smsg / b_sreq / b_sack / b_sbsy / b_satn / b_srst / b_ssel / b_sctrl/ scsi lvd channel b b_diffsens b_rbias b_gpio[4:0] rxt txt uart jtag arm debug xint power_fail/ arm raid mode misc. tck tms tdi tdo trst/ power management event scsi interface interface
4-4 signal descriptions 4.2 pci interface signals the pci bus interface signals section contains tables describing the signals for the following signal groups: system signals , address and data signals , interface control signals , arbitration signals , interrupt signals , the arm signal , error recording signals , the power management signal , and gpio interface signals . 4.2.1 system signals table 4.2 describes the system signals. table 4.2 system signals name bump type strength description clk f25 i n/a clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are de?ned with respect to this edge. clock can optionally serve as the scsi core clock, but this may effect fast scsi transfer rates. rst/ n24 i n/a reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device.
pci interface signals 4-5 4.2.2 address and data signals table 4.3 describes the address and data signals. table 4.3 address and data signals name bump type strength description pci_ad[31:0] m25, m24, m26, l25, l24, l26, k23, k25, j25, h25, j24, h26, h23, g25, g26, h24, c25, d24, a25, c23, b24, a24, d22, b23, b22, a22, d20, b21, a21, c21, b20, a20 t/s 16 ma pci physical dword pci address and data are multiplexed on the same pci pins. during the ?rst clock of a transaction, ad[31:0] contain a physical byte address. during subsequent clocks, ad[31:0] contain data. a bus transaction consists of an address phase followed by one or more data phases. pci supports both read and write bursts. ad[7:0] de?ne the least signi?cant byte, and ad[31:24] de?ne the most signi?cant byte. c_be[3:0]/ k26, g23, e24, a23 t/s 16 ma pci bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ de?ne the bus command. during the data phase, c_be[3:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be[0]/ applies to byte 0, and c_be[3]/ to byte 3. par c26 t/s 16 ma pci parity is even parity across the ad[31:0] and c_be[3:0]/ lines. during the address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered.
4-6 signal descriptions 4.2.3 interface control signals table 4.4 describes the interface control signals. table 4.4 interface control signals name bump type strength description frame/ g24 s/t/s 16 ma pci cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate that a bus transaction is beginning. while frame/ is deasserted, either the transaction is in the ?nal data phase or the bus is idle. irdy/ e26 s/t/s 16 ma pci initiator ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. irdy/ is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates that the master is prepared to accept data. wait cycles can be inserted until both irdy/ and trdy/ are asserted together . trdy/ e25 s/t/s 16 ma pci target ready indicates the target agents (selected devices) ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates that the target is prepared to accept data. wait cycles can be inserted until both irdy/ and trdy/ are asserted together. stop/ d26 s/t/s 16 ma pci stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ f24 s/t/s 16 ma pci device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel k24 i n/a initialization device select is used as a chip select in place of the upper 24 address lines during con?guration read and write transactions.
pci interface signals 4-7 4.2.4 arbitration signals table 4.5 describes the arbitration signals. 4.2.5 interrupt signals table 4.6 describes the interrupt signals. table 4.5 arbitration signals name bump type strength description req/ n26 o 16 ma pci request indicates to the arbiter that this agent desires use of the pci bus. both scsi functions share the req/ signal. gnt/ m23 i n/a grant indicates to the agent that access to the pci bus has been granted. both scsi functions share the gnt/ signal in nonintelligent mode. in intelligent mode, the gnt/ signal is shared by the internal module bus (imb) bus agents. table 4.6 interrupt signals name bump type strength description inta/ p24 o 16 ma pci interrupt function a. this signal, when asserted low, indicates an interrupting condition in scsi function a and that service is required from the host cpu. the output drive of this pin is open drain. if the scsi function b interrupt is rerouted at power-up using the inta/ enable sense resistor (pull-down on mem_addr9), this signal indicates that an interrupting condition has occurred in either the scsi function a or scsi function b. intb/ n23 o 16 ma pci interrupt function b. this signal, when asserted low, indicates an interrupting condition in scsi function b and that service is required from the host cpu. the output drive of this pin is open drain. this interrupt can be rerouted to inta/ at power-up using the inta/ enable sense resistor (pull-down on mem_addr9). this causes the LSI53C1510 to program the scsi function b pci register interrupt pin (3d) to 0x01. in intelligent mode, this signal is not used.
4-8 signal descriptions 4.2.6 arm signal table 4.7 describes the arm signal. 4.2.7 error recording signals table 4.8 describes the error recording signals. 4.2.8 power management signal table 4.9 describes the power management signal. table 4.7 arm signal name bump type strength description xint n25 i C external interrupt. this pin, when asserted, indicates that an interrupting condition is pending. table 4.8 error recording signals name bump type strength description perr/ d25 s/t/s 16 ma pci parity error. this may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruption. however, on detection of a perr/ pulse, the central resource may generate a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing is complete. serr/ e23 o 16 ma pci system error. this output is used to report address and data parity errors. table 4.9 power management signal name bump type strength description pme/ ti o 16 ma pci power management event. this signal, when asserted low, indicates a power management event has occurred.
pci interface signals 4-9 4.2.9 gpio interface signals table 4.10 describes the gpio interface signals. table 4.10 gpio interface signals name bump type strength description a_gpio [4:0] w24, v26, v25, v24, u26 i/o 24 ma a general purpose i/o. signals gpio0Cgpio3 default to input mode on reset. signal gpio4 defaults to output mode on reset. these signals are controlled or observed by ?rmware and may be con?gured as inputs or outputs. b_gpio [4:0] w2, v1, u3, u1, u2 i/o 24 ma b general purpose i/o. signals gpio0Cgpio3 default to input mode on reset. signal gpio4 defaults to output mode on reset. these signals are controlled or observed by ?rmware and may be con?gured as inputs or outputs.
4-10 signal descriptions 4.3 scsi interface signals the scsi bus interface signals section contains tables describing the signals for the following signal groups: the scsi clock signal , scsi a-channel interface signals , and scsi b-channel interface signals . 4.3.1 scsi clock signal table 4.11 describes the scsi clock signal. 4.3.2 scsi a-channel interface signals table 4.12 describes the scsi a-channel interface signals. table 4.11 scsi clock signal name bump type strength description sclk ad13 i n/a scsi clock is used to derive all scsi related timings. the speed of this clock is determined by the applications requirements. the clock supplied to sclk must be at 40 mhz. this frequency is doubled to create the 80 mhz clock required by both scsi functions. for ultra2, this frequency is quadrupled to create 160 mhz. table 4.12 scsi a-channel interface signals 1 name bump type strength description a_sd[15:0] - / aa26, y25, y24, w26, af14, ad15, ae16, af16, ae23, af24, ae24, ae26, ad25, ab23, ac26, ab25 i/o 48 ma scsi scsi function a data. lvd mode: a_sd[15:0] - / signals are the negative half of the lvdlink 16-bit pair of scsi data lines. se mode: the se interface uses only the plus signals, therefore, these signals are not used.
scsi interface signals 4-11 a_sd[15:0]+/ aa24, y26, w25, w23, ae15, af15, ad16, ac17, ac22, ad22, ad23, ac24, ad26, ac25, ab24, ab26 i/o 48 ma scsi scsi function a data. lvd mode: a_sd[15:0]+/ signals are the positive half of the lvdlink 16-bit pair of scsi data lines. se mode: the se interface uses only the plus signals as the 16-bit scsi data and parity bus. a_sdp[1:0] - / y23, ad21 i/o 48 ma scsi scsi function a data parity. lvd mode: a_sdp[1:0] - / are the negative half of the lvdlink pair for scsi data parity lines. se mode: the se interface uses only the plus signals, therefore, these signals are not used. a_sdp[1:0]+/ aa25, af23 i/o 48 ma scsi scsi function a data parity. lvd mode: a_sdp[1:0]+/ are the positive half of the lvdlink pair for scsi data parity lines. se mode: the se interface uses only the plus signals as the 16-bit scsi data and parity bus. a_difffsens ad14 i n/a scsi function a differential sense. this pin detects the presence of a se device on a differential system. when external differential transceivers are used, and a zero is detected on this pin, all scsi function a chip outputs are 3-stated to avoid damage to the transceivers. tie this pin high during se operation. a_sc_d / ae19, af18 i/o 48 ma scsi control/data. the target asserts this signal with the msg/ and c_d signals to determine the information transfer phase. a_si_o / af17, ae17 i/o 48 ma scsi input/output. the target asserts this signal with the msg/ and c_d signals to determine the information transfer phase. a_smsg / ae20, ac19 i/o 48 ma scsi message. the target asserts this signal with the i_o and c_d signals to determine the information transfer phase. table 4.12 scsi a-channel interface signals 1 (cont.) name bump type strength description
4-12 signal descriptions a_sreq / ae18, ae17 i/o 48 ma scsi request. this signal is a data handshake line from a target device. the target asserts this signal when requesting a data transfer. a_sack / af21, ac20 i/o 48 ma scsi acknowledge. this signal is a data handshake signal from initiator device. the initiator asserts this signal in response to the req/ signal to acknowledge a data transfer. a_sbsy / ad20, ae21 i/o 48 ma scsi busy. this signal is asserted when the scsi bus is busy. when a device wants to arbitrate to use the scsi bus, bsy/ is driven active. once the arbitration and selection phases are complete, the target drives this signal active. a_satn / ae22, af22 i/o 48 ma scsi attention. the initiator asserts this signal when requesting a message out phase. a_srst / ad19, af20 i/o 48 ma scsi reset. this signal performs a scsi bus reset when asserted. a_ssel / af, ad18 i/o 48 ma scsi select. this signal selects or reselects another scsi device when asserted. 1. the se interface uses only the - signals. lvd interface uses both the + and - signals. table 4.12 scsi a-channel interface signals 1 (cont.) name bump type strength description
scsi interface signals 4-13 4.3.3 scsi b-channel interface signals table 4.13 describes the scsi b-channel interface signals. table 4.13 scsi b-channel interface signals 1 name bump type strength description b_sd[15:0] - / ae11, ad11, af13, ad12, w1, y2, w3, aa1, ae6, ad6, af7, ae8, ac8, af9, ad9, ae10 i/o 48 ma scsi scsi function b data. lvd mode: b_sd[15:0] -/ signals are the negative half of the lvdlink 16-bit pair of scsi data lines. se mode: the se interface uses only the plus signals, therefore, these signals are not used. b_sd[15:0]+/ ac10, af12, ae12, ae13, v3, w4, y1, y4, ac7, af6, ae7, ad7, af8, ad8, ae9, af10 i/o 48 ma scsi scsi function b data. lvd mode: b_sd[15:0]+/ signals are the positive half of the lvdlink 16-bit pair of scsi data lines. se mode: the se interface uses only the plus signals as the 16-bit scsi data and parity bus. b_sdp[1:0] - / af11, af5 i/o 48 ma scsi scsi function b data parity. lvd mode: b_sdp[1:0] -/ are the negative half of the lvdlink pair for scsi data parity lines. se mode: the se interface uses only the plus signals, therefore, these signals are not used. b_sdp[1:0]+/ ad10, ae5 i/o 48 ma scsi scsi function b data parity. lvd mode: b_sdp[1:0]+/ are the positive half of the lvdlink pair for scsi data parity lines. se mode: the se interface uses only the plus signals as the 16-bit scsi data and parity bus. b_difffsens ac12 i n/a scsi function b differential sense. this pin detects the presence of a se device on a differential system. when external differential transceivers are used, and a zero is detected on this pin, all scsi function b chip outputs are 3-stated to avoid damage to the transceivers. tie this pin high during se operation.
4-14 signal descriptions b_sc_d / aa3, ac1 i/o 48 ma scsi control/data. the target asserts this signal with the msg/ and c_d signals to determine the information transfer phase. b_si_o / aa2, y3 i/o 48 ma scsi input/output. the target asserts this signal with the msg/ and c_d signals to determine the information transfer phase. b_smsg / ad1, ab3 i/o 48 ma scsi message. the target asserts this signal with the i_o and c_d signals to determine the information transfer phase. b_sreq / ab1, ab2 i/o 48 ma scsi request. this signal is a data handshake line from a target device. the target asserts this signal when requesting a data transfer. b_sack / af2, ad4 i/o 48 ma scsi acknowledge. this signal is a data handshake signal from initiator device. the initiator asserts this signal in response to the req/ signal to acknowledge a data transfer. b_sbsy / ae3, af3 i/o 48 ma scsi busy. this signal is asserted when the scsi bus is busy. when a device wants to arbitrate to use the scsi bus, bsy/ is driven active. once the arbitration and selection phases are complete, the target drives this signal active. b_satn / ac5, ae4 i/o 48 ma scsi attention. the initiator asserts this signal when requesting a message out phase. b_srst / ad2, ac3 i/o 48 ma scsi reset. this signal performs a scsi bus reset when asserted. b_ssel / ac2, ab4 i/o 48 ma scsi select. this signal selects or reselects another scsi device when asserted. 1. the se interface uses only the - signals. lvd interface uses both the + and - signals. table 4.13 scsi b-channel interface signals 1 (cont.) name bump type strength description
memory interface signals 4-15 4.4 memory interface signals the memory interface signals section contains tables describing the signals for the following groups: rom/sram interface signals , scan signals , and dram interface signals . 4.4.1 rom/sram interface signals table 4.14 describes the rom/sram interface signals. table 4.14 rom/sram interface signals name bump type strength description mce2_rd/ k4 o 8 ma memory signal for mem_ce(2). mce2_wr/ l2 o 8 ma memory signal for mem_ce(2). mem_ce/[2:0] k3, k2, k1 o 8 ma memory chip enable. these pins are used as chip enable signals to external memory devices. mem_we/ m1 o 8 ma memory write enable . this pin is used as a write enable signal to external memories selected by mem_ce[2:0]. moe/_testout j3 o 8 ma memory. this pin is used as an output enable signal to external memories during read operations. mem_addr [12:0] j2, j1, h3, h1, h2, g3, g1, g2, f3, f1, f2, g4, e1 o24ma memory address. the memory address bus provides a total of 8 k addressing of general purpose memory addressing. the memory address bus is also used for power-on con?guration with pull-up/pull-down resistors. the resistors determine the rom size. is concatenated with dram_addr for mem_ce cycles. mirrors dram_addr signals for dram cycles. mem_data [7:0] n3, m4, p2, m3, n2, n1, m2, l3 i/o 8 ma memory data lines .
4-16 signal descriptions 4.4.2 scan signals table 4.15 describes the scan signals. table 4.15 scan signals name bump type strength description scanmode r1 i n/a scan mode enable. used for manufacturing test. scan_en r3 i n/a scan enable. used for manufacturing test. scan_ram_en p3 i n/a scan ram enable. used for manufacturing test. scan_rst_en r2 i n/a scan reset enable. used for manufacturing test. scan_test_clk_en r4 i n/a scan test clock enable. used for manufacturing test. scan_tri_en p1 i n/a scan 3-state enable . used for manufacturing test.
memory interface signals 4-17 4.4.3 dram interface signals table 4.16 describes the dram interface signals. table 4.16 dram interface signals name bump type strength description dram_casfb_a a5 i n/a dram column address strobe feedback . dram_casfb_b c7 i n/a dram column address strobe feedback . dram_we/ b4 o 24 ma dram write enable . indicates the direction data is to be transferred to/from dram. dram_oe/ a4 o 16 ma dram output enable . dram_addr [12:0] e3, d1, d2, e4, c1, c2, d3, b1, c4, b3, c5, a3, d5 o24ma dram memory address lines. dram_data [31:0] b19, d19, a18, c18, b17, a16, b16, c16, a14, c15, d15, d13, d12, b12, a12, c11, a19, c19, b18, a17, c17, d17, a15, b15, b14, b13, c14, c13, a13, c12, b11, all i/o 8 ma dram data lines. dram_par[3:0] d10, a10, b10, c10 i/o 8 ma dram data parity . these bits provide one parity bit for each byte of data. dram_ras[3:0]/ c6, b5, a9, b8 o 24 ma dram row address strobe. indicates the presence of a valid row address. dram_cas[7:0]/ c9, d8, a7, d7, a8, b7, c8, b6 o26ma dram column address strobe. indicates the presence of a valid column address.
4-18 signal descriptions 4.5 miscellaneous interface signals the miscellaneous interface signals section contains tables describing the signals for the following signal groups: uart interface signals , jtag interface signals , arm debug interface signals , the raid interface signal and power and ground signals . 4.5.1 uart interface signals table 4.17 describes the uart interface signals. 4.5.2 jtag interface signals table 4.18 describes the jtag interface signals. table 4.17 uart interface signals name bump type strength description rxt p25 i n/a receive data. txt r24 o 4 ma transmit data. table 4.18 jtag interface signals name bump type strength description tck t25 i n/a test clock. this signal provides the clock for the jtag test logic. tms t24 i 4 ma test mode select. this signal is decoded to select the jtag test operation. tdi r26 i n/a test data input. this signal is the serial input signal for jtag. it receives the jtag test logic instructions. tdo p26 o 4 ma test data output. this signal is the serial output signal for test instructions and data from the jtag test logic. trst/ r25 i n/a test reset. this signal resets the jtag logic. testin p4 i n/a test in. for test purposes only. this signal, when driven high, is used for manufacturing test. it should be pulled low or left unconnected for normal operation.
miscellaneous interface signals 4-19 4.5.3 arm debug interface signals table 4.19 describes the arm debug interface signals. 4.5.4 raid interface signal table 4.20 describes the signal for the raid interface signal. test_hsc ac14 i n/a test hsc. for test purposes only. test_dramclk e2 i n/a test dram clock. for test purposes only. table 4.18 jtag interface signals (cont.) name bump type strength description table 4.19 arm debug interface signals name bump type strength description arm_tms u23 i n/a arm test mode select. this signal is decoded to select the test operation. arm_tdo u24 o n/a arm test data output. this signal is the serial output for test instructions and data from the arm test logic. arm_trst/ t26 i n/a arm test reset. this signal resets the arm test logic. table 4.20 raid interface signal name bump type strength description power_fail/ t3 i n/a power fail.
4-20 signal descriptions 4.5.5 power and ground signals table 4.21 describes the signals for the power and ground signals. table 4.21 power and ground signals name bump type strength description v dd d6, d11, d16, d21, f4, f23, l4, l23, t4, t23, aa4, aa23, ac6, ac11, ac16, ac21 p n/a power for pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers/receivers, and other i/o pins. v dd -a v dd core [5:0] ac15 v2, h4, a6, c20, j26, u25 p p n/a n/a power for analog cells (clock quadrupler and diffsens logic). power for core logic. v ss v ss -a v ss core [5:0] a1, a2, a26, b2, b25, b26, c3, c24, d4, d9, d14, d18, d23, j4, j23, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n4, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, p23, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, v4, v23, ac4, ac9, ac13, ac18, ac23, ad3, ad24, ae1, ae2, ae25, af1, af25, af26 ae14 u4, l1, b9, c22, f26, r23 g g g n/a n/a n/a ground for pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers, and other i/o pins. ground for analog cells (clock quadrupler and diffsens logic). ground for core logic.
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 5-1 chapter 5 registers (nonintelligent mode) this chapter contains the following sections: section 5.1, pci functional description (nonintelligent mode), page 5-3 section 5.2, pci con?guration registers (nonintelligent mode), page 5-10 section 5.3, differences from the lsi53c895 and the lsi53c896, page 5-26 after power-on, the LSI53C1510 is con?gured as either a nonintelligent or intelligent controller. this chapter describes the pci and host interface registers that are visible to the host in nonintelligent mode. in nonintelligent mode the LSI53C1510 operates similar to the lsi53c896 product. therefore, for detailed information, see the lsi53c896 pci to dual channel ultra2 scsi multifunction controller technical manual .in nonintelligent mode, two base address regions (one for control and one for scripts ram registers) are de?ned for each scsi core. figure 5.1 illustrates which modules are used in the nonintelligent mode.
5-2 registers (nonintelligent mode) figure 5.1 LSI53C1510 block diagram in nonintelligent mode this section contains descriptions of the LSI53C1510 pci and host interface commands and registers. in the descriptions the term set is used to refer to bits that are programmed to a binary one. similarly, the terms clear and reset are used to refer to bits that are programmed to a binary zero. do not set reserved bits. reserved bit functions may change at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. pci master and slave control block, pci con?guration registers (2 sets), and dma channel arbitration 4 kbyte scripts ram 8 dword scripts host pci bus (32-bit, 33 mhz) wide ultra2 scsi bus prefetch buffer 816 byte dma fifo operating registers scsi scripts processor scsi fifo and scsi control block lvdlink drivers and receivers eeprom and auto- con?guration serial (a channel) 2-wire serial eeprom bus 8 kbyte arm instruction/ data buffer jtag parity assist engine dram engine memory control flash rom buffer buffer slave dma internal module bus arm risc processor jtag flash rom/dram memory bus 4 kbyte scripts ram 8 dword scripts wide ultra2 scsi bus prefetch buffer 816 byte dma fifo operating registers scsi scripts processor scsi fifo and scsi control block lvdlink drivers and receivers (b channel) modules not used ultra2 scsi controller ultra2 scsi controller i 2 o msg unit
pci functional description (nonintelligent mode) 5-3 5.1 pci functional description (nonintelligent mode) in nonintelligent mode, the LSI53C1510 implements two pci to wide ultra2 scsi controllers in a single package. this con?guration presents only one load to the pci bus and uses one req/ - gnt/ pair to arbitrate for pci bus mastership. however, separate interrupt signals are generated for scsi function a and scsi function b. 5.1.1 pci addressing there are three physical pci de?ned address spaces: con?guration space i/o space memory space 5.1.1.1 con?guration space the host processor uses this con?guration space to initialize the LSI53C1510. two independent sets of pci con?guration space registers are de?ned, one set for each scsi function. the pci con?guration space registers are accessible only by system bios during pci con?guration cycles. each con?guration space is a contiguous 256 x 8-bit set of addresses. decoding c_be/[3:0] determines if a pci cycle is intended to access the con?guration register space. the idsel bus signal is a chip select that allows access to the con?guration register space only. a con?guration read/write cycle without idsel is ignored. the eight lower order addresses ad[7:0] are used to select a speci?c 8-bit register. since the LSI53C1510 is a pci multifunction device, ad[10:8] decodes either scsi function a con?guration register (ad[10:8] = 000 binary) or scsi function b con?guration register (ad[10:8] = 001 binary).
5-4 registers (nonintelligent mode) at initialization time, each pci device is assigned a base address for memory accesses and i/o accesses. this is accomplished using registers in the con?guration space. on every noncon?guration space access, the LSI53C1510 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if there is a match of the upper 24 bits, the access is for the LSI53C1510 and the low order eight bits to de?ne the register to be accessed. a decode of c_be/[3:0] determines which registers and what type of access is to be performed. 5.1.1.2 i/o space the pci speci?cation de?nes i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the LSI53C1510. base address register zero (i/o) register determines which 256 byte i/o area this device occupies. 5.1.1.3 memory space the pci speci?cation de?nes memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C1510. base address register one (memory) register determines which 1 kbyte memory area this device occupies. each scsi function uses a 4 k scripts ram memory space. base address register two (scripts ram) register determines the 4 kbyte memory area that the scripts ram occupies.
pci functional description (nonintelligent mode) 5-5 5.1.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be/[3:0] lines during the address phase. pci bus command encoding and types appear in table 5.1 . reserved commands are shaded. 5.1.2.1 interrupt acknowledge command the LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. table 5.1 pci bus commands encoding c_be[3:0]/ command type supported as master supported as slave 0000 interrupt acknowledge no no 0001 special cycle no no 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 memory read yes yes 0111 memory write yes yes 1000 reserved n/a n/a 1001 reserved n/a n/a 1010 con?guration read no yes 1011 con?guration write no yes 1100 memory read multiple yes yes (defaults to 0110) 1101 dac yes yes 1110 memory read line yes yes (defaults to 0110) 1111 memory write and invalidate yes yes (defaults to 0111)
5-6 registers (nonintelligent mode) 5.1.2.2 special cycle command the LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. 5.1.2.3 i/o read command the LSI53C1510 uses the i/o read command to read data from an agent mapped in i/o address space. 5.1.2.4 i/o write command the LSI53C1510 uses the i/o write command to write data to an agent mapped in i/o address space. 5.1.2.5 reserved command the LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. 5.1.2.6 memory read command the LSI53C1510 uses the memory read command to read data from an agent mapped in the memory address space. the target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects. 5.1.2.7 memory write command the LSI53C1510 uses the memory write command to write data to an agent mapped in the memory address space. when the target returns ready, it assumes responsibility for the coherency (which includes ordering) of the subject data. 5.1.2.8 con?guration read command the LSI53C1510 uses the con?guration read command to read the con?guration space of each agent. an agent is selected during a con?guration access when its idsel signal is asserted and ad[1:0] are 00. during the address phase of a con?guration cycle ad[7:2] addresses one of the 64 dword registers (where byte enables address the bytes
pci functional description (nonintelligent mode) 5-7 within each dword) in the con?guration space of each device. ad[31:11] are logical dont cares to the selected agent. ad[10:8] indicate which device of a multifunction agent is being addressed. 5.1.2.9 con?guration write command the LSI53C1510 uses the con?guration write command to transfer data to the con?guration space of each agent. an agent is selected when its idsel signal is asserted and ad[1:0] are 00. during the address phase of a con?guration cycle, the ad[7:2] lines address the 64 dword registers (where byte enables address the bytes within each dword) in the con?guration space of each device. ad[31:11] are logical dont cares to the selected agent. ad[10:8] indicate which device of a multifunction agent is addressed. 5.1.2.10 memory read multiple command this command is identical to the memory read command except it indicates that the master may intend to fetch more than one cache line before disconnecting. the LSI53C1510 supports pci memory read multiple functionality and issues memory read multiple commands on the pci bus when the memory read multiple mode is enabled. 5.1.2.11 dac command the LSI53C1510 performs dacs when 64-bit addressing is required. see pci 2.1 speci?cation. 5.1.2.12 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. read multiple with read line enabled C when both the read multiple and read line modes are enabled, a memory read multiple command is issued, even though conditions for memory read line are met.
5-8 registers (nonintelligent mode) if the read multiple mode is enabled and the read line mode is disabled, memory read multiple commands are issued if the memory read multiple conditions are met. 5.1.2.13 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in pci con?guration space. multiple cache line transfers C the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size speci?ed in pci 2.1 speci?cation. after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, and no larger than the burst size. the most likely scenario of this scheme is that the chip selects the burst size after alignment, and issues bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip ?nishes the transfer with this burst size. latency C in accordance with the pci speci?cation, the latency timer is ignored when issuing a memory write and invalidate command such that when a latency time-out occurs, the LSI53C1510 continues to transfer up to a cache line boundary. at that point, the chip relinquishes the bus, and ?nishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. pci target retry C during a memory write and invalidate transfer, if the target device issues a retry (stop with no trdy, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to
pci functional description (nonintelligent mode) 5-9 ?nish the transfer on another bus ownership. the chip issues the appropriate command on the next ownership, in accordance with the pci speci?cation. pci target disconnect C during a memory write and invalidate transfer, if the target device issues a disconnect the LSI53C1510 relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip issues the appropriate command on the next ownership, in accordance with the pci speci?cation. 5.1.3 internal arbiter the pci scsi controller uses a single req/ - gnt/ signal pair to arbitrate for access to the pci bus. an internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for pci bus access. there are two independent bus mastering functions inside the LSI53C1510, one for each of the scsi functions. the internal arbiter uses a round robin arbitration scheme to decide which internal bus mastering function may arbitrate for access to the pci bus. this ensures that no function is starved for access to the pci bus. 5.1.4 pci cache mode the LSI53C1510 supports the pci speci?cation for an 8-bit cache line size register located in the pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands memory read line, memory read multiple, memory write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. 5.1.4.1 memory to memory moves memory to memory moves also support pci cache commands, as described above, with one limitation. memory write and invalidate on memory to memory move writes are only supported if the source and destination address are quad word aligned. if the source and destination are not quad word aligned (i.e. source address[2:0] == destination address[2:0]), no write aligning will be performed nor will memory write and invalidates be issued. the LSI53C1510 is little endian only.
5-10 registers (nonintelligent mode) 5.2 pci con?guration registers (nonintelligent mode) the pci con?guration registers, as shown in table 5.2 , are accessed by performing a con?guration read/write to the device with its idsel pin asserted and the appropriate value in ad[10:8] during the address phase of the transaction. scsi function a is identi?ed by a binary value of 000b, and scsi function b by a value of 001b. each scsi function contains the same register set with identical default values, except the interrupt pin register. all pci compliant devices, such as the LSI53C1510, must support the vendor id , device id , command , and status registers. support of other pci compliant registers is optional. in the LSI53C1510, registers that are not supported are not writable and return all zeros when read. only those registers and bits that are currently supported by the LSI53C1510 are described in this chapter. reserved bits should not be accessed . reserved registers and bits are shaded. table 5.2 pci con?guration register map 31 16 15 0 address page device id vendor id 0x00 5-11 status command 0x04 5-11 class code revision id (rev id) 0x08 5-15 bist header type latency timer cache line size 0x0c 5-15 base address register zero (i/o) 0x10 5-17 base address register one (memory) 0x14 5-18 base address register two (scripts ram) 0x18 5-18 reserved 0x1c 5-18 reserved 0x20 5-18 reserved 0x24 5-18 reserved 0x28 5-18 subsystem id subsystem vendor id 0x2c 5-19 expansion rom base address 0x30 5-20 reserved capabilities pointer 0x34 5-21 reserved 0x38 5-21 max_lat min_gnt interrupt pin interrupt line 0x3c 5-22 power management capabilities next item pointer capability id 0x40 5-23 data bridge support extensions power management control/status 0x44 5-25
pci con?guration registers (nonintelligent mode) 5-11 registers: 0x00C0x01 vendor id read only vid vendor id [15:0] this 16-bit register identi?es the manufacturer of the device. the vendor id is 0x1000. registers: 0x02C0x03 device id read only did device id [15:0] this 16-bit register identi?es the particular device. the device id in nonintelligent mode is 0x000a. registers: 0x04C0x05 command read/write the scsi command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the LSI53C1510 is logically disconnected from the pci bus for all accesses except con?guration accesses. r reserved [15:9] 15 0 vid 0001000000000000 15 0 did 0000000000001010 15 987 6 543 2 1 0 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 00 00
5-12 registers (nonintelligent mode) se serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is clear. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 this bit allows the LSI53C1510 to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled and disabled with this bit. the LSI53C1510 always generates parity for the pci bus. r reserved 5 wie write and invalidate enable 4 this bit allows the LSI53C1510 to generate memory write and invalidate commands on the pci bus. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the LSI53C1510 to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the LSI53C1510 to behave as a bus master. the device must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the LSI53C1510 to respond to memory space accesses. a value of zero disables the device response. a value of one allows the LSI53C1510 to respond to memory space accesses at the address range speci?ed by the base address regis- ter one (memory) and base address register two (scripts ram) registers in the pci con?guration space. eis enable i/o space 0 this bit controls the LSI53C1510 response to i/o space accesses. a value of zero disables the device response. a value of one allows the LSI53C1510 to respond to i/o space accesses at the address range speci?ed by the base address register zero (i/o) register in the pci con?guration space.
pci con?guration registers (nonintelligent mode) 5-13 registers: 0x06C0x07 status read/write reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is reset whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the LSI53C1510 whenever it detects a data parity error, even if the data parity error handling is disabled. sse signaled system error 14 this bit is set whenever the device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. r reserved 11 dt devsel/ timing [10:9] these bits encode the timing of devsel/. these are encoded as: 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt dpr rnc r 0000 0000 0 0 01 0 0 0 0 00b fast 01b medium 10b slow 11b reserved
5-14 registers (nonintelligent mode) these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. the LSI53C1510 supports a value of 01b. dpr data parity error reported 8 this bit is set when the following conditions are met: the bus agent asserted perr/ itself or observed perr/ asserted and; the agent setting this bit acted as the bus master for the operation in which the error occurred and; the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities 4 a value of one implements a list of extended capabilities. r reserved [3:0]
pci con?guration registers (nonintelligent mode) 5-15 register: 0x08 revision id (rev id) read only rid revision id [7:0] this register speci?es a device speci?c revision identi?er. this silicon version of the LSI53C1510 is set to 0x00 for rev a silicon. registers: 0x09C0x0b class code read only cc class code [23:0] this 24-bit register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register level programming interface. the value of this register is 0x010000, which identi?es a scsi controller. register: 0x0c cache line size read/write cls cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. the value in this register is used by the device to determine whether to use memory write and invalidate or write commands for performing write cycles, 7 0 rid 00000000 23 0 cc 000000010000000000000000 7 0 cls 00000000
5-16 registers (nonintelligent mode) and whether to use memory read, memory read line, or memory read multiple commands for performing read cycles as a bus master. devices participating in the caching protocol use this ?eld to know when to retry burst accesses at cache line boundaries. if this register is programmed to a number which is not a power of 2, the device will not use pci performance commands to perform data transfers. register: 0x0d latency timer read/write lt latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the scsi functions of the LSI53C1510 support this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the scsi functions of the LSI53C1510. latency = 2 + (burst size * (typical wait states + 1)) values greater than optimum are also acceptable. 7 0 lt 00000000
pci con?guration registers (nonintelligent mode) 5-17 register: 0x0e header type read only ht header type [7:0] this 8-bit register identi?es the layout of bytes 0x10 through 0x3f in con?guration space and also whether or not the device contains multiple functions. since the LSI53C1510 is a multifunction controller the value of this register is 0x80. register: 0x0f not supported registers: 0x10C0x13 base address register zero (i/o) read/write barz base address register zero - i/o [31:0] this base address register is used to map the operating register set into i/o space. the LSI53C1510 requires 256 bytes of i/o space for this base address register. it has bit zero hardwired to one. bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci 2.1 speci?cation. 7 0 ht[7:0] 10000000 31 0 barz 00000000000000000000000000000001
5-18 registers (nonintelligent mode) registers: 0x14C0x17 base address register one (memory) read/write baro base address register one [31:0] this base address register maps scsi operating registers into memory space. this device requires 1024 bytes of address space for this base register. the default value of this register is 0x00000000. for detailed information on the operation of this register, refer to the pci 2.1 speci?cation. registers: 0x18C0x1b base address register two (scripts ram) read/write bart base address register two [31:0] this base register is used to map the scripts ram into memory space. the LSI53C1510 requires 4 k of address space for this base register. this register has bits [11:0] hardwired to 000000000000. for detailed information on the operation of this register, refer to the pci 2.1 speci?cation. registers: 0x1cC0x2b reserved 31 0 baro 00000000000000000000000000000000 31 0 bart 00000000000000000000000000000000
pci con?guration registers (nonintelligent mode) 5-19 registers: 0x2cC0x2d subsystem vendor id read only svid subsystem vendor id [15:0] this 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendors cards, even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is disabled (mem_addr7 pulled high), this register returns a value of 0x1000 (lsi logic vendor id). the 16-bit value that should be stored in the external serial eeprom for this register is the vendors pci vendor id and must be obtained from the pci sig. please see section 2.4.3, serial eeprom, for more information on downloading a value for this register. if the external serial eeprom interface is enabled (mem_addr7 pulled low), this register is automatically loaded at power-up from the external serial eeprom and will contain the value downloaded from the serial eeprom or a value of 0x0 if the download fails. 15 0 svid 0001000000000000 default : if mem_addr7 is high 0000000000000000 default : if mem_addr7 is low
5-20 registers (nonintelligent mode) registers: 0x2eC0x2f subsystem id read only sid subsystem id [15:0] this 16-bit register is used to uniquely identify the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom is disabled (mem_addr7 pulled high), the register returns a value of 0x1000. the 16-bit value that should be stored in the external serial eeprom is vendor speci?c. if the external serial eeprom interface is enabled (mem_addr7 pulled low), this register is automatically loaded at power-up from the external serial eeprom. registers: 0x30C0x33 expansion rom base address read/write erba expansion rom base address [31:0] this four byte register handles the base address and size information for the expansion rom. it functions exactly like the base address register one (memory) and base address register two (scripts ram) registers, 15 0 sid 0001000000000000 default : if mem_addr7 is high xxxxxxxxxxxxxxxx default : if mem_addr7 is low 31 0 erba 00000000000000000000000000000001
pci con?guration registers (nonintelligent mode) 5-21 except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. the expansion rom enable bit, bit 0, is the only bit de?ned in this register. this bit is used to control whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device is used with or without an expansion rom depending on the system con?guration. to access the external memory interface, also set the memory space bit in the command register. the host system detects the size of the external memory by ?rst writing the expansion rom base address register with all ones and then reading back the register. the scsi functions of the LSI53C1510 respond with zeros in all dont care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. the size of the external memory is set through mem_addr[3:0]. please see section 2.1.2, con?gura- tion and initialization, for the possible size encodings available. register: 0x34 capabilities pointer read only cp capabilities pointer [7:0] this register indicates that the ?rst extended capability register is located at offset 0x40 in the pci con?guration. registers: 0x35C0x3b reserved 7 0 cp 00000100
5-22 registers (nonintelligent mode) register: 0x3c interrupt line read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software writes the routing information into this register as it con?gures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin is connected to. values in this register are speci?ed by system architecture. register: 0x3d interrupt pin read only ip interrupt pin [7:0] this register is unique to each scsi function. it tells which interrupt pin the device uses. its value is set to 0x01 for the function a (inta/) signal, and 0x02 for the function b (intb/) signal at power-up. 7 0 il 00000000 7 0 ip 00000001 default : scsi function a, inta/ signal 00000010 default : scsi function b, intb/ signal
pci con?guration registers (nonintelligent mode) 5-23 register: 0x3e min_gnt read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the LSI53C1510 sets this register to 0x1e. register: 0x3f max_lat read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. the value speci?ed in these registers is in units of 0.25 microseconds. the LSI53C1510 scsi function sets this register to 0x08. register: 0x40 capability id read only cid cap_id [7:0] bits [7:0] identify this register as a pci power management register (0x01). 7 0 mg 00011110 7 0 ml 00001000 7 0 cid 00000001
5-24 registers (nonintelligent mode) register: 0x41 next item pointer read only nip next_item_ptr [7:0] bits [7:0] contain the offset location of the next item in the functions capabilities list. the LSI53C1510 has these bits set to zero indicating no further extended capabilities registers exist. registers: 0x42C0x43 power management capabilities read only pmes[4:0] pme_support [15:11] bits [15:11] de?ne the power management states in which the LSI53C1510 will assert the pme pin. these bits are all set to zero. d2s d2_support 10 d2 power management state is not supported. d1s d1_support 9 d1 power management state is not supported. r reserved [8:6] dsi device speci?c initialization 5 this bit is a device speci?c initialization bit and is set to zero to indicate that no special initialization is required. aps auxiliary power source 4 this bit is set to zero and indicates that an auxiliary power source is not needed for the LSI53C1510. 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes[4:0] d2s d1s r dsi aps pmec ver[2:0] 0000011 0 0 000 0 001
pci con?guration registers (nonintelligent mode) 5-25 pmec pme clock 3 bit 3 is set to zero and indicates that no pci clock is required to assert the pme pin. ver[2:0] version [2:0] these three bits indicate that the LSI53C1510 complies with version 1.0 of the pci power management speci?cation. registers: 0x44C0x45 power management control/status read/write pst pme_status 15 this bit de?nes if the LSI53C1510 has generated a power management event. dscl[1:0] data_scale [14:13] these bits are not used in the LSI53C1510. dslt data_select [12:9] these bits are not used in the LSI53C1510. pen pme_enable 8 this bit is not used in the LSI53C1510. r reserved [7:2] pws[1:0] power state [1:0] these bits are used to determine the current power state of the LSI53C1510. they are used to place the LSI53C1510 in a new power state. power states are de?ned as: 15 14 13 12 9 8 7 2 0 pst dscl[1:0] dslt pen r pws[1:0] 00000000 0 0 0 0 0 000 00b d0 11b d3 hot
5-26 registers (nonintelligent mode) register: 0x46 bridge support extensions read only bse bridge support extensions [7:0] bits [7:0] are not used and will return to 0x00 if read. register: 0x47 data read only data data [7:0] bits [7:0] are not used and will return to 0x00 if read. 5.3 differences from the lsi53c895 and the lsi53c896 the LSI53C1510 scsi cores are similar to the lsi53c895 and lsi53c896, but there are differences. the differences are listed below. fifo depth the LSI53C1510 scsi dma fifos are 816 bytes deep (the same as the lsi53c895). the lsi53c896 fifos are 944 bytes deep. scripts ram the LSI53C1510 scripts rams are 4 kbytes while the lsi53c896 are 8 kbytes. register differences differences do exist between the LSI53C1510 and the lsi53c896 register bits. chapter 12, scsi interface, in the LSI53C1510 i 2 o- ready pci raid ultra2 scsi controller programming guide describes the differences. 7 0 bse 00000000 7 0 data 00000000
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 6-1 chapter 6 registers (intelligent mode) this chapter contains the following sections: section 6.1, programming models, page 6-3 section 6.2, pci con?guration registers (intelligent mode), page 6-4 section 6.3, host interface registers (intelligent mode), page 6-19 section 6.4, shared memory, page 6-27 after power-on, the LSI53C1510 is con?gured as either a nonintelligent or intelligent controller. this chapter describes the pci and host interface registers that are visible to the host in intelligent mode. in intelligent mode, the LSI53C1510 is con?gured as an intelligent iop supporting either dual channel scsi or raid. in intelligent mode, a single base address region is de?ned that contains the i 2 o messaging interface and control. figure 6.1 illustrates how, in intelligent mode of operation, the i 2 o messages are routed to the arm risc processor and the processor controls the other modules including the two scsi modules.
6-2 registers (intelligent mode) figure 6.1 LSI53C1510 block diagram in intelligent mode this section contains descriptions of the LSI53C1510 pci and host interface commands and registers. in the descriptions the term set is used to refer to bits that are programmed to a binary one. similarly, the terms clear and reset are used to refer to bits that are programmed to a binary zero. do not set reserved bits. reserved bit functions may change at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. reserved registers and bits are shaded. pci master and slave control block, pci con?guration registers, and dma channel arbitration 4 kbyte scripts ram 8 dword scripts host pci bus (32-bit, 33 mhz) wide ultra2 scsi bus prefetch buffer 816 byte dma fifo operating registers scsi scripts processor scsi fifo and scsi control block lvdlink drivers and receivers eeprom and auto- con?guration serial (a channel) 2-wire serial eeprom 8 kbyte arm instruction/ data buffer jtag parity assist engine dram engine memory control flash rom buffer i 2 o msg unit slave dma internal module bus arm risc processor jtag flash rom/dram memory bus 4 kbyte scripts ram 8 dword scripts wide ultra2 scsi bus prefetch buffer scsi fifo and scsi control block lvdlink drivers and receivers (b channel) ultra2 scsi controller ultra2 scsi controller arm debug buffer 816 byte dma fifo operating registers scsi scripts processor
programming models 6-3 6.1 programming models the LSI53C1510 in intelligent mode contains two programming models: a system (host) programming model and a local programming model. the system model includes all necessary hardware registers, shared memory and associated memory addresses from the host viewpoint using system addresses. the local programming model includes all hardware and memory which are private from the system. 6.1.1 system programming model the system programming model consists of pci con?guration registers, host interface registers, and a shared memory region. 6.1.2 local programming model the local programming model consists of arm registers, protocol engine registers, and local memory regions.
6-4 registers (intelligent mode) 6.2 pci con?guration registers (intelligent mode) the pci con?guration registers, as shown in table 6.1 , are accessed by performing a con?guration read/write to the device with its idsel pin asserted and the appropriate value in ad[10:8] during the address phase of the transaction. all pci compliant devices, such as the LSI53C1510, must support the vendor id , device id , command , and status registers. support of other pci compliant registers is optional. in the LSI53C1510, registers that are not supported are not writable and return all zeros when read. only those registers and bits that are currently supported by the LSI53C1510 are described in this chapter. reserved bits should not be accessed . reserved registers and bits are shaded. table 6.1 pci con?guration register map 31 16 15 0 address page device id vendor id 0x00 6-5 status command 0x04 6-5 class code revision id (rev id) 0x08 6-8 bist (built-in self test) header type latency timer cache line size 0x0c 6-9 base address register zero (i/o) 0x10 6-11 base address register one (shared memory) 0x14 6-12 reserved 0x18 6-12 reserved 0x1c 6-12 reserved 0x20 6-12 reserved 0x24 6-12 reserved 0x28 6-12 subsystem id subsystem vendor id 0x2c 6-12 expansion rom base address 0x30 6-13 reserved capabilities pointer 0x34 6-14 reserved 0x38 6-14 max_lat min_gnt interrupt pin interrupt line 0x3c 6-14 power management capabilities (pmc) next item pointer capability id 0x40 6-16 data bridge support exten- sions (pmcsr_bse) power management control/status (pmcsr) 0x44 6-17
pci con?guration registers (intelligent mode) 6-5 registers: 0x00C0x01 vendor id read only vid vendor id [15:0] this 16-bit register identi?es the manufacturer of the device. the vendor id is 0x1000. registers: 0x02C0x03 device id read only did device id [15:0] this 16-bit register identi?es the particular device. the device id is 0x10. registers: 0x04C0x05 command read/write the command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the LSI53C1510 is logically disconnected from the pci bus for all accesses except con?guration accesses. 15 0 vid 0001000000000000 15 0 did 0000000000010000 15 987 6 543210 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 0000
6-6 registers (intelligent mode) r reserved [15:9] se serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is zero and enabled when the bit is one. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 this bit allows the LSI53C1510 to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled and disabled with this bit. the LSI53C1510 always generates parity for the pci bus. r reserved 5 wie write and invalidate enable 4 this bit allows the LSI53C1510 to generate write and invalidate commands on the pci bus. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the LSI53C1510 to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the LSI53C1510 to behave as a bus master. the device must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the LSI53C1510 to respond to memory space accesses. a value of zero disables the device response. a value of one allows the LSI53C1510 to respond to memory space accesses. eis enable i/o space 0 this bit controls the LSI53C1510 response to i/o space accesses. a value of zero disables the device response. a value of one allows the LSI53C1510 to respond to i/o space accesses.
pci con?guration registers (intelligent mode) 6-7 registers: 0x06C0x07 status read/write the status register is used to record status information for pci bus related events. reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the LSI53C1510 whenever it detects a data parity error, even if data parity error handling is disabled. sse signaled system error 14 the LSI53C1510 sets this bit whenever it asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt dpr rnc r 0000 0000 0 0 01 0 0 0 0
6-8 registers (intelligent mode) r reserved 11 dt devsel/timing [10:9] these bits encode the timing of devsel/. these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. the LSI53C1510 supports a value of 01b. dpr data parity error reported 8 this bit is set when the following conditions are met: the bus agent asserted perr/ itself or observed perr/ asserted and; the agent setting this bit acted as the bus master for the operation in which the error occurred and; the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities 4 a value of one implements a list of extended capabilities. r reserved [3:0] register: 0x08 revision id (rev id) read only rid revision id [7:0] this register speci?es a device speci?c revision identi?er. this silicon version of the LSI53C1510 is set to 0x00 for rev a silicon. 0, 0 fast 0, 1 medium 1, 0 slow 1, 1 reserved 7 0 rid 00000000
pci con?guration registers (intelligent mode) 6-9 registers: 0x09C0x0b class code read only cc class code [23:0] this 24-bit register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register level programming interface. the value of this register is 0x0e0000, which identi?es an i 2 o iop (LSI53C1510 in intelligent mode). register: 0x0c cache line size read/write cls cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. the value in this register is used by the device to determine whether to use write and invalidate or write commands for performing write cycles, and whether to use memory read, memory read line, or memory read multiple commands for performing read cycles as a bus master. devices participating in the caching protocol use this ?eld to know when to retry burst accesses at cache line boundaries. these devices can ignore the pci cache support lines (sdone and sb0/) when this register is set to 0. if this register is programmed to a number which is not a power of 2, the device will not use pci performance commands to perform data transfers. 23 0 cc 000011100000111000001110 7 0 cls 00000000
6-10 registers (intelligent mode) register: 0x0d latency timer read/write lt latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the scsi functions of the LSI53C1510 support this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the scsi functions of the LSI53C1510. latency = 2 + (burst size * (typical wait states + 1)) values greater than optimum are also acceptable. register: 0x0e header type read only ht header type [7:0] this 8-bit register identi?es the layout of bytes 0x10 through 0x3f in con?guration space and also whether or not the device contains multiple functions. in intelligent mode, the LSI53C1510 is a single function controller, therefore, the value of this register is 0x00. 7 0 lt 00000000 7 0 ht 00000000
pci con?guration registers (intelligent mode) 6-11 register: 0x0f bist (built-in self test) read/write bc bist capable 7 should return a one if the device implements a bist, a zero if it does not. sb start bist 6 writing a one into this bit starts the devices bist. the device resets this bit automatically upon completion. software should fail the device if the bist does not complete within two seconds. r reserved [5:4] cc completion code [3:0] a value of zero indicates successful completion, while a nonzero result indicates a device speci?c error. registers: 0x10C0x13 base address register zero (i/o) read/write barz base address register zero - i/o [31:0] this base address register is used to map the operating register set into i/o space. the LSI53C1510 requires 256 bytes of i/o space for this base address register. this register has bit zero hardwired to one. bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci 2.1 speci?cation. 76543 0 bc sb rcc 00 0 00000 31 0 barz 00000000000000000000000000000000
6-12 registers (intelligent mode) registers: 0x14C0x17 base address register one (shared memory) read/write baro memory base address register one [31:0] this base address register map indicates width (32-bit) and location of memory required by the device and its size is programmable from 1 k (2 10 ) through 128 m (2 27 ) bytes in steps of powers of 2. this memory is speci?ed as nonprefetchable due to the messaging fifos. the default size is 128 k. registers: 0x18C0x2b reserved registers: 0x2cC0x2d subsystem vendor id read only svid subsystem vendor id [15:0] this 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendors cards, even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). the arm programs this 16-bit value at startup or reset time. 31 0 baro[31:0] 00000000000000000000000000000100 15 0 svid 0001000000000000
pci con?guration registers (intelligent mode) 6-13 registers: 0x2eC0x2f subsystem id read only sid subsystem id [15:0] this 16-bit register is used to uniquely identify the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). the arm programs this 16-bit value at startup or reset time. registers: 0x30C0x33 expansion rom base address read/write erba expansion rom base address [31:0] this register indicates the location of expansion rom device and is programmable from 16 k (2 14 ) through 4(2 22 ) mbytes in steps of powers of 2 (using external pin pull-up options on the external memory address (mem_addr) bits [3:0]). 15 0 sid 0001000000000000 31 0 erba 00000000000000000000000000000001
6-14 registers (intelligent mode) register: 0x34 capabilities pointer read only cp capabilities pointer [7:0] this register indicates that the ?rst extended capability register is located at offset 0x40 in the pci con?guration. registers: 0x35C0x3b reserved register: 0x3c interrupt line read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software writes the routing information into this register as it con?gures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin is connected to. values in this register are speci?ed by system architecture. 7 0 cp 00000100 7 0 il 00000000
pci con?guration registers (intelligent mode) 6-15 register: 0x3d interrupt pin read only ip interrupt pin [7:0] this register tells which interrupt pin the device uses. its value is set to 0x01. register: 0x3e min_gnt read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the LSI53C1510 sets this register to 0x1e. register: 0x3f max_lat read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. 7 0 ip 00000001 7 0 mg 00011110 7 0 ml 00001000
6-16 registers (intelligent mode) the value speci?ed in these registers is in units of 0.25 microseconds. the LSI53C1510 scsi function sets this register to 0x08. register: 0x40 capability id read only cid cap_id [7:0] bits [7:0] identify this register as a pci power management register (0x01). register: 0x41 next item pointer read only nip next_item_ptr [7:0] the LSI53C1510 has these bits set to zero indicating pci does not have any further pci extended capabilities registers. registers: 0x42C0x43 power management capabilities (pmc) read only pmes[4:0] pme_support [15:11] bits [15:11] de?ne the power management states in which the LSI53C1510 will assert the pme pin. these bits are all set to zero. 7 0 cid 00000001 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes[4:0] d2s d1s r dsi aps pmec ver[2:0] 0000010 0 0 000 0 001
pci con?guration registers (intelligent mode) 6-17 d2s d2_support 10 d2 power management state is not supported. d1s d1_support 9 d1 power management state is not supported. r reserved [8:6] dsi device speci?c initialization 5 this bit is a device speci?c initialization bit and is set to zero to indicate that no special initialization is required. aps auxiliary power source 4 this bit is set to zero and indicates that an auxiliary power source is not needed for the LSI53C1510. pmec pme clock 3 bit 3 is set to zero and indicates that no pci clock is required to assert the pme pin. ver[2:0] version [2:0] these bits indicate the version of the pci power management speci?cation the LSI53C1510 complies to version 1.0. registers: 0x44C0x45 power management control/status (pmcsr) read/write pst pme_status 15 bit 15 de?nes if the LSI53C1510 has generated a power management event. dscl[1:0] data_scale [14:13] bits [14:13] are not supported in the LSI53C1510. dslt data_select [12:9] bits [12:9] are not supported in the LSI53C1510. pen pme_enable 8 bit 8 is not supported in the LSI53C1510. 15 14 13 12 9 8 7 2 0 pst dscl[1:0] dslt pen r pws[1:0] 00000000 0 0 0 0 0 000
6-18 registers (intelligent mode) r reserved [7:2] pws[1:0] power state [1:0] bits [1:0] are used to determine the current power state of the LSI53C1510. they are also used to set the LSI53C1510 to a new power state. power states are de?ned as: register: 0x46 bridge support extensions (pmcsr_bse) read only bse bridge support extensions [7:0] bits [7:0] are not supported and will return 0x00 when read. register: 0x47 data read only data data [7:0] bits [7:0] are not supported and will return 0x00 when read. 00b00 d0 0b11 d3 hot 7 0 bse 00000000 7 0 data 00000000
host interface registers (intelligent mode) 6-19 6.3 host interface registers (intelligent mode) the host interface contains the following registers as shown in table 6.2 . reserved registers and bits are shaded. table 6.2 LSI53C1510 host interface register map 31 16 15 0 address page diagint 1 0x00 6-20 wrseq 1 0x04 6-21 diag 1 0x08 6-22 test base address 1 0x0c 6-23 reserved 0x10 6-23 reserved 0x14 6-23 reserved 0x18 6-23 reserved 0x1c 6-23 host doorbell 0x20 6-24 reserved 0x24 6-24 reserved 0x28 6-24 reserved 0x2c 6-24 reply interrupt status 0x30 6-25 reply interrupt mask 0x34 6-25 reserved 0x38 6-26 reserved 0x3c 6-26 request free list fifo (read only), request post list fifo (write only) 2 0x40 6-26 reply post list fifo (read only), reply free list fifo (write only) 2 0x44 6-26 1. these registers are for diagnostic or test use only. 2. write access to the request post list and reply free list fifos that are less than 32 bits are ignored.
6-20 registers (intelligent mode) register: 0x00 diagint read/write note: this register is intended for diagnostic/test use only. the diagint register contains interrupt status and control as described below. the LSI53C1510 protocol engine can be con?gured to generate interrupts using direct f/w control. this register is used to report and enable/mask interrupts to pci. the normal pci interrupt reporting mechanism occurs in the reply interrupt status register. this register is provided for diagnostic purposes only. r reserved [31:2] ien interrupt enable 1 the ien control bit provides an enable function for the pci interrupt pin when f/w generated interrupts are selected. in order for the external pci int/ interrupt pin to be asserted when f/w generated interrupts are selected, the ien bit must be set to one. diagint/clrint diagnostic interrupt (read)/ clear interrupt (write) 0 the diagint status bit indicates that the protocol engine is alerting the host of an interrupt condition. when the f/w generated interrupt source is selected, writing a one to bit 0 of this register will clear the f/w generated interrupt. this interrupt status bit is not normally used except for diagnostic purposes. 31 21 0 r ien diagint/clrint 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
host interface registers (intelligent mode) 6-21 register: 0x04 wrseq write only note: this register is intended for diagnostic/test use only. the wrseq register is used to enable write accesses to the diag register. in order to prevent inadvertent access, the diag register cannot be written to unless a speci?c sequence of data is written to the wrseq register. the wrseq register is write only. r reserved [31:4] key_value key_value [3:0] a sequence of ?ve data writes must be written into the key_value ?eld of the wrseq register in order to enable writes to the diag register. any data value written out that does not match the expected sequence value will cause the wrseq register to restart by looking for the ?rst sequence value. the required data sequence is: 0x4, 0xb, 0x2, 0x7, 0xd after the last value (0xd) is written, the diag register may be written to until another write to the wrseq register occurs of any value. a bit is provided within the diag register which may be read at any time to determine if write access is enabled for the diag register (e.g. to verify that the wrseq data sequence was correct or to verify that writes to the diag register are disabled). 31 43 0 r key_value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000
6-22 registers (intelligent mode) register: 0x08 diag read/write note: this register is intended for diagnostic/test use only. the register contains low level diagnostic control and status. r reserved [31:8] dwe diag register write enabled (read only) 7 this read only bit when set indicates that write access to the diag register may occur. the dwe bit is set when the correct key sequence has been written to the wrseq register. r reserved [6:4] ttl_int select ttl output for pci-inta/ 3 this bit determines whether the LSI53C1510 pci-inta/ interrupt pin is con?gured as a ttl or open drain output. this bit defaults to zero (open drain) on reset. this bit should only be set to one (ttl) during chip testing. rsta reset adapter (write only) 2 this write only bit will cause the protocol engine reset controller to generate a soft reset to all LSI53C1510 logic. this bit will be automatically cleared when the soft reset condition is generated. the arm core will start executing from its reset vector when the soft reset condition subsides. disarm disable arm core 1 the disarm control bit causes the arm core, the instruction prefetch unit, the read path control unit, and the write buffer to be held reset. this bit will remain set until cleared by the host. this bit is included to allow low level testing and programming of flash memory using a host resident utility. 31 8 7 6 4 3 2 1 0 rdwe r ttl_int rsta disarm dmmap 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 0
host interface registers (intelligent mode) 6-23 dmmap diagnostic memory map 0 this bit when set causes all pci accesses to memory base 0 address space (except for offsets 0x00C0x7f) to be mapped to internal local bus accesses. this allows host utilities the capability to read or write any arbitrary internal local address. this is useful for low level testing and for programming flash memory using host resident utilities. to form an internal local address, the lower 13 bits of the pci address are combined with the contents of the test base address register. this gives an 8 kbyte window of addressability into local address space at any one time. register: 0x0c test base address read/write note: this register is intended for diagnostic/test use only. tba test base address [31:13] the tba register is used to provide address bits [31:13] of the local address during diagnostic host<->local accesses (the lower 13 address bits come directly from the host address). r reserved [12:0] registers: 0x10C0x1f reserved 31 13 12 0 tba r 0000000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 0
6-24 registers (intelligent mode) register: 0x20 host doorbell read/write hd host doorbell [31:0] this is a 32-bit inbound doorbell register accessible by the host. all 32 bits of the register are read/write by a pci master, although the pci master can only set a bit to one. the pci master cannot clear a bit to zero. the arm can read and write all 32 doorbell bits using a locally mapped arm doorbell register, although the arm can only clear a bit to zero. the arm cannot set a bit to one. should a pci master setting operation occur simultaneously with an arm clearing operation, the clearing operation takes precedence. the default reset state of the doorbell register is all zeros. a read only interrupt status bit is available to the arm to indicate that any of the 32 doorbell bits are set. a read/write interrupt enable bit is available to the arm to allow the interrupt status bit to generate an interrupt to the arm when both the interrupt status bit and the interrupt enable bit are set to one. registers: 0x24C0x2f reserved 31 0 hd 00000000000000000000000000000000
host interface registers (intelligent mode) 6-25 register: 0x30 reply interrupt status read only the reply interrupt status register reports interrupt status to pci. r reserved [31:4] replyint reply message interrupt 3 this read only bit is set whenever a posted reply message is available for the host to process (replypostfifo not empty and prefetch of replypost- mfa complete). this bit will cause a pci interrupt to be generated when replyintmask = 0. this is the default interrupt reporting mechanism for the LSI53C1510 protocol engine. r reserved [2:0] register: 0x34 reply interrupt mask read/write the reply interrupt mask register masks interrupt reporting to pci. r reserved [31:4] replyintmask reply message interrupt mask 3 this bit masks the pci interrupt generated by the reply- postfifo not empty condition. when this bit is set to one, the pci interrupt will not be generated. when this bit is reset to zero, the pci interrupt will be generated. this bit defaults to one on hard or soft reset. r reserved [2:0] 31 432 0 r replyint r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 31 4320 r replyintmask r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0
6-26 registers (intelligent mode) registers: 0x38C0x3f reserved register: 0x40 request free list fifo (read only) request post list fifo (write only) request messages are created by the host to request an action by the LSI53C1510. for a complete explanation of how the request free/post list fifos are used in the message passing i/o interface, see section 2.2, the host interface. register: 0x44 reply post list fifo (read only) reply free list fifo (write only) reply messages are used by the LSI53C1510 to send status information back to the host. for a complete explanation of how the reply post/free list fifos are used in the message passing i/o interface, see section 2.2, the host interface. 31 0 fifo 00000000000000000000000000000000 31 0 fifo 00000000000000000000000000000000
shared memory 6-27 6.4 shared memory a region of shared memory (LSI53C1510 local memory mapped to system addresses) is provided to allow the host to write request message frames into. this is the default method (push model) for request message frame transport, where the host itself copies the request message frame into the LSI53C1510 local memory. the total size of shared memory is con?gured by the protocol engine on reset. supported values are: 32 kbytes, 64 kbytes, 128 kbytes (default), 256 kbytes, 512 kbytes, 1 mbyte, 2 mbytes, 4 mbytes, 8 mbytes, 16 mbytes, 32 mbytes, 64 mbytes, and 128 mbytes. address translation between system and local addresses is performed as illustrated in figure 6.2 . figure 6.2 shared memory address translation pci memory 0 address space address space LSI53C1510 host interface registers LSI53C1510 dram memory 0x01000000 0x01000080 LSI53C1510 dram address 0x01000000 + size of (shared memory) -1 0x00 0x80 0x7f size of (shared memory) -1 offset from pci memory 0 base address
6-28 registers (intelligent mode)
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller 7-1 3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 12 pc 12.938 pc 13.851 pc 48.583 pc 52.5 pc 34.5 pc 34.732 pc chapter 7 speci?cations this chapter speci?es the LSI53C1510 electrical and mechanical characteristics. it is divided into the following sections: section 7.1, dc characteristics, page 7-1 section 7.2, tolerant technology electrical characteristics, page 7-7 section 7.3, ac characteristics, page 7-11 section 7.4, pci and external memory interface timing diagrams, page 7-14 section 7.5, scsi timing diagrams, page 7-36 section 7.6, pinouts and packaging, page 7-43 7.1 dc characteristics this section of the manual describes the LSI53C1510 dc characteristics. table 7.1 through table 7.13 give current and voltage speci?cations. figure 7.1 and figure 7.2 are driver schematics.
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-2 speci?cations table 7.1 absolute maximum stress ratings symbol parameter min max 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. unit test conditions t stg storage temperature - 55 150 cC v dd supply voltage - 0.5 5.0 v C v in input voltage v ss - 0.3 v dd +0.3 v C v in5v input voltage (5 v tolerant pins) v ss - 0.3 5.25 v C i lp 2 2. - 2v 3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc dc characteristics 7-3 figure 7.1 lvd driver note:v cm = 0.7C1.8 v table 7.3 lvd driver scsi signalssd[15:0]+, sdp[1:0]/, sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ symbol parameter min max units test conditions i o + source (+) current 7 11 ma asserted state i o - sink ( - ) current - 7 - 11 ma asserted state i o + source (+) current - 3.5 - 5.5 ma negated state i o - sink ( - ) current 3.5 5.5 ma negated state i oz 3-state leakage - 20 20 m av pin = 0 v, 3.47 v i oz ( srst - only ) 3-state leakage - 500 - 50 m aC notes: v cm = 0.7C1.8 v. r l = 0C110 w. r bias = 9.76 k w. r l 2 v cm + i o + r l 2 i o - - + table 7.4 lvd receiver scsi signalssd[15:0]/, sdp[1:0]/, sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ symbol parameter min max units v i lvd receiver voltage asserting 60 C mv v i lvd receiver voltage negating C - 60 mv
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-4 speci?cations figure 7.2 lvd receiver v cm + - + + + - - - v i 2 v i 2 table 7.5 diffsens scsi signal symbol parameter min max unit test conditions 1 1. functional test speci?ed for each mode (v ih ,v s ,v il ). v ih hvd sense voltage 2.4 5.0 v note 1 v s lvd sense voltage 0.7 1.9 v note 1 v il se sense voltage v ss - 0.3 0.5 v note 1 i in input leakage - 10 10 m av pin = 0 v, 5.25 v table 7.6 rbias scsi signal symbol parameter min max unit test conditions v in input voltage v dd - 0.2 C v - 125 m a table 7.7 input capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C 15 pf C
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc dc characteristics 7-5 table 7.8 bidirectional signalsgpio0, gpio1, gpio2, gpio3, gpio4 symbol parameter min max unit test conditions v ih input high voltage 2.0 5.0 v C v il input low voltage v ss - 0.3 0.8 v C v oh output high voltage 2.4 v dd v - 8 ma dynamic v ol output low voltage v ss 0.4 v 8 ma dynamic i oz 3-state leakage - 10 10 m av pin = 0 v, 5.25 v i pull pull-down current 7.5 75 m aC table 7.9 output signalsmce/, moe/_testout, mwe/, tdo symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 4 ma dynamic v ol output low voltage v ss 0.4 v 4 ma dynamic i oz 3-state leakage - 10 10 m av pin = 0 v, 5.25 v table 7.10 bidirectional signalsad[31:0], c_be[7:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par symbol parameters min max unit test conditions v ih input high voltage 0.5 v dd 5.0 v C v il input low voltage v ss - 0.3 0.3 v dd vC v oh output high voltage 0.9 v dd Cv - 500 m a v ol output low voltage C 0.1 v dd v 1500 m a v oh 5 v tolerant output high voltage 2.4 C v - 16 ma v ol 5 v tolerant output low voltage C 0.55 v 16 ma i oz 3-state leakage - 10 10 m av pin = 0 v, 5.25 v i pull pull-down current 7.5 75 m aC
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-6 speci?cations table 7.11 input signalsclk, gnt/, idsel, rst/, sclk, tck, tdi, test_hsc 1 , test_rstn, tms 1. test_hsc has a pull-down symbol parameters min max unit test conditions v ih input high voltage 0.5 v dd 5.0 v C v il input low voltage v ss - 0.3 0.3 v dd vC i in input leakage 2 2. the input leakage test does not apply to the test_rst/ pin with v pin =0v. - 10 10 m av pin = 0 v, 5.25 v i pull 3 3. pull-up spec does not apply to: sclk, clk, gnt/, idsel, and rst/. pull-down current - 75 - 7.5 m aC table 7.12 output signalsinta, intb symbol parameters min max unit test conditions v oh output high voltage 0.9 v dd Cv - 500 m a v ol output low voltage C 0.1 v dd v 1500 m a v oh 5 v tolerant output high voltage 2.4 C v - 16 ma v ol 5 v tolerant output low voltage C 0.55 v 16 ma i oz 3-state leakage - 10 10 m av pin = 0 v, 5.25 v i pull pull-down current - 75 - 7.5 m aC table 7.13 output signalserr/ symbol parameters min max unit test conditions v ol output low voltage C 0.1 v dd v 1.5 ma i oz 3-state leakage - 10 10 m aC
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc tolerant technology electrical characteristics 7-7 7.2 tolerant technology electrical characteristics the LSI53C1510 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 7.14 provides electrical characteristics for se scsi signals. figure 7.3 through figure 7.7 provide reference information for testing scsi signals. table 7.14 tolerant technology electrical characteristics for se scsi signals 1 symbol parameter min max units test conditions v oh 2 output high voltage 2.0 v dd vi oh = - 7ma v ol output low voltage v ss 0.5 v i ol =48ma v ih input high voltage 2.0 v dd +0.3 v C v il input low voltage v ss - 0.3 0.8 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v dd = 4.75; i i = - 20 ma v th threshold, high to low 1.0 1.2 v C v tl threshold, low to high 1.4 1.6 v C v th Cv tl hysteresis 300 500 mv C i oh 2 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 2 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 3 i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 20 m av dd 5%, v pin = 2.7 v i ll input low leakage - 20 C m av dd 5%, v pin =0v i pd power down leakage C 20 m av dd =0v,v pin = 1.2 v r i input resistance 20 C m w scsi pins 4 c p capacitance per pin C 15 pf 388 bga
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-8 speci?cations figure 7.3 rise and fall time test condition figure 7.4 scsi input filtering t r 2 rise time, 10% to 90% 4.0 18.5 ns figure 7.3 t f fall time, 90% to 10% 4.0 18.5 ns figure 7.3 dv h /dt slew rate low to high 0.15 0.50 v/ns figure 7.3 dv l /dt slew rate, high to low 0.15 0.50 v/ns figure 7.3 esd electrostatic discharge 2 C kv mil-std-883c; 3015-7 latch-up 100 C ma C filter delay 20 30 ns figure 7.4 ultra ?lter delay 10 15 ns figure 7.4 ultra2 ?lter delay 5 8 ns figure 7.4 extended ?lter delay 40 60 ns figure 7.4 1. these values are guaranteed by periodic characterization; they are not 100% tested on every device. 2. active negation outputs only: data, parity, sreq/, sack/. 3. single pin only; irreversible damage may occur if sustained for one second. 4. scsi reset pin has 10 k w pull-up resistor. table 7.14 tolerant technology electrical characteristics for se scsi signals 1 symbol parameter min max units test conditions 2.5 v 47 w 20 pf + - req/ or ack/ input t 1 v th note: t 1 is the input ?ltering period.
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc tolerant technology electrical characteristics 7-9 figure 7.5 hysteresis of scsi receivers figure 7.6 input current as a function of input voltage 1 receiving logic level 0 1.1 1.3 1.5 1.7 input voltage (volts) +40 +20 0 - 20 - 40 - 4 0 4 8 12 16 - 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-10 speci?cations figure 7.7 output current as a function of output voltage output sink current (milliamperes) - 800 - 600 - 400 - 200 0 012345 output voltage (volts) output source current (milliamperes) 20 40 60 80 100 012345 output voltage (volts) 0
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc ac characteristics 7-11 7.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to the section 7.1, dc characteristics ). chip timing is based on simulation at worst case voltage, temperature, and processing. timing was developed with a load capacitance of 50 pf table 7.15 and figure 7.8 provide external clock data. figure 7.8 external clock table 7.15 external clock 1 1. timing is for an external 40 mhz clock. a quadrupled 40 mhz clock is required for ultra2 scsi operation. symbol parameter min max units t 1 pci bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 2 2. this parameter must be met to ensure scsi timing is within speci?cation. 25 60 ns t 2 clk low time 3 3. duty cycle not to exceed 60/40. 12 C ns sclk low time 3 10 36 ns t 3 clk high time 3 12 C ns sclk high time 3 10 36 ns t 4 clk slew rate 1 C v/ns sclk slew rate 1 C v/ns clk, sclk t 1 t 3 t 4 t 2
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-12 speci?cations table 7.16 and figure 7.9 provide reset input data. figure 7.9 reset input table 7.16 reset input symbol parameter min max units t 1 reset pulse width 10 C t clk t 2 reset deasserted setup to clk high 0 C ns t 3 mem_addr setup time to clk high (for con?guring the mem_addr bus only) 20 C ns t 4 mem_addr hold time from clk high (for con?guring the mem_addr bus only) 20 C ns t 1 t 2 t 3 t 4 clk rst/ mad* *when enabled valid data
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc ac characteristics 7-13 table 7.17 and figure 7.10 provide interrupt output data. figure 7.10 interrupt output table 7.17 interrupt output symbol parameter min max units t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 C clk t 1 t 2 t 3 irq/ clk
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-14 speci?cations 7.4 pci and external memory interface timing diagrams figure 7.11 through figure 7.14 represent signal activity when the LSI53C1510 accesses the pci bus. this section includes timing diagrams for access to four groups of memory con?gurations. the ?rst group applies to target timing . the second group applies to initiator timing . the third group applies to external memory timing . note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. timing diagrams included in this section are: target timing C pci con?guration register read C pci con?guration register write C operating registers/scripts ram read, 32-bit C operating registers/scripts ram write, 32-bit initiator timing C nonburst opcode fetch, 32-bit address and data C burst opcode fetch, 32-bit address and data C back-to-back read, 32-bit address and data C back-to-back write, 32-bit address and data C burst read, 32-bit address and data C burst write, 32-bit address and data external memory timing C edo dram burst read C flash rom normal read only mode C flash rom program/verify mode 7.4.1 target timing table 7.18 through table 7.21 and figure 7.11 through figure 7.14 describe target timing.
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-15 figure 7.11 pci con?guration register read table 7.18 pci con?guration register read symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data out byte enable addr in cmd t 2 in out t 1 t 2 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by system) ad (driven by master-addr; LSI53C1510-data) c_be/ (driven by master) pa r (driven by master-addr; LSI53C1510-data) irdy/ (driven by master) trdy/ (driven by LSI53C1510) stop/ (driven by LSI53C1510) devsel/ (driven by LSI53C1510) idsel (driven by master)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-16 speci?cations figure 7.12 pci con?guration register write table 7.19 pci con?guration register write symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data in byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by master) ad (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C1510) stop/ (driven by LSI53C1510) devsel/ (driven by LSI53C1510) idsel (driven by master) t 1 t 2
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-17 figure 7.13 operating registers/scripts ram read, 32-bit table 7.20 operating registers/scripts ram read, 32-bit symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad (driven by master-addr; c_be/ (driven by master) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C1510) stop/ (driven by LSI53C1510) devsel/ (driven by LSI53C1510) out t 3 in out t 3 LSI53C1510-data) LSI53C1510-data)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-18 speci?cations figure 7.14 operating registers/scripts ram write, 32-bit table 7.21 operating registers/scripts ram write, 32-bit symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns addr in byte enable cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C1510) stop/ (driven by LSI53C1510) devsel/ (driven by LSI53C1510) in t 2 data in t 1 in t 2 t 1
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-19 this page intentionally left blank.
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-20 speci?cations 7.4.2 initiator timing table 7.22 through table 7.27 and figure 7.15 through figure 7.20 describe initiator timing. table 7.22 nonburst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-21 figure 7.15 nonburst opcode fetch, 32-bit address and data clk (driven by system) t 3 t 4 t 1 t 3 t 1 req/ (driven by LSI53C1510) pa r (driven by LSI53C1510)- irdy/ (driven by LSI53C1510) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad (driven by c_be/ (driven by LSI53C1510) t 3 cmd t 2 t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by LSI53C1510) t 5 data in addr out data in addr out byte enable cmd byte enable t 3 t 2 t 2 - addr; target-data) LSI53C1510- addr; target-data)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-22 speci?cations table 7.23 burst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-23 figure 7.16 burst opcode fetch, 32-bit address and data t 3 t 4 t 1 t 3 t 1 clk (driven by system) req/ (driven by pa r (driven by irdy/ (driven by trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad (driven by c_be/ (driven by t 3 cmd t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by data in data in byte enable t 3 t 2 t 2 addr out out in in t 5 t 3 t 2 LSI53C1510) LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-24 speci?cations table 7.24 back-to-back read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-25 figure 7.17 back-to-back read, 32-bit address and data t 4 t 1 t 3 t 1 clk (driven by system) req/ (driven by pa r (driven by irdy/ (driven by trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad (driven by c_be/ (driven by t 3 cmd t 2 t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by t 5 data in addr out data in addr out cmd t 3 t 2 t 2 t 3 be be out in out in LSI53C1510) LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-26 speci?cations table 7.25 back-to-back write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-27 figure 7.18 back-to-back write, 32-bit address and data t 4 t 1 t 3 t 1 clk (driven by system) req/ (driven by pa r (driven by irdy/ (driven by trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 6 t 3 ad (driven by c_be/ (driven by t 3 cmd t 2 gnt/ (driven by arbiter) frame/ (driven by t 5 addr out addr out cmd t 3 t 2 t 2 t 3 be be data out data out t 3 t 3 t 3 LSI53C1510) LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510) LSI53C1510) LSI53C1510) t 1
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-28 speci?cations table 7.26 burst read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-29 figure 7.19 burst read, 32-bit address and data t 1 t 2 clk (driven by system) gpio0_fetch/ (driven by gpio1_master/ (driven by req/ (driven by pa r (driven by irdy/ (driven by trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by c_be/ (driven by t 3 cmd gnt/ (driven by arbiter) frame/ (driven by addr out t 2 be data in out in in LSI53C1510) LSI53C1510) LSI53C1510) LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510) addr; target-data) LSI53C1510- LSI53C1510)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-30 speci?cations table 7.27 burst write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-31 figure 7.20 burst write, 32-bit address and data 7.4.3 external memory timing table 7.28 and figure 7.21 through figure 7.23 describe dram timing parameters. t 1 clk (driven by system) req/ (driven by pa r (driven by irdy/ (driven by trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by c_be/ (driven by t 3 cmd gnt/ (driven by arbiter) frame/ (driven by addr out t 2 be data out data out t 1 t 2 LSI53C1510) LSI53C1510) LSI53C1510) LSI53C1510) LSI53C1510) LSI53C1510)
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-32 speci?cations table 7.28 dram timing parameters (using 50 ns extended data out mode) symbol parameter min max unit taa access from column address 25 C ns tasc common address setup 0 C ns tasr row address setup 0 C ns tcac access time from cas/ C 15 ns tcah column address hold 8 C ns tcas cas/ low 10 10,000 ns tcp cas/ precharge 8 C ns tcpa access time from cas/ high 30 C ns tcrp cas/ to ras/ precharge 5 C ns tcsh ras/ low to cas/ high 40 C ns tdh dram data in hold 8 C ns tds dram data in setup 0 C ns tpc edo page cycle time 25 C ns trac access time for ras/ C 50 ns trad ras/ to column address 9 25 ns trah row address hold 9 C ns tral column address lead time to rising ras/ 25 C ns trasp ras/ low, edo fast page mode 50 100,000 ns trc random access cycle time 90 C ns trcd ras/ to cas/ delay 11 35 ns trp ras/ precharge 30 C ns trsh ras/ hold time (cas/ low to ras/ high) 13 C ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-33 figure 7.21 edo dram burst read 123456 789101112131415 m_clk b_clk d_sel b_ a mem_ra nras ncas noe mem_do b_d wait a0+1 a0 a0+2 a0+3 a0+4 col 0+1 row 0 col 0 col 0+2 col 0+3 col 0+4 d0 d0+1 d0+2 d0+3 d0 d0+1 d0+2 d0+3
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-34 speci?cations figure 7.22 flash rom normal read only mode 1 2 3 4 5 6 7 8 9 1011121314 18 m_clk b_clk d_sel b_ a[31:0] dram_addr mem_ceo/ mem_we/ nwait 15 16 17 22 19 20 21 23 24 25 adr-1 adr-2 adr-1 adr-2 byte_rd_cycle ?ash_cs_dly=0(nom) ?ash_oe_dly=0(nom) adr-1 adr-2 d-1 d-1 [12:0] mem_addr [12:0] mem_oen_testout dram_data [31:0] b_d[31:0]
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pci and external memory interface timing diagrams 7-35 figure 7.23 flash rom program/verify mode 1 2 3 4 5 6 7 8 9 1011121314 18 m_clk b_clk d_sel b_ a[31:0] dram_addr mem_ceo/ mem_we/ nwait 15 16 17 22 19 20 21 23 24 25 adr-1 adr-2 adr-1 adr-2 byte_rd_cycle ?ash_cs_dly ?ash_ce_dly adr-1 adr-2 d-1 d-1 [12:0] mem_addr [12:0] mem_oen_testout dram_data [31:0] b_d[31:0] byte_oe_addr_x
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-36 speci?cations 7.5 scsi timing diagrams table 7.29 through table 7.39 and figure 7.24 through figure 7.28 describe scsi timing data. figure 7.24 initiator asynchronous send table 7.29 initiator asynchronous send symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sack/ asserted 55 C ns t 4 data hold from sreq/ deasserted 20 C ns sreq/ sack/ sd[15:0]/ sdp[1:0]/ t 1 t 2 t 3 t 4 n + 1 n valid n valid n + 1 n + 1
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc scsi timing diagrams 7-37 figure 7.25 initiator asynchronous receive table 7.30 initiator asynchronous receive symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sreq/ asserted 0 C ns t 4 data hold from sack/ asserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 3 t 2 t 1 valid n valid n + 1 n + 1 n t 4 n + 1 n
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-38 speci?cations figure 7.26 target asynchronous send figure 7.27 target asynchronous receive table 7.31 target asynchronous send symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sreq/ asserted 55 C ns t 4 data hold from sack/ asserted 20 C ns table 7.32 target asynchronous receive symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sack/ asserted 0 C ns t 4 data hold from sreq/ deasserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 1 t 2 n + 1 valid n + 1 valid n n t 3 t 4 n n + 1 sreq/ sack/ sd[15:0]/, sdp[1:0]/ n n + 1 t 2 t 1 t 3 t 4 valid n valid n + 1 n + 1 n
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc scsi timing diagrams 7-39 table 7.33 scsi-1 transfers (se 5.0 mbytes) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 90 C ns t 2 send sreq/ or sack/ deassertion pulse width 90 C ns t 1 receive sreq/ or sack/ assertion pulse width 90 C ns t 2 receive sreq/ or sack/ deassertion pulse width 90 C ns t 3 send data setup to sreq/ or sack/ asserted 55 C ns t 4 send data hold from sreq/ or sack/ asserted 100 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns table 7.34 scsi-1 transfers (differential 4.17 mbytes) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 96 C ns t 2 send sreq/ or sack/ deassertion pulse width 96 C ns t 1 receive sreq/ or sack/ assertion pulse width 84 C ns t 2 receive sreq/ or sack/deassertion pulse width 84 C ns t 3 send data setup to sreq/ or sack/ asserted 65 C ns t 4 send data hold from sreq/ or sack/ asserted 110 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-40 speci?cations table 7.35 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 45 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns table 7.36 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 50 mhz clock 1 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. symbol parameter 2 2. note: for fast scsi, set the tolerant enable bit (bit 7 in stest3). min max unit t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 40 3 3. analysis of system con?guration is recommended due to reduced driver skew margin in differential systems. Cns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc scsi timing diagrams 7-41 table 7.37 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 1 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. symbol parameter 2 2. note: for fast scsi, set the tolerant enable bit (bit 7 in stest3). during ultra scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. min max unit t 1 send sreq/ or sack/ assertion pulse width 16 C ns t 2 send sreq/ or sack/ deassertion pulse width 16 C ns t 1 receive sreq/ or sack/ assertion pulse width 10 C ns t 2 receive sreq/ or sack/ deassertion pulse width 10 C ns t 3 send data setup to sreq/ or sack/ asserted 12 C ns t 4 send data hold from sreq/ or sack/ asserted 17 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 6 C ns table 7.38 ultra scsi hvd transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) 80 mhz clock 1 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. symbol parameter 2 2. during ultra scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. min max unit t 1 send sreq/ or sack/ assertion pulse width 16 C ns t 2 send sreq/ or sack/ deassertion pulse width 16 C ns t 1 receive sreq/ or sack/ assertion pulse width 10 C ns t 2 receive sreq/ or sack/ deassertion pulse width 10 C ns t 3 send data setup to sreq/ or sack/ asserted 16 C ns t 4 send data hold from sreq/ or sack/ asserted 21 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 6 C ns
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-42 speci?cations figure 7.28 initiator and target synchronous transfer table 7.39 ultra2 scsi transfers 40.0 mbytes (8-bit transfers) or 80.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 1 1. transfer period bits (bits [7:5] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set . symbol parameter 2 2. during ultra2 scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. min max unit t 1 send sreq/ or sack/ assertion pulse width 8 C ns t 2 send sreq/ or sack/ deassertion pulse width 8 C ns t 1 receive sreq/ or sack/ assertion pulse width 6.5 C ns t 2 receive sreq/ or sack/ deassertion pulse width 6.5 C ns t 3 send data setup to sreq/ or sack/ asserted 9.5 C ns t 4 send data hold from sreq/ or sack/ asserted 9.5 C ns t 5 receive data setup to sreq/ or sack/ asserted 3.5 C ns t 6 receive data hold from sreq/ or sack/ asserted 3.5 C ns sreq/ or sack/ send data sd[15:0]/, sdp[1:0]/ receive data sd[15:0]/, sdp[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 n n + 1 valid n valid n + 1 valid n valid n + 1
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pinouts and packaging 7-43 7.6 pinouts and packaging figure 7.29 is pinout information for the LSI53C1510 388 bga chip package. table 7.40 provides the 388 bga pin list by location and table 7.41 provides the same pin list alphabetically. figure 7.30 illustrates the signal locations on the LSI53C1510 388 bga. figure 7.31 is the package drawing for the LSI53C1510.
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-44 speci?cations figure 7.29 left half of the LSI53C1510 388 bga chip - top view 12345678910111213 av ss v ss dram_ add1 dram_oe/ dram_ casfb_a v dd core3 dram_ cas5/ dram_ cas3/ dram_ ras1/ dram_ par2 dram_ data0 dram_ data17 dram_ data3 a b dram_ add5 v ss dram_ add3 dram_we/ dram_ ras2/ dram_ cas0/ dram_ cas2/ dram_ ras0/ v ss core3 dram_ par1 dram_ data1 dram_ data18 dram_ data6 b c dram_ add8 dram_ add7 v ss dram_ add4 dram_ add2 dram_ ras3/ dram_ casfb_b dram_ cas1/ dram_ cas7/ dram_ par0 dram_ data16 dram_ data2 dram_ data4 c d dram_ add11 dram_ add10 dram_ add6 v ss dram_ add0 v dd dram_ cas4/ dram_ cas6/ v ss dram_ par3 v dd dram_ data19 dram_ data20 d e mem_ add0 test_ dramclk dram_ add12 dram_ add9 e f mem_ add3 mem_ add2 mem_ add4 v dd f g mem_ add6 mem_ add5 mem_ add7 mem_ add1 g h mem_ add9 mem_ add8 mem_ add10 v dd core4 h j mem_ add11 mem_ add12 mo3/_ testout v ss j k mem_ce0/ mem_ce1/ mem_ce2/ mce2_rd/ k lv ss core4 mce2_wr/ mem_ data0 v dd v ss v ss v ss l m mem_we/ mem_ data1 mem_ data4 mem_ data6 v ss v ss v ss m n mem_ data2 mem_ data3 mem_ data7 v ss v ss v ss v ss n p scan_ tri_e/ mem_ data5 scan_ ram_e/ testin v ss v ss v ss p r scanmode scan_ rst_e/ scan_e/ scan_test _clk_e/ v ss v ss v ss r t pme nc power_ fail v dd v ss v ss v ss t u b_gpio1 b_gpio0 b_gpio2 v ss core5 u v b_gpio3 v dd core5 b_sd11+/ v ss v w b_sd11 - / b_gpio4 b_sd9 - / b_sd10+/ w y b_sd9+/ b_sd10 - / b_si_o - / b_sd8+/ y aa b_sd8 - / b_si_o+/ b_sc_d+/ v dd aa ab b_sreq+/ b_sreq - / b_smsg - / b_ssel - / ab ac b_sc_d - / b_ssel+/ b_srst - /v ss b_satn+/ v dd b_sd7+/ b_sd3 - /v ss b_sd15+/ v dd b_diffsens v ss ac ad b_smsg+/ b_srst+/ v ss b_sack - / b_rbias- b_sd6 - / b_sd4+/ b_sd2+/ b_sd1 - / b_sdp1+/ b_sd14 - / b_sd12 - / sclk ad ae v ss v ss b_sbsy+/ b_satn - / b_sdp0+/ b_sd7 - / b_sd5+/ b_sd4 - / b_sd1+/ b_sd0 - / b_sd15 - / b_sd13+/ b_sd12+/ ae af v ss b_sack+/ b_sbsy - / b_rbias+ b_sdp0-/ b_sd6+/ b_sd5 - / b_sd3+/ b_sd2 - / b_sd0+/ b_sdp1 - / b_sd14+/ b_sd13 - /af 12345678910111213
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pinouts and packaging 7-45 figure 7.29 right half of the LSI53C1510 388 bga chip - top view (cont.) 14 15 16 17 18 19 20 21 22 23 24 25 26 a dram_ data23 dram_ data9 dram_ data26 dram_ data12 dram_ data29 dram_ data15 pci_ad0 pci_ad3 pci_ad6 c_be0 pci_ad10 pci_ad13 v ss a b dram_ data7 dram_ data8 dram_ data25 dram_ data27 dram_ data13 dram_ data31 pci_ad1 pci_ad4 pci_ad7 pci_ad8 pci_ad11 v ss v ss b c dram_ data5 dram_ data22 dram_ data24 dram_ data11 dram_ data28 dram_ data14 v dd core2 pci_ad2 v ss core2 pci_ad12 v ss pci_ad15 par c dv ss dram_ data21 v dd dram_ data10 v ss dram_ data30 pci_ad5 v dd pci_ad9 v ss pci_ad14 peer/ stop/ d e serr/ c_be1 trdy/ irdy/ e f v dd devsel/ clk v ss core1 f g c_be2 frame/ pci_ad18 pci_ad17 g h pci_ad19 pci_ad16 pci_ad22 pci_ad20 h j v ss pci_ad21 pci_ad23 v dd core1 j k pci_ad25 idsel pci_ad24 c_be3 k lv ss v ss v ss v dd pci_ad27 pci_ad28 pci_ad26 l mv ss v ss v ss gnt/ pci_ad30 pci_ad31 pci_ad29 m nv ss v ss v ss intb rst/ xint req/ n pv ss v ss v ss v ss inta rxt tdo p rv ss v ss v ss v ss core0 txt trst tdi r tv ss v ss v ss v dd tms tck arm_ trst t u arm_tms arm_tdo v dd core0 a_gpio0 u v v ss a_gpio1 a_gpio2 a_gpio3 v w a_sd12+/ a_gpio4 a_sd13+/ a_sd12 - /w y a_sdp1 - / a_sd13 - / a_sd14 - / a_sd14+/ y aa v dd a_sd15+/ a_sdp1+/ a_sd15 - /aa ab a_sd2 - / a_sd1+/ a_sd0 - / a_sd0+/ ab ac test_hsc v dd _a v dd a_sd8+/ v ss a_smsg - / a_sack - /v dd a_sd7+/ v ss a_sd4+/ a_sd2+/ a_sd1 - /ac ad a_diffsens a_sd10 - / a_sd9+/ a_sreq - / a_ssel - / a_srst+/ a_sbsy+/ a_sdp0 - / a_sd6+/ a_sd5+/ v ss a_sd3 - / a_sd3+/ ad ae v ss _a a_sd11+/ a_sd9 - / a_si_o - / a_sreq+/ a_sc_d+/ a_smsg+/ a_sbsy - / a_satn+/ a_sd7 - / a_sd5 - /v ss a_sd4 - /ae af a_sd11 - / a_sd10+/ a_sd8 - / a_si_o+/ a_sc_d-/ a_ssel+/ a_srst - / a_sack+/ a_satn - / a_sdp0+/ a_sd6 - /v ss v ss af 14 15 16 17 18 19 20 21 22 23 24 25 26
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-46 speci?cations table 7.40 signal names and bga position vss a1 vss a2 dram_addr1 a3 dram_oe/ a4 dram_casfb_a a5 vddcore3 a6 dram_cas5/ a7 dram_cas3/ a8 dram_ras1/ a9 dram_par2 a10 dram_data0 a11 dram_data17 a12 dram_data3 a13 dram_data23 a14 dram_data9 a15 dram_data26 a16 dram_data12 a17 dram_data29 a18 dram_data15 a19 pci_ad0 a20 pci_ad3 a21 pci_ad6 a22 c_be0 a23 pci_ad10 a24 pci_ad13 a25 vss a26 dram_addr5 b1 vss b2 dram_addr3 b3 dram_we/ b4 dram_ras2/ b5 dram_cas0/ b6 dram_cas2/ b7 dram_ras0/ b8 vsscore3 b9 dram_par1 b10 dram_data1 b11 dram_data18 b12 dram_data6 b13 dram_data7 b14 dram_data8 b15 dram_data25 b16 dram_data27 b17 dram_data13 b18 dram_data31 b19 pci_ad1 b20 pci_ad4 b21 pci_ad7 b22 pci_ad8 b23 pci_ad11 b24 vss b25 vss b26 dram_addr8 c1 dram_addr7 c2 vss c3 dram_addr4 c4 dram_addr2 c5 dram_ras3/ c6 dram_casfb_b c7 dram_cas1/ c8 dram_cas7/ c9 dram_par0 c10 dram_data16 c11 dram_data2 c12 dram_data4 c13 dram_data5 c14 dram_data22 c15 dram_data24 c16 dram_data11 c17 dram_data28 c18 dram_data14 c19 vddcore2 c20 pci_ad2 c21 vsscore2 c22 pci_ad12 c23 vss c24 pci_ad15 c25 par c26 dram_addr11 d1 dram_addr10 d2 dram_addr6 d3 vss d4 dram_addr0 d5 vdd d6 dram_cas4/ d7 dram_cas6/ d8 vss d9 dram_par3 d10 vdd d11 dram_data19 d12 dram_data20 d13 vss d14 dram_data21 d15 vdd d16 dram_data10 d17 vss d18 dram_data30 d19 pci_ad5 d20 vdd d21 pci_ad9 d22 vss d23 pci_ad14 d24 perr/ d25 stop/ d26 mem_addr0 e1 test_dramclk e2 dram_addr12 e3 dram_addr9 e4 serr/ e23 c_be1 e24 trdy/ e25 irdy/ e26 mem_addr3 f1 mem_addr2 f2 mem_addr4 f3 vdd f4 vdd f23 devsel/ f24 clk f25 vsscore1 f26 mem_addr6 g1 mem_addr5 g2 mem_addr7 g3 mem_addr1 g4 c_be2 g23 frame/ g24 pci_ad18 g25 pci_ad17 g26 mem_addr9 h1 mem_addr8 h2 mem_addr10 h3 vddcore4 h4 pci_ad19 h23 pci_ad16 h24 pci_ad22 h25 pci_ad20 h26 mem_addr11 j1 mem_addr12 j2 moe/_testout j3 vss j4 vss j23 pci_ad21 j24 pci_ad23 j25 vddcore1 j26 mem_ce0/ k1 mem_ce1/ k2 mem_ce2/ k3 mce2_rd/ k4 pci_ad25 k23 idsel k24 pci_ad24 k25 c_be3 k26 vsscore4 l1 mce2_wr/ l2 mem_data0 l3 vdd l4 vss l11 vss l12 vss l13 vss l14 vss l15 vss l16 vdd l23 pci_ad27 l24 pci_ad28 l25 pci_ad26 l26 mem_we/ m1 mem_data1 m2 mem_data4 m3 mem_data6 m4 vss m11 vss m12 vss m13 vss m14 vss m15 vss m16 gnt/ m23 pci_ad30 m24 pci_ad31 m25 pci_ad29 m26 mem_data2 n1 mem_data3 n2 mem_data7 n3 vss n4 vss n11 vss n12 vss n13 vss n14 vss n15 vss n16 intb n23 rst/ n24 xint n25 req/ n26 scan_tri_en p1 mem_data5 p2 scan_ram_en p3 testin p4 vss p11 vss p12 vss p13 vss p14 vss p15 vss p16 vss p23 inta p24 rxt p25 tdo p26 scanmode r1 scan_rst_en r2 scan_en r3 scan_tst_clk_en r4 vss r11 vss r12 vss r13 vss r14 vss r15 vss r16 vsscore0 r23 txt r24 trst/ r25 tdi r26 pme t1 nc t2 power_fail/ t3 vdd t4 vss t11 vss t12 vss t13 vss t14 vss t15 vss t16 vdd t23 tms t24 tck t25 arm_trst/ t26 b_gpio1 u1 b_gpio0 u2 b_gpio2 u3 vsscore5 u4 arm_tms u23 arm_tdo u24 vddcore0 u25 a_gpio0 u26 b_gpio3 v1 vddcore5 v2 b_sd11+/ v3 vss v4 vss v23 a_gpio1 v24 a_gpio2 v25 a_gpio3 v26 b_sd11 - /w1 b_gpio4 w2 s_sd9 - /w3 b_sd10+/ w4 a_sd12+/ w23 a_gpio4 w24 a_sd13+/ w25 a_sd12 - / w26 b_sd9+/ y1 b_sd10 - /y2 b_si_o - /y3 b_sd8+/ y4 a_sdp - / y23 a_sd13 - / y24 a_sd14 - / y25 a_sd14+/ y26 b_sd8 - / aa1 b_si_o+/ aa2 b_sc_d+/ aa3 vdd aa4 vdd aa23 a_sd15+/ aa24 a_sdp1+/ aa25 a_sd15 - / aa26 b_sreq+/ ab1 b_sreq - / ab2 b_smsg - / ab3 b_ssel - / ab4 a_sd2 - / ab23 a_sd1+/ ab24 a_sd0 - / ab25 a_sd0+/ ab26 b_sc_d - /ac1 b_ssel+/ ac2 b_srst - /ac3 vss ac4 b_satn+/ ac5 vdd ac6 b_sd7+/ ac7 b_sd3 - /ac8 vss ac9 b_sd15+/ ac10 vdd ac11 b_diffsens ac12 vss ac13 test_hsc ac14 vdd-a ac15 vdd ac16 a_sd8+/ ac17 vss ac18 a_smsg - / ac19 a_sack - / ac20 vdd ac21 a_sd7+/ ac22 vss ac23 a_sd4+/ ac24 a_sd2+/ ac25 a_sd1 - / ac26 b_smsg+/ ad1 b_srst+/ ad2 vss ad3 b_sack - / ad4 b_rbias - ad5 b_sd6 - / ad6 b_sd4+/ ad7 b_sd2+/ ad8 b_sd1 - / ad9 b_sdp1+/ ad10 b_sd14 - / ad11 b_sd12 - / ad12 sclk ad13 a_diffsens ad14 a_sd10 - / ad15 a_sd9+/ ad16 a_sreq - / ad17 a_ssel - / ad18 a_srst+/ ad19 a_sbsy+/ ad20 a_sdp0 - / ad21 a_sd6+/ ad22 a_sd5+/ ad23 vss ad24 a_sd3 - / ad25 a_sd3+/ ad26 vss ae1 vss ae2 b_sbsy+/ ae3 b_satn - / ae4 b_sdp0+/ ae5 b_sd7 - / ae6 b_sd5+/ ae7 b_sd4 - / ae8 b_sd1+/ ae9 b_sd0 - / ae10 b_sd15 - / ae11 b_sd13+/ ae12 b_sd12+/ ae13 vss-a ae14 a_sd11+/ ae15 a_sd9 - / ae16 a_si_o - / ae17 a_sreq+/ ae18 a_sc_d+/ ae19 a_smsg+/ ae20 a_sbsy - / ae21 a_satn+/ ae22 a_sd7 - / ae23 a_sd5 - / ae24 vss ae25 a_sd4 - / ae26 vss af1 b_sack+/ af2 b_sbsy - / af3 b_rbias+ af4 b_sdp0 - / af5 b_sd6+/ af6 b_sd5 - / af7 b_sd3+/ af8 b_sd2 - / af9 b_sd0+/ af10 b_sdp1 - / af11 b_sd14+/ af12 b_sd13 - / af13 a_sd11 - / af14 a_sd10+/ af15 a_sd8 - / af16 a_si_o+/ af17 a_sc_d - / af18 a_ssel+/ af19 a_srst - / af20 a_sack+/ af21 a_satn - / af22 a_sdp0+/ af23 a_sd6 - / af24 vss af25 vss af26 signal bga name pos signal bga name pos signal bga name pos signal bga name pos signal bga name pos
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pinouts and packaging 7-47 table 7.41 signal names by bga position a_sack - / ac20 a_sack+/ af21 a_satn - / af22 a_satn+/ ae22 a_sbsy - / ae21 a_sbsy+/ ad20 a_sc_d - / af18 a_sc_d+/ ae19 a_diffsens ad14 a_gpio0 u26 a_gpio1 v24 a_gpio2 v25 a_gpio3 v26 a_gpio4 w24 a_si_o - / ae17 a_si_o+/ af17 a_smsg - / ac19 a_smsg+/ ae20 a_sreq - / ad17 a_sreq+/ ae18 a_srst - / af20 a_srst+/ ad19 a_sd0 - / ab25 a_sd1 - / ac26 a_sd2 - / ab23 a_sd3 - / ad25 a_sd4 - / ae26 a_sd5 - / ae24 a_sd6 - / af24 a_sd7 - / ae23 a_sd8 - / af16 a_sd9 - / ae16 a_sd10 - / ad15 a_sd11 - / af14 a_sd12 - / w26 a_sd13 - / y24 a_sd14 - / y25 a_sd15 - / aa26 a_sd0+/ ab26 a_sd1+/ ab24 a_sd2+/ ac25 a_sd3+/ ad26 a_sd4+/ ac24 a_sd5+/ ad23 a_sd6+/ ad22 a_sd7+/ ac22 a_sd8+/ ac17 a_sd9+/ ad16 a_sd10+/ af15 a_sd11+/ ae15 a_sd12+/ w23 a_sd13+/ w25 a_sd14+/ y26 a_sd15+/ aa24 a_sdp0 - / ad21 a_sdp1 - / y23 a_sdp0+/ af23 a_sdp1+/ aa25 a_ssel - / ad18 a_ssel+/ af19 arm_tdo u24 arm_tms u23 arm_trst/ t26 b_sack - / ad4 b_sack+/ af2 b_satn - / ae4 b_satn+/ ac5 b_sbsy - / af3 b_sbsy+/ ae3 b_sc_d - /ac1 b_sc_d+/ aa3 b_diffsens ac12 b_gpio0 u2 b_gpio1 u1 b_gpio2 u3 b_gpio3 v1 b_gpio4 w2 b_si_o - /y3 b_si_o+/ aa2 b_smsg - / ab3 b_smsg+/ ad1 b_rbias - ad5 b_rbias+ af4 b_sreq - / ab2 b_sreq+/ ab1 b_srst - /ac3 b_srst+/ ad2 b_sd0 - / ae10 b_sd1 - / ad9 b_sd2 - / af9 b_sd3 - /ac8 b_sd4 - / ae8 b_sd5 - / af7 b_sd6 - / ad6 b_sd7 - / ae6 b_sd8 - / aa1 b_sd9 - /w3 b_sd10 - /y2 b_sd11 - /w1 b_sd12 - / ad12 b_sd13 - / af13 b_sd14 - / ad11 b_sd15 - / ae11 b_sd0+/ af10 b_sd1+/ ae9 b_sd2+/ ad8 b_sd3+/ af8 b_sd4+/ ad7 b_sd5+/ ae7 b_sd6+/ af6 b_sd7+/ ac7 b_sd8+/ y4 b_sd9+/ y1 b_sd10+/ w4 b_sd11+/ v3 b_sd12+/ ae13 b_sd13+/ ae12 b_sd14+/ af12 b_sd15+/ ac10 b_sdp0 - / af5 b_sdp1 - / af11 b_sdp0+/ ae5 b_sdp1+/ ad10 b_ssel - / ab4 b_ssel+/ ac2 c_be0 a23 c_be1 e24 c_be2 g23 c_be3 k26 clk f25 devsel/ f24 dram_addr0 d5 dram_addr1 a3 dram_addr2 c5 dram_addr3 b3 dram_addr4 c4 dram_addr5 b1 dram_addr6 d3 dram_addr7 c2 dram_addr8 c1 dram_addr9 e4 dram_addr10 d2 dram_addr11 d1 dram_addr12 e3 dram_casfb_a a5 dram_casfb_b c7 dram_cas0/ b6 dram_cas1/ c8 dram_cas2/ b7 dram_cas3/ a8 dram_cas4/ d7 dram_cas5/ a7 dram_cas6/ d8 dram_cas7/ c9 dram_data0 a11 dram_data1 b11 dram_data2 c12 dram_data3 a13 dram_data4 c13 dram_data5 c14 dram_data6 b13 dram_data7 b14 dram_data8 b15 dram_data9 a15 dram_data10 d17 dram_data11 c17 dram_data12 a17 dram_data13 b18 dram_data14 c19 dram_data15 a19 dram_data16 c11 dram_data17 a12 dram_data18 b12 dram_data19 d12 dram_data20 d13 dram_data21 d15 dram_data22 c15 dram_data23 a14 dram_data24 c16 dram_data25 b16 dram_data26 a16 dram_data27 b17 dram_data28 c18 dram_data29 a18 dram_data30 d19 dram_data31 b19 dram_oe/ a4 dram_par0 c10 dram_par1 b10 dram_par2 a10 dram_par3 d10 dram_ras0/ b8 dram_ras1/ a9 dram_ras2/ b5 dram_ras3/ c6 dram_we/ b4 frame/ g24 gnt/ m23 idsel k24 inta p24 intb n23 irdy/ e26 mce2_rd/ k4 mce2_wr/ l2 mem_addr0 e1 mem_addr1 g4 mem_addr2 f2 mem_addr3 f1 mem_addr4 f3 mem_addr5 g2 mem_addr6 g1 mem_addr7 g3 mem_addr8 h2 mem_addr9 h1 mem_addr10 h3 mem_addr11 j1 mem_addr12 j2 mem_ce0/ k1 mem_ce1/ k2 mem_ce2/ k3 mem_data0 l3 mem_data1 m2 mem_data2 n1 mem_data3 n2 mem_data4 m3 mem_data5 p2 mem_data6 m4 mem_data7 n3 mem_we/ m1 moe/_testout j3 nc t2 par c26 pci_ad0 a20 pci_ad1 b20 pci_ad2 c21 pci_ad3 a21 pci_ad4 b21 pci_ad5 d20 pci_ad6 a22 pci_ad7 b22 pci_ad8 b23 pci_ad9 d22 pci_ad10 a24 pci_ad11 b24 pci_ad12 c23 pci_ad13 a25 pci_ad14 d24 pci_ad15 c25 pci_ad16 h24 pci_ad17 g26 pci_ad18 g25 pci_ad19 h23 pci_ad20 h26 pci_ad21 j24 pci_ad22 h25 pci_ad23 j25 pci_ad24 k25 pci_ad25 k23 pci_ad26 l26 pci_ad27 l24 pci_ad28 l25 pci_ad29 m26 pci_ad30 m24 pci_ad31 m25 perr/ d25 pme t1 power_fail/ t3 req/ n26 rst/ n24 rxt p25 scan_en r3 scan_ram_en p3 scan_rst_en r2 scan_tst_clk_en r4 scan_tri_en p1 scanmode r1 sclk ad13 serr/ e23 stop/ d26 tck t25 tdi r26 tdo p26 test_dramclk e2 test_hsc ac14 testin p4 tms t24 trdy/ e25 trst/ r25 txt r24 vdd d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd l4 vdd l23 vdd t4 vdd t23 vdd aa4 vdd aa23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd-a ac15 vddcore0 u25 vddcore1 j26 vddcore2 c20 vddcore3 a6 vddcore4 h4 vddcore5 v2 vss a1 vss a2 vss a26 vss b2 vss b25 vss b26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d18 vss d23 vss j4 vss j23 vss l11 vss l12 vss l13 vss l14 vss l15 vss l16 vss m11 vss m12 vss m13 vss m14 vss m15 vss m16 vss n4 vss n11 vss n12 vss n13 vss n14 vss n15 vss n16 vss p11 vss p12 vss p13 vss p14 vss p15 vss p16 vss p23 vss r11 vss r12 vss r13 vss r14 vss r15 vss r16 vss t11 vss t12 vss t13 vss t14 vss t15 vss t16 vss v4 vss v23 vss ac4 vss ac9 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1 vss ae2 vss ae25 vss af1 vss af25 vss af26 vss-a ae14 vsscore0 r23 vsscore1 f26 vsscore2 c22 vsscore3 b9 vsscore4 l1 vsscore5 u4 xint n25 signal bga name pos signal bga name pos signal bga name pos signal bga name pos signal bga name pos
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-48 speci?cations figure 7.30 LSI53C1510 388 ball grid array
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc pinouts and packaging 7-49 figure 7.31 388 pbga (ii) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ii. md97.ii
3.75 pc 10.25 pc 11.25 pc 38.25 pc 4.333 pc 48.583 pc 52.5 pc 34.5 pc 44.25 pc 7-50 speci?cations
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller a-1 appendix a register summary table a.1 lists the LSI53C1510 pci registers (nonintelligent mode) by register name. table a.1 LSI53C1510 pci registers (nonintelligent mode) register map register name address read/write page base address register one (memory) 0x14C0x17 read/write 5-18 base address register two (scripts ram) 0x18C0x1b read/write 5-18 base address register zero (i/o) 0x10C0x13 read/write 5-17 bridge support extensions 0x46 read only 5-26 cache line size 0x0c read/write 5-15 capabilities pointer 0x34 read only 5-21 capability id 0x40 read only 5-23 class code 0x09C0x0b read only 5-15 command 0x02C0x03 read/write 5-11 data 0x47 read only 5-26 device id 0x02C0x03 read only 5-11 expansion rom base address 0x30C0x33 read/write 5-20 header type 0x0e read only 5-17 interrupt line 0x3c read/write 5-22 interrupt pin 0x3d read only 5-22 latency timer 0x0d read/write 5-16 max_lat 0x3f read only 5-23
a-2 register summary table a.2 lists the LSI53C1510 pci registers (intelligent mode) registers by register name. min_gnt 0x3e read only 5-23 next item pointer 0x41 read only 5-24 not supported 0x0f C 5-17 power management capabilities 0x42C0x43 read only 5-24 power management control/status 0x44C0x45 read/write 5-25 reserved 0x1cC0x2b C 5-18 reserved 0x35C0x3b C 5-21 revision id (rev id) 0x08 read only 5-15 status 0x06C0x07 read/write 5-13 subsystem id 0x2eC0x2f read only 5-20 subsystem vendor id 0x2cC0x2d read only 5-19 vendor id 0x00C0x01 read only 5-11 table a.1 LSI53C1510 pci registers (nonintelligent mode) register map (cont.) register name address read/write page table a.2 LSI53C1510 pci registers (intelligent mode) register map register name address read/write page base address register one (shared memory) 0x14C0x17 read/write 6-12 base address register zero (i/o) 0x10C0x13 read/write 6-11 bist (built-in self test) 0x0f read/write 6-11 bridge support extensions (pmcsr_bse) 0x46 read only 6-18 cache line size 0x0c read/write 6-9 capabilities pointer 0x34 read only 6-14 capability id 0x40 read only 6-16 class code 0x09C0x0b read only 6-9 command 0x04C0x05 read/write 6-5
register summary a-3 data 0x47 read only 6-18 device id 0x02C0x03 read only 6-5 expansion rom base address 0x30C0x33 read/write 6-13 header type 0x0e read only 6-10 interrupt line 0x3c read/write 6-14 interrupt pin 0x3d read only 6-15 latency timer 0x0d read/write 6-10 max_lat 0x3f read only 6-15 min_gnt 0x3e read only 6-15 next item pointer 0x41 read only 6-16 power management capabilities (pmc) 0x42C0x43 read only 6-16 power management control/status (pmcsr) 0x44C0x45 read/write 6-17 reserved 0x18C0x2b C 6-12 reserved 0x35C0x3b C 6-14 revision id (rev id) 0x08 read only 6-8 status 0x06C0x07 read/write 6-7 subsystem id 0x2eC0x2f read only 6-13 subsystem vendor id 0x2cC0x2d read only 6-12 vendor id 0x00C0x01 read only 6-5 table a.2 LSI53C1510 pci registers (intelligent mode) register map (cont.) register name address read/write page
a-4 register summary table a.3 lists the LSI53C1510 host interface registers (intelligent mode) by register name. table a.3 LSI53C1510 host interface registers (intelligent mode) register name address read/write page data 0x08 read/write 6-18 diagint 0x00 read/write 6-20 host doorbell 0x20 read/write 6-24 reply interrupt mask 0x34 read/write 6-25 reply interrupt status 0x30 read only 6-25 test base address 0x0c read/write 6-23 wrseq 0x04 write only 6-21
LSI53C1510 i 2 o-ready pci raid ultra2 scsi controller ix-1 index symbols (baro[31:0]) 6-12 (bart[31:0]) 5-18 (barz[31:0]) 5-17 , 6-11 (bse[7:0]) 5-27 , 6-18 (cc) 5-15 (cc[23:0]) 6-9 (cid[7:0]) 5-24 , 6-16 (cls) 5-15 (cls[7:0]) 6-9 (cp[7:0]) 5-22 , 6-14 (d1s) 5-25 , 6-17 (d2s) 5-25 , 6-17 (data[7:0]) 5-27 , 6-18 (did[15:0]) 5-11 , 6-5 (dpe) 5-13 , 6-7 (dpr) 5-14 , 6-8 (dscl[1:0]) 5-26 , 6-17 (dsi) 5-25 , 6-17 (dslt) 5-26 , 6-17 (dt) 5-13 , 6-8 (ebm) 5-12 , 6-6 (eis) 5-12 , 6-6 (ems) 5-12 , 6-6 (eper) 5-12 , 6-6 (erba[31:0]) 5-20 , 6-13 (ht) 5-17 (ht[7:0]) 6-10 (i/o) 6-11 (il[7:0]) 5-23 , 6-14 (ip[7:0]) 5-23 , 6-15 (lt) 5-16 (lt[7:0]) 6-10 (memory) 6-12 (mg[7:0]) 5-24 , 6-15 (ml[7:0]) 5-24 , 6-15 (nc) 5-14 , 6-8 (nip[7:0]) 5-25 , 6-16 (pen) 5-26 , 6-17 (pmc) 6-16 (pmcsr) 6-17 (pmcsr_bse) 6-18 (pmec) 5-26 , 6-17 (pmes[4:0]) 5-25 , 6-16 (pst) 5-26 , 6-17 (pws[1:0]) 5-26 , 6-18 (rid) 5-15 (rid[7:0]) 6-8 (rma) 5-13 , 6-7 (rta) 5-13 , 6-7 (se) 6-6 (sid[15:0]) 5-20 , 6-13 (sse) 5-13 , 6-7 (ver[2:0]) 5-26 , 6-17 (wie) 5-12 , 6-6 a a general purpose i/o 4-9 a_gpio[4:0] 4-9 absolute maximum stress ratings 7-2 ac characteristics 7-11 address and data signals 4-5 address/data bus 5-4 advanced scsi protocol interface 1-4 applications 1-11 arbitration signals 4-7 arm test data output 4-19 arm test mode select 4-19 arm test reset 4-19 arm_tdo 4-19 arm_tms 4-19 arm_trst/ 4-19 arm7tdmi 1-1 arm7tdmi risc processor 1-4 benefits 1-8 aspi 1-4 b b general purpose i/o 4-9 b_gpio[4:0] 4-9 back-to-back read 32-bit address and data 7-24 back-to-back write 32-bit address and data 7-26 base address 5-1 base address register one 5-4 two 5-4 zero 6-12 zero - i/o (barz[31:0]) 5-17 , 6-11 battery backed up sram 1-3 battery backup support and cache recovery 3-8 bidirectional signals 7-5 bios 1-4 , 5-3 bit 1 disarm (disable arm core) 6-22 bridge support extensions (bse[7:0]) 5-27 , 6-18 bsablockread 2-17 bsablockreassign 2-17 bsablockwrite 2-17
ix-2 index bsablockwriteverify 2-17 bsacacheflush 2-17 bsadevicereset 2-17 bsamediaformat 2-17 bsamediaverify 2-17 bsapowermgt 2-17 bsastatuscheck 2-17 burst opcode fetch 32-bits address and data 7-22 burst read 32-bits address and data 7-28 burst write 32-bits address and data 7-30 bus command and byte enables 4-5 c c_be/[3:0] 4-5 , 5-3 , 5-4 , 5-5 cache line size 5-15 (cls[7:0]) 6-9 caching 3-5 cap_id (cid[7:0]) 5-24 , 6-16 capabilities pointer (cp[7:0]) 5-22 , 6-14 cd-rom 1-4 clk 4-4 clock 4-4 column address strobe feedback 4-17 command configuration read command 5-6 configuration write command 5-7 dac command 5-7 i/o read command 5-6 i/o write command 5-6 interrupt acknowledge 5-5 memory read command 5-6 memory read line command 5-7 memory read multiple command 5-7 memory write and invalidate command 5-8 memory write command 5-6 reserved command 5-6 special cycle command 5-6 configuration and initialization 2-4 options 2-5 read command 5-6 space 5-3 write command 5-7 current function of input voltage 7-9 function of output voltage 7-10 cycle frame 4-6 d d1_support (d1s) 5-25 , 6-17 d2_support (d2s) 5-25 , 6-17 dac 1-3 dac command 5-7 data (data[7:0]) 5-27 , 6-18 parity error reported 5-14 , 6-8 data_scale (dscl[1:0]) 5-26 , 6-17 data_select 5-26 , 6-17 dc characteristics 7-1 detected parity error (from slave) (dpe) 5-13 , 6-7 device id (did[15:0]) 6-5 select 4-6 specific initialization (dsi) 5-25 , 6-17 devsel/ 4-6 timing 5-13 , 6-8 diagint/clrint (diagnostic interrupt (read)/ clear interrupt (write)) 6-20 diffsens scsi signals 7-4 disk array 3-4 dma channel 2-9 engine 2-1 unit 2-3 dmmap (diagnostic memory map) 6-23 dram 1-3 , 2-12 , 2-18 column address strobe 4-17 column address strobe feedback 4-17 data 4-17 data parity 4-17 memory 2-19 memory addresses 4-17 output enable 4-17 row address strobe 4-17 timing parameters 7-32 write enable 4-17 dram_addr[12:0] 4-17 dram_cas[7:0]/ 4-17 dram_casfb_a 4-17 dram_casfb_b 4-17 dram_data[31:0] 4-17 dram_oe/ 4-17 dram_par[3:0] 4-17 dram_ras[3:0]/ 4-17 dram_we/ 4-17 drive hot swap 3-7 dual address cycle (dac) 1-3 dwe (diag register write enabled) (read only) 6-22 dword 2-9 dynamic capacity expansion 3-7 dynamic raid migration (drm) 3-7 e edo dram 1-3 , 2-4 , 2-19 , 3-9 embedded motherboard application 1-11 enable bus mastering (ebm) 5-12 , 6-6 i/o space (eis) 5-12 , 6-6 memory space (ems) 5-12 , 6-6 parity error response (eper) 5-12 , 6-6 expansion rom base address 6-13 external clock 7-11 interrupt 4-8 external memory interface multiple byte accesses 7-14 timing 7-31 f fast-20 1-6 features list 1-5 fifo 2-9 , 2-12 depth 5-27 flash rom 3-9 flash rom 1-3 , 2-4 , 2-18 , 2-19 , 3-9 frame/ 4-6
index ix-3 g global hot spare drives 3-6 gnt/ 4-7 grant 4-7 h hardware assisted parity calculation 3-6 hardware parity assist engine 1-4 header type 5-17 , 6-10 high power differential 1-6 host adapter board application 1-12 host doorbell 6-24 host interface 2-1 , 2-11 registers 5-1 i i/o processor (iop) 2-4 , 6-1 read command 5-6 space 5-4 write command 5-6 i2o benefits 1-7 , 2-7 communications model 2-8 conceptual overview 2-6 message unit 1-3 messages 6-1 overview 2-6 raid device driver module (ddm) 1-2 raid software 1-2 ready 1-1 , 1-11 idsel 4-6 , 5-3 signal 5-6 initialization 5-4 device select 4-6 initiator asynchronous receive 7-37 asynchronous send 7-36 ready 4-6 synchronous transfer 7-42 timing 7-20 input current as a function of input voltage 7-9 signals 7-6 inta/ 4-7 intb/ 4-7 integration 1-10 intelligent controller 1-4 , 5-1 intelligent input/output 1-1 , 2-1 interface control signals 4-6 internal arbiter 5-9 interrupt a 4-7 acknowledge command 5-5 b 4-7 line 5-23 , 6-14 output 7-13 pin 5-23 (ip[7:0]) 6-15 signals 4-7 irdy/ 4-6 ixworks 1-5 l latch-up protection 1-10 latency 5-8 timer 5-16 (lt[7:0]) 6-10 low voltage differential 1-6 LSI53C1510 benefits 1-5 summary 1-8 features 1-4 modes 2-2 overview 2-3 protocol engine 2-16 overview 2-9 register map a-1 lvd driver scsi signals 7-3 receiver scsi signals 7-3 lvd scsi 1-4 , 1-5 lvdlink benefits 1-6 m management software features 3-3 max_lat (ml[7:0]) 5-24 , 6-15 maximum stress ratings 7-2 mce2_rd/ 4-15 mce2_wr/ 4-15 mem_addr bus 2-4 mem_addr[12:0] 4-15 mem_ce/[2:0] 4-15 mem_data[7:0] 4-15 mem_we/ 4-15 memory 4-15 address 4-15 chip enable 4-15 controller 1-3 data 4-15 read command 5-6 read line command 5-7 read multiple command 5-7 signal 4-15 space 5-4 to memory moves 5-9 write enable 4-15 memory signal 4-15 message frame address (mfa) 2-9 messages 2-11 passing i/o interface 2-1 queuing 2-8 transport 2-11 min_gnt (mg[7:0]) 5-24 , 6-15 modes of operation 2-2 module overviews 1-3 moe/_testout 4-15 moves memory to memory moves 5-9 multiple cache line transfers 5-8 n new capabilities 5-14 (nc) 6-8 next_item_ptr (nip[7:0]) 5-25 , 6-16
ix-4 index nonburst opcode fetch 32-bits address and data 7-20 nonintelligent 1-2 , 1-4 , 6-1 controller 1-4 , 5-1 nvram 3-9 o online dynamic capacity expansion 3-7 raid level migration/reconfiguration 3-7 operating conditions 7-2 register/scripts ram read 32-bit 7-17 register/scripts ram write 32-bit 7-18 operational overview 2-8 osm 2-8 output current as a function of output voltage 7-10 signals 7-5 , 7-6 p packetized 2-1 par 4-5 parity 4-5 assist engine (pae) 1-1 , 2-1 , 2-4 error 4-8 pci addressing 5-3 bus commands and functions supported 5-5 cache line size register 5-8 cache mode 5-9 commands 5-5 configuration cycles 5-3 configuration register map 5-10 configuration register read 7-15 configuration register write 7-16 configuration registers 1-3 , 5-10 , 6-4 configuration space registers 5-3 external memory interface timing diagrams 7-14 functional description (nonintelligent mode) 5-3 i/o space 5-4 interface 1-3 interface registers 5-1 interface signals 4-4 master 1-3 memory space 5-4 performance 1-8 power management 1-3 raid 3-1 software solutions 3-1 slave 1-3 target disconnect 5-9 target retry 5-8 pci_ad[31:0] 4-5 perr/ 4-8 physical dword pci address and data 4-5 pin type description 4-1 pme clock (pmec) 5-26 , 6-17 enable (pen) 5-26 , 6-17 pme/ 4-8 status (pst) 5-26 , 6-17 support (pmes[4:0]) 5-25 , 6-16 power fail 4-19 power management event 4-8 power state (pws[1:0]) 5-26 , 6-18 power_fail/ 4-19 programming models 6-3 protocol engine 2-9 , 2-16 push model 2-9 , 2-15 r raid 1-1 , 1-11 , 3-4 , 6-1 controller 1-2 , 1-5 firmware features 3-3 host adapter 1-2 level 3-4 level 0 3-4 level 1 3-4 level 3 3-5 level 5 3-5 levels 0, 1, 3, 5, and 10 3-4 parity assist engine 1-4 , 2-1 performance 1-9 symplicity 1-5 random block storage class 2-16 read multiple with read line enabled 5-7 receive data 4-18 received master abort (from master) (rma) 5-13 , 6-7 target abort (from master) (rta) 5-13 , 6-7 register differences 5-27 register map a-1 reliability 1-10 reply free 1-3 free list 2-8 message 2-14 post 1-3 post list 2-8 replyint (reply message interrupt) 6-25 replyintmask (reply message interrupt mask) 6-25 req/ 4-7 req/ - gnt/ 5-3 request 4-7 free 1-3 free list 2-8 message 2-12 message frames 2-9 post 1-3 post list 2-8 reserved command 5-6 reset 4-4 input 7-12 revision id 5-15 register (rid[7:0]) 6-8 risc processor 1-1 , 1-4 , 2-1 , 6-1 rise and fall time test condition 7-8 rom size configurations 2-5 rst/ 4-4 rxt 4-18 s scan 3-state enable 4-16 enable 4-16
index ix-5 scan (cont.) mode enable 4-16 ram enable 4-16 reset enable 4-16 test clock enable 4-16 scan_en 4-16 scan_ram_en 4-16 scan_rst_en 4-16 scan_test_clk_en 4-16 scan_tri_en 4-16 scanmode 4-16 scatter/gather 1-9 sclk 4-10 scripts ram 2-3 , 5-1 , 5-4 , 5-27 scsi accessed fault-tolerant enclosure (saf-te) 3-4 , 3-8 clock 4-10 cores 1-4 , 5-1 function a 5-3 function b 5-3 hysteresis of receivers 7-9 input filtering 7-8 interface signals 4-10 performance 1-8 scripts 1-4 , 1-8 timing diagrams 7-36 scsi-1 transfers (differential 4.17 mbytes) 7-39 (single-ended 5.0 mbytes) 7-39 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) 40 mhz clock 7-40 50 mhz clock 7-40 20.0 mbytes (16-bit transfers) 40 mhz clock 7-40 50 mhz clock 7-40 scsi-3 parallel interface 1-6 sdms 1-4 , 3-8 send a reply message 2-14 send a request message 2-13 serial eeprom 2-19 , 3-9 serr/ 4-8 enable (se) 5-12 , 6-6 signal groupings 4-2 signal names and bga position 7-45 , 7-46 by bga position 7-46 signaled system error (sse) 5-13 , 6-7 single-ended scsi 1-6 signals 7-7 slave access and messaging unit 2-3 special cycle command 5-6 sram 1-3 , 2-4 , 2-18 stop/ 4-6 storage manager 1-5 stress ratings 7-2 subsystem id (sid[15:0]) 5-20 , 6-13 subsystem vendor id (svid[15:0]) 5-19 , 6-12 support components 2-18 supported random block storage messages 2-17 symplicity i2o raid 1-5 software 2-16 storage manager 1-2 , 3-2 system error 4-8 interface 2-8 programming model 6-3 signals 4-4 t tagged command queuing 3-6 target asynchronous receive 7-38 asynchronous send 7-38 ready 4-6 synchronous transfer 7-42 timing 7-14 tck 4-18 tdi 4-18 tdo 4-18 test base address 6-23 clock 4-18 data input 4-18 data output 4-18 dram clock 4-19 in 4-18 mode select 4-18 reset 4-18 test_dramclk 4-19 test_hsc 4-19 testability 1-9 testin 4-18 tms 4-18 tolerant technology benefits 1-6 technology electrical characteristics 7-7 transmit data 4-18 trdy/ 4-6 trst/ 4-18 ttl_int (select ttl output for pci-inta/) 6-22 txt 4-18 u ultra scsi high voltage differential transfers 20.0 mbytes (8-bit transfers) 80 mhz clock 7-41 40.0 mbytes (16-bit transfers) 80 mhz clock 7-41 single-ended transfers 20.0 mbytes (8-bit transfers) quadrupled 40 mhz clock 7-41 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 7-41 ultra2 scsi 1-1 , 1-4 , 1-5 , 1-11 benefits 1-5 transfers 40.0 mbytes (8-bit transfers) quadrupled 40 mhz clock 7-42 80.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 7-42
ix-6 index v vdd 4-20 vdd-a 4-20 vendor id (vid[15:0]) 6-5 version (ver[2:0]) 5-26 , 6-17 voltage feed-through protection 1-10 vss 4-20 vss-a 4-20 vss-core 4-20 w wide ultra2 scsi 1-8 , 5-3 wind river system ixworks 1-2 , 1-5 , 3-3 write and invalidate enable (wie) 5-12 , 6-6 x xint 4-8 z zero wait-state 2-1
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (components and boards) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287
sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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