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cmos the mc145003/5004 are 128segment, multiplexedbyfour lcd drivers. the two devices are functionally the same except for their data input proto- cols. the mc145003 uses an spi data input protocol which is directly com- patible with that of the mc6805 family of microcomputers. using a minimal amount of software (see example), the device may be interfaced to the mc68hcxx product families. the mc145004 has a iic interface and has es- sentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eightbit byte is received. mc145004 also has a aread modeo, whereby data sent to the device may be retrieved via the iic bus. the mc145003/mc145004 drives the liquidcrystal displays in a multi- plexedbyfour configuration. the device accepts data from a microproces- sor or other serial data source to drive one segment per bit. the chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. devices are independently addressable via a twowire (or threewire) communication link which can be common with other mc145003/mc145004 and/or other peripheral devices. ? drives 128 segments per package ? devices may be cascaded for larger lcd applications ? may be used with the following lcds: segmented alphanumeric, bar graph, dot matrix, custom ? quiscent supply current: 85 m a @ 2.8 v v dd ? operating voltage range: 2.8 to 5.5 v ? operating temperature range: 40 to 85 c ? separate access to lcd drive section's supply voltage to allow for temperature compensation ? see application notes an1066 and an442 this document contains information on a new product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mc145003/d semiconductor technical data fp32 fp31 fp30 fp29 fp28 fp27 fp26 fp25 fp24 fp23 fp22 fp21 fp20

qfp fu suffix case 848b ordering information mc145003fu qfp MC145004FU qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 pin assignment 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 nc fp19 fp18 fp17 fp16 fp15 fp14 fp13 fp12 fp11 nc v ss v lcd nc osc1 osc2 bp1 bp4 a0 a1 a2 enb nc 39 38 37 36 35 34 33 32 31 30 29 28 27 d in dclk fs fp1 fp2 fp3 fp4 fp5 fp6 fp7 fp8 fp9 fp10 v dd bp2 bp3 nc = no connection 1 52 block diagram 128bit latch fs lcd voltage waveform and timing generator frame sync generator oscillator 128bit shift register osc2 osc1 por drivers drivers 128 32 multiplex data and address control and timing a2 a0 a1 enb dclk d in v lcd bp1bp4 fp1fp32 ? motorola, inc. 1994 rev 1 12/94
mc145003 ? mc145004 motorola 2 absolute maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 0.5 to + 6.5 v v in input voltage, d in , and data clock 0.5 to 15 v v in osc input voltage, osc in of master 0.5 to v dd + 0.5 v i in dc input current, per pin 10 ma t stg storage temperature range 65 to + 150 c * maximum ratings are those values beyond which damage to the device may occur. func- tional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. electrical characteristics (voltages referenced to v ss ) ch i i sbl v dd v lcd 40 c 25 c 85 c ui characteristic symbol v dd v v lcd v min max min max min max unit output drive current e frontplanes v o = 0.15 v i fh i fl 5 5 2.8 2.8 360 360 e e 260 260 e e 240 240 e e m a v o = 2.65 v i fh i fl 5 5 2.8 2.8 320 320 e e 240 240 e e 240 240 e e v o = 1.72 v i fh i fl 5 5 2.8 2.8 95 e e 1.5 40 e e 1.5 60 e e 1 v o = 1.08 v i fh i fl 5 5 2.8 2.8 90 e e 2 40 e e 2 55 e e 1 v o = 0.15 v i fh i fl 5 5 5.5 5.5 600 600 e e 600 600 e e 580 580 e e v o = 5.35 v i fh i fl 5 5 5.5 5.5 490 490 e e 520 520 e e 520 520 e e v o = 3.52 v i fh i fl 5 5 5.5 5.5 100 e e 1.5 35 e e 1.5 50 e e 1 v o = 1.98 v i fh i fl 5 5 5.5 5.5 100 e e 1.5 55 e e 1 70 e e 1 supply currents (f osc ) = 110 khz i dd = quiescent @ i out = 0 m a i lcd = quiescent @ i out = 0 m a i dd = quiescent @ i out = 0 m a i lcd = quiescent @ i out = 0 m a i ddq i lcdq i ddq i lcdq 2.8 e 5.5 e e 2.8 e 5.5 e e e e 65 30 350 60 e e e e 140 45 1050 90 e e e e 85 20 350 35 m a input current i in e e e e 0.1 0.1 e e m a input capacitance c in e e e e e 7.5 e e pf frequencies osc2 frequency @ r1; r1 = 200 k w fs frequency @ r1 fs pulse @ r1 bp frequency @ r1 osc2 frequency @ r2; r2 = 996 k w f osc2 f fs f fs f bp f osc2 5 5 5 5 5 5 5 5 5 5 103 100 4.7 100 22.5 111 110 5 110 24.5 100 100 3.6 100 23 150 140 5.6 140 33 123 120 3.5 120 28 136 133 3.9 133 31 khz hz m s hz khz average dc offset voltage (bp relative to fp) v oo 5 2.8 50 +50 50 +50 50 +50 mv input voltage a0o level v il v il 2.8 5.5 5 5 e e e e e e 0.85 1.65 e e e e v a1o level v ih v ih 2.8 5.5 5 5 e e e e 2 3.85 e e e e e e (continued) this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precau- tions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit.
mc145003 ? mc145004 3 motorola electrical characteristics (continued) ch i i sbl v dd v lcd 40 c 25 c 85 c ui characteristic symbol v dd v v lcd v min max min max min max unit output drive current e backplanes v o = 2.65 v i bh * i bl 5 5 2.8 2.8 290 290 e e 240 240 e e 240 240 e e m a v o = 0.15 v i bh i bl 5 5 2.8 2.8 310 310 e e 260 260 e e 230 230 e e v o = 1.08v i bh i bl 5 5 2.8 2.8 90 e e 1 40 e e 2 55 e e 1 v o = 1.72 v i bh i bl 5 5 2.8 2.8 90 e e 1.5 40 e e 1 60 e e 1 v o = 5.35 v i bh i bl 5 5 5.5 5.5 490 490 e e 520 520 e e 520 520 e e v o = 0.15 v i bh i bl 5 5 5.5 5.5 600 600 e e 600 600 e e 580 580 e e v o = 1.98 v i bh i bl 5 5 5.5 5.5 100 e e 1.5 55 e e 1 70 e e 1 v o = 3.52 v i bh i bl 5 5 5.5 5.5 100 e e 1 35 e e 1 50 e e 1 pulse width, data clock (figure 1) t w 5 3 50 100 e e ns dclk rise/fall time (figure 1) t r , t f 5 3 e e 20 120 m s setup time, d in to dclk (figure 2) t su 5 3 0 0 e e ns hold time, d in to dclk (figure 2) t h 5 3 30 60 e e ns dclk low to enb high (figure 3) t h 5 3 10 20 e e ns enb high to dclk high (figure 3) t rec 5 3 10 20 e e ns enb high pulse width (figure 3) t w 5 3 50 100 e e ns enb low to dclk high (figure 3) t su 5 3 10 20 e e ns note: timing for figures 1, 2, and 3 are design estimates only. * for a time (t = 4/osc freq.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the highcurrent state to allow the load capacitances to charge quickly. the circuit is then returned to the lowcurrent state until the next voltage change. switching waveforms v dd gnd clk 90% 50% 10% t w t w t f t r figure 1. d in clk 50% valid 50% t su t h v dd gnd v dd gnd figure 2. t su t h t rec t w t w v dd gnd v dd gnd clk enb first clk last clk figure 3. 50% 50%
mc145003 ? mc145004 motorola 4 functional description the mc145003/mc145004 has essentially two sections which operate asynchronously from each other; the data input and storage section and the lcd drive section. the lcd drive and timing is derived from the oscillator, while the data input and storage is controlled by the data in (d in ), data clock (dclk), address (a0, a1, a2), and enable (enb ) pins. data is shifted serially into the 128bit shift register and arranged into four consecutive blocks of 32 parallel data bits. a timemultiplex of the four backplane drivers is made (each backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the corresponding block of 32 bits is made available at the front- plane drivers. a high input to a plane driver turns the driver on, and a low input turns the driver off. figure 4 shows the sequence of backplanes. figure 5 shows the possible configurations of the frontplanes relative to the backplanes. when a backplane driver is on, its output switches from v lcd to 0 v, and when it is off, it switches from 1/3 v lcd to 2/3 v lcd . when a frontplane driver is on, its output switches from 0 v to v lcd , and when it is off, it switches from 2/3 v lcd to 1/3 v lcd . the lcd drive and timing section provides the multiplex sig- nals and backplane driver input signals and formats the front- plane and backplane waveforms. it also provides a aframe synco pulse which may be used in a system where many lcd drivers are cascaded, to synchronize the backplanes/front- planes of all participating lcd drivers. the address pins are used in cascaded systems to uniquely distinguish one lcd driver from another (and from any other chips on the same bus) and to define one lcd driver as the amastero in the system. there must be one master in any system. the enable pin may be used as a third control line in the communication bus. it may be used to define the moment when the data is latched. if not used, then the data is latched after 128 bits of data have been received. bp1 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v frame sync pulse v lcd 0 v time frame bp2 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v bp3 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v bp4 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v figure 4. backplane sequence
mc145003 ? mc145004 5 motorola fp data bits 4321 0000 1000 0100 1100 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v frame sync pulse v lcd 0 v time frame v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v 0010 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v 1010 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v 0110 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v fp data bits 4321 0001 1001 v lcd 0 v frame sync pulse v lcd 0 v time frame v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 2/3 (v lcd ) 1/3 (v lcd ) 0101 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 1101 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 0011 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 1011 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 0111 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 1111 v lcd 0 v 2/3 (v lcd ) 1/3 (v lcd ) 1110 v lcd 2/3 (v lcd ) 1/3 (v lcd ) 0 v figure 5. frontplane combinations
mc145003 ? mc145004 motorola 6 pin descriptions a0a2 address inputs (pins 4244) the devices have to receive a correct address before they will accept data. three address pins (a2, a1, a0) are used to define the states of the three programmable bits of mc145003/mc145004's 8bit address. the address is 0111vwxy where v, w, x represent a2, a1, and a0 respectively. where v, w, x = 0, then a2, a1, and a0 should be tied to 0 v. where v, w, x = 1, then a2, a1, and a0 should be tied to v dd . for systems where only one mc145003/mc145004 is used, the address pins must be tied to v dd . this defines the device as a master. other configurations of the address pins (except 000*) defines a device to be a slave. for systems with more than one mc145003/mc145004 (cascaded application) one of the mc145003/mc145004 must have all of its address pins tied to v dd (this defines it as the master). the master is responsible for: 1. supplying the oscillator input to all slaves. 2. sending one frame sync pulse at the beginning of every bp1 (backplane 1) period to keep the mc145003/ mc145004 synchronized. 3. supplying a common set of backplane signals to be shared by all participating devices in the cascaded sys- tem (if desired). note note: in applications where the circuit will be isolated from external manual interference the system designer may take ad- vantage of the selfprogramming feature. upon poweron, ad- dress pins which are left opencircuit will be charged to v dd . however, care must be taken not to inadvertently discharge the pins after poweron since the address may then be lost. a simi- lar feature is also available on the enb pin. caution the configuration a0, a1, a2 = 000 should not be used. this does not give a valid address and is reserved for motorola's use only. all three address pins should never be tied to 0 v simulta- neously. any other combination of master (111) plus six slaves (110, 101, 100, 011, 010, 001) is allowed. enb enable input (pin 41) if the enb pin is tied to v dd , the mc145003/mc145004 will always latch the data after 128 bits have been received. the latched data is multiplexed and fed to the frontplane drivers for display. if external control of this latching function is required (for example, in a cascaded application where multiplexing of new data may require a delay until all participating mc145003/mc145004 data is updated), then the enb pin should be held low, followed by one high pulse on enb when data display is required. (this may also be useful in a system where one mc145003/mc145004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). the pulse on the enb pin must occur while dclk is high. dclk, d in data clock and data input (pins 38, 39) address input and data input controls. see data input protocol sections for relevant option. osc1, osc2 oscillator pins (pins 51, 50) to use the onboard oscillator, an external resistor should be connected between osc1 and osc2 of the master device. optionally, the osc1 pin of the master device may be driven by an externally generated clock signal. the oscillator signal for any slave(s) in the system is provided by the master device by connecting the master's osc2 pin to the slaves'(s) osc2 pin(s). the slaves'(s) osc1 pin(s) should be connected to ground. a resistor of 680 k w connected between the master's osc1 and osc2 pins gives an oscillator frequency of about 30 khz, giving approximately 30 hz as seen at the lcd driver outputs. a resistor of 200 k w gives about 100 khz, which results in 100 hz at the driver outputs. lcd manufacturers recommend an lcd drive frequency of between 30 hz and 100 hz. see figure 6. 1 k 10 k 100 k 1 m 10 m 10 m 1 m 100 k 10 k external resistor value oscillator frequency figure 6. oscillator frequency vs load resistance (approximate) fs frame sync (pin 37) the frame sync pin (fs) is configured as an output on the master device and as an input on the slave device(s). the master device outputs a pulse on the fs pin once at the begin- ning of each bp1 (backplane 1) active period to keep all mc145003/mc145004s synchronized. fp1fp32 frontplane drivers (pins 3627, 2522, 1915, 131) frontplane driver outputs. bp1bp4 backplane drivers (pins 4845) backplane driver outputs. v lcd lcd driver supply (pin 20) power supply input for lcd drive outputs. may be used to supply a temperaturecompensated voltage to the lcd drive section, which can be separate from the logic voltage supply, v dd .
mc145003 ? mc145004 7 motorola v dd positive power supply (pin 49) this pin supplies power to the main processor interface and logic portions of the device. the voltage range is 2.8 to 5.5 v with respect to the v ss pin. for optimum performance, v dd should be bypassed to v ss using a low inductance capacitor mounted very closely to these pins. lead length on this capacitor should be minimized. v ss ground (pin 21) common ground. data input protocol twowire communication bus dclk, d in ; threewire com- munication bus dclk, d in , enb . mc145003 e spi device (figure 7) before communication with an mc145003 can begin, a start condition must be set up on the bus by the transmitter. to establish a start condition, the transmitter must pull the data line low while the clock line is high. the aidleo state for the clock line and data line is the high state. after the start condition has been established, an eightbit address should be sent by the transmitter. if the address sent corresponds to the address of (one of) the mc145003(s) then on each successive clock pulse, the addressed device will accept a data bit. if the enb pin is permanently high, then the addressed mc145003's internal counter latches the data to be displayed after 128 data bits have been received. otherwise, the control of this latch function may be overridden by holding the enb line low until the new data is required to be displayed, then a high pulse should be sent on the enb line. the high pulse must be sent during dclk high (clock idle). to end communication with an mc145003, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. in such a case, the 129th rising dclk edge, which normally would be used to set up the stop or start condition, is ignored by the mc145003 and data con- tinues to be received on the 130th rising dclk. the latch func- tion continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as required). at any time during data transmission, the transfer may be interrupted with a stop condition. data transmission may be resumed with a start condition and resending the address. interfacing the mc145003 with the mc6805 family the mc145003 performs as a slave receiver in an spi envi- ronment if the clock idle state has been defined to be ahigho (spicr5 = 1). in threewire or fourwire spi environments, the slave select wire (spiss) can be used for the enb pin on the mc145003 as described above. note that in full duplex spi environments, mc145003 only receives data, it does not retransmit data. mc145004 e iic device (figure 8) before communication with an mc145004 can begin, a start condition must be set up on the bus by the controller. to estab- lish a start condition, the controller must pull the data line low while the clock line is high. after the start condition has been established, an eightbit address should be sent by the controller followed by an extra clock pulse while the data line is left high. in this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit is used as a read/write control: if the least significant bit is 0, then the controller writes to the lcd driver; if it is 1, then the con- troller reads from the lcd driver's 128bit shift register on a firstin firstout basis. if the seven most significant address bits sent correspond to the address of (one of) the lcd driv- er(s) then the addressed lcd driver responds by sending an aacknowledgeo bit back to the controller (i.e., the lcd driver pulls the data line low during the extra clock pulse supplied by the controller). if the least significant address bit was 0, then the controller should continue to send data to the lcd driver in blocks of eight bits followed by an extra ninth clock pulse to allow the lcd driver to pull the data line d in low as an acknowl- edgement. if the least significant address bit was 1, then the lcd driver sends data back to the controller (the clock is sup- plied by the controller). after each successive group of eight bits sent, the lcd driver leaves the data line high for one pulse. if the enb pin is permanently high, then the addressed mc145004's internal counter latches the data to be displayed after 128 data bits have been received. otherwise the control of this latch function may be overridden by holding the enb line low until the new data is required to be displayed, then a high pulse should be sent on the enb line. the high pulse must be sent during dclk high (clock idle). to end communication with an mc145004, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. in such a case the rising dclk edge which comes after all 128 data bits have been sent and after the last acknowledgerelated clock pulse has been made is ignored; data continues to be received on the following dclk high. the latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been re- ceived or under external control as required). at any time during data transmission, the transfer may be interrupted with a stop condition. data transmission may be resumed with a start condition and resending the address. cascaded operation the master device supplies the oscillator input via its osc2 pin to the slave devices via their osc2 pin(s). it sends a frame sync pulse via its fs pin to the slaves via their fs pins at the beginning of every bp1 valid time. in figure 9, the enb pins are tied together and used as a chip enable to latch the new data e the enb pins could have been tied to v dd if it were de- sirable to use the internal data bit counter to latch the new data. the four backplane inputs may come from the master only, with the slave backplanes being left open, as shown in figure 6, or if more drive is required, then the slaves' backplanes may be connected to the corresponding backplanes of the master. example: at room temperature, with a drive frequency of 30 hz, around four to five mc145003/mc145004s may be used in a system where only the master's backplanes are con- nected to the lcd. for applications with heavier loads (e.g., large liquid crystals) or high drive frequencies or at high tem- peratures, the dc voltage component seen by the lcd may be kept to a minimum by connecting the corresponding back- planes of all participating mc145003/mc145004s together.
mc145003 ? mc145004 motorola 8 figure 7a. data input e mc145003 figure 7b. serial 128 bits data d in bp 4 32 14 3 21432 1 4 32143214321 x fp1 fp2 fp3 fp4 fp5 fp6 fp32 432 1 ? ? ? x: 1 0 (bpi, fpj) on (bpi, fpj) off a2 a1 a0 bp4 bp3 bp2 bp1 bp4 bp3 bp2 bp1 fp1 fp2 d in dclk enb (if used) start 8-bits address 128-bits data 129th dclk high: (does not shift data) enable pulse may occur as required; but must be during dclk high. start figure 7. mc145003 (spi device)
mc145003 ? mc145004 9 motorola write to lcd driver read from lcd driver a2 a1 a0 bp4 bp3 bp2 bp1 bp4 bp3 bp2 bp1 fp1 fp2 d in dclk enb (if used) start 8-bits address 8-bits data last dclk pulse (does not shift data) enable pulse may occur as required; but must be during dclk high. by controller left high by controller left high (from controller) acknowledge entire clk for acknowledge entire clk for continues to clock data and acknowledge d in (from lcd driver) pulled low by driver (low-order bit = 0) pulled low by driver stop d in dclk start 8-bits address 8-bits data last dclk pulse (does not shift data) (from controller) acknowledge entire clk for acknowledge entire clk for continues to clock data and acknowledge d in address acknowledged by driver left high by driver (from lcd driver) left high by driver stop acknowledge entire clk for (low-order bit = 1) figure 8. data input mc145004 (iic device)
mc145003 ? mc145004 motorola 10 fp1fp32 bp1bp4 fp33fp64 osc1 osc2 v bp1 bp2 bp3 bp4 a0 a1 a2 enb fp19 fp18 fp17 fp16 fp15 v v fp14 fp13 fp12 fp11 lcd driver (master) lcd ss dd liquid crystal display osc1 osc2 v bp1 bp2 bp3 bp4 a0 a1 a2 enb fp19 fp18 fp17 fp16 fp15 v v fp14 fp13 fp12 fp11 lcd ss dd fp32 fp20 lcd driver (slave) v v lcd ss v dd controller clock data fp1fp32 bp1bp4 other on bus chips to 680 k ss fp21 fp22 fp23 fp24 fp25 fp26 fp27 fp28 fp29 fp30 fp31 fp10 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fs dclk d in figure 9. cascading example fp1fp32 w fp32 fp20 fp21 fp22 fp23 fp24 fp25 fp26 fp27 fp28 fp29 fp30 fp31 fp10 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fs dclk d in
allows the latch of data to the fp outputs mc145003 ? mc145004 11 motorola application information figure 10 shows an interface example. example 1 shows a semiautomatic spi mode (only start and stop conditions are done in nonspi mode). example 2 contains the software to use hc11 with mc145003 in manual spi mode. both examples use the same hardware connection. 1/4 mux display a0 mc145003 mc68hc11 r = 470 k w bp1bp4 mosi sck ss fp1fp32 a1 a2 d in dclk enb osc1 osc2 v dd v dd 1 k w figure 10. interface example between mc68hc11 and mc145003 cpol = 0 cpha = 0 spi off ew = 0 setup start condition with spi off (write data port to 0) spi on < ldaa $73, staa $1028 send address byte $7e send 16 bytes of data spi off < ldaa $33, staa $1028 data = 0 spi off enb = 1 clk = 1 data = 1 stop condition example 1. semiautomatic spi method
mc145003 ? mc145004 motorola 12 1 2 ;=======constants================================================= 3 0000 t extram equ $a000 ;$a000 for 8k ram 4 0000 t stack equ $00ff ;last ram byte 5 0000 t intofs equ $1000 ;internal registers 6 0000 t data equ $08 7 0000 t clock equ $10 8 0000 t enable equ $20 9 0000 t portd equ 8 10 11 12 ;=======program begin============================================= 13 a000 t org extram ;program into ram 14 a000 n 8e00ff cold lds #stack ;set stack pointer 15 a003 m 8638 ldaa #$38 ;set of mosi,ss,sck 16 a005 t b71009 staa $1009 ;ddrd 17 a008 m c611 ldab #17 18 a00a n cea05e ldx #send 19 a00d t bda010 jsr spi 20 a010 t end cold 21 22 a010 u 18ce1000 spi ldy #intofs 23 a014 j 181d0820 bclr portd,y #enable ;en = 0 24 a018 t bda031 jsr start ;start condition 25 a01b x a600 again ldaa 0 , x ;spi mode use 26 a01d t b7102a staa $102a ;spdr 27 a020 l 181f2980fb brclr $29,y,#$80,* 28 a025 h 08 inx ;next data 29 a026 h 5a decb 30 a027 r 26f2 bne again 31 a029 j 181c0820 bset portd,y #enable 32 a02d t bda04c jsr stop ;stop condition 33 a030 h 39 rts 34 35 a031 m 8633 start ldaa #$33 ;normal mode 36 a033 t b71028 staa $1028 ;spcr 37 a036 j 181c0808 bset portd,y #data ;data = 1 38 a03a j 181c0810 bset portd,y #clock ;clk = 1 39 a03e j 181d0808 bclr portd,y #data ;data = 0 40 a042 j 181d0810 bclr portd,y #clock ;clk = 0 41 a046 m 8673 ldaa #$73 ;spi mode 42 a048 t b71028 staa $1028 ;spcr 43 a04b h 39 rts 44 a04c m 8633 stop ldaa #$33 ;normal mode 45 a04e t b71028 staa $1028 ;spcr 46 a051 j 181d0808 bclr portd,y #data ;data = 0 47 a055 j 181c0810 bset portd,y #clock ;clk = 1 48 a059 j 181c0808 bset portd,y #data ;data = 0 49 a05d h 39 rts 50 51 a05e t 7e send fcb $007e ;lcd driver address 52 a05f t f0 fcb $00f0 ;data to sent 53 a060 t f0 fcb $00f0 54 a061 t f0 fcb $00f0 55 a062 t f0 fcb $00f0 56 a063 t f0 fcb $00f0 57 a064 t f0 fcb $00f0 58 a065 t f0 fcb $00f0 59 a066 t f0 fcb $00f0 60 a067 t f0 fcb $00f0 61 a068 t f0 fcb $00f0 62 a069 t f0 fcb $00f0 63 a06a t f0 fcb $00f0 64 a06b t f0 fcb $00f0 65 a06c t f0 fcb $00f0 66 a06d t f0 fcb $00f0 67 a06e t f0 fcb $00f0 68 a06f h 39 rts 69 70 ;=======program end=============================================== example 2. manual method
mc145003 ? mc145004 13 motorola package dimensions qfp fu suffix case 848b02 min min max max millimeters inches dim 0.026 bsc 0.307 ref 0.063 ref 0.65 bsc 7.80 ref 1.6 ref a b c d e f g h j k l m n q r s t u v w x 9.90 9.90 2.10 0.22 2.00 0.22 e 0.13 0.65 5 0.13 0 0.13 12.95 0.13 0 12.95 0.35 10.10 10.10 2.45 0. 38 2.10 0.33 0.25 0.23 0.95 10 0.17 7 0.30 13.45 e e 13.45 0.45 0.390 0.390 0.083 0.009 0.079 0.009 e 0.005 0.026 5 0.005 0 0.005 0.510 0.005 0 0.510 0.014 0.398 0.398 0.096 0.015 0.083 0.013 0.010 0.009 0.037 10 0.007 7 0.012 0.530 e e 0.530 0.018 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. b b detail a -a,b,d- base metal f d n section b-b j -h- datum plane k u q r t w x detail c 40 27 1 13 14 26 52 39 v -a- l -d- l b -d- detail a detail c c h e -c- seating plane g m m -h- datum plane 0.10 (0.004) b v h 0.20 (0.008) ab d ab 0.05 (0.002) s s m c 0.20 (0.008) ab d s s m 0.20 (0.008) h ab d 0.05 (0.002) ab m s s 0.20 (0.008) c ab d m s s c 0.02 (0.008) ab d s s m
mc145003 ? mc145004 motorola 14 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mc145003/d
? codeline to be placed here literature distribution centers: usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd.; 4321, nishigotanda, shinagawaku, tokyo 141, japan. asia pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong.

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