2dad-c5r - integrated passive & active device using csp specifications are subject to change without notice. customers should verify actual device performance in their specific applications. solder bumps silicon die electrical characteristics symbol minimum nominal maximum unit (t a = 25 ? unless otherwise noted) capacitance @ 2.5 v 1 mhz c 12 15 18 pf rated standoff voltage v wm 5.0 v breakdown voltage @ 1 ma v br 6.0 v forward voltage @ 10 ma v f 0.8 v leakage current @ 3.3 v i r 0.1 a esd protection: iec 61000-4-2 contact discharge ? kv air discharge ?5 kv thermal characteristics (t a = 25 ? unless otherwise noted) dc power rating p 200 mw operating temperature range t j -40 25 +85 ? storage temperature range t stg -55 25 +150 ? general information features lead free versions available rohs compliant (lead free version)* esd protection protects four lines low capacitance 15 pf applications cell phones pdas and notebooks mp3 players electrical & thermal characteristics the 2dad-c5r device, manufactured using thin film on silicon technology, provides esd protection for the external ports of portable electronic devices such as cell phones, modems and pdas. the esd protection provided by the component enables a data port to withstand a minimum ? kv contact / ?5 kv air d ischarge per the esd test method specified in iec 61000-4-2. the device measures 1.00 mm x 1.33 mm and is available in a 5 bump csp package intended to be mounted directly onto an fr4 printed circuit board. the csp device meets typical thermal cycle and bend test specifications without the use of an underfill material. *rohs compliant versions available *rohs directive 2002/95/ec jan 27 2003 including annex
dimensions = millimeters (inches) specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical characteristics 2dad-c5r - integrated passive & active device using csp b2 a1 a3 c3 c1 0.432 - 0.559 (0.017 - 0.022) 0.971 - 1.001 (0.038 - 0.039) 0.330 - 0.457 (0.013 - 0.018) 1.285 - 1.375 (0.051 - 0.054) 0.180 - 0.280 (0.007 - 0.011) 0.435 (0.017) 0.435 (0.017) 0.3 (0.012) 0.180 - 0.280 (0.007 - 0.011) dia. 0.50 (0.020) this is a silicon-based device and is packaged using chip scale packaging technology. solder bumps, formed on the silicon die, provide the interconnect medium from die to pcb. the bumps are arranged on the die in a regular grid formation. the grid pitch is 0.5 mm and the dimensions for the packaged device are shown below. reliability data is gathered on an ongoing basis for bourns integrated passive and active devices. ?ackage level?testing of the integrity of the solder joint is carried out on an independent daisy-chain test device. a 25-pin daisy chain component is available from bourns for this purpose (part number 2tad-c25r). this is a 5 x 5 array featuring 0.5 mm pitch solder bumps. the distance to neutral point (dnp) on that component is larger than that of the 2dad-c5r and is thus deemed suitable for thermal cycle testing. ?ilicon level?reliability performance is based on simila rity to other integrated passive csp devices from bourns. reliability data overshoot and clamping voltage response esd test pulse - 25 kilovolt, 1/30 ns (waveshape) 5 volts per division -90,000 ns -5 5 15 25 35 10,000 ns 110,000 ns
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. 2dad-c5r - integrated passive & active device using csp block diagram gnd ext1 ext2 ext4 ext3 the csp device block diagram below includes the pin names and basic electrical connections associated with each channel. please consult the ?ourns design guide using csp?for notes on pcb design and smt processing. pcb design and smt processing how to order 2 dad - c5r __ __ thinfilm model chipscale no. of solder bumps packaging option r = tape and reel packaged 3000 pcs. / 7 ?reel terminations lf = sn/ag/cu (lead free) blank = sn/pb
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. 2dad-c5r - integrated passive & active device using csp the pin-out for the device is shown below with the bumps facing up. device pin out the surface mount product is packaged in an 8 mm x 4 mm tape and reel format per eia-481 standard. packaging 123 gnd ext2 c b a ext1 ext3 ext4 2.0 0.05 (.08 .002) 0.3 0.05 (.01 .002) 1.18 0.1 (.05 .004) 1.52 0.1 (.06 .004) 1.75 0.1 (.07 .004) 3.5 0.05 (.14 .002) 8.0 0.3 (.31 .01) 0.76 0.1 (.03 .004) orientation of component in pocket backside facing up top side view (into component pocket) 0.3 (0.01) 4.0 0.1 (.16 .004) 4.0 0.1 (.16 .004) 0.25 (0.010) typ. r 1.5 0.1/-0 (.06 .004/-0) dia. max. r pin out function pin out function a1 ext1 a3 ext4 c1 ext2 c3 ext3 b2 gnd dimensions = millimeters (inches) asia-pacific: tel +886- (0)2 25624117 ?fax +886- (0)2 25624116 europe: tel +41-41 768 5555 ?fax +41-41 768 5510 the americas: tel +1-951 781-5492 ?fax +1-951 781-5700 www.bourns.com reliable electronic solutions copyright? 2004, bourns, inc. litho in u.s.a. 06/05 e/ipa0507 2dad-c5r rev. b, 1/05
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