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ads8325 description the ads8325 is a 16-bit, sampling, analog-to-digital (a/d) converter specified for a supply voltage range from 2.7v to 5.5v. it requires very little power, even when operating at the full 100khz data rate. at lower data rates, the high speed of the device enables it to spend most of its time in the power- down mode. for example, the average power dissipation is less than 1mw at a 10khz data rate. the ads8325 offers excellent linearity and very low noise and distortion. it also features a synchronous serial (spi/ssi compatible) interface and a differential input. the reference voltage can be set to any level within the range of 2.5v to v dd . low power and small size make the ads8325 ideal for portable and battery-operated systems. it is also a perfect fit for remote data acquisition modules, simultaneous multi- channel systems, and isolated data acquisition. the ads8325 is available in msop-8 and son-8 packages. the son package size is the same as a 3x3 qfn package. features 16-bits no missing codes very low noise: 3lsbp-p excellent linearity: 1.5lsb typ micro power: 4.5mw at 100khz 1mw at 10khz msop-8 and son-8 packages (son package size same as 3x3 qfn) 16-bit upgrade to the 12-bit ads7816 and ads7822 pin-compatible with the ads7816, ads7822, ads7826, ads7827, ads7829, and ads8320 serial (spi ? /ssi) interface 16-bit, high-speed, 2.7v to 5.5v micro power sampling analog-to-digital converter www.ti.com copyright ?2002-2003, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. sbas226a ?march 2002 ?revised june 2003 production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. sar serial interface comparator ads8325 s/h amp dclock d out cs/shdn +in ref in cdac applications battery-operated systems remote data acquisition isolated data acquisition simultaneous sampling, multi-channel systems industrial controls robotics vibration analysis all trademarks are the property of their respective owners. a d s 8 3 2 5 a d s 8 3 2 5
ads8325 2 sbas226a www.ti.com maximum no integral missing specified linearity codes error package- package temperature package ordering transport product error (lsb) (lsb) (1) lead designator (2) range marking number media, quantity ads8325i 6 15 msop-8 dgk 40 c to 85 c b25 ads8325idgkt tape and reel, 250 "" " " " " " ads8325idgkr tape and reel, 2500 ads8325ib 4 16 msop-8 dgk 40 c to 85 c b25 ads8325ibdgkt tape and reel, 250 "" " " " " " ads8325ibdgkr tape and reel, 2500 ads8325i 6 15 son-8 drb 40 c to 85 c b25 ADS8325IDRBT tape and reel, 250 "" " " " " " ads8325idrbr tape and reel, 2500 ads8325ib 4 16 son-8 drb 40 c to 85 c b25 ads8325ibdrbt tape and reel, 250 "" " " " " " ads8325ibdrbr tape and reel, 2500 note: (1) no missing codes error specifies a 5v power supply and reference voltage. (2) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information absolute maximum ratings (1) over operating free-air temperature, unless otherwise noted. supply voltage, dgnd to v dd .................................................................. 0.3v to 6v analog input voltage (2) ............................................................... 0.3v to v dd + 0.3v reference input voltage (2) ........................................................ 0.3v to v dd + 0.3v digital input voltage (2) ............................................................. 0.3v to v dd + 0.3v input current to any pin except supply ......................... 20ma to 20ma power dissipation ....................................... see dissipation rating table operating virtual junction temperature range, t j ...... 40 c to +150 c operating free-air temperature range, t a .................... 40 c to +85 c storage temperature range, t stg ................................ 65 c to +150 c lead temperature 1.6mm (1/16 inch) from case for 10sec ..................... 260 c electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper han- dling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. notes: (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions of extended periods may affect device reliability. (2) all voltage values are with respect to ground terminal. equivalent input circuit derating factor t a 25 ct a = 70 ct a = 85 c package r jc r ja above t a = 25 c power rating power rating power rating dgk 39.1 c/w 206.3 c/w 4.847mw/ c 606mw 388mw 315mw drb 5 c/w 45.8 c/w 3.7mw/ c 370mw 204mw 148mw min typ max unit supply voltage low-voltage levels 2.7 3.6 v gnd to v dd 5v logic levels 4.5 5.0 5.5 v reference input voltage 2.5 v dd v analog input in 0.3 0 0.5 v voltage +in ( in) 0 v ref v operating junction temperature 40 125 c range, t j recommended operating conditions package dissipation rating table r on 20 ? c (sample) 20pf shut-down switch v dd i/o gnd v dd analog in gnd diode turn-on voltage: 0.35v equivalent analog input circuit v dd ref gnd equivalent reference input circuit equivalent digital input/output circuit 20pf 5k ?
ads8325 3 sbas226a www.ti.com electrical characteristics: v dd = +5v over recommended operating free-air temperature at 40 c to +85 c, v ref = +5v, in = gnd, f sample = 100khz, and f clk = 24 f sample , unless otherwise noted. ads8325i ads8325ib parameter conditions min typ max min typ max units analog input full-scale range fsr +in ( in) 0 v ref ?? v operating common-mode signal 0.3 0.5 ?? v input resistance in = gnd 5 ? g ? input capacitance in = gnd, during sampling 45 ? pf input leakage current in = gnd 50 ? na differential input capacitance +in to in, during sampling 20 ? pf full-power bandwith fsbw f s sinewave, sinad at 3db 20 ? khz dc accuracy resolution 16 ? bits no missing code nmc 15 16 bits integral linearity error inl 3 6 1.5 4lsb offset error v os 0.75 1.5 0.5 1mv offset error drift tcv os 0.2 ? ppm/ c gain error g err 24 12 lsb gain error drift tcg err 0.3 ? ppm/ c noise 20 ? vrms power-supply rejection 4.75v v dd 5.25 3 ? lsb sampling dynamics conversion time t conv 24khz < f clk 2.4mhz 6.667 666.7 ?? s acquisition time t aq f clk = 2.4mhz 1.875 ? s throughout rate 100 ? ksps clock frequency 0.024 2.4 ?? mhz ac accuracy total harmonic distortion thd 5vp-p sinewave, at 1khz 100 106 db spurious-free dynamic range sfdr 5vp-p sinewave, at 1khz 100 108 db signal-to-noise ratio snr 90 91 db signal-to-noise + distortion sinad 5vp-p sinewave, at 1khz 90 91 db effective number of bits enob 14.6 14.7 bits voltage reference input reference voltage 2.5 v dd + 0.3 ?? v reference input resistance cs = gnd, f sample = 0hz 5 ? k ? cs = v dd 5 ? g ? reference input capacitance 20 ? pf reference input current 1 1.5 ?? ma cs = v dd 0.1 ?? a digital inputs (1) logic family cmos ? high-level input voltage v ih 0.7 v dd v dd + 0.3 ?? v low-level input voltage v il 0.3 0.3 v dd ?? v input current i in v i = v dd or gnd 50 na input capacitance c i 5 ? pf digital outputs (1) logic family cmos ? high-level output voltage v oh v dd = 4.5v, i oh = 100 a 4.44 ? v low-level output voltage v ol v dd = 4.5v, i ol = 100 a 0.5 ? v high-impedance-state output current i oz cs = v dd , v i = v dd or gnd 50 ? na output capacitance c o 5 ? pf load capacitance c l 30 ? pf data format straight binary ? ? indicates the same specifications as the ads8325i. note: (1) applies for 5.0v nominal supply: v dd (min) = 4.5v and v dd (max) = 5.5v.
ads8325 4 sbas226a www.ti.com electrical characteristics: v dd = +2.7v over recommended operating free-air temperature at 40 c to +85 c, v ref = +2.5v, in = gnd, f sample = 100khz, and f clk = 24 f sample , unless otherwise noted. ads8325i ads8325ib parameter conditions min typ max min typ max units analog input full-scale range fsr +in ( in) 0 v ref ?? v operating common-mode signal 0.3 0.5 ?? v input resistance in = gnd 5 ? g ? input capacitance in = gnd, during sampling 45 ? pf input leakage current in = gnd 50 ? na differential input capacitance +in to in, during sampling 20 ? pf full-power bandwith fsbw f s sinewave, sinad at 3db 4 ? khz dc accuracy resolution 16 ? bits no missing code nmc 14 15 bits integral linearity error inl 3 6 1.5 4lsb offset error v os 0.75 1.5 0.5 1mv offset error drift tcv os 3 ? ppm/ c gain error g err 33 16 lsb gain error drift tcg err 0.3 ? ppm/ c noise 20 ? vrms power-supply rejection 2.7v v dd 3.6v 7 ? lsb sampling dynamics conversion time t conv 24khz < f clk 2.4mhz 6.667 666.7 s acquisition time t aq f clk = 2.4mhz 1.875 s throughout rate 100 ksps clock frequency 0.024 2.4 mhz ac accuracy total harmonic distortion thd 2.5vp-p sinewave, at 1khz 94 ? db spurious-free dynamic range sfdr 2.5vp-p sinewave, at 1khz 96 ? db signal-to-noise ratio snr 85 86 db signal-to-noise + distortion sinad 2.5vp-p sinewave, at 1khz 85 85.5 db effective number of bits enob 13.8 13.9 bits voltage reference input reference voltage 2.5 v dd + 0.3 ?? v reference input resistance cs = gnd, f sample = 0hz 5 ? k ? cs = v dd 5 ? g ? reference input capacitance 20 ? pf reference input current 0.5 0.75 ?? ma cs = v dd 0.1 ? a digital inputs (1) logic family lvcmos ? high-level input voltage v ih v dd = 3.6v 2 v dd + 0.3 ?? v low-level input voltage v il v dd = 2.7v 0.3 0.8 ?? v input current i in v i = v dd or gnd 50 ?? na input capacitance c i 5 ? pf digital outputs (1) logic family lvcmos ? high-level output voltage v oh v dd = 2.7v, i oh = 100 a v dd 0.2 ? v low-level output voltage v ol v dd = 2.7v, i ol = 100 a 0.2 ? v high-impedance-state output current i oz cs = v dd , v i = v dd or gnd 50 ?? na output capacitance c o 5 ? pf load capacitance c l 30 ? pf data format straight binary ? ? indicates the same specifications as the ads8325i. note: (1) applies for 3.0v nominal supply: v dd (min) = 2.7v and v dd (max) = 3.6v.
ads8325 5 sbas226a www.ti.com pin configuration name pin i/o description ref 1 ai reference input +in 2 ai noninverting input in 3 ai inverting analog input gnd 4 p ground cs/shdn 5 di chip select when low, shutdown mode when high. d out 6 do the serial output data word. dclock 7 di data clock synchronizes the serial data transfer and determines conversion speed. v dd 8 p power supply note: ai is analog input, di is digital input, do is digital output, and p is power-supply connection. top view msop electrical characteristics over recommended operating free-air temperature at 40 c to 85 c, v ref = v dd , in = gnd, f sample = 100khz, and f clk = 24 f sample , unless otherwise noted. ads8325i ads8325ib parameter conditions min typ max min typ max units power-supply requirements power supply (v dd) low-voltage levels 2.7 3.6 ?? v 5v logic levels 4.5 5.5 ?? v operating supply current (i dd )v dd = 3v 0.75 1.5 ?? ma v dd = 5v 0.9 1.5 ?? ma power-down supply current (i dd )v dd = 3v 0.1 ? a v dd = 5v 0.2 ? a power dissipation v dd = 3v 2.25 4.5 ?? mw v dd = 5v 4.5 7.5 ?? mw power dissipation in power-down v dd = 3v, cs = v dd 0.3 ? w v dd = 5v, cs = v dd 0.6 ? w ? indicates the same specifications as the ads8325i. 1 2 3 4 8 7 6 5 +v dd dclock d out cs/shdn ref +in in gnd ads8325 pin descriptions 1 2 3 4 8 7 6 5 +v dd dclock d out cs/shdn ref +in in gnd ads8325 top view son
ads8325 6 sbas226a www.ti.com d out 1.4v test point 3k ? 100pf c load load circuit for t ddo , t r , and t f voltage waveforms for d out rise and fall times, t r , t f voltage waveforms for d out delay times, t ddo voltage waveforms for t dis voltage waveforms for t en load circuit for t dis and t en t r d out 90% 10% t f d out test point t dis waveform 2, t en v cc t dis waveform 1 100pf c load 3k ? t dis cs/shdn d out waveform 1 (1) d out waveform 2 (2) 90% 10% 90% 4 1 b15 5 t en cs/shdn dclock d out t ddo d out dclock t hdo notes: (1) waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (2) waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. timing diagrams and test circuits for the parameters in the timing characteristics table. cs/shdn d out dclock complete cycle power down conversion sample use positive clock edge for data transfer t sucs t conv t smpl note: a minimum of 22 clock cycles are required for 16-bit conversion. shown are 24 clock cycles. if cs remains low at the end of conversion, a new datastream with lsb-first is shifted out again. b15 (msb) b14 b13 b12 b11 b10 b9 b8 b0 (lsb) b7 b1 b6 b2 b5 b3 b4 hi-z 0 hi-z t csd timing characteristics symbol description min typ max units t smpl analog input sample time 4.5 5.0 clk cycles t conv conversion time 16 clk cycles t cyc throughput rate 100 khz t csd cs falling to dclock low 0ns t sucs cs falling to dclock rising 20 ns t hdo dclock falling to current d out not valid 5 15 ns t dis cs rising to d out tri-state 70 100 ns t en dclock falling to d out enabled 20 50 ns t f d out fall time 5 25 ns t r d out rise time 7 25 ns timing diagrams
ads8325 7 sbas226a www.ti.com typical characteristics: v dd = +5v at t a = 25 c, v dd = +5v, v ref = +5v, f sample = 100khz, f clk = 24 f sample , unless otherwise noted. 3 2 1 0 1 2 3 ile(lsbs) 0000 h 4000 h 8000 h c000 h ffff h output code integral linearity error vs code 0 20 40 60 80 100 120 140 160 amplitude (db) 0 1020304050 frequency (khz) frequency spectrum (8192 point fft, f in = 1.0132khz, 0.2db) 0 20 40 60 80 100 120 140 160 amplitude (db) 0 1020304050 frequency (khz) frequency spectrum (8192 point fft, f in = 10.0022khz, 0.2db) snr sinad 105 100 95 90 85 80 75 70 65 snr and sinad (db) 1 10 100 245 frequency (khz) signal-to-noise ratio and signal-to-noise + distortion vs input frequency 3 2 1 0 1 2 3 dle(lsbs) 0000 h 4000 h 8000 h c000 h ffff h output code differential linearity error vs code 110 105 100 95 90 85 80 75 70 110 105 100 95 90 85 80 75 70 sfdr (db) thd (db) 1 10 100 245 frequency (khz) spurious-free dynamic range and total harmonic distortion vs input frequency sfdr thd (1) note: (1) first nine harmonics of the input frequency.
ads8325 8 sbas226a www.ti.com typical characteristics: v dd = +5v (cont.) at t a = 25 c, v dd = +5v, v ref = +5v, f sample = 100khz, f clk = 24 f sample , unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 signal-to-noise + distortion (db) 80 70 60 50 40 30 20 10 0 input level (db) signal-to-noise + distortion vs input level f in = 1.0132khz 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 effective number of bits 1 10 100 frequency (khz) effective number of bits vs input frequency 0.4 0.2 0.0 0.2 0.4 0.6 0.8 delta from 25 c (db) 50 25 0 25 50 75 100 temperature ( c) change in signal-to-noise + distortion vs temperature f in = 1.0132khz, 0.2db 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 delta from 25 c (lsbs) 50 25 0 25 50 75 100 temperature ( c) change in gain vs temperature 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 delta from 25 c (lsbs) 50 25 0 25 50 75 100 temperature ( c) change in upo vs temperature 1.1 1.0 0.9 0.8 0.7 supply current (ma) 50 25 0 25 50 75 100 temperature ( c) supply current vs temperature
ads8325 9 sbas226a www.ti.com 3 2 1 0 1 2 3 ile(lsbs) 0000 h 4000 h 8000 h c000 h ffff h output code integral linearity error vs code 3 2 1 0 1 2 3 dle(lsbs) 0000 h 4000 h 8000 h c000 h ffff h output code differential linearity error vs code 0 20 40 60 80 100 120 140 160 amplitude (db) 0 1020304050 frequency (khz) frequency spectrum (8192 point fft, f in = 1.0132khz, 0.2db) 0 20 40 60 80 100 120 140 160 amplitude (db) 0 1020304050 frequency (khz) frequency spectrum (8192 point fft, f in = 10.0022khz, 0.2db) snr sinad 95 85 75 65 55 45 snr and sinad (db) 1 10 100 245 frequency (khz) signal-to-noise ratio and signal-to-noise + distortion vs input frequency 100 90 80 70 60 50 40 100 90 80 70 60 50 40 sfdr (db) thd (db) 1 10 100 245 frequency (khz) spurious free dynamic range and total harmonic distortion vs input frequency sfdr thd (1) note: (1) first nine harmonics of the input frequency. typical characteristics: v dd = +2.7v at t a = 25 c, v dd = 2.7v, v ref = 2.5v, f sample = 100khz, f clk = 24 f sample , unless otherwise noted.
ads8325 10 sbas226a www.ti.com typical characteristics: v dd = +2.7v (cont.) at t a = 25 c, v dd = 2.7v, v ref = 2.5v, f sample = 100khz, f clk = 24 f sample , unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 signal-to-noise + distortion (db) 80 70 60 50 40 30 20 10 0 input level (db) signal-to-noise + distortion vs input level f in = 1.0132khz 0.9 0.8 0.7 0.6 supply current (ma) 50 25 0 25 50 75 100 temperature ( c) supply current vs temperature 1.2 0.8 0.4 0.0 0.4 0.8 delta from 25 c (lsbs) 50 25 0 25 50 75 100 temperature ( c) change in upo vs temperature 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 delta from 25 c (lsbs) 50 25 0 25 50 75 100 temperature ( c) change in gain vs temperature 0.4 0.2 0.0 0.2 0.4 0.6 0.8 delta from 25 c (db) 50 25 0 25 50 75 100 temperature ( c) change in signal-to-noise + distortion vs temperature f in = 1.0132khz, 0.2db 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 effective number of bits 1 10 100 frequency (khz) effective number of bits vs input frequency
ads8325 11 sbas226a www.ti.com theory of operation the ads8325 is a classic successive approximation register (sar) analog-to-digital (a/d) converter. the architecture is based on capacitive redistribution that inherently includes a sample-and- hold function. the converter is fabricated on a 0.6 cmos process. the architecture and process allow the ads8325 to acquire and convert an analog signal at up to 100,000 conver- sions per second while consuming less than 4.5mw from +v dd . the ads8325 requires an external reference, an external clock, and a single power source (v dd ). the external reference can be any voltage between 2.5v and 5.5v. the value of the reference voltage directly sets the range of the analog input. the reference input current depends on the conversion rate of the ads8325. the external clock can vary between 24khz (1khz throughput) and 2.4mhz (100khz throughput). the duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns (v dd = 4.75v or greater). the minimum clock frequency is set by the leakage on the internal capacitors to the ads8325. the analog input is provided to two input pins: +in and in. when a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. while a conversion is in progress, both inputs are disconnected from any internal function. the digital result of the conversion is clocked out by the dclock input and is provided serially, most significant bit first, on the d out pin. the digital data that is provided on the d out pin is for the conversion currently in progress there is no pipeline delay. it is possible to continue to clock the ads8325 after the conversion is complete and to obtain the serial data least significant bit first. see the digital timing section for more information. analog input the analog input of ads8325 is differential. the +in and in input pins allow for a differential input signal. the amplitude of the input is the difference between the +in and in input, or (+in) ( in). unlike some converters of this type, the in input is not resampled later in the conversion cycle. when the converter goes into the hold mode or conversion, the voltage difference between +in and in is captured on the internal capacitor array. the range of the in input is limited to 0.3v to +0.5v. due to this, the differential input could be used to reject signals that are common to both inputs in the specified range. thus, the in input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. the general method for driving the analog input of the ads8325 is shown in figures 1 and 2. the in input is held at the common-mode voltage. the +in input swings from in (or common-mode voltage) to in + v ref (or common- mode voltage + v ref ), and the peak-to-peak amplitude is +v ref . the value of v ref determines the range over which the common-mode voltage may vary (see figure 3). figures 5 and 6 illustrate the typical change in gain and offset as a function of the common-mode voltage applied to the in pin. figure 2. methods of driving the ads8325 figure 1. differential input mode of the ads8325. ads8325 0v to +v ref peak-to-peak common-mode voltage the input current required by the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. essentially, the current into the ads8325 charges the internal capacitor array during the sample period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (20pf) to a 16-bit settling level within 4.5 clock cycles (1.875 s). when the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1g ? . common-mode voltage + v ref +v ref t +in common-mode voltage note: the maximum differential voltage between +in and in of the ads8325 is v ref . see figure 3 for a further explanation of the common-mode voltage range for differential inputs. in = common-mode voltage
ads8325 12 sbas226a www.ti.com figure 3. +in analog input: common-mode voltage range vs v ref . 60 50 40 30 20 10 0 10 delta relative to v cm = 0v (lsbs) 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v cm (v) change in gain vs common-mode voltage v dd = 5v v ref = 4v 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v cm (v) 30 20 10 0 10 20 delta relative to v cm = 0v (lsbs) change in upo vs common-mode voltage v dd = 5v v ref = 4v figure 5. change in gain vs common-mode voltage. figure 6. change in unipolar offset vs common-mode voltage. figure 4. single-ended and differential methods of interfacing the ads8325. 23456 v ref (v) common voltage range (v) 1 0 1 0.3 0.5 4.8 2.5 v dd = 5v 50 ? 20 ? opa340 20pf 100pf 1nf 50 ? 20 ? opa340 20pf 100pf +in in ads8325 50 ? 20 ? opa340 20pf 100pf 20 ? 20pf +in in ads8325 single-ended differential care must be taken regarding the absolute analog input voltage. to maintain the linearity of the converter, the in input should not drop below gnd 0.3v or exceed gnd + 0.5v. the +in input should always remain within the range of gnd 0.3v to v dd + 0.3v, or in to in + v ref , whichever limit is reached first. outside of these ranges, the converter s linearity may not meet specifications. to minimize noise, low bandwidth input signals with low- pass filters should be used. in each case, care should be taken to ensure that the output impedance of the sources driving the +in and in inputs are matched. often, a small capacitor (20pf) between the positive and negative inputs helps to match their impedance. to obtain maximum perfor- mance from the ads8325, the input circuit from figure 4 is recommended.
ads8325 13 sbas226a www.ti.com figure 7. change in offset and gain versus the difference between power-supply and reference voltage. figure 8. input reference circuit and its interface. 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 delta (mv) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 0 v dd to v ref (v) change in offset and gain vs supply/reference differential offset gain 100 ? opa340 20pf 47 f ads8325 5k ? v ref reference input the external reference sets the analog input range. the ads8325 will operate with a reference in the range of 2.5v to v dd . there are several important implications to this. as the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. this is often referred to as the least significant bit (lsb) size and is equal to the reference voltage divided by 65,536. this means that any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference voltage is reduced. for a reference voltage of 2.5v, the value of lsb is 38.15 v, and for reference voltage of 5v, the lsb is 76.3 v. the noise inherent in the converter will also appear to increase with lower lsb size. with a 5v reference, the internal noise of the converter typically contributes only 1.5lsbs peak-to-peak of potential error to the output code. when the external reference is 2.5v, the potential error contribution from the internal noise will be 2 times larger (3lsbs). the errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. for more information regarding noise, consult the typical characteristic peak-to-peak noise vs reference voltage. note that the effective number of bits (enob) figure is calculated based on the converter s signal-to-(noise + distor- tion) ratio with a 1khz, 0db input signal. sinad is related to enob as follows: sinad = 6.02 enob + 1.76 as the difference between the power-supply voltage and refer- ence voltage increases, the gain and offset performance of the converter will decrease. figure 7 shows the typical change in gain and offset as a function of the difference between the power-supply voltage and reference voltage. for the combina- tion of v dd = 2.7v and v ref = 2.5v, or v dd = 5v and v ref = 5v, offset and gain error will be minimal. the most dramatic difference in offset can be seen when v dd = 5v and v ref = 2.5v. with lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. due to the lower lsb size, the converter will also be more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. the equivalent input circuit for the reference voltage is presented in the figure 8. the 5k ? resistor presents a constant load during the conversion process. at the same time, an equivalent capacitor of 20pf is switched. to obtain optimum performance from the ads8325, special care must be taken in designing the interface circuit to the reference input pin. to ensure a stable reference voltage, a 47 f tantalum capacitor with low esr should be connected as close as possible to the input pin. if a high output impedance reference source is used, an additional operational amplifier with a current limiting resistor must be placed in front of the capacitors. when the ads8325 is in power-down mode, the input resis- tance of the reference pin will have a value of 5g ? . since the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic character- istics must be used to buffer the reference input. noise the transition noise of the ads8325 itself is extremely low (see figures 9 and 10); it is much lower than competing a/d converters. these histograms were generated by applying a low-noise dc input and initiating 5000 conversions. the digital output of the a/d converter will vary in output code due to the internal noise of the ads8325. this is true for all 16-bit, sar- type a/d converters. using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. the 1 , 2 , and 3 distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. the transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the 3 distribution, or 99.7%, of all codes. statistically, up to three codes could fall outside the distribution when executing 1000 conversions. the ads8325, with < 3 output codes for the 3 distribution, will yield a < 0.5lsbs of transition noise. remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50 v.
ads8325 14 sbas226a www.ti.com 7ffe 4005 7fff 476 519 8000 code 8001 0 0 7ffd v dd = 5.0v v ref = 5.0v 7ffe 3499 7fff 683 649 90 79 8000 code 8001 7ffd v dd = 2.7v v ref = 2.5v figure 9. 5000 conversion histogram of a dc input. figure 10. 5000 conversion histogram of a dc input. averaging the noise of the a/d converter can be compensated by averaging the digital codes. by averaging conversion results, transition noise will be reduced by a factor of 1/ n , where n is the number of averages. for example, averaging four conversion results will reduce the transition noise from 0.5lsb to 0.25lsb. averaging should only be used for input signals with frequencies near dc. for ac signals, a digital filter can be used to low-pass filter and decimate the output codes. this works in a similar manner to averaging; for every decimation by 2, the signal- to-noise ratio will improve 3db. digital interface signal levels the ads8325 has a wide range of power-supply voltage. the a/d converter, as well as the digital interface circuit, is designed to accept and operate from 2.7v up to 5.5v. this voltage range will accommodate different logic levels. when the ads8325 s power-supply voltage is in the range of 4.5v to 5.5v (5v logic level), the ads8325 can be connected directly to another 5v cmos integrated circuit. another possibility is that the ads8325 s power-supply volt- age is in the range of 2.7v to 3.6v. the ads8325 can be connected directly to another 3.3v lvcmos integrated cir- cuit. serial interface the ads8325 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the timing diagram and timing characteristics table. the dclock signal synchronizes the data transfer with each bit being transmitted on the falling edge of dclock. most receiving systems will capture the bitstream on the rising edge of dclock. however, if the minimum hold time for d out is acceptable, the system can use the falling edge of dclock to capture each bit. a falling cs signal initiates the conversion and data transfer. the first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. after the fifth falling dclock edge, d out is enabled and will output a low value for one clock period. for the next 16 dclock periods, d out will output the conversion result, most significant bit first. after the least significant bit (b0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format. after the most significant bit (b15) has been repeated, d out will tri-state. subsequent clocks will have no effect on the converter. a new conversion is initiated only when cs has been taken high and returned low. data format the output data from the ads8325 is in straight binary format (see figure 11). this figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise.
ads8325 15 sbas226a www.ti.com 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 straight binary digital output code vz = vcm = 0v 38.15 v 76.29 v 152.58 v 2.499962v 2.500038v vms = vcm + vref/2 = 2.5v unipolar analog input voltage 1lsb = 76.29 v vcm = 0v v ref = 5v 4.999847v vfs 1lsb = 4.999924v vfs = vcm + vref = 5v 0 1 2 32767 32768 32769 65533 65534 65535 step 16-bit zero code midscale code full-scale code straight binary output vz = 0000h vms = 8000h vfs = 7fffh unipolar analog input vcode = vcm vcode = vcm + vref/2 vcode = (vcm + vref) 1lsb figure 11. ideal conversion characteristics (condition: vcm = 0v, vref = 5v). power dissipation the architecture of the converter, the semiconductor fabrica- tion process, and a careful design, allow the ads8325 to convert at up to a 100khz rate while requiring very little power. however, for the absolute lowest power dissipation, there are several things to keep in mind. the power dissipation of the ads8325 scales directly with conversion rate. therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. in addition, the ads8325 is in power-down mode under two conditions: when the conversion is complete and whenever cs is high (see timing diagram). ideally, each conversion should occur as quickly as possible, preferably at a 2.4mhz clock rate. this way, the converter spends the longest possible time in the power-down mode. this is very important as the converter not only uses power on each dclock t ransition (as is typical for digital cmos components), but also uses some current for the analog circuitry, such as the comparator. the analog section dissipates power continuously until the power-down mode is entered. see figures 12 and 13 for the current consumption of the ads8325 versus sample rate. for these graphs, the con- verter is clocked at 2.4mhz regardless of the sample rate. cs is held high during the remaining sample period. there is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when cs is high. cs low will shutdown only the analog section. the digital section is completely shutdown only when cs is high. thus, if cs is left low at the end of a conversion, and the converter is continually clocked, the power consumption will not be as low as when cs is high.
ads8325 16 sbas226a www.ti.com 1000 100 10 1 current ( a) 10 100 sample rate (khz) power supply and reference current vs sample rate t a = 25 c v dd = 5.0v v ref = 5.0v f clk = 2.4mhz i ref i dd 1000 100 10 1 current ( a) 10 100 sample rate (khz) power supply and reference current vs sample rate t a = 25 c v dd = 2.7v v ref = 2.5v f clk = 2.4mhz i ref i dd figure 12. power-supply and reference current vs sample rate at v dd = 5v. figure 13. power-supply and reference current vs sample rate at v dd = 2.7v. short cycling another way to save power is to utilize the cs signal to short cycle the conversion. due to the ads8325 placing the latest data bit on the d out line as it is generated, the converter can easily be short cycled. this term means that the conversion can be terminated at any time. for example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling cs high ) after the 14th bit has been clocked out. this technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. for example, if the signal is outside a prede- termined range, the full 16-bit conversion result may not be needed. if so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. this results in lower power dissipation in both the converter and the rest of the system as they spend more time in power-down mode. layout for optimum performance, care should be taken with the physical layout of the ads8325 circuitry. this will be particularly true if the reference voltage is low and/or the conversion rate is high. at a 100khz conversion rate, the ads8325 makes a bit decision every 416ns. that is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. the basic sar architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. thus, during any single conversion for an n-bit sar converter, there are n windows in which large external transient voltages can easily affect the conversion result. such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few. this particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter s dclock si gnal as the phase difference between the two changes with time and temperature, causing sporadic misoperation. with this in mind, power to the ads8325 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close as possible to the ads8325 package. in addition, a 1 f to 10 f capacitor and a 5 ? or 10 ? series resistor may be used to low-pass filter a noisy supply. the reference should be similarly bypassed with a 47 f capaci- tor. again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. if the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). keep in mind that while the ads8325 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. texas instrument s opa627 op amp provides optimum perfor- mance for buffering both the signal and reference inputs. for low-cost, low-voltage, single-supply applications, the opa2350 or opa2340 dual op amps are recommended. also, keep in mind that the ads8325 offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50hz or 60hz) can be difficult to remove. the gnd pin on the ads8325 should be placed on a clean ground point. in many cases, this will be the analog ground. avoid connecting the gnd pin too close to the grounding point for a microprocessor, microcontroller, or digital signal proces- sor. if needed, run a ground trace directly from the converter to the power-supply connection point. the ideal layout will include an analog ground plane for the converter and associated analog circuitry.
ads8325 17 sbas226a www.ti.com application circuits figure 14 shows a basic data acquisition system. the ads8325 input range is connected to 2.5v or 4.096v. the 5 ? resistor and 1 f to 10 f capacitor filters the microcon- troller noise on the supply, as well as any high-frequency noise from the supply itself. the exact values should be picked such that the filter provides adequate rejection of noise. operational amplifiers and voltage reference are con- nected to analog power supply, av dd . figure 14. two examples of a basic data acquisition system. +in ads8325 100pf 50 ? in 0.1 f 5 ? cs d out dclock 47 f in gnd out 0.47 f ref v dd ref3025 av dd 2.7v to 5v dv dd 2.7v to 3.6v v cm + (0v to 2.5v) gnd gnd dsp tms320c6xx or tms320c5xx or tms320c2xx 0.1 f 10 f 10 f + + 100 ? opa340 opa340 100pf 50 ? v cm opa340 1nf +in ads8325 100pf 50 ? in 0.1 f 5 ? cs d out dclock 47 f in gnd out 0.47 f ref v dd ref3040 av dd 4.3v to 5.5v dv dd 4.5v to 5.5v 0v to 4.096v gnd gnd microcontroller or dsp 0.1 f 10 f 10 f + + 100 ? opa340 opa340
ads8325 18 sbas226a www.ti.com dgk (r-pdso-g8) plastic small-outline package 0,69 0,41 0,25 0,15 nom gage plane 4073329/c 08/01 4,98 0,25 5 3,05 4,78 2,95 8 4 3,05 2,95 1 0,38 1,07 max seating plane 0,65 m 0,08 0 C 6 0,10 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec mo-187 package drawing
ads8325 19 sbas226a www.ti.com package drawing (cont.)
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads8325ibdgkr active msop dgk 8 2500 none call ti level-1-220c-unlim ads8325ibdgkt active msop dgk 8 250 none call ti level-1-220c-unlim ads8325ibdrbr active son drb 8 2500 none cu snpb level-1-240c-unlim ads8325ibdrbt active son drb 8 250 none cu snpb level-1-240c-unlim ads8325idgkr active msop dgk 8 2500 none call ti level-1-220c-unlim ads8325idgkt active msop dgk 8 250 none call ti level-1-220c-unlim ads8325idrbr active son drb 8 2500 none call ti level-1-240c-unlim ADS8325IDRBT active son drb 8 250 none call ti level-1-240c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 9-dec-2004 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2004, texas instruments incorporated

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