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03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 24 ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram features ? 128k x 36 or 256k x 18 organizations ? cmos technology ? synchronous register latch mode of operation with self-timed late write ? single differential input and output clock ? +3.3v power supply, 1.9v v ddq , v ref & ground ? pseudo hstl input and output levels ? registered addresses, write enables, sync select and data ins ? common i/o ? asynchronous output enable and power down inputs ? boundary scan using limited set of jtag 1149.1 functions ? byte write capability & global write enable ? 7 x 17 bump ball grid array package with sram jedec standard pinout and boundary scan order ? programmable impedance output drivers description the ibm04184aqlad and ibm04364aqlad 4mb sram s are synchronous register latch mode, high performance cmos static random access memo- ries that are versatile, wide i/o, and achieve 5.0ns access and cycle times. dual differential k clocks are used to initiate the read/write operation, and all internal operations are self-timed. at the rising edge of the k clock, all addresses, write-enables, sync select, and data ins are registered internally. an internal write buffer allows write data to follow one cycle after addresses and controls. the chip is oper- ated with a +3.3v core power supply, has a 1.9v or 1.5v output power supply, and is compatible with hstl i/o interfaces and 1.5v i/o levels as well. .
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 24 03k4297.e35614 revised 2/99 x36 bga bump layout (top view) 1234567 a v ddq sa5 sa7 nc sa16 sa14 v ddq b nc nc sa8 nc sa11 nc nc c nc sa6 sa9 v dd sa10 sa15 nc d dqc18 dqc19 v ss zq v ss dqb10 dqb9 e dqc20 dqc21 v ss ss v ss dqb12 dqb11 f v ddq dqc22 v ss gv ss dqb13 v ddq g dqc23 dqc24 sbwc nc sbwb dqb15 dqb14 h dqc25 dqc26 v ss nc v ss dqb17 dqb16 j v ddq v dd v ref v dd v ref v dd v ddq k dqd34 dqd35 v ss kv ss dqa8 dqa7 l dqd32 dqd33 sbwd k sbwa dqa6 dqa5 m v ddq dqd31 v ss sw v ss dqa4 v ddq n dqd29 dqd30 v ss sa0 v ss dqa3 dqa2 p dqd27 dqd28 v ss sa1 v ss dqa1 dqa0 r nc sa4 m1* v dd m2* sa12 nc t nc nc sa3 sa2 sa13 nc zz u v ddq tms tdi tck tdo nc v ddq note: * m1 and m2 are clock mode pins. for this application, m1 and m2 must connect to v dd and v ss , respectively. x18 bga bump layout (top view) 1234567 a v ddq sa5 sa7 nc sa16 sa14 v ddq b nc nc sa8 nc sa11 nc nc c nc sa6 sa9 v dd sa10 sa15 nc d dqb9 nc v ss zq v ss dqa1 nc e nc dqb12 v ss ss v ss nc dqa2 f v ddq nc v ss gv ss dqa4 v ddq g nc dqb15 sbwb nc v ss nc dqa5 h dqb16 nc v ss nc v ss dqa8 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb17 v ss kv ss nc dqa7 l dqb14 nc v ss k sbwa dqa6 nc m v ddq dqb13 v ss sw v ss nc v ddq n dqb11 nc v ss sa0 v ss dqa3 nc p nc dqb10 v ss sa1 v ss nc dqa0 r nc sa4 m1 v dd m2 sa13 nc t nc sa2 sa3 nc sa17 sa12 zz u v ddq tms tdi tck tdo nc v ddq note: * m1 and m2 are clock mode pins. for this application, m1 and m2 must connect to v dd and v ss , respectively.
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 24 pin description sa0-sa17 address input g asynchronous output enable dq0-dq35 data i/o ss synchronous select k, k differential input register clocks m1, m2 clock mode inputs - selects single or dual clock operation. sw write enable, global v ref (2) gtl/hstl input reference voltage sbw a write enable, byte a (dq0-dq8) v dd power supply (+3.3v) sbw b write enable, byte b (dq9-dq17) v ss ground sbwc write enable, byte c (dq18-dq26) v ddq output power supply sbwd write enable, byte d (dq27-dq35) zz asynchronous sleep mode tms,tdi,tck ieee 1149.1 test inputs (lvttl levels) zq output driver impedance control tdo ieee 1149.1 test output (lvttl level) nc no connect block diagram 128k x 36 or 256k x 18 buffer write column decode read/write amp row decode 2:1 mux 2:1 mux data out latch dq0-dq35 wr add register rd add register match latch latch k zz sa0-sa17 sw sbw sbw register sbw register sw g register register ss ss ss sw register register array
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 24 03k4297.e35614 revised 2/99 sram features late write late write function allows for write data to be registered one cycle after addresses and controls. this feature will alleviate sram data bus contention going from a read to write cycle by eliminating one dead cycle. late write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. in case a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. during the first write cycle preceded by a read cycle, the sram array will be updated with address and data in the holding registers. read cycle addresses are monitored to deter- mine if read data is to be supplied from the sram array or the write buffer. the bypassing of the sram array occurs on a byte by byte basis. when one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the sram array. mode control mode control pins: m1 and m2 are used to select four different jedec standard read protocols. this sram supports the single clock register latch (m1 = v dd , m2 = v ss ). this data sheet only describes single differ- ential clock register latch functionality. mode control inputs must be set with power up and must not change during sram operation. power down mode power down mode or sleep mode is enabled by switching asynchronous signal zz high. when powering the sram down, inputs should be dropped first followed by v ref then v ddq ; v dd must be dropped last. v ddq can be simultaneously dropped with v dd . programmable impedance/power up requirements an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow for the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a toler- ance of 15% is between 175 w and 350 w . periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. one evaluation occurs every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a time toward the optimum level. the output driver has 32 discrete binary weighted steps. the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore triggering an update. the user may choose to invoke asyn- chronous g updates by providing a g setup and hold about the k clock to guarantee the proper update. power up requirements for the sram are that v dd must be powered before or simultaneously with v ddq fol- lowed by v ref ; inputs should be powered last. the limitation on v ddq is that it must not exceed v dd by more than 0.4v during power up. in order to guarantee the optimum internally regulated supply voltage, the sram requires 4 m s of power-up time after v dd reaches its operating range.to guarantee optimum output driver impedance after power up, the sram needs 2080 clock cycles followed by a single low-z to high-z transi- tion at the end of 2080 cycles. sleep mode operation sleep mode is a low power mode initiated by bringing the asynchronous zz pin high. during sleep mode, all other inputs are ignored and outputs are brought to a high-z state. sleep mode current and output high z are
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 24 guaranteed after the specified sleep mode enable time. during sleep mode, the array data contents are pre- served. sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated. sense amp data is lost. normal operation can be resumed by bringing zz low, but only after specified sleep mode recovery time. ordering information part number organization speed leads ibm04184aqlad-5p 256k x 18 5.0ns access / 5.0ns cycle 7 x 17 bga ibm04184aqlad-5 256k x 18 5.5ns access / 5.5ns cycle 7 x 17 bga ibm04184aqlad-6 256k x 18 6.0ns access / 6.0ns cycle 7 x 17 bga ibm04364aqlad-5p 128k x 36 5.0ns access / 5.0ns cycle 7 x 17 bga ibm04364aqlad-5 128k x 36 5.5ns access / 5.5ns cycle 7 x 17 bga IBM04364AQLAD-6 128k x 36 6.0ns access / 6.0ns cycle 7 x 17 bga
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 24 03k4297.e35614 revised 2/99 output enable truth table operation gdq read l d out 0-35 read h high-z sleep (zz=h) x high-z write ( sw=l) x high-z deselect ( ss=h) x high-z clock truth table k clk zz ss sw sbw a sbw b sbw c sbw d dq (n) dq (n+1) mode l ? h llhx x xx d out 0-35 x read cycle all bytes l ? h l l l l h h h high-z d in 0-8 write cycle 1st byte l ? h l l l h l h h high-z d in 9-17 write cycle 2nd byte l ? h l l l h h l h high-z d in 18-26 write cycle 3rd byte l ? h l l l h h h l high-z d in 27-35 write cycle 4th byte l ? h l l l l l l l high-z d in 0-35 write cycle all bytes l ? h l l l h h h h high-z high-z abort write cycle l ? h l h x x x x x high-z x deselect cycle x h x x x x x x high-z high-z sleep mode absolute maximum ratings item symbol rating units notes power supply voltage v dd -0.5 to 3.9 v 1 input voltage v in -0.5 to v dd +0.5 v1 output voltage v out -0.5 to v dd +0.5 v1 operating temperature t j 0 to +110 c 1 storage temperature t stg -55 to +125 c 1 short circuit output current i out 25 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability.
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 24 pbga thermal characteristics item symbol rating units thermal resistance junction to case r q jc 1 c/w ac input characteristics item symbol min max notes ac input logic high (volts) v ih (ac) v ref +0.4 3 ac input logic low (volts) vil (ac) v ref -0.4 3 clock input differential voltage (volts) v dif (ac) 0.4 2 v ref peak to peak ac voltage (volts) v ref (ac) 5% v ref (dc) 1 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . implies very stable signal. sourcing from v ddq not recommended. separate board plane recommended. do not use noisy signal line. 2. performance is a function on v ih and v il levels to clock inputs. 3. see ac input de?nition ?gure on page 9. ac input de?nition v ih (ac) v ref v il (ac)
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 24 03k4297.e35614 revised 2/99 recommended dc operating conditions (t a =0 to 85 c) parameter symbol min. typ. max. units notes supply voltage v dd 3.135 3.3 3.465 v 1 output driver supply voltage v ddq 1.4 1.9 2.0 v 1 input high voltage v ih v ref +0.1 v ddq + 0.3 v 1, 2 input low voltage v il -0.3 v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.90 v 1 clocks signal voltage v in - clk -0.3 v ddq + 0.3 v 1, 4 differential clocks signal voltage v dif - clk 0.1 v ddq + 0.6 v 1, 5 clocks common mode voltage v cm - clk 0.55 0.90 v 1 output current i out 5 8 ma 1. all voltages referenced to v ss . all v dd, v ddq and v ss pins must be connected. 2. v ih (max)dc = v ddq + 0.3v, v ih (max)ac = v dd + 1.5v (pulse width 4.0ns). 3. v il (min)dc = - 0.3v, v il (min)ac= -1.5v (pulse width 4.0ns). 4. v in-clk speci?es the maximum allowable dc excursions of each differential clock (k, k). 5. v dif-clk speci?es the minimum clock differential voltage required for switching. capacitance (t a =0 to 85 c, v dd =3.3v 5%, f=1mhz) parameter symbol test condition max units input capacitance c in v in = 0v 4pf data i/o capacitance (dq0-dq35) c out v out = 0v 5pf
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 24 dc electrical characteristics (t a = 0 to +85 c, v dd =3.3v 5%) parameter symbol min. max. units notes average power supply operating current- x36 (i out = 0, v in = v ih or v il , zz & ss = v il ) i dd5.0 i dd5.5 i dd6 675 650 575 ma 1 average power supply operating current - x18 (i out = 0, v in = v ih or v il , zz & ss = v il ) i dd5.0 i dd5.5 i dd6 625 600 525 ma 1 power supply standby current (zz= v ih , all other inputs = v ih or v il , i out = 0) ( ss=v ih , zz=v il , all other inputs=v ih or v il , i out =0) i sbzz i sbss 150 200 ma ma 1 1 input leakage current, any input (v in = v ss or v dd ) i li +1 m a output leakage current (v out = v ss or v dd , dq in high-z i lo +1 m a output high level voltage (i oh =-6ma @ v ddq / 2 + 0.3) v oh v ddq -.4 v ddq v2 output low level voltage (i ol =+6ma @ v ddq / 2 -0.3) v ol v ss v ss +.4 v2 1. i out = chip output current. i eyc means current at 5ns cycle time for example. 2. minimum impedance output driver. programmable impedance output driver dc electrical characteristics (t a = 0 to +85 c, v dd =3.3v 5%) parameter symbol min. max. units notes output high level voltage v oh v ddq / 2 v ddq v1 output low level voltage v ol v ss v ddq / 2 v2 1. i oh = (v ddq / 2) / (rq / 5) 15% @ v oh = v ddq / 2 for: 150 w rq 350 w . 2. i ol = (v ddq / 2) / (rq / 5) 15% @ v ol = v ddq / 2 for: 150 w rq 350 w .
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 24 03k4297.e35614 revised 2/99 ac test conditions (t a =0 to 85 c, v dd =3.3v 5%, v ddq =1.9v) parameter symbol conditions units notes input high level v ih 1.3 v input low level v il 0.4 v input reference voltage v ref 0.85 v differential clocks voltage v dif-clk 0.75 v clocks common mode voltage v cm-clk 1.3 v input rise time t r 0.5 ns input fall time t f 0.5 ns i/o signals reference level (except k clock) 0.85 v clocks reference level differential cross point v output load conditions 1 1. see ac test loading figure on page 10. ac test loading dq 0.85v 50 w 50 w 16.7 w 16.7 w 5pf 0.85v 50 w 50 w 16.7 w 5pf 0.85v
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 24 ac characteristics (t a =0 to +85 c, v dd = 3.3v 5%, v ddq = 1.9v, clocks run from 0.9 to 1.7v, v ref = 0.85). parameter symbol -5p -5 -6 units notes min. max. min. max. min. max. cycle time t khkh 5.0 5.5 6.0 ns clock high pulse width t khkl 1.5 1.5 1.5 ns clock low pulse width t klkh 1.5 1.5 1.5 ns clock high to output valid t khqv 5.0 5.5 6.0 ns 1 clock low to output valid t klqv 2.4 2.5 2.7 ns 1 address setup time t avkh 0.4 0.5 0.5 ns 3 address hold time t khax 1.0 1.0 1.5 ns sync select setup time tsvkh 0.5 0.5 0.5 ns sync select hold time t khsx 1.0 1.0 1.5 ns write enables setup time t wvkh 0.5 0.5 0.5 ns write enables hold time t khwx 1.0 1.0 1.5 ns data in setup time t dvkh 0.4 0.5 0.5 ns 3 data in hold time t khdx 0.8 1.0 1.5 ns clock low to data out hold time t klqx 0.5 0.5 0.5 ns 1 clock low to output active t klqx4 0.5 0.5 0.5 ns 1, 2 clock high to output high-z t khqz 2.5 2.5 2.5 ns 1, 2 output enable to high-z t ghqz 2.5 2.5 2.5 ns 1, 2 output enable to low-z t glqx 0.5 0.5 0.5 ns 1, 2 output enable to output valid t glqv 2.0 2.0 2.0 ns 1 sleep mode recovery time t zzr 5.0 5.5 6.0 ns sleep mode enable time t zze 5.0 5.5 6.0 ns 1. see ac test loading on page 12. 2. veri?ed by design and tested without guardband. 3. for the -5p sort, this spec is veri?ed by design to 0.4ns. strobed at 0.3ns
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 24 03k4297.e35614 revised 2/99 timing diagram (read and deselect cycles) k ss sw g dq sa t khkh q2 q3 q4 t klkh t khkl t avkh t khax t khwx t wvkh t ghqz t klqx t klqv t khqv t khqz a1 a3 a3 a4 a2 t klqv t klqx4 t klqv t khsx t svkh t glqv t khqv t khqz t glqx
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 24 timing diagram (read and write cycles) k ss sw g dq sa t khkh a3 d2 q3 d4 t klkh t khkl t khqv t svkh t khsx t khwx t wvkh t khqz t ghqz sbw t dvkh t khdx t klqv q2 a1 a2 a4 q1 notes: 1. d2 is the input data written in memory location a2. 2. q2 is output data read from the write buffer, as a result of address a2 being a match from the last write cycle address. t khwx t wvkh t wvkh t khwx t khwx t wvkh t dvkh t khdx t klqx4 t khqv t khqz a2 t avkh t khax
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 24 03k4297.e35614 revised 2/99 timing diagram (sleep mode) k zz dq t khkh t zzr t zze
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 24 ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions intended to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee std. 1149.1, the srams contain a tap controller, instruction register, boundary scan register, bypass register and id register. the tap controller has a standard 16-state state machine that resets internally upon power-up, therefore, trst signal is not required. signal list ? tck: test clock ? tms: test mode select ? tdi: test data in ? tdo: test data out caution: tck, tms, tdi inputs must be biased down, even if jtag is not used. tck tied off will not allow any data to be clocked in, however. jtag recommended dc operating conditions (t a =0 to 85 c) parameter symbol min. typ. max. units notes jtag input high voltage v ih1 2.2 v dd +0.3 v1 jtag input low voltage v il1 -0.3 0.8 v 1 jtag output high level v oh1 2.4 v 1, 2 jtag output low level v ol1 0.4 v 1, 3 1. all jtag inputs/outputs are lvttl compatible only. 2. i oh1 = -8ma at 2.4v. 3. i ol1 = +8ma at 0.4v. jtag ac test conditions (t a =20 to 85 c, v dd =3.3v 5%) parameter symbol conditions units notes input pulse high level v ih1 3.0 v input pulse low level v il1 0.0 v input rise time t r1 2.0 ns input fall time t f1 2.0 ns input and output timing reference level 1.5 v 1 1. see ac test loading figure on page 10.
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 24 03k4297.e35614 revised 2/99 jtag ac characteristics (t a =0 to 85 c, v dd =3.3v 5%) parameter symbol min. max. units notes tck cycle time t thth 20 ns tck high pulse width t thtl 7 ns tck low pulse width t tlth 7 ns tms setup t mvth 4 ns tms hold t thmx 4 ns tdi setup t dvth 4 ns tdi hold t thdx 4 ns tck low to valid data t tlov 7 ns 1 1. see ac test loading figure on page 10. jtag timing diagram tck tms tdi tdo t thtl t tlth t thth t thmx t mvth t dvth t thdx t tlov .
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 24 list of ieee 1149.1 standard violations: ? 7.2.1.b, e ? 7.7.1.a-f ? 10.1.1.b, e ? 10.7.1.a-d scan register de?nition register name bit size x18 bit size x36 instruction 3 3 bypass 1 1 id 32 32 boundary scan * 51 70 * the boundary scan chain consists of the following bits: ? 36 or 18 bits for data inputs depending on x18 or x36 con?guration ? 17 bits for sa0 - sa16 for x36, 18 bits for sa0 - sa15 for x18 ? 4 bits for sbw a - sbwd in x36, 2 bits for sbw a and sbwb in x18 ? 9 bits for k, k, zq, ss, g, sw, zz, m1 and m2 ? 4 bits for place holders * k and k clocks connect to a differential receiver that generates a single-ended clock signal. this signal and its inverted value are used for boundary scan sampling. id register de?nition part field bit number and description revision number (31:28) device density and con?guration (27:18) vendor de?nition (17:12) manufacture jedec code (11:1) start bit (0) 256k x 18 0001 011 100 1011 001000 000 101 001 00 1 128k x 36 0001 011 010 1100 001000 000 101 001 00 1 instruction set code instruction notes 000 sample-z 1, 5 001 idcode 2 010 sample-z 1, 5 011 private 100 sample 4, 5 101 private 110 private 111 bypass 3 1. places dqs in high-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the ?rst id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to vss when bypass instruction is invoked. the bypass register also holds the last serially load ed tdi when exiting the shift dr state. 4. sample instruction does not place dqs in high-z. 5. sram must not be in sleep mode (zz = h) when sample-z or sample instructions are invoked.
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 24 03k4297.e35614 revised 2/99 boundary scan order (x36) (ph =place holder) exit order signal bump # exit order signal bump # exit order signal bump # 1 m2 5r 25 dq13 6f 49 dq26 2h 2 sa1 4p 26 dq11 7e 50 dq25 1h 3 sa2 4t 27 dq12 6e 51 sbwc 3g 4 sa12 6r 28 dq9 7d 52 zq 4d 5 sa13 5t 29 dq10 6d 53 ss 4e 6 zz 7t 30 sa14 6a 54 c=0 2 4g 7 dq1 6p 31 sa15 6c 55 c=1 2 4h 8 dq0 7p 32 sa10 5c 56 sw 4m 9 dq3 6n 33 sa16 5a 57 sbwd 3l 10 dq2 7n 34 ph 1 6b 58 dq34 1k 11 dq4 6m 35 sa11 5b 59 dq35 2k 12 dq6 6l 36 sa8 3b 60 dq32 1l 13 dq5 7l 37 ph 1 2b 61 dq33 2l 14 dq8 6k 38 sa7 3a 62 dq31 2m 15 dq7 7k 39 sa9 3c 63 dq29 1n 16 sbwa 5l 40 sa6 2c 64 dq30 2n 17 k 4l 41 sa5 2a 65 dq27 1p 18 k 4k 42 dq19 2d 66 dq28 2p 19 g 4f 43 dq18 1d 67 sa3 3t 20 sbwb 5g 44 dq21 2e 68 sa4 2r 21 dq16 7h 45 dq20 1e 69 sa0 4n 22 dq17 6h 46 dq22 2f 70 m1 3r 23 dq14 7g 47 dq24 2g 24 dq15 6g 48 dq23 1g 1. input of ph register connected to v ss . 2. balls 4g and 4h are unused c clock pins in this application
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 24 boundary scan order (x18) (ph =place holder) exit order signal bump # exit order signal bump # 1m25r27 ph 1 2b 2 sa12 6t 28 sa7 3a 3 sa1 4p 29 sa9 3c 4 sa13 6r 30 sa6 2c 5 sa17 5t 31 sa5 2a 6 zz 7t 32 dq9 1d 7 dq0 7p 33 dq12 2e 8 dq3 6n 34 dq15 2g 9 dq6 6l 35 dq16 1h 10 dq7 7k 36 sbwb 3g 11 sbwa 5l 37 zq 4d 12k4l38ss4e 13 k 4k 39 c=0 2 4g 14 g 4f 40 c=1 2 4h 15 dq8 6h 41 sw 4m 16 dq5 7g 42 dq17 2k 17 dq4 6f 43 dq14 1l 18 dq2 7e 44 dq13 2m 19 dq1 6d 45 dq11 1n 20 sa14 6a 46 dq10 2p 21 sa15 6c 47 sa3 3t 22 sa10 5c 48 sa4 2r 23 sa16 5a 49 sa0 4n 24 ph 1 6b 50 sa2 2t 25 sa11 5b 51 m1 3r 26 sa8 3b 1. input of ph register connected to v ss . 2. balls 4g and 4h are unused c clock pins in this application
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 24 03k4297.e35614 revised 2/99 tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 24 7 x 17 bga dimensions plate 0.71 0.05 typ 0.701 0.099 2.549 0.13 under ?ll 0.1778 ref note: all dimensions in millimeters unless otherwise noted 22.00 1 2 3 4 5 6 7 7.62 1.27 20.32 (119x) ? 0.89 0.04 solder ball utrpn ml k j h f gedcb a 0.035 0.0015(mils) 0.84 ref 3.19 ref indicates a1 location under ?ll 16.764 plate chip 0.625.254 12.7 ref structural adhesive 14.00
ibm04184aqlad ibm04364aqlad 128k x 36 & 256k x 18 sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 24 03k4297.e35614 revised 2/99 references rev d - last character in part number (d) the following documents give recommendations, restrictions, and limitations for 2nd level attach process: c4 sram assembly guide for single sided assembly double sided 4meg coupled cap pbga card assembly guide qualification information, including scope of application conditions qualified, is available from your marketing representative.
ibm04184aqlad ibm04364aqlad preliminary 128k x 36 & 256k x 18 sram 03k4297.e35614 revised 2/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 24 revision log rev contents of modi?cation 9/97 initial release 11/97 added -5p sort. 5/98 updated -5p sort. added tri-state timing test definition. 6/98 updated ac input data. changed programmable impedance tolerance to 15% and 2080 max cycle update. changed rev b to rev d. added references for rev d and changed package diagram. added sleep mode statement. updated mode pins. minor boundary scan update. 2/99 tightened the bga ball diameter tolerance.
intern ational business machines corp.1999 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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