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? 1994 mos integrated circuit m pd16430a 1/2, 1/3, 1/4 duty lcd controller/driver document no. ic-2776 (1st edition) (o.d. no. ic-8302) date published march 1997 n printed in japan the m pd16430a is an lcd controller/driver that enables the display of lcds of 1/2 duty, 1/3 duty and 1/4 duty cycle. the lcd controller contained in the m pd16430a employs serial data transfer and uses an automatic increment function for data addresses which eliminates the need to set addresses newly each time. the lcd driver uses a medium voltage output (14 v max.), which enables higher contrast and a wider viewing angle even with a 1/3 or 1/4 duty cycle. by using an on-chip drive bias circuit, it is possible to eliminate the need for external resistors. features ? lcd direct drive (medium voltage output: 14 v max.) ? choice of 3 duty cycles 1/2 duty, 1/3 duty, 1/4 duty ? display dot number: 1/2 duty: 120 1/3 duty: 160 1/4 duty: 240 ? 2 types of drive bias 1/2 bias, 1/3 bias ? choice of 4 types of frame frequency ? multi-chip configuration possible ? control through 8-bit serial interface ? on-chip power-on reset circuit ? low-power dissipation cmos ? 3.5 to 6.0 v logic supply voltage ordering information part number package m pd16430agf-3b9 80-pin plastic qfp (14 20)
m pd16430a 2 pin configuration (top view) com1 com0 lcd59 lcd58 lcd57 lcd56 lcd55 lcd54 lcd53 lcd52 lcd51 lcd50 lcd49 lcd48 lcd47 lcd46 lcd45 lcd44 lcd43 lcd42 lcd41 lcd40 lcd39 lcd38 lcd0 lcd1 lcd2 lcd3 lcd4 lcd5 lcd6 lcd7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 lcd16 lcd17 lcd18 lcd19 lcd20 lcd21 lcd22 lcd23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 lcd24 lcd25 lcd26 lcd27 lcd28 lcd29 lcd30 lcd31 nc v ss lcd32 lcd33 lcd34 lcd35 lcd36 lcd37 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dd lcdoff busy clk data stb sync v ss osc out osc in v lcd v lc0 v lc1 v lc2 com3 com2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 remark be sure to leave pin 33 open since it is connected to the lead frame.
m pd16430a 3 pin functions no. symbol i/o output type description 1 lcd0 output cmos these pins serve as the lcd drivers segment signal output pins. to to the following display modes can be selected for the lcd driver. 32 lcd31 35 lcd32 to to 62 lcd59 a matrix of these segment signal output pins and com3, com2, com1 and com0 pins enables the maximum display of 240 dots (1/4 duty selected). the output voltage of the segment signal output pins is supplied by the v lcd pin. the output voltage of the segment signal output pin is supplied by dividing and outputting 0 to v lcd voltage using any driving method (any bias method). either internal or external voltage dividing resistor can be selected. 63 com0 output cmos these pins serve as the lcd drivers common signal output pins. to to the lcd driver can select three display modes. 66 com3 a matrix of these common signal output pins and lcd59 through lcd0 pins enables the maximum display of 240 dots (1/4 duty selected). the output voltage of the common signal output pins is supplied by the v lcd pin. v dd to 14 v voltage is supplied by this pin. the output voltage of the common signal output pins is supplied by dividing and outputting 0 to v lcd voltage using any driving method (any bias method). either internal or external dividing resistor can be selected. 67 v lc2 these pins serve as the lcd drivers drive voltage generation pins. 68 v lc1 the drive voltage can be set by using either these pins or the on-chip 69 v lc0 drive voltage generation circuit, as specified by command data. 70 v lcd this pin supplies the lcd drivers supply voltage. v dd to 14 v voltage is supplied to this pin. the output voltage of the segment signal and command signal output pins is supplied by dividing and outputting the voltage applied to these pins using any driving method (any bias method). do not supply a voltage exceeding v dd to the v lcd pin before the devices supply voltage reaches 3.5 v, as this may cause incorrect display. duty bias display frame frequency (hz) dot no. (fosc = 140 khz) 1/2 1/2 120 fosc fosc fosc fosc 256 , 512 , 1024 , 2048 (547) (273) (137) (68) 1/3 1/3 160 fosc fosc fosc fosc 384 , 768 , 1536 , 3072 (365) (182) (91) (46) 1/4 1/3 240 fosc fosc fosc fosc 512 , 1024 , 2048 , 4096 (273) (137) (68) (34)
m pd16430a 4 no. symbol i/o output type description 71 osc in i/o cmos these pins serve to connect the resistors of the system clock rc oscillator. 72 osc out 70 100 k w osc in 71 osc out when several devices are used, connect as follows: 70 100 k w osc in 71 osc out 70 osc in 71 osc out 34 v ss gnd pin for device. 73 74 sync i/o nch synchronous signal i/o pin. open drain this pin is used to synchronize two or more m pd16430as. at this time, each chip must be wire-ored and a pull-up resistor (5 k to 10 k w ) is required. this pin must be pulled up even when only one m pd16430a is used. 75 stb input strobe signal input pin for devices select signal and serial communica- tions. this pin serves to latch display ram data outputs, set the command data receive mode and initialize serial communications. serial communication is enabled when this signal is a logic low. when this pin is a logic high, shift clocks that are input are ignored. (1) display ram data output buffer latch function the internal display ram data output is latched to the output latch circuit at the rising edge of the stb signal when the busy pin outputs a logic high. however, latch timing depends on the latch md and latch flags. the latch time is 504.5/f osc . when the busy signal is a logic low, latching can cause incorrect display. (2) command data receive mode setting the command data receive mode is set by the rising edge of the stb signal when the busy pin outputs a logic high. once the command data receive mode is set, the initial byte (8 bits) is processed as a command. the command data processing time is approximately 300 ns. the busy signal does not change during this time. (3) serial communication is initialized by the rising edge or the falling edge of the stb signal when the busy pin outputs a logic low. once serial communication is initialized, the command data receive mode is started. during command data decoding or display data ram interrupt, the stb signal interrupts processing and initializes serial communications. at this time, all displays are turned off (lcdon flag is reset). 76 data input this pin inputs serial data for serial communication at the rising edge of the shift clock. 77 clk input this pin inputs a shift clock for serial communication. the signal is output at the rising edge of the shift clock signal.
m pd16430a 5 no. symbol i/o output type description 78 busy output nch this pin outputs the serial communication status and the internal data open drain processing status. when this signal is a logic high, serial communication is executed. when this signal is a logic low, it indicates that the display ram data is latched to the output buffer. when the power-on reset circuit is operating, this pin holds a logic low until a rising or falling signal is input to the stb pin. 79 lcdoff input this pin serves to turn off all the lcd displays. when a logic low is input to this pin, all lcd displays are turned off. display ram data is maintained. since displays are turned off only by the output driver, serial communica- tions can be executed as usual. to turn on displays, it is necessary to input a logic high to this pin and reset the lcdon flag. 80 v dd this pin is a power supply pin to the device. a voltage of 3.5 to 6.0 v is supplied to this pin. when the supply voltage rises from 0 v to 3 v, or when it reaches a value under 3 v and then rises again, the power-on reset circuit starts operating and the device is set to its initialized state. when the device is in its initialized state, all displays are turned off (segment and common signals are fixed to v lcd ). do not supply a voltage higher than v dd to the v lcd pin before the supply voltage reaches 3.5 v as this will cause incorrect display.
m pd16430a 6 block diagram segment driver (2 60 circuits) level shifter (60 circuits) selector (60 circuits) output data latch (4 60 bits) latch pulse generator (60 bits) data selector read address counter write address counter 8 bit shift register common driver level shifter selector drive voltage genera- tion circuit timing controller oscillator power-on detector command register command decoder write controller 0 1 2 3 0 1 2 3 lcd59 lcd0 com3 com0 v lcd v lcd0 v lcd1 v lcd2 lcdoff res res res osc in osc out v dd v ss res 29 0 29 0 display memory ram 8 30 bits res 0 1 2 3 busy stb data clk
m pd16430a 7 display ram addresses and display dots display ram temporarily stores display data that has been sent serially. display ram addresses are allocated in units of 8 bits (group address), and it is possible to store the display data of a group address transferred at one time. the relations between group addresses and display dots for the three display modes are shown below. (1) 1/2 duty com1 com2 group address 0 1 2 3 4 9 1 0 3 2 lcd 0 lcd 1 lcd 2 lcd 3 lcd 4 lcd 5 lcd 6 lcd 7 lcd 8 lcd 9 lcd 56 lcd 57 lcd 58 lcd 59 lcd 55 10 11 12 13 14 5 4 7 6 (2) 1/3 duty com2 com1 com0 group address 0 1 2 3 4 5 12 13 2 1 0 5 4 3 lcd 0 lcd 1 lcd 2 lcd 3 lcd 4 lcd 5 lcd 6 lcd 7 lcd 8 lcd 9 lcd 56 lcd 57 lcd 58 lcd 59 lcd 55 7 6 14 15 16 17 18 19 the shaded parts are always 1. (3) 1/4 duty com3 com2 com1 com0 group address 0 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 3 2 1 0 7 6 5 4 lcd 0 lcd 1 lcd 2 lcd 3 lcd 4 lcd 5 lcd 6 lcd 7 lcd 8 lcd 9 lcd 56 lcd 57 lcd 58 lcd 59 lcd 55 remark during auto incrementing, incrementing past the last group address of each duty (for example group address 14 in the case of 1/2 duty) brings the counter back to 0.
m pd16430a 8 commands commands serve to set the lcd drivers display mode and status. the first byte (8 bits) after the falling edge input of the stb signal is processed as a command. the various types of commands are shown below. (1) display mode setting command msb 0 0 ? ? ? ? ? ? ? ? f r c k 1 f r c k 0 l c d m d 1 l c d m d 0 lsb frame frequency setting flag 00 : (f osc /128) n, n = duty (1/2, 1/3, 1/4) 01 : (f osc /256) n 10 : (f osc /512) n 11 : (f osc /1024) n display mode setting flag 00 : 1/2 duty, 1/2 bias 01 : 1/2 duty, 1/2 bias 10 : 1/3 duty, 1/3 bias 11 : 1/4 duty, 1/3 bias don? care values at power-on reset
m pd16430a 9 (2) data setting command msb 0 1 ? ? ? 0 0 0 0 ? l a t c h m d a d d r i n c r / w m d 1 r / w m d 0 lsb sets data address increment mode. 0 : auto increment (increments group address after input/output of 8 bits of data) 1 : holds address even after data input/output. sets data latch mode. 0 : depends on latch flag of status setting command. 1 : latches to output buffer at the rising edge of the stb signal immediately after data input. sets data write mode 00 : write 01 : write 10 : setting prohibited 11 : setting prohibited don? care values at power-on reset
m pd16430a 10 (3) status setting command msb 1 0 0 0 0 0 0 0 l c d e x t e s t 1 t e s t 0 a d d r r e s l a t c h l c d o n lsb resets group address. 0 : does not reset group address. 1 : resets group address at rising edge of stb signal following data write (000000b). sets drive voltage supply method. 0 : external 1 : internal turns on all displays. (no display unless logic high is input to lcdoff pin) 0 : all displays are turned off at the rising edge of the stb signal immediately after this command is input. 1 : all displays are turned on at the rising edge of the stb signal immediately after this command is input. sets method for latching to ram data output buffer note 0 : does not latch ram data to output buffer. 1 : latches to output buffer at every rising edge of stb signal. sets test mode. 00 : normal operation (master) 01 : normal operation (slave) 10 : test mode 11 : test mode values at power-on reset remark latch md flag and latch flag the relations between the latch md flag and the latch flag are shown below. mode latch md latch operation 1 0 0 does not latch ram data to output buffer. 2 0 1 latches every time to output buffer at rising edge of stb signal. 3 1 0 latches to output buffer at rising edge of stb signal immediately after data input. 4 1 1 latches every time to output buffer at rising edge of stb signal. in modes 2 and 4, since latching to the output buffer is executed at the rising edge of the stb signal when only a command has been issued from the stb pin, busy status comes at each rising edge of the stb signal.
m pd16430a 11 (4) address setting command msb 1 1 0 ? 0 0 0 0 0 b4 b3 b2 b1 b0 lsb sets ram group address. 000000 to 001110 (1/2 duty) 000000 to 010011 (1/3 duty) 000000 to 011101 (1/4 duty) values at power-on reset
m pd16430a 12 data transmission format <1> start serial communications by setting stb signal to logic low <2> internal processing time = 300 ns <3> transmit mode setting command if initialized (duty cycle and others) <4> internal processing time = 300 ns <5> wait for command data input after input of stb signal <6> input data write method or address setting command <7> transmit (receive) ram data specified by set address <8> transmit (receive) ram data specified by set address <9> input data write method or address setting command <10> execute ram data latch or display enable by rising stb pin. <11> output logic low from busy pin during data latching. the time is 504.5/f osc . command data clk stb busy command data <4> <7> <4> <6> <5> <4> <3> <2> <1> data command <8> <4> <5> <9> <4> <10> 504.5/f osc
m pd16430a 13 power-on reset 1) device operation <1> apply supply voltage v dd . <2> when v dd becomes higher than power-on reset voltage, device starts operating. <3> device stabilization time (less than 10 ms for internal oscillator) during this time, do not execute stb pin input. <4> after oscillation stabilization time is over, an stb signal input is waited for. <5> when a logic high or logic low stb signal is input, a logic high is output from the busy pin, and a command input is waited for. <6> a command input is waited for. <7> when v dd becomes again a value lower than the power-on reset voltage, device operation stops. <8> when v dd becomes again a value higher than the power-on reset voltage, device operation starts. <9> oscillation stabilization time (less than 10 ms for internal oscillator). <10> after oscillation stabilization time is over, an stb signal input is waited for. <11> when a logic high or logic low stb signal is input, a logic high is output from the busy pin, and a command input is waited for. <12> a command input is waited for. 2) functions of power-on reset (1) turns off all displays. (2) initializes serial communication. v dd internal poc osc1 busy <1> power-on reset voltage (3 v) stb <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
m pd16430a 14 application data transmission examples according to address increment mode command 1 data clk stb command 2 command 3 data 1 data n-1 data n command 1 0 0 ? ? 0 0 1 0 1/3 duty, 1/3 bias frame frequency: (f osc /128) (1/3) don? care command 2 0 1 ? ? 1 0 0 0 data write mode data address increment mode don? care latches to output buffer at rising edge of stb signal immediately after data input command 3 1 0 0 0 1 1 0 1 display on doesn? latch ram data to output buffer normal operation internal drive voltage resets ram group address data 1 to n b7 b6 b5 b4 b3 b2 b1 b0 display data (when v dd is applied, data address is initialized to 000000b because the address increment mode is selected, the address is incremented every time 8 bits of data are input, and the next data input is waited for.)
m pd16430a 15 absolute maximum ratings (t a = 25 c, gnd = 0 v) parameter symbol condition rating unit logic supply voltage v dd C0.3 to +7.0 v logic input voltage v i1 C0.3 to v dd +0.3 v logic output voltage v o1 C0.3 to v dd +0.3 v driver supply voltage v lcd C0.3 to +16 v driver input voltage v lc0 - v lc2 C0.3 to v lcd + 0.3 v driver output voltage v o2 C0.3 to v lcd + 0.3 v operating temperature range t opt C40 to +85 c storage temperature range t stg C65 to +150 c permissible package power dissipation p d 1000 mw recommended operating conditions (t a = C40 to +85 c, gnd = 0 v) parameter symbol condition min. typ. max. unit logic supply voltage v dd 3.5 6.0 v driver supply voltage v lcd v dd 14 v driver input voltage v lc0 - v lc2 0v lcd v electrical characteristics (t a = C40 to +85 c, v dd = 5 v 10 %, v lcd = 9 to 12 v) parameter symbol condition min. typ. max. unit input voltage, high v ih 0.7v dd v dd v input voltage, low v il 0 0.3v dd v output voltage, high v oh osc out , sync, busy 0.9v dd v i oh = C1 ma output voltage, low v ol osc out , sync, busy 0.1v dd v i ol = 1 ma input leak current, high i ih v in = v dd 10 m a input leak current, low i il v in = 0 v C10 m a output leak current, high i loh sync, busy 10 m a v o = v dd output leak current, low i lol sync, busy C10 m a v o = 0 v common output on resistance r com com0 - com3, v lcd = 9 v 1.2 2.4 k w llol = 100 m a segment output on resistance r seg lcd0 - lcd59, v lcd = 9 v 2.0 4.0 k w llol = 100 m a logic current dissipation i dd f osc = 140 khz 100 500 m a driver current dissipation i lcd v lcd = 12 v, without load 500 1000 m a
m pd16430a 16 switching characteristics (t a = C40 to +85 c, v dd = 5 v 10 %, v lcd = 9 to 12 v, r l = 5 k w , c l = 150 pf) parameter symbol condition min. typ. max. unit oscillation frequency f soc r = 100 k w 98 140 182 khz busy delay time t dbsy stb - ? busy 1.5 m s sync delay time t dsync 1.5 m s timing requirements (t a = C40 to +85 c, v dd = 5 v 10 %, v lcd = 9 to 12 v, r l = 5 k w , c l = 150 pf) parameter symbol condition min. typ. max. unit clock frequency fc osc in external clock 50 150 khz high-level clock pulse width t whc osc in external clock 3 16 m s low-level clock pulse width t wlc osc in external clock 3 16 m s shift clock cycle t cyk clk 900 ns high-level shift clock pulse width t whk clk 400 ns low-level shift clock pulse width t wlk clk 400 ns data setup time t ds 100 ns data hold time t dh 200 ns stb removal time t rstbk stb ? clk - 300 ns stb hold time t hkstb from the 8th clk pulse 1 m s high-level stb pulse width t whstb 1 m s low-level stb pulse width t wlstb 8.2 m s sync removal time t srem 250 ns output load circuit v dd 5 k w 150 pf output
m pd16430a 17 switching characteristic waveform measurement points: input: 0.7 v dd , 0.3 v dd output: 0.8 v dd , 0.2 v dd t wlstb 1/fc t whc t wlc t whstb t rstbk t hkstb t cyk t wlk t whk t ds t dh sync timing (master) 1 frame 1 frame t dsync f osc sync internal reset sync timing (slave) 1 frame 1 frame t srem data clk stb osc in
m pd16430a 18 stb t dbsy busy
m pd16430a 19 application circuit example 5 v 5 v microcontroller lcd controller/driver lcd, com lcd panel 5 v for driver lcdoff busy data clk stb osc in sync osc out v dd v lcd multi-chip configuration osc in sync power detection v dd acc power battery remark use low-v f diodes such as schottky-barrier diodes, and make sure that v dd , v lcd , v i , etc. do not exceed absolute maximum ratings of the diodes. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
m pd16430a 20 1. m pd16430a external bias resistor setting method v lcd v dd up to 14 v v lc0 v lc1 v lc2 en vr = v lc 1/2 bias 2 (v lcd ?v lc ) (h = display on) lcdoff pd16430a r r vr m v lcd v dd up to 14 v v lc0 v lc1 v lc2 en vr = v lc 1/3 bias 3 (v lcd ?v lc ) (h = display on) lcdoff pd16430a r r r vr m v lc is the peak value of the optimum drive voltage for lcd. (it varies depending on the lcd.) r is a resistance of 1 k w to 10 k w . select the resistance value according to the load. a larger value for r reduces the power dissipation, but causes drive waveform distortions. select a largish value for a variable resistor so as to satisfy the equation above. 2. when using internal bias a heavy lcd load may cause distortions in the common waveform. in this case, insert a capacitor for v lc0 , v lc1 and v lc2 . pd16430a m m v lcd v dd up to 14 v c = 0.001 to 0.1 f v lc2 v lc1 v lc0
m pd16430a 21 characteristic curves f osc - r characteristics oscillation frequency f osc (hz) external resistor r ( w ) 100 k 200 k 300 k 400 k 500 k 0 100 k 200 k v dd = +5 v t a = +25 ? oscillation frequency f osc (hz) f osc - v dd , t a characteristics temperature t a (?) ?0 25 85 v dd = 5.5 v r = 100 k w v dd = 3.5 v v dd = 4.5 v 100 k 10 k v dd = 5.0 v recommended soldering conditions when soldering on this product, please observe the recommended conditions indicated in the table below. if planning to solder under different conditions, please consult an nec sales representative. m pd16430agf-3b9 soldering method soldering conditions symbol infrared ray reflow peak package temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-00-2 number of reflow processes: 2, exposure limit: none note vps peak package temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-2 number of reflow processes: 2, exposure limit: none note wave soldering solder temperature: 260 c max., time: 10 seconds max. ws60-00-1 number of reflow processes: 1, exposure limit: none note partial heating pin temperature: 300 c max., time: 10 seconds max., exposure limit: none note note exposure limit before soldering after dry-package is opened. storage conditions: 25 c, relative humidity of 65 % or less. caution do not apply two or more soldering methods (except partial heating) in combination.
m pd16430a 22 item millimeters inches g q f 1.8 0.125?.075 1.0 s 0.031 0.005?.003 0.039 s80gf-80-3b9-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 3.0 max. 0.119 max. d 17.2?.2 0.677?.008 r5 ? 5 ? b 20.0?.2 0.787 +0.009 ?.008 a 23.2?.2 0.913 +0.009 ?.008 80 pin plastic qfp (14 20) c 14.0?.2 0.551 +0.009 ?.008 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.35?.10 0.014 +0.004 ?.005 p 2.7 0.106 n 0.10 0.004 l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 +0.004 ?.003 k 1.6?.2 0.063?.008 +0.10 ?.05 detail of lead end m 64 65 40 80 1 25 24 41 a b c d f g h i j k m l n p s q r
m pd16430a 23 [memo]
m pd16430a 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 [memo]

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