this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. addendum to coldfire 2/2m user manual coldfire 2/2m 1998 motorola, inc. all rights reserved. communications and advanced consumer technologies group consumer systems group semiconductor product information revision 0.0 april 14, 1998 this addendum to the coldfire 2/2m user?s manual provides corrections to the original text, plus additional information not included in the original. this document and other information on this product is maintained on the world wide web at http://sps.motorola.com/coldfire. instruction set architecture the instruction set summary shown on pages 1-19 through 1-23 should be replaced with the follow- ing : notational conventions opcode wildcards cc logical condition (example: ne for not equal) register operands an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rn any address or data register ry,rx any source and destination registers, respectively rw any second destination register rc any control register (example vbr is the vector base register) register/port names acc mac accumulator ddata debug data port ccr condition code register (lower byte of status register) macsr mac status register mask mask register pc program counter pst processor status port sr status register miscellaneous operands # immediate data following the instruction word(s) effective address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
y,x source and destination effective addresses, respectively assembly program label list of registers (example: d3ed0) operand data size: byte (b), word (w), longword (l) operations + arithmetic addition or postincrement indicator e arithmetic subtraction or predecrement indicator x arithmetic multiplication / arithmetic division ~ invert; operand is logically complemented & logical and | logical or ~ logical exclusive or << shift left (example: d0 << 3 is shift d0 left 3 bits) >> shift right (example: d0 >> 3 is shift d0 right 3 bits) ? source operand is moved to destination operand ?? two operands are exchanged sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion if then else test the condition. if true, the operations after ?then? are performed. if the condition is false and the optional ?else? claus e is present, the operations after ?else? are performed. if the condition is false and else is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. subfields and qualifiers {} optional operation () identifies an indirect address d n displacement value, n-bits wide (example: d 16 is a 16-bit displacement) address calculated effective address (pointer) bit bit selection (example: bit 3 of d0) lsb least significant bit (example: msb of d0) lsw least significant word msb most significant bit msw most significant word condition code register bit names p branch prediction bit in ccr c carry bit in ccr n negative bit in ccr v overflow bit in ccr x extend bit in ccr z zero bit in ccr notational conventions (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
x y,dx 32 32 source + destination ? destination adda y,ax 32 source + destination ? destination addi #,dx 32 immediate data + destination ? destination addq #,x 32 immediate data + destination ? destination addx dy,dx 32 source + destination + x ? destination and dy,x y,dx 32 32 source & destination ? destination andi #,dx 32 immediate data & destination ? destination asl dx,dy #,dx 32 32 x/c ? (dy << dx) ? 0 x/c ? (dy << #) ? 0 asr dx,dy ,dx 32 32 msb ? (dy >> dx) ? x/c msb ? (dy >> #) ? x/c bcc 8,16 if condition true, then pc + d n ? pc bchg dy,x #,x 8,32 8,32 ~( of destination) ? z, bit of destination bclr dy,x #,x 8,32 8,32 ~( of destination) ? z; 0 ? bit of destination bra 8,16 pc + d n ? pc bset dy,x #,x 8,32 8,32 ~( of destination) ? z; 1? bit of destination bsr 8,16 sp e 4 ? sp; next sequential pc ? (sp); pc + d n ? pc btst dy,x #,x 8,32 8,32 ~( of destination) ? z clr x 8,16,32 0 ? destination cmpi #,dx 32 destination e immediate data cmp y,dx 32 destination e source cmpa y,ax 32 destination - source cpush (an) 32 push and invalidate cache line divs y,dx 16 32 dx / y ? dx {16-bit remainder; 16-bit quotient} dx / y ? dx {32-bit quotient} signed operation divu y,dx 16 dx / y ? dx {16-bit remainder; 16-bit quotient} dx / y ? dx {32-bit quotient} unsigned operation eor dy,x 32 source ~ destination ? destination eori #,dx 32 immediate data ~ destination ? destination ext dx dx 8 ? 16 16 ? 32 sign-extended destination ? destination extb dx 8 ? 32 sign-extended destination ? destination halt none none enter halted state jmp none address of ? pc jsr 32 spe 4 ? sp; next sequential pc ? (sp); ? pc lea y,ax 32 ? ax link ax,# 16 sp e 4 ? sp; ax ? (sp); sp ? ax; sp + d16 ? sp lsl dx,dy #,dx 32 32 x/c ? (dy << dx) ? 0 x/c ? (dx << #) ? 0 lsr dx,dy #,dx 32 32 0 ? (dy >> dx) ? x/c 0 ? (dx >> #) ? x/c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ry,rx,y,rw 16 16 + 32 ? 32 32 ? 32 acc + (ry rx){<< 1 | >> 1} ? acc acc + (ry rx){<< 1 | >> 1} ? acc; (y{&mask}) ? rw macl ry,rx ry,rx,,y,rw 32 32 + 32 ? 32 32 ? 32 acc + (ry rx){<< 1 | >> 1} ? acc acc + (ry rx){<< 1 | >> 1} ? acc; (y{&mask}) ? rw move y,x 8,16,32 y ? x move from acc acc,rx 32 acc ? rx move from ccr dx 16 ccr ? dx move from macsr macsr,rx macsr,ccr 32 8 macsr ? rx macsr ? ccr move from mask mask,rx 32 mask ? rx move from sr dx 16 sr ? dx move to acc ry,acc <#,acc 32 32 ry ? acc # ? acc move to ccr dy,ccr #,ccr 8 dy ? ccr # ? ccr move to macsr ry,macsr #,macsr 32 ry ? macsr # ? macsr move to mask ry,mask #,mask 32 32 ry ? mask # ? mask move to sr dy,sr #,sr 16 source ? sr movea y,ax 16,32 ? 32 source ? destination movec ry,rc 32 ry ? rc movem list,x y,list 32 32 listed registers ? destination source ? listed registers moveq #,dx 8 ? 32 sign-extended immediate data ? destination msac ry,rx ry,rx,y,rw 32 - 16 16 ? 32 32 ? 32 acc - (ry rx){<< 1 | >> 1} ? acc acc - (ry rx){<< 1 | >> 1} ? acc, (y{&mask}) ? rw msacl ry,rx ry,rx,y,rw 32 - 32 32 ? 32 32 ? 32 acc - (rw rx){<< 1 | >> 1} ? acc acc - (rw rx){<< 1 | >> 1} ? acc; (y{&mask}) ? rw muls y,dx 16 x 16 ? 32 32 x 32 ? 32 source destination ? destination signed operation mulu y,dx 16 x 16 ? 32 32 x 32 ? 32 source destination ? destination unsigned operation neg x 32 0 e destination ? destination negx x 32 0 e destinatione x ? destination nop none none pc + 2 ? pc; synchronize pipelines not 32 ~ destination ? destination or dy,x y,dx 32 source | destination ? destination ori #,dx 32 immediate data | destination ? destination pea 32 sp e 4 ? sp; address of ? (sp) pulse none none set pst= $4 rems y,dx:dw 32 dx/y ? dw {32-bit remainder} signed operation remu y,dx:dw 32 dx/y ? dw {32-bit remainder} unsigned operation rte none none (sp+2) ? sr; sp+4 ? sp; (sp) ? pc; sp + formatfield ? sp rts none none (sp) ? pc; sp + 4 ? sp scc dx 8 if condition true, then 1's ? destination; else 0's ? destination stop # 16 immediate data ? sr; enter stopped state instruction set summary (continued) instruction operand syntax operand size operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
x y,dx 32 32 destination - source ? destination suba y,ax 32 destination - source ? destination subi #,dx 32 destination e immediate data ? destination subq #,x 32 destination - immediate data ? destination subx dy,dx 32 destination e source e x ? destination swap dn 16 msw of dn ?? lsw of dn trap none none sp e 4 ? sp;pc ? (sp); sp e 2 ? sp;sr ? (sp); sp e 2 ? sp; format ? (sp); vector address ? pc trapf none # none 16 32 pc + 2 ? pc pc + 4 ? pc pc + 6 ? pc tst y 8,16,32 set condition codes unlk ax 32 ax ? sp; (sp) ? ax; sp + 4 ? sp wddata y 8,16,32 y ? ddata port wdebug y 2 x 32 y ? debug module instruction set summary (continued) instruction operand syntax operand size operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
