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06k8049.h03530 5/00 ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 22 features ? 168-pin registered 8-byte dual in-line memory module ? 64mx72 synchronous dram dimm ? performance: ? intended for 100mhz and 133mhz applications ? inputs and outputs are lvttl (3.3v) compatible ? single 3.3v 0.3v power supply ? single pulsed ras interface ? sdrams have four internal banks ? module has two physical banks ? fully synchronous to positive clock edge ? programmable operation: - dimm cas latency: 3, 4 (registered mode) - burst type: sequential or interleave - burst length: 1, 2, 4, 8 - operation: burst read and write or multiple burst read with single write ? data mask for byte read/write control ? auto refresh (cbr) and self refresh ? automatic and controlled precharge commands ? suspend mode and power down mode ? 13/10/2 addressing (row/column/bank) ? 8192 refresh cycles distributed across 64ms ? card size: 5.25" x 0.157" x 1.70" ? gold contacts ? sdrams in tsop ? serial presence detect with write protect description ibm13m64734hca is a registered 168-pin synchro- nous dram dual in-line memory module (dimm) organized as a 64mx72 high-speed memory array and is configured as two 32m x 72 physical banks. the dimm uses eighteen 32mx8 sdrams in 400 mil tsop packages. the dimm achieves high- speed data-transfer rates of 100mhz and 133mhz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system clock. the dimm is intended for use in applications operat- ing at 100mhz and 133mhz memory bus speeds. all control and address signals are re-driven through registers to the sdram devices. the dimm oper- ates in registered mode (rege pin tied high), during which the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge (data access is delayed by one clock). a phase-lock loop (pll) on-board the dimm re- drives the clock signals to the sdram devices and registers to minimize system clock loading. (ck0 is connected to the pll, and ck1, ck2, and ck3 are terminated on the dimm.) a single clock enable (cke0) controls all devices on the dimm, enabling the use of sdram power-down modes. prior to any access operation, the device cas latency and burst type/length/operation type must be programmed into the dimm by address inputs a0-a9 using the mode register set cycle. the dimm cas latency is one clock later due to the address and control signals being clocked to the sdram devices. the dimm uses serial presence detects imple- mented via a serial eeprom using the two-pin iic protocol. the first 128 bytes of serial pd data are programmed and locked by the dimm manufacturer. the last 128 bytes are available to the customer and can be write protected by providing a high level to pin 81 on the dimm. an on-board pulldown resistor keeps this in the write-enable mode. all ibm 168-pin dimms provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. -75a units dimm cas latency 4 f ck clock frequency 133 100 mhz f ck clock cycle 7.5 10 ns t ac clock access 5.65 5.65 ns .
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 22 06k8049.h03530 5/00 card outline pin description ck0-ck3 clock inputs dq0 - dq63 data input/output cke0 clock enable cb0 - cb7 check bit data input/output ras row address strobe dqmb0 - dqmb7 data mask cas column address strobe v dd power (3.3v) we write enable v ss ground s0, s1, s2, s3 chip selects nc no connect a0-a9, a11, a12 address inputs scl serial presence detect clock input a10/ap address input/autoprecharge sda serial presence detect data input/output ba0, ba1 sdram bank address inputs sa0-2 serial presence detect address inputs wp spd write protect rege register enable 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back)
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 22 pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 22 cb1 106 cb5 43 v ss 127 v ss 64 v ss 148 v ss 2 dq0 86 dq32 23 v ss 107 v ss 44 nc 128 cke0 65 dq21 149 dq53 3 dq1 87 dq33 24 nc 108 nc 45 s2 129 s3 66 dq22 150 dq54 4 dq2 88 dq34 25 nc 109 nc 46 dqmb2 130 dqmb6 67 dq23 151 dq55 5 dq3 89 dq35 26 v dd 110 v dd 47 dqmb3 131 dqmb7 68 v ss 152 v ss 6 v dd 90 v dd 27 we 111 cas 48 nc 132 nc 69 dq24 153 dq56 7 dq4 91 dq36 28 dqmb0 112 dqmb4 49 v dd 133 v dd 70 dq25 154 dq57 8 dq5 92 dq37 29 dqmb1 113 dqmb5 50 nc 134 nc 71 dq26 155 dq58 9 dq6 93 dq38 30 s0 114 s1 51 nc 135 nc 72 dq27 156 dq59 10 dq7 94 dq39 31 nc 115 ras 52 cb2 136 cb6 73 v dd 157 v dd 11 dq8 95 dq40 32 v ss 116 v ss 53 cb3 137 cb7 74 dq28 158 dq60 12 v ss 96 v ss 33 a0 117 a1 54 v ss 138 v ss 75 dq29 159 dq61 13 dq9 97 dq41 34 a2 118 a3 55 dq16 139 dq48 76 dq30 160 dq62 14 dq10 98 dq42 35 a4 119 a5 56 dq17 140 dq49 77 dq31 161 dq63 15 dq11 99 dq43 36 a6 120 a7 57 dq18 141 dq50 78 v ss 162 v ss 16 dq12 100 dq44 37 a8 121 a9 58 dq19 142 dq51 79 ck2 163 ck3 17 dq13 101 dq45 38 a10/ap 122 ba0 59 v dd 143 v dd 80 nc 164 nc 18 v dd 102 v dd 39 ba1 123 a11 60 dq20 144 dq52 81 wp 165 sa0 19 dq14 103 dq46 40 v dd 124 v dd 61 nc 145 nc 82 sda 166 sa1 20 dq15 104 dq47 41 v dd 125 ck1 62 nc 146 nc 83 scl 167 sa2 21 cb0 105 cb4 42 ck0 126 a12 63 nc 147 rege 84 v dd 168 v dd note: all pin assignments are consistent with all 8-byte unbuffered versions. ordering information part number organization clock cycle (cl, t rcd , t p ) device access time leads dimension power IBM13M64734HCA-75AT 64mx72 7.5ns (3,3,3) 5.65ns gold 5.25" x 0.157" x 1.70" 3.3v
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 22 06k8049.h03530 5/00 64mx72 sdram dimm block diagram (2 bank, 32mx8 sdrams) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d0 dqmb0 dqm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dqm i/o 0 i/o 1 i/o 2 i/o 3 d1 dqm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqm i/o 0 i/o 1 i/o 2 i/o 3 d3 dqm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqm i/o 0 i/o 1 i/o 2 i/o 3 d4 dqm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqm i/o 0 i/o 1 i/o 2 i/o 3 d5 dqmb4 dqm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqm i/o 0 i/o 1 i/o 2 i/o 3 d6 dqm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dqm i/o 0 i/o 1 i/o 2 i/o 3 d7 dqm d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqm i/o 0 i/o 1 i/o 2 i/o 3 d8 dqm d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d2 dqm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 * rs0 rs1 rs2 rs3 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs note: exact dq wiring may differ from that shown above. a0 serial presence detect a1 a2 sa0 sa1 sa2 scl sda v dd v ss d0 - d17 d0 - d17 note: dq wiring may differ from that described in this drawing; however, dq/dqmb relationships are maintained as shown. wp 47k rege pck ras: sdrams d0 - d17 cas: sdrams d0 - d17 cke: sdrams d0 - d17 we: sdrams d0 - d17 s0- s3 dqmb0 to dqmb7 ba0-ba1 a0-a12 ras cas cke0 we rs0- rs3 rdqmb0 - rdqmb7 r ras r cas rcke0 r we r e g i s t e r rba0 - rba1 ra0-ra12 bs0-bs1: sdrams d0-d17 a0-a12: sdrams d0-d17 v dd 10k # unless otherwise noted, resistor values are 10 ohms. ck0 pll ck1, ck2, ck3 terminated
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 22 input/output functional description symbol type signal polarity function ck0 - ck3 input pulse positive edge the system clock inputs. all the sdram inputs are sampled on the rising edge of their associated clock. ck0 drives the pll. ck1, ck2, and ck3 are terminated. cke0 input level active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, the suspend mode, or the self refresh mode. s0- s3 input pulse active low enables the associated sdram command decoder when low and disables the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. ba0, 1 input level selects which sdram bank of four is activated. a0 - a9 a10/ap a11, a12 input level during a bank activate command cycle, a0-a12 defines the row address (ra0- ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 define the column address (ca0- ca9) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be pre- charged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to con- trol which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1. if ap is low, ba0 and ba1 are used to define which bank to precharge. dq0 - dq63, cb0 - cb7 input output level data and check bit input/output pins. dqmb0 - dqmb7 input pulse active high the data input/output masks, associated with one data byte, place the dq buffers in a high-impedance state when sampled high. in read mode, dqmb has a latency of two clock cycles in buffered mode or three clock cycles in registered mode, and con- trols the output buffers like an output enable. in write mode, dqmb has a zero clock latency in buffered mode and a latency of one clock cycle in registered mode. in this case, dqmb operates as a byte mask by allowing input data to be written if it is low but blocking the write operation if it is high. v dd , v ss supply power and ground for the module. rege input level active high (register mode enable) the register enable pin must be held high to permit the dimm to operate in regis- tered mode (signals re-driven to sdrams when clock rises, and held valid until next rising clock). sa0 - 2 input level these signals are tied at the system planar to either v ss or v dd to configure the serial spd eeprom. sda input output level this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup. scl input pulse this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pullup. wp input level active high this signal is pulled low on the dimm to enable data to be written into the last 128 bytes of the spd eeprom.
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 22 06k8049.h03530 5/00 serial presence detect (part 1 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram 04 3 number of row addresses on assembly 13 0d 4 number of column addresses on assembly 10 0a 5 number of dimm banks 2 02 6 - 7 data width of assembly x72 4800 8 assembly voltage interface levels lvttl 01 9 sdram device cycle time (cl = 3) 7.5ns 75 1, 2 10 sdram device access time from clock at cl=3 5.4ns 54 11 assembly error detection/correction scheme ecc 02 12 assembly refresh rate/type sr/1x(7.8125 m s) 82 13 sdram device width x8 08 14 error checking sdram device width x8 08 15 sdram device attr: min clk delay, random col access 1 clock 01 16 sdram device attributes: burst lengths supported 1,2,4,8 0f 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latency 2, 3 06 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 0 01 21 sdram module attributes registered/buffered with pll if 22 sdram device attributes: general write-1/read burst, precharge all, auto-precharge 0e 23 minimum clock cycle at clx-1 (cl = 2) 15.0ns 1f 1, 2 24 maximum data access time (t ac ) from clock at clx-1 (cl = 2) 9.0ns 90 25 minimum clock cycle time at clx-2 (cl = 1) n/a 00 26 maximum data access time (t ac ) from clock at clx-2 (cl = 1) n/a 00 27 minimum row precharge time (t rp ) 20.0ns 14 28 minimum row active to row active delay (t rrd ) 15.0ns 0f 29 minimum ras to cas delay (t rcd ) 20.0ns 14 30 minimum ras pulse width (t ras ) 45.0ns 2d 31 module bank density 256mb 40 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. minimum application clock cycle time is 7.5ns (133 mhz). 3. cc = checksum data byte, 00-ff (hex). 4. r = alphanumeric revision code, a-z, 0-9. 5. rr = ascii coded revision code byte r. 6. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex). 7. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex). 8. ss = serial number data byte, 00-ff (hex). 9. these values apply to pc100 applications only.
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 22 32 address and command setup time before clock 1.5ns 15 33 address and command hold time after clock 0.8ns 08 34 data input setup time before clock 1.5ns 15 35 data input hold time after clock 0.8ns 08 36 - 61 reserved undefined 00 62 spd revision jedec 02 63 checksum for bytes 0 - 62 checksum data cc 3 64 - 71 manufacturers jedec id code ibm a400000000000000 72 assembly manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 assembly part number ascii 13m64734hcr-75at 31334d363437333448 43rr2d373548542020 4, 5 91 - 92 assembly revision code r plus ascii blank rr20 5 93 - 94 assembly manufacturing date year/week code yyww 6, 7 95 - 98 assembly serial number serial number ssssssss 8 99 - 125 reserved undefined not specified 126 module supports this clock frequency 100mhz 64 9 127 attributes for clock frequency defined in byte 126 clk0, cl=3, conap 85 9 128 - 255 open for customer use undefined 00 serial presence detect (part 2 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. minimum application clock cycle time is 7.5ns (133 mhz). 3. cc = checksum data byte, 00-ff (hex). 4. r = alphanumeric revision code, a-z, 0-9. 5. rr = ascii coded revision code byte r. 6. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex). 7. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex). 8. ss = serial number data byte, 00-ff (hex). 9. these values apply to pc100 applications only.
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 22 06k8049.h03530 5/00 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v1 v in input voltage sdram devices -1.0 to +4.6 serial pd device -0.3 to +6.5 register 0 - v dd pll 0 - v dd v out output voltage sdram devices -1.0 to +4.6 serial pd device -0.3 to +6.5 t a operating temperature (ambient) 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 11.9 w 1, 2 i out short circuit output current 50 ma 1 f min minimum operating frequency 66 mhz 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. maximum power is calculated assuming the physical bank is in auto refresh mode. recommended dc operating conditions (t a = 0 to 70?c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v1 v il input low voltage -0.3 0.8 v 1 1. all voltages referenced to v ss .
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 22 capacitance (t a = 25?c, f=1mhz, v dd = 3.3v 0.3v) symbol parameter organization units x72 max. c i1 input capacitance (a0 - a9, a10/ap, ba0, ba1, a11, a12) 21 pf c i2 input capacitance ( ras) 20 pf c i3 input capacitance ( cas) 20 pf c i4 input capacitance ( s0, s3) 13 pf c i5 input capacitance (cke0) 15 pf c i6 input capacitance (ck0) 28 pf c i7 input capacitance (dqmb0 - dqmb7) 13 pf c i8 input capacitance (sa0 - sa2, scl, wp) 9 pf c i9 input capacitance (rege) 10 pf c i10 input capacitance (ck1 - ck3) 14 pf c i11 input capacitance (we) 23 pf c io1 input/output capacitance (dq0 - dq63, cb0 - cb7) 18 pf c io2 input/output capacitance (sda) 11 pf
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 22 06k8049.h03530 5/00 dc output load circuit input/output characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter x72 units notes min. max. i i(l) input leakage current, any input (0.0v v in 3.6v), all other pins not under test = 0v address and control inputs 10 10 m a dq0-63, cb0 - 7 -2 +2 i o(l) output leakage current (d out is disabled, 0.0v v out 3.6v) dq0-63, cb0 - 7 -2 +2 m a sda -1 +1 v oh output level output h level voltage (i out = -2.0ma) 2.4 v dd v1 v ol output level output l level voltage (i out = +2.0ma) 0.0 0.4 1. see dc output load circuit. output 1200 w 50pf 3.3 v 870 w v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 22 operating, standby, and refresh currents (t a = 0 to +70 c, v dd = 3.3v 0.3v) parameter symbol (physical bank 0/ physical bank 1) test condition speed -75a clock cycle units notes 7.5ns burst operating mode/active standby i cc4 /i cc3n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 2085 ma 1, 2 burst operating mode/precharge standby i cc4 /i cc2n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 1815 ma 1, 2 burst operating mode/auto refresh i cc4 /i cc5 cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 3279 ma 1, 2 non-burst operating mode/active standby i cc1 /i cc3n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 1929 ma 1, 2 non-burst operating mode/precharge standby i cc1 /i cc2n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 1407 ma 1, 2 non-burst operating mode/auto refresh i cc1 /i cc5 cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 2964 ma 1 active standby/active standby i cc3n /i cc3n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 1389 ma active standby/precharge standby i cc3n /i cc2n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 1119 ma active standby/auto refresh i cc3n /i cc5 cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 2424 ma 1 precharge standby/precharge standby i cc2n /i cc2n cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 849 ma precharge standby/auto refresh i cc2n /i cc5 cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 2154 ma 1 auto refresh/auto refresh i cc5 /i cc5 cke 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 3300 ma 1 active standby power down/ active standby power down i cc3p /i cc3p cke v il (max), t ck = min, s0 - s3 =v ih (min) 417 ma active standby power down/precharge standby power down i cc3p /i cc2p cke v il (max), t ck = min, s0 - s3 =v ih (min) 381 ma precharge standby power down/ precharge standby power down i cc2p /i cc2p cke v il (max), t ck = min, s0 - s3 =v ih (min) 345 ma precharge standby non-power down/pre- charge standby non-power down (no clock) i cc2ns /i cc2ns cke 3 v ih (min), t ck = infinity, s0 - s3 =v ih (min) 156 ma precharge standby power down/precharge standby power down (no clock) i cc2ps /i cc2ps cke v ih (min), t ck = infinity, s0 - s3 =v ih (min) 84 ma self refresh current /self refresh current i cc6 /i cc6 cke v ih (min), t ck = infinity, s0 - s3 =v ih (min) 102 ma 1. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed once during t ck (min). 2. the specified values are obtained with the output open.
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 22 06k8049.h03530 5/00 ac characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) 1. an initial pause of 200 m s, with cke0 held high, is required after power-up. a precharge all banks com- mand must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set operation. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.40v crossover point. 3. the transition time is measured between v ih and v il (or between v il and v ih ). 4. ac measurements assume t t =1.2ns (1 volt/ns rise time). 5. in addition to meeting the transition rate speci?cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 6. a 1 ms stabilization time is required by the on-board pll circuit to phase lock its feedback signal to its ref- erence signal. 7. all timings are speci?ed at the input receiver of the signal, not at the dimm connector. ac characteristics diagrams output input clock t oh t setup t hold t ac t lz 1.4v 0.8v 1.4v 1.4v 2.0v t t t ckh t ckl output 50pf z o = 50 w ac output load circuit
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 22 clock and clock enable parameters symbol parameter -75a max. (device cl, t rcd , t rp = 3, 3, 3) units notes min. max. t ck4 clock cycle time, dimm cas latency = 4 7.5 1000 ns 1 t ac4 clock access time, dimm cas latency = 4 5.65 ns 1, 2 t ckh clock high pulse width 2.5 ns 3 t ckl clock low pulse width 2.5 ns 3 t ces clock enable setup time 1.65 ns 1 t ceh clock enable hold time 0.35 ns 1 t sb power down mode entry time 0 7.5 ns t t transition time (rise and fall) 0.5 10 ns 1. dimm cas latency = device cl [clock cycles] + 1 for register mode. 2. access time is measured at 1.4v. see ac output load circuit. 3. t ckh is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max).
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 22 06k8049.h03530 5/00 common parameters symbol parameter -75a units notes min. max. t cs command setup time 1.65 ns 1 t ch command hold time 0.35 ns 1 t as address and bank select setup time 1.65 ns 1 t ah address and bank select hold time 0.35 ns 1 t rcd ras to cas delay 20 ns 1 t rc bank cycle time 67.5 ns 1 t ras active command period 45 100000 ns 1 t rp precharge time 20 ns 1 t rrd bank to bank delay time 15 ns 1 t ccd cas to cas delay time (same bank) 1 clk 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num- ber of clock cycles = specified value of timing/clock period (count fractions as a whole number). mode register set style symbol parameter -75a units notes min. max. t rsc mode register set cycle time 2 clk 1 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num- ber of clock cycles = specified value of timing/clock period (count fractions as a whole number). refresh cycle symbol parameter -75a units notes min. max. t ref refresh period 64 ns 1, 2 t refi average refresh interval time 7.813 m s t srex self refresh exit time 10 ns 3 1. 8192 cycles 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake up the device. 3. self refresh exit is asynchronous, requiring 10ns to ensure initiation. self refresh exit is complete in 10ns + t rc .
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 22 read cycle symbol parameter -75a units notes min. max. t oh data out hold time 3.1 ns t lz data out to low impedance time 0.6 ns t hz3 data out to high impedance time 3.6 6.6 ns 1 t dqz dqm data out disable latency 3 clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. write cycle symbol parameter -75a units min. max. t ds data in setup time 1.75 ns t dh data in hold time 1.05 ns t dpl data input to precharge 15 ns t dal3 data in to active delay ( cas latency = 3) 5 clk t dqw dqm write mask latency 1 clk presence detect read and write cycle symbol parameter -75a units notes min. max. f scl scl clock frequency 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4 m s t low clock low period 4.7 m s t high clock high period 4 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 22 06k8049.h03530 5/00 wiring and topology this section contains the information needed to understand the timing relationships presented in ac charac- teristics beginning on page 12. each timing parameter is measured at the first receiving device (sdram dq pin for data input, register input pin for address and control, and pll clk input pin for clock). this section will enable the user to understand the pin numbers on the dimm, the net structures, and the loading associated with these devices. for detailed timing analysis, contact the ibm marketing representative for simulation models. modeling is strongly recommended to determine delay adders of the entire net structure. pin assignments for the 256mbit sdram planar component top view 54-pin plastic tsop(ii) 400mil 16mbit x 8 i/o x 4 bank 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc v dd nc dq2 nc we cas ras cs bs0 bs1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc v ss nc dq5 nc dqm clk cke a12 a11 a9 23 24 25 32 31 30 a10/ap a0 a1 a2 a8 a7 a6 a5 26 27 29 28 a3 v dd a4 v ss
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 22 the table below describes the physical dq wiring information for each sdram on the dimm. note that the dq wiring is different from that described in the block diagram on page 4; the dqs are scrambled within the same device for wiring optimization. the table below describes the input wiring for each clock on the dimm. data wiring cross reference dq sdram designator dq sdram pin number device position to dimm tab data i/o 1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 dq0 2 7 38 15 47 cb2 55 23 63 31 0 33 8 41 cb1 48 16 55 25 dq1 5 6 37 14 46 cb7 54 22 62 30 1 34 9 42 cb5 49 17 57 26 dq2 8 5 36 13 45 cb3 53 21 61 29 2 35 10 40 cb4 50 18 58 27 dq3 11 4 39 12 44 cb6 52 20 60 28 3 32 11 43 cb0 51 19 59 24 dq4 44 3 32 11 43 cb0 51 19 59 24 4 39 12 44 cb6 52 20 60 28 dq5 47 2 35 10 40 cb4 50 18 58 27 5 36 13 45 cb3 53 21 61 29 dq6 50 1 34 9 42 cb5 49 17 57 26 6 37 14 46 cb7 54 22 62 30 dq7 53 0 33 8 41 cb1 48 16 56 25 7 38 15 47 cb2 55 23 63 31 1. these numbers can be associated with the corresponding dimm tab pin by referencing the dimm connector pinout on page 3 of this specification. example: dq14 at the dimm tab (pin 19) is wired to both sdram device position d2, pin 5 and sdram d11, pin 50. data topology clock input wiring ck0 ck1 ck2 ck3 pll clk input pin 24 termination rc termination rc termination rc tl0 tl1 total unit min max min max min max 0.126 0.345 1.013 1.415 1.145 1.658 in. sdram note: transmission lines (tl) are represented as cylinders and labeled with length designators. these are the only lines which represent physical trace segments. for more detailed topology information please refer to the cur- rent pc133 sdram registered dimm specification. 10 w 5% dimm connector tl1 tl0
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 22 06k8049.h03530 5/00 clock topology ck0 10 w ck1, ck2, and ck3 12pf tl0 tl1 unit 0.127 2.647 in. 10 w dimm connector tl1 tl0 12pf phase lock loop (pll)
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 22 the table below describes the address and control information for each signal on the dimm. note that several signals are double loaded at the input of the register. functional description and timing diagrams refer to the ibm pc133 256mb synchronous dram data sheet (document 29l0000) for the functional description and timing diagrams for buffered-mode operation. refer to the ibm application notes serial presence detect on memory dimms and sdram presence detect definitions for the serial presence detect functional description and timings. register input wiring register type:alvcf162835 register pin number register 1 signal register 2 signal register 3 signal 30 clk clk clk 31 cas nc dqmb0 33 ras nc dqmb4 34 a1 bs1 dqmb1 36 a0 a11 dqmb5 37 a3 a10 a12 38 a2 bs0 a12 40 a5 a8 s0 41 a4 a9 nc 42 a7 a6 we 43 a6 a7 we 44 a9 a4 nc 45 a8 a5 s2 47 bs0 a2 dqmb6 48 a10 a3 dqmb2 49 a11 a0 nc 51 bs1 a1 nc 52 cke0 ras dqmb7 54 cke0 cas dqmb3 address/control signal topology note: each signal has two register input loads with the exception of dqmbs and chip select which have one. for more detailed topology information please refer to the current pc133 sdram registered dimm specification. register input register input tl0 unit min max 0.199 1.336 in. dimm connector tl0
ibm13m64734hca 64m x 72 two-bank registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 22 06k8049.h03530 5/00 layout drawing r 1.00 .0393 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 detail a scale: 4/1 millimeters inches 65.68 2.63 6.35 .250 42.18 1.661 1.27 pitch .050 1.00 width .039 see detail a 1.7 43.33 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.78 front 3.99 0.157 max. side 1.273 0.10 .050 .004 4.24 .167 min. front back 4.24 .167 min. (2) 0 3.1877 .1255 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 register 2 back register 1 register 3 pll
ibm13m64734hca 64m x 72 two-bank registered sdram module 06k8049.h03530 5/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 22 revision log rev contents of modi?cation 5/00 initial release
copyright and disclaimer copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america may 2000 the following are trademarks of international business machines corporation in the united states, or other coun- tries, or both. ibm ibm logo other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com 06k8049.h03530. 5/00 a

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