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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com august 2005 rev. 0 advanced* w3eg264m64efsu-d4 white electronic designs 1gb C 2x64mx64 ddr sdram, unbuffered, fbga features fast data transfer rate: pc-2100, pc-2700 and pc3200 clock speeds of 133 mhz, 166 mhz and 200mhz supports ecc error detection and correction bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 3 and 4 (clock) programmable burst length (2, 4 or 8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect (spd) with eeprom v cc = v ccq = +2.6v 0.1v (200mhz) v cc = v ccq = +2.5v 0.2v (133 and 166mhz) gold edge contacts dual rank jedec standard 200 pin, small-outline, so-dimm package ? pcb height option: d4: 31.75 mm (1.25) note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option description the w3eg264m64efsu is a 2x64mx64 double data rate sdram memory module based on 512mb ddr sdram components. the module consists of sixteen 64mx8 ddr sdrams in fbga packages mounted on a 200 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. operating frequencies ddr400@cl=3 ddr333@cl=2.5 ddr266@cl=2 ddr266@cl=2.5 clock speed 200mhz 166mhz 133mhz 133mhz cl-t rcd -t rp 3-3-3 2.5-3-3 2-2-2 2.5-3-3
w3eg264m64efsu-d4 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced pin names symbol description a0-a12 address input ba0, ba1 bank address dq0-dq63 input/output: data i/os, data bus cb0-cb7 input/output: check bits ck0, ck0# ck1, ck1# ck2, ck2# clock input cke0-cke1 clock enable input cs0#-cs1# chip select input we#, cas#, ras# command input dqs0-dqs8 data strobe dm0-dm8 data write mask v cc supply: power supply: +2.5v 0.2v v ccspd supply: serial eeprom positive power supply v ref supply: sstl_2 reference voltage v ss supply: ground scl serial clock sa0-sa2 presence detect address input sda input/output: serial presence- detect data nc no connect dnu do not use pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7dq157v cc 107 a5 157 v cc 8dq558v cc 108 a4 158 ck1# 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 ck1 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 dnu 121 cs0# 171 dq50 22 v cc 72 dnu 122 cs1# 172 dq54 23 dq9 73 dnu 123 nc 173 v ss 24 dq13 74 dnu 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dnu 127 dq32 177 dq56 28 v ss 78 dnu 128 dq36 178 dq60 29 dq10 79 dnu 129 dq33 179 v cc 30 dq14 80 dnu 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 dnu 133 dqs4 183 dqs7 34 v cc 84 dnu 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 dnu 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 dnu 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 dnu 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 v ss
w3eg264m64efsu-d4 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced functional block diagram a0 sa0 serial pd sda a1 sa1 a2 sa2 ba0, ba1 a0-a12 ras# ba0, ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams cke1: ddr sdrams we#: ddr sdrams cas# cke0 cke1 we# v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm s0# dqs dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 cs0# dq dq dq dq dq dq dq dq wp scl dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq cs1# dm s1# dqs dm s0# dqs dm s1# dqs dm s0# dqs dm s1# dqs dm s0# dqs dqs0 dm7 dqs7 dm2 dqs2 dm5 dqs5 dq dq dq dq dq dq dq dq dm s1# dqs dm4 dqs4 dm3 dqs3 dm s1# dqs dm s0# dqs dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dm s1# dqs dm s0# dqs dm s0# dqs dm s0# dqs dm6 dqs6 dm1 dqs1 dq dq dq dq dq dq dq dq dm s1# dqs dq dq dq dq dq dq dq dq dm s1# dqs v ccspd v cc ddr sdrams spd/eeprom ddr sdrams ck0 ck0# 120 ddr sdrams ck1 ck1# 120 120 ck2 ck2# note: 1. all resistor values are 22? unless otherwise speci? ed.
w3eg264m64efsu-d4 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced dc electrical characteristics parameter/condition symbol min max units supply voltage v cc 2.3 2.7 v i/o supply voltage v ccq 2.3 2.7 v i/o reference voltage v ref 0.49 v ccq 0.51 v ccq v i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v input high (logic 1) voltage v ih v ref + 0.15 v cc + 0.3 v input low (logic 0) voltage v il -0.3 v ref - 0.15 v high current (v out = v ccq - 0.373v, minimum v ref , minimum v tt )v oh -16.8 ma low current (v out = 0.373v, maximum v ref , maximum v tt )v ol 16.8 ma capacitance parameter symbol max units input/output capacitance: dq, dqs,dm c i0 12 pf input capacitance: command and address c i1 47 pf input capacitance: ck, ck#, c i2 25 pf input capacitance: cke, s# c i3 25 pf
w3eg264m64efsu-d4 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced i dd specifications and conditions 0c t a +70c; v cc , v ccq = +2.5v 0.2v ddr400: v cc = v ccq = +2.6v 0.2v max parameter/condition sym ddr400 @cl=3 ddr333 @cl=2.5 ddr266 @cl=2 ddr266 @cl=2.5 units operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 2475 2070 2070 1845 ma operating current: one device bank; active-read-precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle i dd1 2745 2340 2340 2115 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 90 90 90 90 ma idle standby current: cs# = high; all device banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. vi n = v ref for dq, dqs, and dm i dd2f 990 810 810 720 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p 810 630 630 540 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 1080 900 900 810 ma operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 2790 2385 2385 2115 ma operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 2790 2295 2295 2025 ma auto refresh burst current: t refc = t rfc (min) i dd5 4185 3510 3510 3330 ma self refresh current: cke 0.2v i dd6 90 90 90 90 ma operating current: four device bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 5130 4545 4545 3960 ma
w3eg264m64efsu-d4 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced ddr sdram component electrical characteristics and recommended ac operating conditions 0c t a +70c; v cc = v ccq = +2.5v 0.2v ac characteristics 403 335 262 265 units notes parameter symbol min max min max min max min max access window of dqs from ck/ck# t ac -0.65 +0.65 -0.70 +0.70 -0.75 +0.75 -0.75 0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 3 t ck (3) 5 10 ns 39, 44 cl = 2.5 t ck (2.5) 6 13 7.5 13 7.5 13 ns 39, 44 cl = 2 t ck (2) 7.5 13 7.5 13 7.5/10 13 ns 39, 44 dq and dm input hold time relative to dqs t dh 0.40 0.45 0.5 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.40 0.45 0.5 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.55 +0.55 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.4 0.4 0.5 0.5 ns 22, 23 write command to ? rst dqs latching transition t dqss 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.20 0.20 0.20 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.20 0.20 0.20 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.65 +0.70 +0.75 +0.75 ns 16, 36 data-out low-impedance window from ck/ck# t lz -0.65 +0.65 -0.70 -0.75 -0.75 ns 16, 36 address and control input hold time (fast slew rate) t ihf 0.60 0.75 0.90 0.90 ns 12 address and control input setup time (fast slew rate) t isf 0.60 0.75 0.90 0.90 ns 12 address and control input hold time (slow slew rate) t ihs 0.8 0.8 1 1 ns 12
w3eg264m64efsu-d4 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced ddr sdram component electrical characteristics and recommended ac operating conditions (continued) 0c < t a <+70c; v cc = v ccq = +2.5v 0.2v ac characteristics 403 335 262 265 units notes rameter symbol min max min max min max min max address and control input setup time (slow slew rate) t iss 0.8 0.8 1 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 2.2 2.2 ns load mode register command cycle time t mrd 12 12 15 15 ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.50 0.50 0.75 0.75 ns active to precharge command t ras 40 70,000 42 70,000 40 120,000 40 120,000 ns 30, 47 active to read with auto precharge command t rap 15 18 15 20 ns active to active/auto refresh command period t rc 55 60 60 65 ns auto refresh command period t rfc 70 72 75 78 ns 42 active to read or write delay t rcd 15 18 15 20 ns precharge command period t rp 15 18 15 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 37 active bank a to active bank b command t rrd 10 12 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0000ns18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 15 ns internal write to read command delay t wtr 1111t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval t refc 70.3 70.3 70.3 70.3 s 21 average periodic refresh interval t refi 7.8 7.8 7.8 7.8 s 21 terminating voltage delay to vdd t vtd 0000ns exit self refresh to non-read command t xsnr 75 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 200 t ck
w3eg264m64efsu-d4 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced 11. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 12. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 13. the valid data window is derived by achieving other speci? cations - t hp (t ck/2 ), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycled variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 14. referenced to each output group: x8 = dqs with dq0-dq7. 15. r eads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 16. jedec speci? es ck and ck# input slew rate must be > 1v/ns (2v/ns differentially). 17. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rates exceed 4v/ns, functionality is uncertain. 18. t hp min is the lesser of t cl min and t ch min actually applied to the device ck and ck# inputs, collectively during bank active. 19. t hz (max) will prevail over the t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + pre (max) condition. 20. for slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. 21. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t rfc has been satis? ed. 22. w henever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles (before read commands). notes 1. all voltages referenced to v ss 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at normal reference / supply voltage levels, but the related speci? cations and device operations are guaranteed for the full voltage range speci? ed. 3. outputs are measured with equivalent load: output o u t p u t (v ( v out o u t ) reference r e f e r e n c e point p o i n t 50? 5 0 ? v tt t t 30pf 3 0 p f 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are de? ned in the sstl_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. for slew rates less than 1v/ns and greater than or equal to 0.5v/ ns. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. for 403 and 335, slew rates must be greater than or equal to 0.5v/ns. 7. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v ccq is recognized as low. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) and begins driving (lz). 9. the intent of the dont care state after completion of the postamble is the dqs-driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ihdc (min) then it must not transition low (below v ihdc ) prior to t dqsh (min). 10. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround.
w3eg264m64efsu-d4 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced * all dimensions are in millimeters and (inches) 200-pin ddr2 sodimm dimensions ordering information for d4 part number speed cas latency t rcd t rp height* w3eg264m64efsu403d4-x 200mhz/400mbps 3 3 3 31.75 (1.25") max w3eg264m64efsu335d4-x 166mhz/333mbps 2.5 3 3 31.75 (1.25") max w3eg264m64efsu262d4-x 133mhz/266mbps 2 2 2 31.75 (1.25") max w3eg264m64efsu265d4-x 133mhz/266mbps 2.5 3 3 31.75 (1.25") max notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case -x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option 3.81 (0.150 ) max 1.10 (0.043) pin 1 67.56 (2.66) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.61 (0.024) typ 0.46 (0.018) typ 2.00 (0.079) r (2x) pin 199 pin 200 pin 2 front view 2.00 (0.079) 6.00 (0.236) 63.60 (2.504) 2.44 (0.096) 0.99 (0.039) typ 31.75 (1.25) typ back view
w3eg264m64efsu-d4 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced part numbering guide w 3 e g 264m 64 e f s u xxx d4 -x g wedc memory ddr gold depth (dual rank) bus width x8 fbga 2.5v unbuffered speed (mhz) package 200 pin component vendor name (m = micron) (s = samsung) g = rohs compliant
w3eg264m64efsu-d4 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 0 advanced document title 1gb - 2x64mx64 ddr sdram, unbuffered, fbga revision history rev # history release date status rev 0 created 8-05 advanced

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