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xicor, inc. 1994 ?1997 patents pending 7033-1.1 5/8/97 t1/c0/d0 sh 1 characteristics subject to change without notice 4k X25057 512 x 8 bit 5mhz low power spi serial e 2 prom with idlock memory features 5mhz clock rate idlock memory idlock first or last page, any 1/4 or lower 1/2 of e 2 prom array low power cmos ?1 m a standby current <3ma active current during write <400 m a active current during read 1.8v to 3.6v, 2.7v-5.5v or 4.5v to 5.5v operation built-in inadvertent write protection power-up/power-down protection circuitry write enable latch write protect pin spi modes (0,0 & 1,1) 512 x 8 bits 16 byte page mode self-timed write cycle 5ms write cycle time (typical) high reliability endurance: 100,000 cycles/byte data retention: 100 years esd: 2000v on all pins 8-lead msop package 8-lead tssop package 8-lead soic package 8-lead pdip package description the X25057 is a cmos 4k-bit serial e 2 prom, internally organized as 512 x 8. the X25057 features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. idlock is a programmable locking mechanism which allows the user to lock system id and parametric data in different portions of the e 2 prom memory space, ranging from as little as one page to as much as 1/2 of the total array. the X25057 also features a wp pin that can be used for hardwire protection of the part, disabling all write attempts, as well as a write enable latch that must be set before a write operation can be initiated. the X25057 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. functional diagram command decode and control logic write control logic data register y decode logic x decode logic high voltage control 4k e 2 prom array (512 x 8) so si sck cs wp 8 16 32 7033 frm f01
X25057 2 pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is a serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) when cs is high, the X25057 is deselected and the so output pin is at high impedance and unless an internal write operation is underway, the X25057 will be in the standby power mode. cs low enables the X25057, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect (wp ) when wp is low, nonvolatile writes to the X25057 are disabled, but the part otherwise functions normally. when wp is held high, all functions, including nonvolatile writes operate normally. wp going low while cs is still low will interrupt a write to the X25057. if the internal write cycle has already been initiated, wp going low will have no affect on this write. pin names 7033 frm t01 pin configuration principles of operation the X25057 is a 512 x 8 e 2 prom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the X25057 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low and the wp input must be high during the entire operation. table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb ?st. data input is sampled on the ?st rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then start it again to resume opera- tions where left off. symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage nc no connect v cc nc si sck 7033 frm f02.1 so cs v ss wp 1 2 3 4 8 7 6 5 8 lead msop sck si v ss wp 7033 frm f02.2 nc v cc cs so 1 2 3 4 8 7 6 5 8 lead tssop v cc nc sck si 7033 frm f02 cs so wp v ss 1 2 3 4 8 7 6 5 8 lead soic/pdip X25057 X25057 X25057 *0.197" *0.244" 0.120" 0.193" 0.122" 0.252" not to scale *soic measurement
X25057 3 write enable latch the X25057 contains a ?rite enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruc- tion will reset the latch (figure 4). this latch is automati- cally reset upon a power-up condition and after the completion of a byte or page write cycle. idlock memory xicors idlock memory provides a ?xible mechanism to store and lock system id and parametric information. there are seven distinct idlock memory areas within the array which vary in size from one page to as much as half of the entire array. these areas and associated address ranges are idlocked by writing the appropriate two byte idlock instruction to the device as described in table 1 and figure 7. once an idlock instruction has been com- pleted, that idlock setup is held in a nonvolatile status register (figure 1) until the next idlock instruction is issued. the sections of the memory array that are idlocked can be read but not written until idlock is removed or changed. figure 1. status register/idlock protection byte clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the e 2 prom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the X25057, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] speci?d to be zeroes). after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (01ffh), the address counter rolls over to address 0000h, allowing the read cycle to be continued inde?itely. the read operation is terminated by taking cs high. refer to the read operation sequence illustrated in figure 2. read status operation if there is not a nonvolatile write in progress, the read status instruction returns the id lock byte from the sta- tus register which contains the id lock bits idl2-idl0 (figure 1). the id lock bits de?e the id lock condition (figure 1/table1). the other bits are reserved and will return ? when read. see figure 3. if a nonvolatile write is in progress, the read status instruction returns a high on so. when the nonvolatile write cycle is completed, the status register data is read out. clocking sck is valid during a nonvolatile write in progress, but is not necessary. if the sck line is clocked, the pointer to the status register is also clocked, even though the so pin shows the status of the nonvolatile write operation (see figure 3). write sequence prior to any attempt to write data into the X25057, the ?rite enable latch must ?st be set by issuing the wren instruction (see table 1 and figure 4). cs is ?st taken low. then the wren instruction is clocked into the X25057. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the e 2 prom memory array, the user then issues the write instruction, followed by the 16 bit address and the data to be written. only the last 9 bits of the address are used and bits [15:9] are speci?d to be zeroes. this is minimally a thirty-two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 16 bytes of data to the X25057. the only restriction is the 16 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will ?oll over to the ?st address of the page and overwrite any data that may have been previously written. for a byte or page write operation to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed. refer to figures 5 and 6 for detailed illustration of the write sequences and time frames in which cs going high are valid. 76543210 0 0 0 0 0 idl2 idl1 idl0 note: bits [7:3] specified to be ?? 7038 frm t02.1
X25057 4 idlock operation prior to any attempt to perform an idlock operation, the wren instruction must ?st be issued. this instruction sets the ?rite enable latch and allows the part to respond to an idlock sequence (figure 7). the idlock instruction follows and consists of one command byte fol- lowed by one idlock byte (see figure 1). this byte con- tains the idlock bits idl2-idl0. the rest of the bits [7:3] are unused and must be written as zeroes. bringing cs high after the two byte idlock instruction initiates a nonvolatile write to the status register. writing more than one byte to the status register will overwrite the previously written idlock byte. see table 1. operational notes the X25057 powers up in the following state: the device is in the low power, standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is at high impedance. the ?rite enable latch is reset. data protection the following circuitry has been included to prevent inad- vertant writes: the ?rite enable latch is reset upon power-up. a wren instruction must be issued to set the ?rite enable latch. ?s must come high at the proper clock count in order to start a write cycle. table 1. instruction set and block lock protection byte definition 7033 frm t03 *instructions are shown with msb in leftmost position. instructions are transferred msb ?st. instruction format* instruction name and operation 0000 0110 wren: set the write enable latch (write enable operation) 0000 0100 wrdi: reset the write enable latch (write disable operation) 0000 0001 idlock instruction?ollowed by: idlock byte: (see figure 1) 0000 0000 --->no idlock: 00h-00h ---------->none of the array 0000 0001 --->idlock q1: 00h-7fh ---------->lower quadrant (q1) 0000 0010 --->idlock q2: 80h-ffh----------->q2 0000 0011 --->idlock q3: 100h-17fh-------->q3 0000 0100 --->idlock q4: 180h-1ffh-------->upper quadrant (q4) 0000 0101 --->idlock h1: 00h-ffh----------->lower half of the array (h1) 0000 0110 --->idlock p0: 0h-fh-------------->lower page (p0) 0000 0111 --->idlock pn: 1f0h-1ffh-------->upper page (pn) 0000 0101 read status: reads idlock & write in progress status on so pin 0000 0010 write: write operation followed by address and data 0000 0011 read: read operation followed by address
X25057 5 figure 2. read operation sequence figure 3. read status operation sequence 0123456789 cs sck si so high impedance read instruction (1 byte) byte address (2 byte) data out 15 14 3210 20 21 22 23 24 25 26 27 28 29 30 7033 frm f03.1 76543210 01234567 cs sck si so nonvolatile write in progress read status instruction 7033 frm f04.2 i so high during nonvolatile write cycle so = status reg bit when no nonvolatile write cycle ... ... ... d l 2 i d l 1 i d l 0
X25057 6 figure 4. wren/wrdi sequence figure 5. byte write operation sequence 01234567 7033 frm f05.1 cs si sck high impedance so instruction (1 byte) 0123456789 cs sck si so high impedance write instruction (1 byte) byte address (2 byte) data byte 1514 3210 20 21 22 23 24 25 26 27 28 29 30 31 7033 frm f06 76543210
X25057 7 figure 6. page write operation sequence figure 7. idlock operation sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si program instruction byte address (2 byte) 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 151413 3210 20 21 22 23 24 25 26 27 28 29 30 31 6543210 7033 frm f07.3 data byte 16 data byte 1 146 145 147 149 148 150 151 0123456789 cs sck si so high impedance idlock 10 11 12 13 14 15 7033 frm f08.2 idlock byte 0 0 0 0 0 instruction i d l 2 i d l 1 i d l 0
X25057 8 absolute maximum ratings* temperature under bias ................... ?5 c to +135 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to v ss ................................... ?v to +7v d.c. output current.............................................. 5ma lead temperature (soldering, 10 seconds).............................. 300 c *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) 7033 frm t06 power-up timing 7033 frm t07 notes: (1) v il min. and v ih max. are for reference only and are not 100% tested. (2) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. limits symbol parameter min. max. units test conditions i cc1 v cc supply current (write) 3 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open, cs = v ss i cc2 v cc supply current (read ) 400 m a sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open, cs = v ss i sb v cc supply current (standby) 1 m acs = v cc , v in = v ss or v cc i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v il (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc ?0.8 v v cc > 3.3v, i oh = -1.0ma v oh2 output high voltage v cc ?0.4 v 2v < v cc 3.3v, i oh = -0.4ma v oh3 output high voltage v cc ?0.2 v v cc 2v, i oh = -0.25ma symbol parameter min. max. units t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms recommended operating conditions 7033 frm t04 temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c 7033 frm t05 supply voltage limits X25057 4.5v to 5.5v X25057-2.7 2.7v to 5.5v X25057-1.8 1.8v to 3.6v
X25057 9 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) data input timing 7033 frm t10 notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. symbol parameter voltage min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 05 3.3 mhz t cyc cycle time 2.7v?.5v 1.8v?.6v 200 300 ns t lead cs lead time 2.7v?.5v 1.8v?.6v 100 150 ns t lag cs lag time 2.7v?.5v 1.8v?.6v 100 150 ns t wh clock high time 2.7v?.5v 1.8v?.6v 80 130 ns t wl clock low time 2.7v?.5v 1.8v?.6v 80 130 ns t su data setup time 20 ns t h data hold time 20 ns t ri (3) data in rise time 2 m s t fi (3) data in fall time 2 m s t cs cs deselect time 100 ns t wc (4) write cycle time 10 ms a.c. test conditions 7033 frm t09 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 equivalent a.c. load circuit output 5v 2061 w 3025 w 30pf output 3.3v 2696 w 5288 w 30pf output 2v 2800 w 5600 w 30pf capacitance t a = +25 c, f = 1mhz, v cc = 5.0v. 7033 frm t08 symbol parameter max. units conditions c out (3) output capacitance (so) 8 pf v out = 0v c in (3) input capacitance (sck, si, cs , wp ) 6 pf v in = 0v 7033 frm f09.1
X25057 10 data output timing 7033frm t11 notes: (5) this parameter is periodically sampled and not 100% tested. figure 8. serial output timing symbol table symbol parameter voltage min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 05 3.3 mhz t dis output disable time 2.7v?.5v 1.8v?.6v 100 150 ns t v output valid from clock low 2.7v?.5v 1.8v?.6v 80 130 ns t ho output hold time 0 ns t ro (5) output rise time 50 ns t fo (5) output fall time 50 ns sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis 7033 frm f10 t lag waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
X25057 11 figure 9. serial input timing sck cs si so msb in t su t ri t lag 7033 frm f11 t lead t h lsb in t cs t fi high impedance
X25057 12 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8-lead miniature small outline gull wing package type m note: 1. all dimensions in inches and (millimeters) 3003 frm 01
X25057 13 packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
X25057 14 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 3926 frm f22.1 8-lead plastic small outline gull wing package type s 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint note: all dimensions in inches (in parentheses in millimeters)
X25057 15 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X25057 16 ordering information part mark convention device X25057 p t temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package 8-lead msop limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. v = 8-lead tssop s = 8-lead soic aaa = 1.8 to 3.6v, 0 to +70 c v v cc limits blank = 4.5v to 5.5v 2.7 = 2.7v to 5.5v 1.8 = 1.8v to 3.6v eyww xxx aac = 1.8 to 3.6v, -40 to +85 c aao = 2.7 to 5.5v, 0 to +70 c aap = 2.7 to 5.5v, -40 to +85 c aaf = 4.5 to 5.5v, 0 to +70 c aag = 4.5 to 5.5v, -40 to +85 c 8-lead tssop ag = 1.8 to 3.6v, 0 to +70 c eyww 5057xx ah = 1.8 to 3.6v, -40 to +85 c f = 2.7 to 5.5v, 0 to +70 c g = 2.7 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c 8-lead soic/pdip X25057 x xx m = 8-lead msop blank = 8-lead soic ag = 1.8 to 3.6v, 0 to +70 c ah = 1.8 to 3.6v, -40 to +85 c f = 2.7 to 5.5v, 0 to +70 c g = 2.7 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c p = 8-lead pdip p = 8-lead pdip
X25057 17 notes
X25057 18 u.s. sales offices corporate of?e xicor inc. 1511 bu ckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne@smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se@smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma@smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 630/372-3200 fax: 630/372-3210 e-mail: xicor-nc@smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 972/669-2022 fax: 972/644-5835 e-mail: xicor-sc@smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com northwest region xicor inc. 3333 bowers ave. suite 238 santa clara, ca 95054 phone: 408/492-1966 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com international sales offices europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.703844 fax: (44) 1933.703833 e-mail: xicor-uk@smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm@smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp@smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com singapore/malaysia/india xicor inc. 3333 bowers ave. suite 238 santa clara, ca 95054 phone: 408/492-1966 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com korea xicor korea, ltd. 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2.551.2750 fax: (82) 2.551.2710 e-mail: xicor-ka@smtpgate.xicor.com ( ) = country code xicor, inc., marketing dept. 1511 buc keye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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