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tl/h/11026 LMD18400 quad high side driver june 1996 LMD18400 quad high side driver general description the LMD18400 is a fully protected quad high side driver. it contains four common-drain dmos n-channel power switches, each capable of switching a continuous 1 amp load ( l 3 amps transient) to a common positive power sup- ply. the switches are fully protected from excessive voltage, current and temperature. an instantaneous power sensing circuit calculates the product of the voltage across and the current through each dmos switch and limits the power to a safe level. the device can be disabled to produce a ``sleep'' condition reducing the supply current to less than 10 m a. separate on/off control of each switch is provided through standard lstll/cmos logic compatible inputs. a microwire tm compatible serial data interface is built in to provide extensive diagnostic information. this information includes switch status readback, output load fault conditions and thermal and overvoltage shutdown status. there are also two direct-output error flags to provide an immediate indication of a general system fault and an indication of ex- cessive operating temperature. the LMD18400 is packaged in a special power dissipating leadframe that reduces the junction to case thermal resist- ance to approximately 20 c/w. features y four independent outputs with l 3a peak, 1a continu- ous current capability y 1.3 x maximum on resistance over temperature y true instantaneous power limit for each switch y high survival voltage (60 v dc , 80v transient) y shorted load (to ground and supply) protection y overvoltage shutdown at v cc l 35v y ls ttl/cmos compatible logic inputs and outputs y k 10 m a supply current in ``sleep'' mode y b 5v output clamp for discharging inductive loads y serial data interface for 11 diagnostic checks: e switch on/off status e open or shorted load e operating temperature e excessive supply voltage y two direct-output error flags applications y relay and solenoid drivers y high impedance automotive fuel injector drivers y lamp drivers y power supply switching y motor drivers typical application tl/h/11026 1 connection diagram tl/h/11026 2 order number LMD18400n see ns package number n20a tri-state is a registered trademark of national semiconductor corporation. microwire tm is a trademark of national semiconductor corporation. c 1996 national semiconductor corporation rrd-b30m76/printed in u. s. a. http://www.national.com
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply survival voltage (pin 20) transient (t e 10 ms) 80v continuous b 0.5v to a 60v output transient current (each switch) 3.75a output transient current (total, all switches) 6a output steady state current (each switch) 1a logic input voltage (pins 3, 9, 10, 11, 12) b 0.3v to a 16v logic input voltage (pins 4, 7) b 0.3v to a 6v error flag voltage 16v esd susceptibility (note 2) 2000v power dissipation (note 3) 5w internally limited junction temperature (t j max ) 150 c storage temperature range b 65 cto a 150 c lead temperature (soldering, 10 sec.) a 260 c operating ratings (note 1) ambient temperature range (t a ) b 25 cto a 85 c supply voltage range 7v to 28v electrical characteristics v cc e 12v, c cp e 0.01 m fd, unless otherwise indicated. boldface limits apply over the entire operating temperature range, b 25 c s t a s a 85 c, all other limits are for t a e t j ea 25 c. parameter conditions typical limit units (note 4) (note 5) (limit) dc characteristics supply current enable input e 0v 0.04 10 m a (max) enable input e 5v, inputs e 0v 7.5 15 ma (max) enable input e 5v, inputs e 5v open loads 7.5 15 ma (max) output leakage enable input e 0v, inputs e 0v 0.01 300 m a (max) (pins 1, 2, 18, 19) rds on i out e 1a, (note 6) 0.8 1.3 x (max) short circuit current v cc e 12v, (note 6) 1.2 0.6 a (min) v cc e 7v, (note 6) 2.4 a v cc e 28v, (note 6) 0.6 a maximum output current v cc b v o e 4v, (note 6) 3.75 a load error threshold voltage pins 1, 2, 18, 19 4.1 v open load detection current pins 1, 2, 18, 19 150 m a negative clamp output voltage i o e 1a, (note 6) b 5v overvoltage shutdown threshold 31 40 v (max) overvoltage shutdown hysteresis 0.75 v error output leakage current v pin 13 e 12v 0.001 10 m a (max) thermal warning temperature v pin 13 k 0.8v 145 c thermal shutdown temperature v pin 17 k 0.8v 170 c http://www.national.com 2
electrical characteristics v cc e 12v, c cp e 0.01 m f, unless otherwise indicated. boldface limits apply over the entire operating temperature range, b 25 c s t a s a 85 c, all other limits are for t a e t j ea 25 c. (continued) parameter conditions typical limit units (note 4) (note 5) (limit) ac characteristics switch turn-on delay enable (pin 3) e 5v, 510 m s (max) (t d(on) )i out e 1a switch turn-on rise i out e 1a 715 m s (max) time (t on ) switch turn-off delay enable (pin 3) e 5v, 0.5 2 m s (max) (t doff )i out e 1a switch turn-off fall i out e 1a 0.15 1 m s (max) time (t off ) enable time (t en ) measured with switch 1, 30 50 m s (max) pin 9 e 5v error reporting delay enable (pin 3) e 5v, 75 150 m s (max) (t error ) switch 1 load opened data setup time (t ds )c l e 30 pf 200 500 ns (min) tri-state control (t 1h ,t oh ) pin 8, hi-z enable time 2 m s data clock frequency 3 1 mhz (max) digital characteristics logic ``1'' input voltage pins 3, 4, 7, 9, 10, 11, 12 2.0 v (min) logic ``0'' input voltage pins 3, 4, 7, 9, 10, 11, 12 0.8 v (max) logic ``1'' input current pins 4, 7 0.001 1 m a (max) logic ``0'' input current pins 4, 7 b 0.001 b 1 m a (max) tri-state output current pin 8, pin 4 e 5v 0.05 10 m a (max) pin 8 e 0v b 0.05 b 10 m a (max) enable input current pin 3 e 2.4v 12 25 m a (max) channel input resistance pins 9, 10, 11, 12 75 15 k x (min) error output sink current pin 13 e 0.8v 4 1.6 ma (min) logic ``1'' output voltage pin 8 i out eb 360 m a 4.4 2.4 v (min) i out eb 10 m a 5.1 4.5 v (min) i out eb 10 m a 5.5 v (max) logic ``0'' output voltage pin 8 0.4 v (max) i out e 100 m a thermal shutdown output pin 17 e 2.4v 53 m a (min) source current thermal shutdown output pin 17 e 0.8v 360 250 m a (min) sink current http://www.national.com 3
electrical characteristics notes note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. for guaranteed specifications and test conditions, see the electrical characteristics. note 2: human body model; 100 pf discharge through a 1.5 k x resistor. all pins except pins 8 and 13 which are protected to 1000v and pins 1, 2, 18 and 19 which are protected to 500v. note 3: the maximum power dissipation is a function of t j max , i ja , and t a and is limited by thermal shutdown. the maximum allowable power dissipation at any ambient temperature is p d e (t j max b t a )/ i ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the device will eventually go into thermal shutdown. for the LMD18400 the junction-to-ambient thermal resistance, i ja ,is60 c/w. with sufficient heatsinking the maximum continuous power dissipation for the package will be, i dc max 2 c r on (max) c 4 switches (1a 2 c 1.3 x c 4 e 5.2w). note 4: typical values are at t j ea 25 c and represent the most likely parametric norm. note 5: all limits are 100% production tested at a 25 c. limits at temperature extremes are guaranteed through correlation and accepted statistical quality control (sqc) methods. note 6: pulse testing techniques used. pulse width is k 5 ms with a duty cycle k 1%. timing specification definitions switching turn on/off tl/h/11026 3 enable turn-on tl/h/11026 4 error reporting delay tl/h/11026 5 data setup time tl/h/11026 6 http://www.national.com 4
typical performance characteristics for all curves, v cc e 12v, temperature is the junction temperature unless otherwise noted. vs temperature switch on resistance tl/h/11026 31 vs temperature ``sleep'' mode supply current tl/h/11026 32 ambient temperature dissipation vs maximum power tl/h/11026 33 vs temperature short circuit current tl/h/11026 34 vs temperature clamp characteristics tl/h/11026 35 voltage vs temperature error sense threshold tl/h/11026 36 vs temperature turn on rise time tl/h/11026 37 vs temperature turn on delay time tl/h/11026 38 vs temperature turn off time tl/h/11026 39 resistance vs temperature switch select logic input tl/h/11026 40 vs temperature enable threshold voltage tl/h/11026 41 vs sink current error output voltage tl/h/11026 42 http://www.national.com 5
functional block diagram tl/h/11026 8 truth table enable chip select switch control error thermal sd input input input output output conditions (pin 3) (pin 4) (pins 9, 10, 11, 12) (pin 13) (pin 17) 0 x x 1 0 ``sleep'' mode, i supply k 10 m a 1 x 0 1 1 selected switch is off 1 x 1 1 1 selected switch is on, normal operation 1 x 0 0 1 switch is off but: a. load is open circuited, or b. load is shorted to v cc ,or c. t j l a 145 c, or d. v cc l a 35v 1 x 1 0 1 switch is on, but; a. load is shorted to ground, or b. switch is in power limit, or c. t j l a 145 c, or d. v cc l a 35v and switch is actually off 1x 1 0 0t j l a 170 c, all switches are off 1 1 x x x data output pin is tri-state 1 0 x x x data output pin is enabled and ready to output diagnostic information http://www.national.com 6
applications information basic operation high-side drivers are used extensively in automotive and industrial applications to switch power to ground referred loads. the major advantage of using high-side drive, as op- posed to low-side drive, is to protect the load from being energized in the event that the load drive wire is inadver- tently shorted to ground as shown in figure 1 . a high-side driver can sense a shorted condition and open the power switch to disable the load and eliminate the excessive cur- rent drain on the power supply. the LMD18400 can control and protect up to four separate ground referenced loads. high side drive tl/h/11026 9 low side drive tl/h/11026 10 figure 1. high-side vs low-side drive the LMD18400 combines low voltage cmos logic control circuitry with a high voltage dmos process. each dmos power switch has an individual on/off control input. when commanded on, the output of the switch will connect the load to the v cc supply through a maximum resistance of 1.3 x (the on resistance of the dmos switch). the voltage applied to the load will depend upon the load current and the designed current capability of the LMD18400. when a switch is commanded off, the load will be disconnected from the supply except for a small leakage current of typi- cally less than 0.01 m a. the LMD18400 can be continually connected to a live pow- er source, a car battery for example, while drawing less than 10 m a from the power source when put into a ``sleep'' con- dition. this ``sleep'' mode is enacted by taking the enable input (pin 3) low. during this mode the supply current for the device is typically only 0.04 m a. special low current con- sumption standby circuitry is used to hold the dmos switches off to eliminate the possibility of supply voltage transients from turning on any of the loads (a common prob- lem with mos power devices). when in the ``sleep'' mode, all diagnostic and logic circuitry is inactive. when the enable input is taken to a logic 1, the switches become ``armed'' and ready to respond to their control input after a short, 30 m s, enable delay time. this delay interval prevents the switches from transient turn-on. figure 2 shows the switch control logic. tl/h/11026 11 figure 2. control logic for each power switch each dmos switch is turned on when its gate is driven approximately 3.5v more positive than its source voltage. because the source of the switch is the output terminal to the load it can be taken to a voltage very near the v cc supply potential. to ensure that there is sufficient voltage available to drive the gates of the dmos device a charge pump circuit is built in. this circuit is controlled by an internal 300 khz oscillator and using an external 10 nf capacitor connected from pin 14 to ground generates a voltage that is approximately 20v greater than the v cc supply voltage. this provides sufficient gate voltage drive for each of the switches which is applied under command of standard 5v logic input levels. the turn-on time for each switch is approximately 12 m s when driving a 1a load current. this relatively slow switch- ing time is beneficial in minimizing electromagnetic interfer- ence (emi) related problems created from switching high current levels. http://www.national.com 7
applications information (continued) protection circuitry the LMD18400 has extensive protection circuitry built in. with any power device, protection against excessive volt- age, current and temperature conditions is essential. to achieve a ``fail-safe'' system implementation, the loads are deactivated automatically by the LMD18400 in the event of any detected overvoltage or over-temperature fault condi- tions. voltage protection the v cc supply can range from b 0.5v to a 60 v dc without any damage to the LMD18400. the cmos logic circuitry is biased from an internal 5.1v regulator which protects these lower voltage transistors from the higher v cc potentials. in order to protect the loads connected to the switch outputs however, an overvoltage shutdown circuit is employed. should the v cc potential exceed 35v all of the switches are turned off thereby disconnecting the loads. this 35v threshold has 750 mv of hysteresis to prevent potential os- cillations. additionally, there is an undervoltage lockout feature built in. with v cc less than 5v it becomes uncertain whether the logic circuitry can hold the switches in their commanded state. to avoid this uncertainty, all of the switches are turned off when v cc drops below approximately 5v. figure 3 illustrates the shutoff of an output during a 0v to 80v v cc supply transient. over/under voltage shutdown tl/h/11026 12 figure 3. overvoltage/undervoltage shutdown the LMD18400 has been designed to drive all types of loads. when driving a ground referenced inductive load such as a relay or solenoid, the voltage across the load will reverse in polarity as the field in the inductor collapses when the power switch is turned off. this will pull the output pin of the LMD18400 below ground. this negative transient voltage is clamped at approximately b 5v to protect the ic. this clamping action is not done with diodes but rather the power dmos switch turning back on momentarily to con- duct the inductor current as it de-energizes as shown in figure 4. tl/h/11026 13 figure 4. turn-off conditions with an inductive load when the output inductance produces a negative voltage, the gate of the dmos transistor is clamped at 0v. at b 3.5v, the source of the power device is less than the gate by enough to cause the switch to turn on again. during this negative transient condition the power limiting circuitry to protect the switch is disabled due to the gate being held at 0v. the maximum current during this clamping interval, which is equal to the steady state on current through the inductor, should be kept less than 1a. another concern dur- ing this interval has to do with the size of an inductive load and the amount of time required to de-energize it. with larg- er inductors it may be possible for the additional power dis- sipation to cause the die temperaure to exceed the thermal shutdown limit. if this occurs all of the other switches will turn off momentarily (see section on thermal manage- ment). power limiting the LMD18400 utilizes a true instantaneous power limit cir- cuit rather than simple current limiting to protect each switch. this provides a higher transient current capability while still maintaining a safe power dissipation level. the power dissipation in each switch (the product of the drain-to source voltage and the output current, v ds c i out ) is con- http://www.national.com 8
applications information (continued) tinually monitored and limited to 15w by varying the gate voltage and therefore the on resistance of the switch. basi- cally the on resistance will be as low as possible until 15w is being dissipated. to maintain 15w, the on resistance increases to reduce the load current. this results in a de- crease of the output voltage. for resistive loads, the output voltage when in power limit will be: v out (in power limit) e v cc b 0 v cc 2 b 60 r l 2 this provides a maximum transient current and drain-to- source voltage characteristic as shown in figure 5 . tl/h/11026 14 figure 5. maximum output current with instantaneous power limiting driving a lamp tl/h/11026 15 figure 6. soft turn-on of a lamp load the steady state current to the load is limited by the pack- age power dissipation, ambient temperature and the on re- sistance of the switch which has a positive temperature co- efficient as shown in the typical performance characteris- tics. this dynamic current limiting of the switches is beneficial when driving lamp and large capacitive loads. lamps re- quire a large inrush current, on the order of 10 times the normal operating current, when first switched on with a cold filament. the LMD18400 will limit this initial current to the level where 15w is dissipated in the switch. as the filament warms up the voltage across the lamp increases thereby decreasing the voltage across the switch which permits more current to fully light the lamp. with limited inrush cu- rent the lifetime of a lamp load is increased significantly. figure 6 illustrates the soft turn-on of a lamp load. the same principle of increasing output current as the volt- age across the load increases allows large capacitive loads to be charged more quickly by an LMD18400 driver than as opposed to a driver with a fixed 1a current limit protection scheme. figure 7 shows the output response while driving a large capacitive load. thermal protection the die temperature of the LMD18400 is continually moni- tored. should any conditions cause the die temperature to rise to a 170 c, all of the power switches are turned off automatically to reduce the power dissipation. it is important to realize that the thermal shutdown affects all four of the switches together. that is, if just one switch load is enough to heat the die to the thermal shutdown threshold, all of the other switches, regardless of their power dissipation condi- tions, will be switched off. all of the switches will be re-en- abled when the die temperature has cooled to approximate- ly a 160 c. until the high temperature forcing conditions have been removed the switches will cycle on and off thus maintaining an average die temperature of a 165 c. the LMD18400 will signal that excessive temperatures exist through several diagnostic output signals (see diagnostics). driving a large capacitive load tl/h/11026 16 figure 7. driving a large capacitive load http://www.national.com 9
applications information (continued) diagnostics the LMD18400 has extensive circuit diagnostic information reporting capability. use of this information can produce systems with intelligent feedback of switch status as well as load fault conditions for troubelshooting purposes. all of the diagnostic information is contained in an 11-bit word. this data can be clocked out of the LMD18400 in a serial fashion as shown in figure 8 . the shift register is parallel loaded with the diagnostic data whenever the chip select input is at a logic 1 and changes to the serial shift mode when chip select is taken to a logic 0. the data output line (pin 8) is biased internally from a 5.1v regulator which sets the logic 1 output voltage. this pin has low current sourcing capability so any load on this pin will reduce the logic 1 output level which is guaranteed to be at least 2.4v with a 360 m a load. the data interface is microwire compatible in that data is clocked out of the LMD18400 on the falling edge of the clock, to be clocked into the controlling microprocessor on the rising edge. any number of devices can share a com- mon data output line because the data output pin is held in a high impedance (tri-state) condition until the device is selected by taking its chip select input low. following chip select going low there is a short data setup time interval (500 ns min) required. this is necessary to allow the first data bit of information to be established on the data output line prior to the first rising clock edge which will input the data bit into the controller. when all 11 bits of diagnostic data have been shifted out the data output goes to a logic 1 level until the chip select line is returned high. figure 8 also indicates the significance of the diagnostic data bits. the first 4 bits indicate an output load error condi- tion, one for each channel in succession (see load error detection). bits 5 through 8 provide a readback of the commanded on/off status of each switch. a unique feature of the LMD18400 is that it provides an early warning of excessive operating temperature. should the die temperature exceed a 145 c, bit 9 will be set to a logic 0. acting on this information a system can be pro- grammed to take corrective action, shutting off specific loads perhaps, while the LMD18400 is still operating nor- mally (not yet in thermal shutdown). if this early warning is ignored and the device continues to rise in temperature, the thermal shutdown circuitry will come into action at a die tem- perature of a 170 c. should this occur bit 10 of the diag- nostic data stream will be set to a logic 0 indicating that the device is in thermal shutdown and all of the outputs have been shut off. the final data bit, bit 11, indicates an overvoltage condition on the v cc supply (v cc is greater than 35v) and again indi- cates that all of the drivers are off. the diagnostic data can be read periodically by a controller or only in the event of a general system error indication to determine the cause of any system problem. this general indication of a fault is provided by an error flag output (pin 13). this pin goes low whenever any type of error is detect- ed. there is a built-in delay of approximately 75 m s from the time an error is detected until pin 13 is taken low. this is to help mask short duration error conditions such as may be caused by driving highly capacitive loads ( l 2 m f). a lamp load may generate a shorted load error for several hundred milliseconds as it turns on which should be ignored. tl/h/11026 17 figure 8. serial diagnostic data assignments http://www.national.com 10
applications information (continued) the error flag output pin is an open drain transistor which requires a pull-up resistor to a positive voltage of up to 16v. typically this pull-up is to the same 5v supply which is bias- ing the enable input and any other external logic circuitry. the error flag pins of several LMD18400 packages can be connected together with just one pull-up resistor to provide an all-encompassing general system error indication. upon detection of an error, each device could then be polled for diagnostic information to determine the source of the fault condition. a second direct output error flag is for an indication of ther- mal shutdown (pin 17). this active low flag provides an im- mediate indication that the die temperature has reached a 170 c and that the drive to all four switches has been removed. this output is pulled up to the internal 5.1v logic regulator through a small (5 m a) current source so use of a buffer on this pin is recommended. tl/h/11026 18 figure 9. thermal shutdown flag and shutdown input a useful feature of pin 17 is that it can also be used as a shutdown input. driving this pin low immediately switches all of the drivers off, just the same as if thermal shutdown temperatures has been reached, yet all of the control logic and diagnostic circuits remain active. this is useful in de- signing ``fail-safe'' systems where the loads can be disabled under any sort of externally detected system fault condition. the diagnostic logic however does not distinguish between normal thermal shutdown or the fact that pin 17 has been driven low. as such, various switch errors and an over-tem- perature indication will be reported in the diagnostic data stream. figure 9 illustrates the use of pin 17 as both an output ther- mal shutdown flag and as an input to shut down only the switches. directly tying pin 17 to a 5v will prevent the inter- nal thermal shutdown circuitry from disabling the switches. for reliability purposes however this is not recommended as there will then be no limit to the maximum die temperature. refer to the truth table for a summary of the action of these direct-output error flags. load error detection an important feature of the LMD18400 is the ability to de- tect open or shorted load connections. figure 10 illustrates the detection circuit used with each of the drivers. tl/h/11026 19 figure 10. detection circuitry for open/shorted loads a voltage comparator monitors the voltage to the load and compares it to a fixed 4.1v reference level. when a switch is off, the ground referenced load should have no voltage across it. under this condition, an internal 50 k x resistor connected to v cc will provide a small amount of current to the load. if the load resistance is large enough to create a voltage greater than 4.1v an open load error will be indi- cated for that switch. the maximum load resistance that will not generate an open load error when a switch is off can be found by: r max e 4.1v v cc b 4.6v c 50 k x ; for no open load indication to make this open load error threshold more sensitive, an external pull-up resistor can be added from the output to the v cc supply. also when a switch is commanded off, should the load be shorted to the v cc supply, this same circuitry will again indi- cate an error. when a switch is commanded on, the load is expected to have a voltage across it that approaches the v cc potential. if the output voltage is less than the 4.1v threshold an error will again be reported, indicating that the load is either short- ed to ground or that the driver is in power limit and not able to pull the output voltage any closer to v cc . the minimum load resistance that will not generate a shorted load error when a switch is on can be found by: r min e 4.1v (v cc b 4.1v) 15w ; for no shorted load error http://www.national.com 11
applications information (continued) figure 11 indicates the range of load resistance for normal operation, open load, and shorted load or power limit indica- tion. tl/h/11026 20 figure 11. load resistance detected as errors thermal management it is particularly important to consider the total amount of power being dissipated by all four switches in the LMD18400 at all times. any combination of the switches driving loads will cause an increase in the die temperature. should the die temperature reach the thermal shutdown threshold of a 170 c, all of the switches will be disabled. careful calculation of the worst case total power dissipation required at any point in time, together with providing suffi- cient heatsinking will prevent this from occurring. the LMD18400 is packaged with a special leadframe that helps dissipate heat through the two ground pins on each side of the package. the thermal resistance from junction- to-case ( i jc ) for this package is approximately 20 c/w. the thermal resistance from junction-to-ambient ( i ja ), with- out any heatsinking, is approximately 60 c/w. figure 12 il- lustrates how the copper foil of a printed circuit board can be designed to provide heatsinking and reduce the overall junction-to-ambient thermal resistance. the power dissipation in each switch is equal to: p d (each switch) e i load 2 c r on or (v cc b v out ) 2 r on where r on is the on resistance of the switch (1.3 x maxi- mum). these equations hold true until the power dissipation reaches the maximum limit of 15w. with resistive loads, the 15w power limit threshold will be reached when: r l s v cc 2 60w inductive loads will create additional power dissipation when switched off. figure 13 shows the idealized voltage and current waveforms for an inductive load. tl/h/11026 21 maximum power dissipated and junction to ambient thermal resistance vs size tl/h/11026 22 figure 12. recommended pc board layout to reduce the thermal resistance from junction-to-ambient http://www.national.com 12
applications information (continued) tl/h/11026 23 figure 13. switching an inductive load when switched on, the worst case power dissipation is: p d(on) e i peak 2 c r on ; where i peak e v cc r on a r s the steady-state on current of the inductor should be kept less than 1a per power switch. the additional power dissipation during turn-off, as the in- ductor is de-energized and the voltage across the inductor is clamped to b 5v, can be found by: p d(off) e (v cc a 5v) c i peak 2 for the time interval, t clamp , which is the time required for the inductor current to fall to zero; t clamp e i peak c l 5v the size of the inductor will determine the time duration for this additional power dissipation interval. even though the peak current is kept less than 1a, the switch during this interval will see a voltage across it of v cc a 5v with no power limit protection. if the inductor is too large, the time interval may be long enough to heat the die temperature to a 170 c thereby shutting off all other loads on the pack- age. the total average power dissipation during a full on/off switching cycle of an inductive load will be: p d(tot) e e i peak 2 r on t on a i peak 2 l(v cc a 5v) 10 ( 1 t on a t off due to the common cut-off of all loads forced by thermal shutdown, the thermal time constants of the package be- come a concern. figure 14 provides an indication of the time it takes to heat the die to thermal shutdown with a step increase in package power dissipation from an initial junc- tion temperature of a 25 c. this data was measured using a pc board layout providing a thermal resistance from junc- tion to ambient of approximately 35 c/w. less heatsinking will, of course, result in faster thermal shutdown of the pow- er switches. tl/h/11026 24 figure 14. approximate time required for the die to reach the 170 c thermal shutdown point from 25 c for different total package power dissipation levels. http://www.national.com 13
applications on/off switching of multiple voltage regulated circuit loads tl/h/11026 25 unipolar drive for a 4-phase stepper motor tl/h/11026 26 http://www.national.com 14
applications (continued) recommended connection if no diagnostics are required tl/h/11026 27 simple protection of the LMD18400 against supply voltage reversal. loads will be energized through the intrinsic diodes in parallel with the power switches. the schottky diode will add approximately 0.2v to the logic input switching thresholds and the logic output low levels. tl/h/11026 28 http://www.national.com 15
applications (continued) simple light ``chaser'' tl/h/11026 29 parallelling switches for higher current capability. positive temperature coefficient of the switch on resistance provides ballasting to evenly share the load current between the switches. any combination of switches can be paralleled. required peak load current will depend upon the motor load. motor speed control can be provided by a pwm signal of up to 20 khz applied to the motor drive input lines. tl/h/11026 30 http://www.national.com 16
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LMD18400 quad high side driver physical dimensions inches (millimeters) unless otherwise noted order number LMD18400n ns package number n20a life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: a 49 (0) 180-530 85 86 13th floor, straight block, tel: 81-043-299-2308 arlington, tx 76017 email: europe.support @ nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: a 49 (0) 180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: a 49 (0) 180-532 78 32 hong kong fran 3 ais tel: a 49 (0) 180-532 93 58 tel: (852) 2737-1600 http://www.national.com italiano tel: a 49 (0) 180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.

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