vishay siliconix si9165 document number: 70845 s-72058-rev. d, 08-oct-07 www.vishay.com 1 high frequency 600-ma sync hronous buck/boost converter features ? voltage mode control ? fully integrated mosfet switches ? 2.7 v to 6 v input voltage range ? programmable pwm/psm control - up to 600 ma output current at 3.3 v in pwm - up to 2 mhz adjustable switching frequency in pwm - less than 200 a quiescent current in psm ? integrated uvlo and por ? integrated soft-start ? synchronization ? shutdown current < 1 a description the si9165 provides fully integrated synchronous buck or boost converter solution for the latest one cell lithium ion cellular phones. capable of delivering up to 600 ma of output current at + 3.3 v, the si9165 provides ample power for various baseband circuits as well as for some pas. it combines the 2 mhz switching controller with fully integrated high-frequency mosfets to del iver the smallest and most efficient converter available today. the 2 mhz switching frequency reduces the inductor height to new level of 2 mm and minimizes the output capacitance requirement to less than 10 f with peak-to-peak output ripple as low as 10 mv. combined with low-gate charge high-frequency mosfets, the si9165 delivers efficiency up to 95 %. the programmable pulse skipping mode maintains this high efficiency even during the standby and idle modes to increase overall battery life and talktime. in order to extract the last ounce of power from the battery, the si9165 is designed with 100 % duty cycle control for buck mode. with 100 % duty cycle, the si9165 operates like a saturated linear regulator to deliver the highest potential output voltage for longer talktime. the si9165 is available in lead (pb)-free tssop-20 pin packages. in order to satisfy the stringent ambient temperature requirements, the si9165 is rated to handle the industrial temperature range of - 25 c to 85 c. standard application circuits boost configuration v dd mode shutdo wn p w m/psm sy n c v o v s v i n /out fb comp r osc ref pg n dg n d coil v out 0 to 600 ma v i n 2.7 to 6 v buck configuration v i n /out v s v dd shutdo wn p w m/psm sy n c coil pg n d fb comp r osc ref pg n dg n d v o v out 0 to 600 ma v i n 2.7 to 6 v mode rohs compliant
www.vishay.com 2 document number: 70845 s-72058-rev. d, 08-oct-07 vishay siliconix si9165 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 8.0 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit voltages referenced to gnd v dd 6.5 v mode, pwm/psm , sync, sd , v ref , r osc , comp, fb - 0.3 v to v dd + 0.3 v v o - 0.3 v to v s + 0.3 v pgnd 0.3 voltages referenced to pgnd v s , v in/out 6.5 v coil - 0.4 v to v in/out + 0.4 v peak output current 3 a continuous output current 1 storage temperature range - 65 to 150 c operating junction temperature 150 power dissipation (package) a 20-pin tssop (q suffix) b 1.0 w thermal impedance ( ja ) 20-pin tssop 125 c/w recommended operating conditions parameter limit unit voltages referenced to gnd v dd 2.7 v to 6 v v v mode, pwm/psm , sync, sd 0 v to v dd voltages referenced to pgnd v s , v in/out 2.7 v to 6 v v f osc 200 khz to 2 mhz r osc 25 k to 300 k k v ref capacitor 0.1 f specifications parameter symbol test conditions unless otherwise specified 2.7 v < v dd < 6 v, v in/out = 3.3 v, v s = 3.3 v limits unit min a typ b max a reference output voltage v ref i ref = 0 a 1.268 1.3 1.332 v t a = 25 c, i ref = 0 1.280 1.3 1.320 load regulation v ref v dd = 3.3 v, - 500 a < i ref < 0 3mv power supply rejection p srr 60 db uvlo under voltage lockout (turn-on) v uvlo/lh 2.3 2.4 2.5 v hysteresis v hys v uvlolh - v uvlohl 0.1 soft-start time ss time t ss 6ms mode logic high v ih 0.7 v dd v logic low v il 0.3 v dd input current i l - 1.0 1.0 a
document number: 70845 s-72058-rev. d, 08-oct-07 www.vishay.com 3 vishay siliconix si9165 notes: a. the algebraic convention whereby the most negative value is a minimu m and the most positive a maximum. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. v in = v dd , v out = v in/out = v s = v o , l = 1.5 h. d. v in = v dd = v s = v in/out , v out = v o , l = 1.5 h. specifications parameter symbol test conditions unless otherwise specified 2.7 v < v dd < 6 v, v in/out = 3.3 v, v s = 3.3 v limits unit min a typ b max a sd , sync, pwm/psm logic high v ih 2.4 v logic low v il 0.8 input current i l - 1.0 1.0 a oscillator maximum frequency f max 2mhz accuracy nominal 1.60 mhz, r osc = 30 k - 20 20 % maximum duty cycle (buck, non ldo mode) d max f sw = 2 mhz 75 85 maximum duty cycle (boost) 50 65 sync range f sync /f osc 1.2 1.5 sync low pulse width 50 ns sync high pulse width 50 sync t r , t f 50 error amplifier input bias current i bias v fb = 1.5 v - 1 1 a open loop voltage gain a vol 50 60 db fb threshold v fb t a = 25 c 1.270 1.30 1.330 v 1.258 1.30 1.342 unity gain bw bw 2 mhz output current i ea source (v fb = 1.05 v), v comp = 0.75 v - 3 - 1 ma sink (v fb = 1.55 v), v comp = 0.75 v 13 output current output current (pwm) boost mode c i out v in v out = 2.7 to 5.0 v 600 ma buck mode d v in v out = 2.7 to 6.0 v 600 output current (psm ) boost mode c v in = 3.3 v, v out = 3.6 v 150 buck mode d v in = 3.6 v, v out = 2.7 v 150 r ds(on) n-channel r ds(on) v s 3.3 v 130 300 m r ds(on) p-channel 160 330 over temperature protection trip point rising temperature 165 c hysteresis 25 supply current normal mode i dd v dd = 3.3 v, f osc = 2 mhz 500 750 a psm mode v dd = 3.3 v 180 250 shutdown mode v dd = 3.3 v, sd = 0 v 1
www.vishay.com 4 document number: 70845 s-72058-rev. d, 08-oct-07 vishay siliconix si9165 typical characteristics 25 c, unless otherwise noted v ref vs. v dd frequency vs. temperature buck mode efficiency, v o = 2.7 v 1.290 1.295 1.300 1.305 1.310 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd - (v) ) v ( v f e r 1.70 1.75 1.80 1.85 1.90 1.95 2.00 - 100 - 50 0 50 100 150 ) z h m ( y c n e u q e r f temperature (c) r osc = 25 k 1 60 65 1000 70 80 85 90 100 load current (ma) ) % ( y c n e i c i f f e 10 100 75 psm - 3.6 v psm - 3 v psm - 4.2 v pwm - 3 v pwm - 3.6 v pwm - 4.2 v 95 v ref vs. temperature frequency vs. r osc boost mode efficiency, v o = 3.6 v 1.28 1.29 1.30 1.31 1.32 - 50 0 50 100 150 temperature (c) ) v ( v f e r 100 1000 10000 10 100 1000 r osc (k ) ) z h k ( y c n e u q e r f 1 60 65 1000 70 80 85 90 95 load current (ma) ) % ( y c n e i c i f f e 10 100 75 psm - 3.3 v psm - 2.7 v pwm - 3.3 v pwm - 2.7 v
document number: 70845 s-72058-rev. d, 08-oct-07 www.vishay.com 5 vishay siliconix si9165 typical characteristics 25 c, unless otherwise noted pin configuration and ordering information pwm supply current 200 300 400 500 600 700 800 234567 v dd - (v) ) a m ( i d d psm supply current 50 100 150 200 250 234567 v dd - (v) ) a m ( i d d 20 19 18 17 1 2 3 4 16 15 14 13 5 6 7 8 nc coil sd coil pwm/psm mode v in/out pgnd v in/out pgnd v in/out v s sync v o gnd v dd tssop-20 top view 12 11 9 10 v ref r osc fb comp si9165bq ordering information part number temperature range package SI9165BQ-T1-E3 - 25 to 85 c tape and reel eval kit temperature range board type si9165db - 25 to 85 c surface mount pin description pin number name function 1 n/c not used 2sd shuts down the ic completely and decreases current consumed by the ic to < 1 a. 3 pwm/psm logic high = pwm mode, logic low = psm mode. in psm mode, synchronous rectification is disabled. 4, 5, 6 v in/out input node for buck mode and output node for boost mode. 7 sync externally controlled synchronizat ion signal. logic high to low transiti on forces the clock synchronization. if not used, the pin must be connected to v dd , or logic high. 8 gnd low power controller ground 9 v ref 1.3 v reference. decoupled with 0.1 f capacitor. 10 fb output voltage feedback connected to the inverting input of an error amplifier. 11 comp error amplifier output for external compensation network. 12 rosc external resistor to determine the switching frequency. 13 v dd input supply voltage for the analog circuitry. input voltage range is 2.7 v to 6 v. 14 v o direct output voltage sensing to cont rol peak inductor current in psm mode. 15 v s supply voltage for the inter nal mosfet drive circuit. 16, 17 pgnd power ground. 18 mode determines the converter topology. connect to agnd for buck or v dd for boost. 19, 20 coil inductor connection node
www.vishay.com 6 document number: 70845 s-72058-rev. d, 08-oct-07 vishay siliconix si9165 functional block diagram detail operational description start-up the uvlo circuit prevents t he internal mosfet switches and oscillator circuit from turning on, if the voltage on v dd pin is less than 2.5 v. with typi cal uvlo hysteresis of 0.1 v, controller is continuously powered on until the v dd voltage drops below 2.4 v. this hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. once the v dd voltage exceeds the uvlo threshold, and with no other shutdown condition detected, an internal power-o n-reset timer is activated while most circuitry, except t he output driver, are turned on. after the por timeout of about 1 ms, the internal soft-start capacitor is allowed to charge. when the soft-start capacitor voltage reaches 0.5 v, the pwm circuit is enabled. thereafter, the constant current charging the soft-start capacitor will force the output voltage to rise gradually without overshooting. to prevent negative undershoot, the synchronous switch is tri-st ated until the duty cycle reaches about 10 %. in tri-state, the high- side p-channel mosfet is turned off by pulling up the gate voltage to v s potential. the low-side n-channel mosfet is turned off by pulling down the gate voltage to pgnd potential. note that the si9165 will always soft starts in the pwm mo de regardless of the voltage level on the pwm/psm pin. shutdown the si9165 is designed to conserve as much battery life as possible by decreasing current consumption of ic during normal operation as well as t he shutdown mode. with logic low level on the sd pin, current consumption of the si9165 is decreased to less than 1 a by shutting off most of the circuits. the logic high enables the controller and starts up as described in "start-up" section above. reference threshold generator oscillator psm modulator pwm modulator soft-start timer uvlo por bias generator otp drivers pwm/psm select v dd sd v s v in/out gnd pgnd positive supply coil negative return and substrate p n pwm en psm en pwm in psm in 0.5 v 1.0 v ramp c osc v ref v o fb comp sync r osc pwm/psm mode
document number: 70845 s-72058-rev. d, 08-oct-07 www.vishay.com 7 vishay siliconix si9165 detail operational description (cont?d) over temperature protection the si9165 is designed with over temperature protection circuit to prevent mosfet switches from running away. if the temperature reaches 165 c, internal soft-start capacitor is discharged, shutting down the output stage. converter remains in the disabled mode unt il the temperature in the ic decreases below 140 c. pwm mode with pwm/psm mode pin in logic high condition, the si9165 operates in constant freque ncy (pwm) mode. as the load and line varies, switching frequency remain constant. the switching frequency is programmed by the rosc value as shown by the oscillator cu rve. in the pwm mode, the synchronous drive is always enabled, even when the output current reaches 0 a. in continuous current mode, transfer function of the converter remain constant, providing fast transient response. if t he converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. this transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltag e regulation. therefore, the pwm/psm pin is available to dynamically program the controller. the maximum duty cycle of the si9165 can reach 100 % in buck mode. this allows the system designers to extract out the maximum stored energy fr om the battery. once the controller delivers 100 % dut y cycle, converter operates like a saturated linear regulator. at 100 % duty cycle, synchronous rectification is completely turned off. up to a maximum duty cycle of 80 % at 2 mhz switching frequency, controller maintains perfect out put voltage regulation. if the input voltage drops below the level where the converter requires greater than 80 % duty cycle, controller will deliver 100 % duty cycle. this instan taneous jump in duty cycle is due to fixed bbm time, mosfet delay/rise/fall time, and the internal propagational delays. in order to maintain regulation, controller might fluctuate it s duty cycle back and forth from 100 % to something less than maximum duty cycle while the converter is operating in this input voltage range. if the input voltage drops further, controller will remain on 100 %. if the input voltage increases to a point where it requires less than 80 % duty cycle, synchronous rectification is once again activated. the maximum duty cycle under boost mode is internally limited to 75 % to prevent inductor saturation. if the converter is turned on for 100 % duty cycle, inductor never gets a chance to discharge its energy and eventually saturates. in boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. the controller will de liver 0 % duty cycle, if the input voltage is greater than the programmed output voltage. because of signal propagation time and mosfet delay/rise/ fall time, controller will not transition smoothly from minimum controllable duty cycle to 0 % duty cycle. for example, controller may decrease its duty cycle from 5 % to 0 % abruptly, instead of gradual decrease you see from 75 % to 5 %. pulse skipping mode the gate charge losses produced from the miller capacitance of mosfets are the dominant power dissipation parameter during light load (i.e. < 10 ma). therefore, less gate switching will improve overall converter efficiency. this is exactly why the si9165 is designed with pulse skipping mode. if the pwm/psm pin is connected to logic low level, converter operates in pulse skipping modulation (psm ) mode. during the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 a, instead of 500 a during the pwm mode. this is accomplished by turning off most of internal control circuitry and utilizing a simple constant on-time control with feedback comparat or. the controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blank ing time. if the output voltage drops below the desired level, the main switch is first turned on and then off. if the applied on-t ime is insufficient to provide the desired voltage, the contro ller will force another on and off sequence, until the desired voltage is accomplished. if the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. the excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. the on-time and off-time are set internally based on inductor used (1.5 h typical), mode pin selection and maximum load current. wide duty cycle range can be achieved in both buck and boost configurations. in pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss, which in turn improves overall converter efficiency. reference the reference voltage of the si9165 is set at 1.3 v. the reference voltage is internally connected to the non-inverting inputs of the error amplifier. the reference is decoupled with 0.1 f capacitor.
www.vishay.com 8 document number: 70845 s-72058-rev. d, 08-oct-07 vishay siliconix si9165 detail operational description (cont?d) error amplifier the error amplifier gain-bandwidth product and slew rate is critical parameters which dete rmines the transient response of converter. the transient respon se is function of both small and large signal response. the small signal is the converter closed loop bandwidth and phase margin while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. besides the inductance value, error amplifier determines the converter response time. in order to minimize the response time, the si9165 is designed with 2 mhz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 v/s slew rate for ultra- fast large signal response. oscillator the oscillator is designed to operate up to 2 mhz minimal. the 2 mhz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. even with 2 mhz switching frequency, quiescent current is only 500 a with unique power saving circuit design . the switching frequency is easily programmed by attaching a resistor to r osc pin. see oscillator frequency versus r osc curve to select the proper values for desired operating frequency. the tolerance on the operating frequency is 20 % with 1 % tolerance resistors. synchronization the synchronization to external clock is easily accomplished by connecting the external clock into the sync pin. a logic high to low transition synchronizes the clock. the external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. break-before-make timing a proper bbm time is essential in order to prevent shoot- through current and maintain high efficiency. the break- before-make time is set internally at 20 ns at v s = 3.6 v. the high and low-side mosfet drai n voltages are monitored and when the drain voltage reaches the 1.75 v below or above its initial starting voltage, 20 ns bbm time is set before the other switch turns on. the maximum controllable duty cycle is limited by the bbm time . since the bbm time is fixed, maximum controllable duty cycle will vary depending on the switching frequency. output mosfet stage the high- and low-side switches are integrated to provide optimum performance and to minimize the overall converter size. both, high and low-side switches are designed to handle up to 600 ma of continuous current. the mosfet switches were designed to minimize the gate charge loss as well as the conduction loss. for the high frequency operation, switching losses can exceed conduction loss, if the switches are designed incorrectly. under full load, efficiency of 90 % is accomplished with 3.6 v battery voltage in both buck and boost modes (+ 2.7 v output voltage for buck mode and + 5 v output voltage for boost mode). vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70845 .
1.00 seating plane 1.00 dia. d b e e/2 4x 0.20 c a ? bd 0.20 h a ? bd 2x n/2 tips 1.00 1.00 a n 123 see detail ?a? c l b b c e/2 x x = a and b lead sides top view h c aaa c a 1 a 2 a m c bbb a?b d 9 0.05 c b e d side view detail ?a? (scale: 30/1) (view rotated 90 c.w.) (14 ) h (14 ) 6 + + l ( ) 0.25 parting line end view e 1 package information vishay siliconix document number: 72818 28-jan-04 www.vishay.com 1 tssop: 20-lead (power ic only) millimeters dim min nom max a ? ? 1.10 a 1 0.05 ? 0.15 a 2 0.85 0.90 0.95 aaa 0.076 b 0.19 ? 0.30 b1 0.19 0.22 0.25 bbb 0.10 c 0.09 ? 0.20 c1 0.09 0.127 0.16 d 6.50 bsc e 6.40 bsc e 1 4.30 4.40 4.50 e 0.65 bsc l 0.50 0.60 0.70 n 20 p 4.2 p 1 3.0 0 ? 8 ecn: s-40082?rev. a, 02-feb-04 dwg: 5923
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