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ht9170b/ht9170d dtmf receiver selection table function operating voltage osc frequency tristate data output power down 1633hz inhibit dv dvb package part no. ht9170b 2.5v~5.5v 3.58mhz 18 dip ht9170d 2.5v~5.5v 3.58mhz 18 sop block diagram rev. 1.10 1 september 24, 2002 features operating voltage: 2.5v~5.5v minimal external components no external filter is required low standby current (on power down mode) excellent performance tristate data output for mcu interface 3.58mhz crystal or ceramic resonator 1633hz can be inhibited by the inh pin ht9170b: 18-pin dip package ht9170d: 18-pin sop package general description the ht9170b/d are dual tone multi frequency (dtmf) receivers integrated with digital decoder and bandsplit filter functions as well as power-down mode and inhibit mode operations. such devices use digital counting techniques to detect and decode all the 16 dtmf tone pairs into a 4-bit code output. highly accurate switched capacitor filters are imple - mented to divide tone signals into low and high group signals. a built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering.
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pin assignment pin description pin name i/o internal connection description vp i operational amplifier operational amplifier non-inverting input vn i operational amplifier inverting input gs o operational amplifier output terminal vreef o vref reference voltage output, normally v dd /2 x1 i oscillator the system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. a standard 3.579545mhz crystal connected to x1 and x2 terminals imple- ments the oscillator function. x2 o pwdn i cmos in pull-low active high. this enables the device to go into power down mode and inhibits the oscillator. this pin input is internally pulled down. inh i cmos in pull-low logic high. this inhibits the detection of tones representing characters a, b, c and d. this pin input is internally pulled down. vss negative power supply, ground oe i cmos in pull-high d0~d3 output enable, high active d0~d3 o cmos out tristate receiving data output terminals oe= h : output enable oe= l : high impedance dv o cmos out data valid output when the chip receives a valid tone (dtmf) signal, the dv goes high; other - wise it remains low. est o cmos out early steering output (see functional description) rt/gt i/o cmos in/out tone acquisition time and release time can be set through connection with ex - ternal resistor and capacitor. vdd positive power supply, 2.5v~5.5v for normal operation ht9170b/ht9170d rev. 1.10 2 september 24, 2002
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approximate internal connection circuits absolute maximum ratings supply voltage ............................................ 0.3v to 6v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 20 cto75 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.5 5 5.5 v i dd operating current 5v 3.0 7 ma i stb standby current 5v pwdn=5v 10 25 a v il low input voltage 5v 1.0 v v ih high input voltage 5v 4.0 v i il low input current 5v v vp =v vn =0v 0.1 a i ih high input current 5v v vp =v vn =5v 0.1 a r oe pull-high resistance (oe) 5v v oe =0v 60 100 150 k r in input impedance (vn, vp) 5v 10 m i oh source current (d0~d3, est, dv) 5v v out =4.5v 0.4 0.8 ma i ol sink current (d0~d3, est, dv) 5v v out =0.5v 1.0 2.5 ma f osc system frequency 5v crystal=3.5795mhz 3.5759 3.5795 3.5831 mhz ht9170b/ht9170d rev. 1.10 3 september 24, 2002 & 8 - . / 2 ' 2 " 2 - . ' % % 2 / . % 2 ' & $ # $ % 9 / / - ' % 9 / % 2 ' 0 9 / . - " 1 ! " 1 1 ! " % 2 ' &
a.c. characteristics f osc =3.5795mhz, ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions dtmf signal input signal level 3v 36 6 dbm 5v 29 1 twist accept limit (positive) 5v 10 db twist accept limit (negative) 5v 10 db dial tone tolerance 5v 18 db noise tolerance 5v 12 db third tone tolerance 5v 16 db frequency deviation acceptance 5v 1.5 % frequency deviation rejection 5v 3.5 % t pu power up time (see figure 4.) 5v 30 ms gain setting amplifier r in input resistance 5v 10 m i in input leakage current 5v v ss <(v vp ,v vn )100k 4.5 v pp r l load resistance (gs) 5v 50 k c l load capacitance (gs) 5v 100 pf v cm common mode range 5v no load 3.0 v pp steering control t dp tone present detection time 5 16 22 ms t da tone absent detection time 4 8.5 ms t acc acceptable tone duration 42 ms t rej rejected tone duration 20 ms t ia acceptable inter-digit pause 42 ms t ir rejected inter-digit pause 20 ms t pdo propagation delay (rt/gt to do) 811 s t pdv propagation delay (rt/gt to dv) 12 s t dov output data set up (do to dv) 4.5 s t ddo disable delay (oe to do) 300 ns t edo enable delay (oe to do) 50 60 ns note: do=d0~d3 ht9170b/ht9170d rev. 1.10 4 september 24, 2002
ht9170b/ht9170d rev. 1.10 5 september 24, 2002
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1 " 1 1 : ) ) 4 7 6 1 1 : 1 1 : 1 " / 1 ! " 1 ! " figure 1. test circuit functional description overview the ht9170b/d tone decoders consist of three band pass filters and two digital decode circuits to convert a tone (dtmf) signal into digital code output. an operational amplifier is built-in to adjust the input sig - nal (refer to figure 2). the pre-filter is a band rejection filter which reduces the dialing tone from 350hz to 400hz. the low group filter filters low group frequency signal output whereas the high group filter filters high group frequency signal output. each filter output is followed by a zero-crossing detector with hysteresis. when each signal amplitude at the out - put exceeds the specified level, it is transferred to full swing logic signal. when input signals are recognized to be effective, dv becomes high, and the correct tone code (dtmf) digit is transferred. steering control circuit the steering control circuit is used for measuring the ef - fective signal duration and for protecting against drop out of valid signals. it employs the analog delay by exter - nal rc time-constant controlled by est. the timing is shown in figure 3. the est pin is normally low and draws the rt/gt pin to keep low through dis- charge of external rc. when a valid tone input is de- tected, est goes high to charge rt/gt through rc. when the voltage of rt/gt changes from 0 to v trt (2.35v for 5v supply), the input signal is effective, and the correct code will be created by the code detector. af- ter d0~d3 are completely latched, dv output becomes high. when the voltage of rt/gt falls down from vdd to v trt (i.e.., when there is no input tone), dv output be - comes low, and d0~d3 keeps data until a next valid tone input is produced. by selecting adequate external rc value, the minimum ac - ceptable input tone duration (t acc ) and the minimum ac - ceptable inter-tone rejection (t ir ) can be set. external components (r, c) are chosen by the formula (refer to fig - ure 5.): t acc =t dp +t gtp ; t ir =t da +t gta ; where t acc : tone duration acceptable time t dp : est output delay time ( l
h ) t gtp : tone present time t ir : inter-digit pause rejection time t da : est output delay time ( h
l ) t gta : tone absent time ' % . - "
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figure 2. input operation for amplifier application circuits
timing diagrams ht9170b/ht9170d rev. 1.10 6 september 24, 2002 2 2 . / - % / . / 0 / ) 1 > ) ) - ) ) ) ) - ) / . - ? ) ) / ) / / 8 / * 8 / . / ) ) ) / * / * figure 3. steering timing / 3 ) ' - % / / 9 figure 4. power up timing
figure 5. steering time adjustment circuits dtmf dialing matrix dtmf data output table low group (hz) high group (hz) digit oe d3 d2 d1 d0 697 1209 1 h l l l h 697 1336 2 h l l h l 697 1477 3 h l l h h 770 1209 4hlhl l 770 1336 5hlhlh 770 1477 6hlhhl 852 1209 7hlhhh 852 1336 8 h h l l l 852 1477 9 h h l l h 941 1336 0 h h l h l 941 1209 * h h l h h 941 1477 # h h h l l 697 1633 a h h h l h 770 1633 b hhhh l 852 1633 chhhhh 941 1633 d h l l l l any l z z z z note: z high impedance; any any digit ht9170b/ht9170d rev. 1.10 7 september 24, 2002 6 4 @
1 5 7 a , ) . 3 . 3 . 3 . 3 6 6 . ) ) . / 0 / - % / ) )
(a) fundamental circuit: t gtp =r c ln (v dd /(v dd v trt )) t gta =r c ln (v dd /v trt ) . ) ) . / 0 / - % / . ) ) )
(b) t gtp (c) t gtp >t gta : t gtp =r1 c ln (v dd /(v dd v trt )) t gta = (r1 // r2) c ln (v dd /v trt )
data output the data outputs (d0~d3) are tristate outputs. when oe input becomes low, the data outputs (d0~d3) are high imped - ance. application circuits application circuit 1 application circuit 2 ht9170b/ht9170d rev. 1.10 8 september 24, 2002
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! " # $ " % & ' " ( ) * + + . 1 2 2 2 0 % 1 1 ! " # $ " % & ' " note: x tal = 3.579545mhz crystal c1=c2 20pf x tal = 3.58mhz ceramic resonator c1=c2 39pf note: x tal = 3.579545mhz crystal c1=c2 20pf x tal = 3.58mhz ceramic resonator c1=c2 39pf
package information 18-pin dip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 895 915 b 240 260 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 335 375 0 15 ht9170b/ht9170d rev. 1.10 9 september 24, 2002
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18-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 447 460 d92 104 e 50 f4 g32 38 h4 12 0 10 ht9170b/ht9170d rev. 1.10 10 september 24, 2002
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product tape and reel specifications reel dimensions sop 18w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 12.75+0.15 d key slit width 2.0+0.6 t1 space between flange 24.4 0.2 t2 reel thickness 28.4 0.4 ht9170b/ht9170d rev. 1.10 11 september 24, 2002 , / / )
carrier tape dimensions sop 18w symbol description dimensions in mm w carrier tape width 24.0+0.3 0.1 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 12.0 0.1 k0 cavity depth 2.8 0.1 t carrier tape thickness 0.3 0.05 c cover tape width 21.3 ht9170b/ht9170d rev. 1.10 12 september 24, 2002 ) 3 1 ) - " h 1 , 1 1
ht9170b/ht9170d rev. 1.10 13 september 24, 2002 copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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