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dac7617 quad, serial input, 12-bit, voltage output digital-to-analog converter features l low power: 3mw l settling time: 10 m s to 0.012% l 12-bit linearity and monotonicity: C40 c to +85 c l double-buffered data inputs l so-16 or ssop-20 packages l single-supply +3v operation applications l process control l ate pin electronics l closed-loop servo-control l motor control l data acquisition systems l dac-per-pin programmers description the dac7617 is a quad, serial input, 12-bit, voltage output digital-to-analog converter (dac) with guar- anteed 12-bit monotonic performance over the C40 c to +85 c temperature range. an asynchronous reset clears all registers to either mid-scale (800 h ) or zero- scale (000 h ), selectable via the resetsel pin. the individual dac inputs are double buffered to allow for simultaneous update of all dac outputs. the device is powered from a single +3v supply. low power and small size makes the dac7617 ideal for automatic test equipment, dac-per-pin program- mers, data acquisition systems, and closed-loop servo- control. the device is available in so-16 and ssop-20 packages and is guaranteed over the C40 c to +85 c temperature range. dac a dac register a input register a dac b dac register b input register b dac c dac register c input register c dac d dac register d input register d v refh v dd agnd v outd v outc v outb v outa v refl ldac gnd clk cs 12 sdi reset resetsel loadreg serial-to- parallel shift register dac select dac7617 dac7617 copyright ? 2001, texas instruments incorporated sbas185 printed in u.s.a. february, 2001 www.ti.com
2 dac7617 sbas185 specifications at t a = C40 c to +85 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, unless otherwise noted. [ specification same as dac7617e, u. notes: (1) specification applies at code 00a h and above. (2) lsb means least significant bit, with v refh equal to +1.25v and v refl equal to 0v, one lsb is 0.305mv. (3) all dac outputs will match within the specified error band. (4) ideal output voltage does not take into account zero or full-scale error. dac7617e, u dac7617eb, ub parameter conditions min typ max min typ max units accuracy linearity error (1) 2 1 lsb (2) linearity matching (3) 2 1 lsb differential linearity error 1 1 lsb monotonicity 12 [ bits zero-scale error code = 00a h 2.4 [ mv zero-scale drift 510 [[ ppm/ c zero-scale matching (3) 1 2 [ 1.2 mv full-scale error code = fff h 2.4 [ mv full-scale matching (3) 1 2 [ 1.2 mv power supply rejection 30 [ ppm/v analog output voltage output (4) v refl v refh [[ v output current C625 +625 [[ m a load capacitance no oscillation 100 [ pf short-circuit current +8, C2 [ ma short-circuit duration indefinite [ reference input v refh input range 0 +1.25 [[ v v refl input range 0 [ v dynamic performance settling time to 0.012% 5 10 [[ m s channel-to-channel crosstalk full-scale step 0.1 [ lsb on any other dac output noise voltage bandwidth: 0hz to 1mhz 65 [ nv/ ? hz digital input/output logic family cmos [ logic levels v ih | i ih | 10 m av dd ? 0.7 v dd [[ v v il | i il | 10 m a C0.3 v dd ? 0.3 [[ v data format straight binary [ power supply requirements v dd 3.0 3.3 3.6 [[[ v i dd 0.8 1 [[ ma power dissipation 2.4 3 [[ mw temperature range specified performance C40 +85 [[ c
3 dac7617 sbas185 electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. absolute maximum ratings (1) v dd to gnd ........................................................................ C0.3v to +5.5v v refl to gnd ........................................................... C0.3v to (v dd + 0.3v) v dd to v refh .......................................................................... C0.3v to v dd v refh to v refl ........................................................................ C0.3v to v dd digital input voltage to gnd ...................................... C0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ......................................... C40 c to +85 c storage temperature range .......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. package/ordering information maximum maximum linearity differential package specification error linearity drawing temperature ordering transport product (lsb) (lsb) package number range number (1) media dac7617u 2 1 so-16 211 C40 c to +85 c dac7617u rails "" " "" " dac7617u/1k tape and reel dac7617ub 1 1 so-16 211 C40 c to +85 c dac7617ub rails "" " "" " dac7617ub/1k tape and reel dac7617e 2 1 ssop-20 334 C40 c to +85 c dac7617e rails "" " "" " dac7617e/1k tape and reel dac7617eb 1 1 ssop-20 334 C40 c to +85 c dac7617eb rails "" " "" " dac7617eb/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 dev ices per reel). ordering 1000 pieces of dac7617eb/1k will get a single 1000-piece tape and reel.
4 dac7617 sbas185 pin configurationu package top view so pin configuratione package top view ssop pin descriptionse package pin label description 1v dd positive analog supply voltage, +3v nominal. 2v outd dac d voltage output 3v outc dac c voltage output 4v refl reference input voltage low. sets minimum out- put voltage for all dacs. 5 nic not internally connected. 6 nic not internally connected. 7v refh reference input voltage high. sets maximum out- put voltage for all dacs. 8v outb dac b voltage output 9v outa dac a voltage output 10 agnd analog ground 11 gnd ground 12 sdi serial data input 13 clk serial data clock 14 cs chip select input 15 nic not internally connected. 16 nic not internally connected. 17 ldac all dac registers becomes transparent when ldac is low. they are in the latched state when ldac is high. 18 loadreg the selected input register becomes transparent when loadreg is low. it is in the latched state when loadreg is high. 19 reset asynchronous reset input. sets all dac registers to either zero-scale (000 h ) or mid-scale (800 h ) when low. resetsel determines which code is active. 20 resetsel when low, a low on reset will cause all dac registers to be set to code 000 h . when resetsel is high, a low on reset will set the registers to code 800 h . pin descriptionsu package pin label description 1v dd positive analog supply voltage, +3v nominal. 2v outd dac d voltage output 3v outc dac c voltage output 4v refl reference input voltage low. sets minimum out- put voltage for all dacs. 5v refh reference input voltage high. sets maximum out- put voltage for all dacs. 6v outb dac b voltage output 7v outa dac a voltage output 8 agnd analog ground 9 gnd ground 10 sdi serial data input 11 clk serial data clock 12 cs chip select input 13 ldac all dac registers become transparent when ldac is low. they are in the latched state when ldac is high. 14 loadreg the selected input register becomes transparent when loadreg is low. it is in the latched state when loadreg is high. 15 reset asynchronous reset input. sets dac and input registers to either zero-scale (000 h ) or mid-scale (800 h ) when low. resetsel determines which code is active. 16 resetsel when low, a low on reset will cause the dac and input registers to be set to code 000 h . when resetsel is high, a low on reset will set the registers to code 800 h . 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v outd v outc v refl v refh v outb v outa agnd resetsel reset loadreg ldac cs clk sdi gnd dac7617u 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd v outd v outc v refl nic nic v refh v outb v outa agnd resetsel reset loadreg ldac nic nic cs clk sdi gnd dac7617e
5 dac7617 sbas185 typical performance curves at t a = +25 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, representative unit, unless otherwise specified. 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +85 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, ?0 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +25 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +85 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, ?0 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h
6 dac7617 sbas185 typical performance curves at t a = +25 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, representative unit, unless otherwise specified. 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +25 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, +85 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac c, ?0 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, +25 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, +85 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h 0.50 0.25 0 ?.25 ?.50 0.50 0.25 0 ?.25 ?.50 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac d, ?0 c) 000 h 200 h 400 h 600 h 800 h digital input code a00 h c00 h e00 h fff h
7 dac7617 sbas185 typical performance curves at t a = +25 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, representative unit, unless otherwise specified. 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 temperature ( c) ?0 ?0 ?0 0 ?0 10 20 40 50 30 70 80 90 60 negative full-scale error vs temperature negative full-scale error (mv) dac a dac d dac c dac b code (0040 h ) code (000 h ) 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 temperature ( c) ?0 ?0 ?0 0 ?0 10 20 40 50 30 70 80 90 60 positive full-scale error vs temperature positive full-scale error (mv) dac a dac d dac c dac b code (0040 h ) code (fff h ) 0.000 0.050 ?.100 ?.150 ?.200 digital input code 000 h 400 h 200 h 600 h a00 h 800 h e00 h fff h c00 h v refl current vs code v ref current (ma) 0.200 0.150 0.100 0.050 0.000 digital input code 000 h 400 h 200 h 600 h a00 h 800 h e00 h fff h c00 h v refh current vs code v ref current (ma) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 digital input code 000 h 400 h 200 h 600 h 800 h c00 h a00 h e00 h fff h supply current vs digital input code i dd (ma) no load 10 8 6 4 2 0 ? ? input code 000 h 400 h 200 h 600 h 800 h c00 h a00 h e00 h fff h supply current limit vs input code i out (ma) short to v dd short to ground
8 dac7617 sbas185 1000 900 800 700 600 500 400 300 200 100 0 temperature ( c) ?0 0 ?0 20 40 60 80 100 power supply current vs temperature quiescent current (ua) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r load (k w ) 0.01 0.1 1 10 100 output voltage vs r load v out (v) source sink time (2 s/div) output voltage vs settling time (0v to +1.25v) large-signal output (0.5v/div) small-signal error (1mv/div) ldac (5.0v/div) time (2 s/div) output voltage vs settling time (+1.25v to 0v) large-signal output (0.5v/div) small-signal error (1mv/div) ldac (5.0v/div) time (1 s/div) mid-scale glitch performance (code 7ff h to 800 h ) ldac (5.0v/div) glitch waveform (20mv/div) time (1 s/div) mid-scale glitch performance (code 800 h to 7ff h ) ldac (5.0v/div) glitch waveform (20mv/div) typical performance curves at t a = +25 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, representative unit, unless otherwise specified.
9 dac7617 sbas185 120 100 80 60 40 20 0 frequency (hz) 100 1k 10k 100k 1m output noise voltage vs frequency noise (nv/ ? hz) code fff h typical performance curves at t a = +25 c, v dd = +3v, v refh = +1.25v, and v refl = 0v, representative unit, unless otherwise specified. time (100 s/div) wideband noise (bandwidth = 10khz) noise voltage (20 v/div)
10 dac7617 sbas185 theory of operation the dac7617 is a quad, serial input, 12-bit, voltage output dac. the architecture is a classic r-2r ladder configuration followed by an operational amplifier that serves as a buffer. each dac has its own r-2r ladder network and output op amp, but all share the reference voltage inputs. the minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by external voltage references (v refl and v refh , respectively). the digital input is a 16-bit serial word that contains the 12-bit dac code and a 2-bit address code that selects one of the four dacs (the two remaining bits are unused). the converter can be powered from a single +3v supply. each device offers a reset function which imme- diately sets all dac output voltages and internal registers to either zero-scale (code 000 h ) or mid-scale (code 800 h ). the reset code is selected by the state of the resetsel pin (low = 000 h , high = 800 h ). see figure 1 for the basic operation of the dac7617. analog outputs the output of the dac7617 can swing to ground. note that the settling time of the output op amp will be longer with voltages very near ground. additionally, care must be taken when measuring the zero-scale error. if the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes (000 h , 001 h , 002 h , etc.) since the output voltage cannot swing below ground. the behavior of the output amplifier can be critical in some applications. under short-circuit conditions (dac output shorted to v dd ), the output amplifier can sink a great deal more current than it can source. see the specifications table for more details concerning short-circuit current. figure 1. basic single-supply operation of the dac7617. note: (1) u package pin configuration shown. (2) as configured, reset low sets all internal registers to code 000 h (0v). if resetsel is high, reset low sets all internal registers to code 800 h (1.25v). 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v outd v outc v refl v refh v outb v outa agnd resetsel reset loadreg ldac cs clk sdi gnd reset dacs (2) update selected register update all dac registers chip select clock serial data in dac7617 (1) 0.1 f 0.1 f 0v to +1.25v 1 f to 10 f +3v + 0v to +1.25v 0v to +1.25v 0v to +1.25v +1.25v
11 dac7617 sbas185 reference inputs the minimum output of each dac is equal to v refl plus a small offset voltage (essentially, the offset of the output op amp). the maximum output is equal to v refh C 1lsbplus a similar offset voltage. the current into the reference inputs depends on the dac output voltages and can vary from a few microamps to approximately 0.4 milliamp. bypassing the reference volt- age or voltages with a 0.1 m f capacitor placed as close as possible to the dac7617 package is strongly recommended. digital interface figure 2 and table i provide the basic timing for the dac7617. the interface consists of a serial clock (clk), serial data (sdi), a load register signal (loadreg), and a load all dac registers signal (ldac). in addition, a chip select (cs) input is available to enable serial communication when there are multiple serial devices. an asynchronous reset input (reset) is provided to simplify start-up condi- tions, periodic resets, or emergency resets to a known state. symbol description min typ max units t ds data valid to clk rising 25 ns t dh data held valid after clk rises 20 ns t ch clk high 30 ns t cl clk low 50 ns t css cs low to clk rising 55 ns t csh clk high to cs rising 15 ns t ld1 loadreg high to clk rising 40 ns t ld2 clk rising to loadreg low 15 ns t ldrw loadreg low time 45 ns t lddw ldac low time 45 ns t rssh resetsel valid to reset low 25 ns t rstw reset low time 70 ns t s settling time 10 m s figure 2. dac7617 timing. the dac code and address are provided via a 16-bit serial interface, as shown in figure 2. the first two bits select the input register that will be updated when loadreg goes low (see table ii). the next two bits are not used. the last 12 bits are the dac code which is provided, most significant bit first. table i. timing specifications (t a = C40 c to +85 c). a1 (msb) (lsb) sdi clk cs loadreg a0 x x d11 d10 d9 d3 d2 d1 d0 sdi clk ldac reset v out t css t ld1 t cl t ch t ds t dh t ld2 t ldrw t lddw t s t rstw t rssh t csh t s 1 lsb error band 1 lsb error band resetsel
12 dac7617 sbas185 if both cs and clk are used, then cs should rise only when clk is high. if not, then either cs or clk can be used to operate the shift register. see table iii for more information. the digital data into the dac7617 is double-buffered. this allows new data to be entered for each dac without disturb- ing the analog outputs. when the new settings have been entered into the device, all of the dac outputs can be updated simultaneously. the transfer from the input regis- ters to the dac registers is accomplished with a high to low transition on the ldac input. it is possible to keep this pin low and update each dac via loadreg be- cause the dac registers become transparent when ldac is low. however, as each new data word is entered into the device, the corresponding output will update immediately when loadreg is taken low. digital input coding the dac7617 input data is in straight binary format. the output voltage is given by the following equation: where n is the digital input code (in decimal). this equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. state of selected selected state of input input all dac a1 a0 loadreg ldac reset register register registers l (1) llh (2) h a transparent latched l h l h h b transparent latched h l l h h c transparent latched h h l h h d transparent latched x (3) x h l h none (all latched) transparent x x h h h none (all latched) latched x x x x l all reset (4) reset (4) notes: (1) l = logic low. (2) h = logic high. (3) x = dont care. (4) resets to either 000h or 800 h , per the resetsel state (low = 000 h , high = 800 h ). when reset rises, all registers that are in their latched state retain the reset value. cs (1) clk (1) loadreg reset serial shift register h (2) x (3) h h no change l (4) l h h no change l - (5) h h advanced one bit - l h h advanced one bit h (6) xl (7) h no change h (6) xhl (8) no change notes: (1) cs and clk are interchangeable. (2) h = logic high. (3) x = dont care. (4) l = logic low (5) = positive logic transition. (6) a high value is suggested in order to avoid a false clock from advancing the shift register and changing the shift register. (7) if data is clocked into the serial register while loadreg is low, the selected input register will change as the shift register bits flow through a1 and a0. this will corrupt the data in each input register that has been erroneously selected. (8) reset low causes no change in the contents of the serial shift register. table ii. control logic truth table. table iii. serial shift register truth table. note that cs and clk are combined with an or gate and the output controls the serial-to-parallel shift register inter- nal to the dac7617 (see the block diagram on the front of this data sheet). these two inputs are completely inter- changeable. in addition, care must be taken with the state of clk when cs rises at the end of a serial transfer. if clk is low when cs rises, the or gate will provide a rising edge to the shift register, shifting the internal data one additional bit. the result will be incorrect data and possible selection of the wrong input register. (v refh C v refl ) ? n 4096 v out = v refl +
13 dac7617 sbas185 layout a precision analog component requires careful layout, ad- equate bypassing, and clean, well-regulated power supplies. as the dac7617 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switch- ing speed, the more difficult it will be to keep digital noise from appearing at the converter output. due to the dac7617s single ground pin, all return currents, including digital and analog return currents, must flow through the gnd pin. ideally, gnd would be connected directly to an analog ground plane. this plane would be separate from the ground connection for the digital compo- nents until they were connected at the power entry point of the system (see figure 3). the power applied to v dd should be well regulated and low noise. switching power supplies and dc/dc converters will often have high-frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high-frequency spikes as their internal logic switches states. this noise can easily couple into the dac output voltage through various paths between the power connec- tions and analog output. as with the gnd connection, v dd should be connected to a +3v power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. in addition, the 1 m f to 10 m f and 0.1 m f capacitors shown in figure 3 are strongly recommended. in some situations, additional bypassing may be required, such as a 100 m f electrolytic capacitor or even a p filter made up of inductors and capacitorsall designed to essentially low- pass filter the +3v supply, removing the high-frequency noise (see figure 3). figure 3. suggested power and ground connections for a dac7617 sharing a +3v supply with a digital system. +3v power supply optional digital circuits dac7617 other analog components +3v 100 f 1 f to 10 f ground +3v ground v dd agnd 0.1 f ++
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, license, warranty or endorsement thereof. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. resale of ti's products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. also see: standard terms and conditions of sale for semiconductor products. www.ti.com/sc/docs/stdterms.htm mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated

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