www.fairchildsemi.com ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 AN-400A low-power green-mode pwm flyback power controller without secondary feedback abstract this highly integrated pwm controller, fan400a, offers several features to enhance the performance of a flyback converter for low-power appli cations. using the controller reduces the costs of battery chargers and ac adapters. the no-load power consumption can be less than 200mw for universal ac input voltage range to meet the power conservation requirements. features ? linearly decreasing pwm frequency ? green mode under light-load and zero-load conditions ? constant voltage (cv) and constant current (cc) ? no secondary feedback ? low startup current: 8 a ? low operating current: 3.6ma ? leading-edge blanking ? constant power limit ? universal ac input range ? synchronized slope compensation ? 140 c otp sensor with hysteresis ? v dd over-voltage clamping ? cycle-by-cycle current limiting ? under voltage lockout (uvlo) ? fixed pwm frequency with hopping ? gate output maximum voltage clamped at 17v ? small sot-26 package figure 1. sot-26 pin configuration figure 2. dip-8 pin configuration gnd fb nc gate vdd sense nc nc fb gnd sense nc vdd gate
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 2 application diagram figure 3. typical application internal block diagram figure 4. functional block diagram v in c in r in d 1 w aux c o d o q1 v o r s sense gate vdd gnd
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 3 start-up circuitry when the power is turned on, the input rectified voltage v dc charges the hold-up capacitor c1 via a startup resistor r in . as the voltage of the vdd pin reaches the start threshold voltage v dd-on , the fan400a activates and drives the entire power supply. figure 5. circuit providing power to fan400a the maximum power-on delay time is determined as: ? ? ? ? ? ? ? ? ? ? ? = ? ? ? c1 r t in st dd dc on - dd in d_on e 1 ) r i (v v (1) where i dd _ st is the startup current of fan400a and t d _ on is the power-on delay time of the power supply. due to the low startup current, a large r in , such as 1.5m , can be used. with a hold-up capacitor of 10 f/50v, the power-on delay t d_on is less than 2.8s for 90v ac input. constant voltage (cv) operation the fan400a can regulate the output voltage without secondary-side feedback signal. as shown in figure 6, an internal v dd feedback comparator (v dd-comp ) is used to modulate the pwm output pulses when the fb pin is floating. the primary v dd voltage is maintained at 22.7v due to internal feedback compensation circuit. the output voltage is proportional to v dd according to the ratio between transformer auxiliary winding and secondary winding. a typical output characteristic using fan400a is shown in figure 7. if more precise output voltage regulation is required, secondary feedback circuitry should be used. figure 6. voltage regulated by v dd feedback i o v o without secondary feedback circuitry with secondary feedback circuitry figure 7. output character istics with and without secondary feedback circuitry a typical secondary feedback circuit mainly consisting of a shunt regulator and an opto-coupler is shown in figure 8. r1 and r2 form a voltage divider for the output voltage regulation. r3 and c1 are adjusted for control-loop compensation. a small-value rc filter (e.g. r fb = 47 , c fb =1nf) placed from fb pin to gnd can increase stability. the maximum sourcing current of the fb pin is 1.4ma. the phototransistor must be capable of sinking this current to pull fb level down at no load. the value of biasing resistor r b is determined as follows: 1.4ma k r v v v b z d o ? ? ? (2) where: v d is the drop voltage of photodiode, about 1.2v; v z is the minimum operating voltage of the shunt regulator (typically 2.5v), and; k is the current transfer rate (ctr) of the opto-coupler. for an output voltage v o =5v, with ctr=100%, the maximum value of r b is around 910 .
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 4 figure 8. feedback circuit using secondary feedback circuitry, the primary v dd voltage should be maintained lower than 20v. otherwise, the internal v dd feedback circuitry may activate with heavy output loading. the transformer auxiliary turn number should be reduced compared with primary feedback application. when the secondary feedback circuitry is open loop, the primary feedback circuitry acts as a back-up protection to prevent the v dd exceeding 22.7v. constant current (cc) operation for a discontinuous-current mode flyback converter in constant current operation, the output power is proportional to the square of the peak primary current, and to the output voltage. when the output voltage reduces to half, the primary current drops to 0.707 times the original. inside the fan400a, the v dd voltage is used to modulate the level of the saw current limiting threshold voltage. as shown in figure 9, the valley voltage of the saw current limiting curve reduces to 0.707 times of the original when the v dd voltage reduces to half. with a good coupling of the transformer, the ratio of the v dd voltage to the output voltage is almost constant. a constant current operation is therefore achieved. figure 9. voltage controlled saw current limiting curves oscillator & green mode operation the proprietary green-mode function provides off-time modulation to reduce the pwm frequency at light-load and in no-load conditions. the feedback voltage of the fb pin is taken as a reference. when the feedback voltage is lower than about 2.6v, the pwm frequency decreases. because most losses in a switching-mode power supply are proportional to the pwm frequency, the o ff-time modulation reduces the power consumption of the power supply at light-load and no-load conditions. the pwm frequency is 65khz at nominal load and decreases to 17khz at light load. the power supply enters ?adaptive off- time modulation? in zero-load conditions. figure 10. pwm frequency vs. fb voltage built-in slope compensation a flyback converter can be operated in either discontinuous current mode (dcm) or continuous current mode (ccm). there are many advantages to operating in ccm. with the same output power, a converter in ccm exhibits smaller peak inductor current than in dcm. therefore, a small- sized transformer and a low-rating mosfet can be applied. on the secondary side of the transformer, the rms output current of dcm can be up to twice that of ccm. larger wire gauge and output capacitors with larger ripple current rating are required. dcm operation also results in a higher output voltage spike. a large lc filter has to be added. therefore, a flyback converter in ccm achieves better performance with lower component cost. despite the above advantages of ccm operation, there is one concern ? stability. in ccm operation, the output power is proportional to the average inductor current, while the peak current is controlled. this causes the well-known sub- harmonic oscillation when the pwm duty cycle exceeds 50%. adding slope compensation (reducing the current- loop gain) is an effective way to prevent oscillation. fan400a introduces a synchronized positive-going ramp (v slope ) in every switching cycle to stabilize the current loop. the sensed voltage, plus this slope compensation signal (v slope ), is fed into the non-inverting input of the pwm comparator. the resulting voltage is compared with the fb signal to adjust the pwm duty cycle such that the output voltage is regulated. therefore, fan400a allows design of cost effective, highly efficient, and compact-sized fb v o r b r1 c1 r2 r3 r fb c fb v x v vdd 2 vdd x 0.707
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 5 flyback power supplies operating in ccm without adding external components. the positive ramp added is: d v v sl slope ? = (3) where v sl = 0.33v and d = duty cycle. figure 11. synchronized slope compensation over-temperature protection (otp) a built-in temperature sensing circuit shuts down pwm output once the junction temperature exceeds 140c. while pwm output is shuts down, the v dd voltage gradually drops to the uvlo voltage (around 8v). then v dd is charged up to the startup threshold voltage of 17v through the start up resistor until pwm output is restarted. this ?hiccup? mode protection occurs repeatedly as long as the temperature remains above 110c. the temperature hysteresis window for the otp circuit is 30c. constant output power limit the maximum output power of a flyback converter can be generally designed by the current-sense resistor r s . when the load increases, the peak inductor current increases accordingly. when the output current arrives at the protection value, the ocp comparator dominates the current control loop. ocp occurs when the current-sense voltage reaches the threshold value. the output gate driver is turned off after a small propagation delay, t d . the delay time results in unequal power-limit level under universal input. in fan400a, a sawtooth power-limiter is designed to solve the unequal power-limit problem. as shown in figure 12, the power limiter is designed as a positive ramp signal fed to the non-inverting input of ocp comparator. this results in a lower current limit at high-line input than at low- line. however, with fixed propagation delay t d , the peak primary current would be the same for various line input voltage. therefore, the maximum output power can almost be limited to a constant value within a wide input voltage range without adding external circuits. figure 12. constant power limit compensation leading-edge blanking (leb) a voltage signal proportional to the mosfet current develops on the current-sense resistor r s . each time the mosfet turns on, a spike induced by the diode reverse recovery and by the output capacitances of the mosfet and diode, appears on the sensed signal. a leading-edge blanking time about 310ns is introduced to avoid premature termination of mosfet by the spike. therefore, only a small-value rc filter (e.g. 100 + 47pf) is required between the sense pin and r s . a non-inductive resistor for the r s is recommended. figure 13. turn-on spike gate drive fan400a?s output stage is a fast totem-pole driver that can directly drive mosfet gate. it is equipped with a voltage clamping zener diode to protect mosfet from damage caused by undesirable over-drive voltage. the output voltage is clamped at 17v. an internal pull-down resistor is used to avoid floating state of gate before startup. a gate drive resistor in the range of 47 to 100 is recommended to limit the peak gate drive current and provide damping to prevent oscillations at the mosfet gate terminal. t d t on1 t on2 actual power limit point high line sense voltage low line sense voltage 0
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 6 figure 14. gate drive lab note before rework or solder/desolder on the power supply, discharge primary capacitors by external bleeding resistor. otherwise, the pwm ic may be destroyed by external high voltage during solder/desolder. this device is sensitive to esd discharge. to improve production yield, the production line should be esd protected according to ansi esd s1.1, esd s1.4, esd s7.1, esd stm 12.1, and eos/esd s6.1.
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 7 printed circuit board layout high-frequency switching current / voltage make printed circuit board layout a very important design issue. good pcb layout minimizes excessive emi helps the power supply survive during surge/esd tests. guidelines: to get better emi performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor c1 fi rst, then to the switching circuits. ? the high frequency current loop is in c1 ? transformer ? mosfet ? r s ? c1. the area enclosed by this current loop should be as small as possible. keep the tr aces (especially 4 1 ) short, direct, and wide. high-voltage traces related the drain of mosfet and rcd snubber should be kept far way from control circuits to prevent unnecessary interference. if heatsink is used for mosfet, connect this heatsink to ground. ? as indicated by 3 , the ground of control circuits should be connected first, then to other circuitry. ? as indicated by 2 , the area enclosed by transformer auxiliary winding, d1, and c2 should also be kept small. pl ace c2 close to fan400a for good decoupling. two suggestions with different pro and cons for ground connections are recommended. ? gnd 3 2 4 1 : this could avoid common impedance interference for the sense signal. ? gnd3 2 1 4: this could be better for esd tests where the earth ground is not available on the power supply. regarding the esd discharge path, the charges go from secondary, through the transformer stray capacitance, to gnd 2 first. then the charges go from gnd 2 to gnd 1 and back to mains. it should be noted that control circuits should not be placed on the discharge path. point discharge for common choke can decrease high-frequency impedance and increase esd immunity. ? should a y-cap between primary and secondary be required, connect this y-cap to the positive terminal of c1 (v dc ). if this y-cap is connected to primary gnd, it should be connected to the negative terminal of c1 (gnd 1 ) directly. point discharge of this y-cap also helps for esd. however, the creepage between these two pointed ends should be at least 5mm according to safety requirements . figure 15. layout considerations sense gate v dc vdd fb gnd fan400a c1 c2 r in c fb r fb r g r f r s cf d1 3 2 1 4 y - cap 5 common mode choke
AN-400A application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 5/29/08 8 disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeli ng, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness
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