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m pd77018a, 77019 are 16 bits fixed-point dsps (digital signal processors) developed for digital signal processing with its demand for high speed and precision. maximum operating speed of the m pd77018a, 77019 is improved compared with the m pd77015, 77017, 77018. and the m pd77019 internal instruction ram (4k 32 bits) is suitable for program code replacement. features ? functions ? instruction cycle: 16.6 ns (min.) operation clock: 60 mhz external clock: 60, 30, 20, 15, 7.5 mhz crystal: 60 mhz ? on-chip pll to provide higher operation clock than the external clock ? dual load/store ? hardware loop function ? conditional execution ? executes product-sum operation in one instruction cycle ? programming ? 16 bits 16 bits + 40 bits ? 40 bits multiply accumulator ? 8 general registers (40 bits each) ? 8 rom/ram data pointer: each data memory area has 4 registers ? 10 source interrupts (external: 4, internal: 6) ? 3 operand instructions (example: r0 = r0 +r1l * r2l) ? nonpipeline on execution stage ? memory areas ? instruction memory area : 64k words 32 bits ? data memory areas : 64k words 16 bits 2 (x memory, y memory) in this document, all descriptions of the m pd77018a also apply to the m pd77019, unless otherwise specified. mos integrated circuit 16 bits, fixed-point digital signal processor m pd77018a, 77019 the mark shows major revised points. document no. u11849ej2v0ds00 (2nd edition) date published october 1997 n printed in japan the information in this document is subject to change without notice. 1996 data sheet
m pd77018a, 77019 2 ? clock generator ? mask option for clkout pin: fixed to the low level. does not output the internal system clock. ? selectable source clock: external clock input and crystal resonator [external clock] on-chip pll to provide higher operation clock (60 mhz max.) than the external clock. variable multiple rates (1, 2, 3, 4, 8) by mask option. [crystal resonator] oscillation frequency corresponds directly to the system clock frequency (sure to specify the mask option frequency multiple as "1"). ? on-chip peripheral ? i/o port: 4 bits ? serial i/o (16 bits): 2 channels ? host i/o (8 bits): 1 channel ? cmos ? +3 v single power supply ordering information part number package m pd77018agc- -9eu 100-pin plastic tqfp (fine pitch) (14 14 mm) m pd77019gc- -9eu 100-pin plastic tqfp (fine pitch) (14 14 mm) remark indicates a code suffix.
3 m pd77018a, 77019 block diagram serial i/o #1 serial i/o #2 ports host i/o x memory data pointers x memory y memory data pointers y memory interrupt control loop control stack pc stack instruction memory cpu control mpy 16 16+40 ? 40 alu (40) r0er7 xebus yebus external memory int1 e int4 reset clkout x1 main bus x2 wait controller ie i/o wait
m pd77018a, 77019 4 functional pin groups so1 sorq1 soen1 sck1 si1 sien1 siak1 so2 soen2 sck2 si2 sien2 p0 - p3 hcs ha0, ha1 hrd hre hwr hwe hd0 - hd7 (8) (2) (4) serial interface #1 serial interface #2 host interface ports reset int1 int2 int3 int4 x/y da0 - da13 d0 - d15 wait mrd mwr external data memory data bus control interrupts (14) (16) +3 v v dd gnd x1 x2 clkout holdrq bstb holdak tdo, tice tck, tdi, tms debugging interface (2) (3)
5 m pd77018a, 77019 item m pd77016 m pd77015 m pd77017 m pd77018 m pd77018a m pd77019 internal instruction ram 1.5k words 256 words 4k words internal instruction rom none 4k words 12k words 24k words external instruction memory 48k words none data ram (x/y memory) 2k words each 1k words each 2k words each 3k words each data rom (x/y memory) none 2k words each 4k words each 12k words each external data memory 48k words each 16k words each instruction cycle (maximum operation speed) external clock (at maximum operation speed) crystal (at maximum operation speed) instruction C stop instruction is added. serial interface (2 channels) power supply 5v 3 v package 160-pin plastic qfp 100-pin plastic tqfp functional differences among the m pd7701 family channel 1 has the same functions as channel 2. channel 1 has the same functions as that of the m pd77016. channel 2 has no sorq2 or siak2 pin (channel 2 is used for codec connection). 33/16.5/8.25/4.125 mhz variable multiple rate (1, 2, 4, 8 ) by mask option. 66 mhz 60/30/20/15/7.5 mhz variable multiple rate (1, 2, 3, 4, 8 ) by mask option. 60 mhz 30 ns (33 mhz) 16.6 ns (60 mhz) C 33 mhz
m pd77018a, 77019 6 pin configuration 100-pin plastic tqfp (fine pitch) (14 14 mm ) (top view) 100 wait 99 bstb 98 mrd 97 v dd 96 gnd 95 94 93 mwr holdak holdrq 92 tms 91 tdi 90 tck 89 tice 88 tdo 87 clkout 86 v dd 85 84 83 x1 x2 gnd 82 ha1 81 ha0 80 hwr 79 hrd 78 hcs 77 hd0 76 hd1 hd2 75 hd3 74 hd4 73 hd5 72 hd6 71 hd7 70 v dd 69 gnd 68 hwe 67 hre 66 p0 65 p1 64 p2 63 p3 62 si2 61 sien2 60 sck2 59 so2 58 soen2 57 v dd 56 gnd 55 soen1 54 sorq1 53 so1 52 siak1 51 reset int4 int3 int2 int1 i.c. x/y da13 da12 gnd v dd da11 da10 da9 da8 da7 da6 da5 da4 gnd v dd da3 da2 da1 da0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d15 d14 d13 d12 gnd v dd d11 d10 d9 d8 gnd v dd d7 d6 d5 d4 gnd v dd d3 d2 d1 d0 si1 sien1 sck1
7 m pd77018a, 77019 bstb: bus strobe clkout: clock output d0-d15: 16 bits data bus da0-da13: external data memory address bus gnd: ground ha0,ha1: host data access hcs: host chip select hd0-hd7: host data bus holdak: hold acknowledge holdrq: hold request hrd: host read hre: host read enable hwe: host write enable hwr: host write i.c.: internally connection int1-int4: interrupt mrd: memory read output mwr: memory write output p0-p3: port reset: reset sck1,sck2: serial clock input si1,si2: serial data input siak1: serial input acknowledge sien1,sien2: serial input enable so1,so2: serial data output soen1,soen2: serial output enable sorq1: serial output request tck: test clock input tdi: test data input tdo: test data output tice: test in-circuit emulator tms: test mode select v dd : power supply wait: wait input x1: clock input/crystal connection x2: crystal connection x/y: x/y memory select pin identification
m pd77018a, 77019 8 pin name pin no. symbol 1 reset 2 int4 3 int3 4 int2 5 int1 6 i.c. note 7 x/y 8 da13 9 da12 10 gnd 11 v dd 12 da11 13 da10 14 da9 15 da8 16 da7 17 da6 18 da5 19 da4 20 gnd 21 v dd 22 da3 23 da2 24 da1 25 da0 pin no. symbol 26 d15 27 d14 28 d13 29 d12 30 gnd 31 v dd 32 d11 33 d10 34 d9 35 d8 36 gnd 37 v dd 38 d7 39 d6 40 d5 41 d4 42 gnd 43 v dd 44 d3 45 d2 46 d1 47 d0 48 si1 49 sien1 50 sck1 pin no. symbol 51 siak1 52 so1 53 sorq1 54 soen1 55 gnd 56 v dd 57 soen2 58 so2 59 sck2 60 sien2 61 si2 62 p3 63 p2 64 p1 65 p0 66 hre 67 hwe 68 gnd 69 v dd 70 hd7 71 hd6 72 hd5 73 hd4 74 hd3 75 hd2 pin no. symbol 76 hd1 77 hd0 78 hcs 79 hrd 80 hwr 81 ha0 82 ha1 83 gnd 84 x2 85 x1 86 v dd 87 clkout 88 tdo 89 tice 90 tck 91 tdi 92 tms 93 holdrq 94 holdak 95 mwr 96 gnd 97 v dd 98 mrd 99 bstb 100 wait note i.c. (internally connected): leave this pin open.
9 m pd77018a, 77019 contents 1. pin functions ................................................................................................................ ............... 10 1.1 pin functions ............................................................................................................... ............................ 10 1.2 recommended connection for unused pins ...................................................................................... .15 2. functions .................................................................................................................... .................. 16 2.1 pipeline processing ......................................................................................................... ....................... 16 2.1.1 outline ................................................................................................................... ........................ 16 2.1.2 instructions with delay ................................................................................................... ............... 16 2.2 program control unit ........................................................................................................ ...................... 17 2.3 operation unit .............................................................................................................. ........................... 17 2.3.1 general register (r0 to r7) ............................................................................................... ............ 17 2.3.2 mac: multiply accumulator ................................................................................................ ......... 18 2.3.3 alu: arithmetic logic unit ............................................................................................... ............ 18 2.3.4 bsft: barrel shifter ..................................................................................................... .............. 18 2.3.5 sac: shifter and count circuit ........................................................................................... ......... 18 2.3.6 cjc: condition judge circuit ............................................................................................. .......... 19 2.4 memory ...................................................................................................................... ............................... 19 2.4.1 instruction ram outline ................................................................................................... ............. 20 2.4.2 data memory outline ....................................................................................................... ............. 21 2.4.3 data memory addressing .................................................................................................... .......... 22 2.5 on-chip peripheral circuit .................................................................................................. .................... 22 2.5.1 serial interface outline .................................................................................................. ................ 22 2.5.2 host interface outline .................................................................................................... ............... 22 2.5.3 general input/output ports outline ........................................................................................ ........ 22 2.5.4 wait cycle register ....................................................................................................... ................ 22 3. instructions ................................................................................................................. ............... 23 3.1 outline ..................................................................................................................... ................................. 23 3.2 instruction set and operation ............................................................................................... ................. 24 4. electrical specifications .................................................................................................... .32 5. package drawing .............................................................................................................. ........ 53 6. recommended soldering conditions ................................................................................ 54
m pd77018a, 77019 10 1. pin functions 1.1 pin functions ? power supply v dd C +3v power supply gnd C ground ? system control symbol pin no. i/o function x1 85 i clock input / crystal connection pin ? the clock signal is connected to x1, when using external clock for system clock. x2 84 _ crystal connection pin ? x2 should be left open when using external clock for system clock. clkout 87 o internal system clock output reset 1 i internal system reset signal input symbol pin no. i/o function 11, 21, 31, 37, 43, 56, 69, 86, 97 10, 20, 30, 36, 42, 55, 68, 83, 96 ? interrupt symbol pin no. i/o function int4 - int1 2 - 5 i maskable external interrupt input ? falling edge detection
11 m pd77018a, 77019 remark the state of the pins added 3s becomes high impedance when bus release signal (holdak = 0) is output. ? external data memory interface symbol pin no. i/o function x/y 7 o memory select signal output (3s) ? 0: x memory is used. ? 1: y memory is used. da13 - da0 8, 9, 12 -19, 22 - 25 o address bus to external data memory (3s) ? external data memory is accessed. ? during the external memory is not accessed, these pins keep the previous level. these pins are set to low level; 0000h, by reset. they continue outputting low level until the first external memory access. d15 - d0 26 -29, 32 - 35, 38 - 41, i/o 16 bits data bus to external data memory 44 - 47 (3s) ? external data memory is accessed. mrd 98 o read output (3s) ? reads external memory mwr 95 o write output (3s) ? writes external memory wait 100 i wait signal input ? wait cycle is input when external memory is read. 1: no wait 0: wait holdrq 93 i hold request signal input ? input low level when external data memory bus is expected to use. bstb 99 o bus strobe signal output ? outputs low level while the m pd77018a is occupying external memory bus. holdak 94 o hold acknowledge signal output ? outputs low level when the m pd77018a permits external device to use external data memory bus.
m pd77018a, 77019 12 ? serial interface symbol pin no. i/o function sck1 50 i clock input for serial 1 sorq1 53 o serial output 1 request soen1 54 i serial output 1 enable so1 52 o (3s) serial data output 1 sien1 49 i serial input 1 enable si1 48 i serial data input 1 sck2 59 i clock input for serial 2 soen2 57 i serial output 2 enable so2 58 o (3s) serial data output 2 sien2 60 i serial input 2 enable si2 61 i serial data input 2 siak1 51 o serial input 1 acknowledge remark the state of the pins added 3s becomes high impedance, when data output have been finished or reset is input.
13 m pd77018a, 77019 symbol pin no. i/o function ha1 82 i specifies register which hd7 to hd0 access 1: accesses hst: host interface status register when ha1 = 0 0: accesses hdt(in): host transmit data register when hwr = 0 0: accesses hdt(out): host receive data register when hrd = 0 ha0 81 i specifies bits of registers which hd7 to hd0 access ? 1: accesses bits 15-8 of hst, hdt(in) or hdt(out) ? 0: accesses bits 7-0 of hst, hdt(in) or hdt(out) hcs 78 i chip select input hrd 79 i host read input hwr 80 i host write input hre 66 o host read enable output hwe 67 o host write enable output hd7 - hd0 70 - 77 i/o (3s) 8 bits host data bus ? host interface remark the state of the pins added 3s becomes high impedance when the host does not access host interface. ? i/o port symbol pin no. i/o function p3 - p0 62 - 65 i/o i/o port
m pd77018a, 77019 14 symbol pin no. i/o function i.c. 6 _ internal connected pin. leave this pin open. caution when any signal is applied to or read out from this pin, normal operation of the m pd77018a is not assured. symbol pin no. i/o function tdo 88 o for debugging tice 89 o for debugging tck 90 i for debugging tdi 91 i for debugging tms 92 i for debugging ? debugging interface ? other
15 m pd77018a, 77019 recommended connection connect to v dd open connect to v dd or gnd, via a resistor open connect to v dd open connect to v dd or gnd connect to gnd open connect to v dd or gnd connect to v dd open connect to v dd or gnd, via a resistor connect to gnd, via a resistor open open(pull-up internally) open pin i/o int1 - int4 i x/y o da0 - da13 o d0 - d15 note1 i/o mrd o mwr o wait i holdrq i bstb o holdak o sck1, sck2 i si1, si2 i soen1, soen2 i sien1, sien2 i sorq1 o so1, so2 o siak1 o ha0, ha1 i hcs i hrd i hwr i hre o hwe o hd0 - hd7 note2 i/o p0 - p3 i/o tck i tdo, tice o tms, tdi i clkout o 1.2 recommended connection for unused pins notes 1. can leave open, if no access to external data memory is executed in the whole of program. 2. can leave open, if hcs, hrd, hwr are fixed to high level. remark i: input pin o: output pin i/o: input/output pin
m pd77018a, 77019 16 2. functions 2.1 pipeline processing this section describes the m pd77018a pipeline processing. 2.1.1 outline the m pd77018a basic operations are executed in following 3-stage pipeline. (1) instruction fetch; if (2) instruction decoding; id (3) execution; ex when the m pd77018a operates a result of a instruction just executed before, the data is input to alu in parallel with written back to general registers. pipeline processing actualizes programming without delay time to execute instructions and write back data. three successive instructions and their processing timing are shown below. pipeline processing timing 2.1.2 instructions with delay the following instructions have delay time in execution. (1) instructions to control interrupt 2 instruction cycles have been taken between instruction fetch and execution. (2) inter-register transfer instructions and immediate data set instructions when data is set in data pointer, it needs 2 instruction cycles before the data is valid. if1 id1 ex1 if2 id2 ex2 if3 id3 ex3 1 instruction c y cle
17 m pd77018a, 77019 2.2 program control unit program control unit controls not only count up of program counter in normal operation, but loop, repeat, branch, halt and interrupt. in addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multi- loop and multi-interrupt/subroutine call. the m pd77018a has external 4 interruptions and internal 6 interruptions from peripheral, and specifies interrupt enable or disable independently. the halt and stop instructions cause the m pd77018a to place in low power standby mode. when the halt instruction is executed, power consumption decreases. halt mode is released by interrupt input or hardware reset input. it takes several system clock to recover. when the stop instruction is executed, power consumption decreases. stop mode is released by hardware reset input. it takes a few ms to recover. 2.3 operation unit operation unit consists of the following five parts. C 40 bits general register 8 for data load/store and input/output of operation data C 16 bits 16 bits + 40 bits ? 40 bits multiply accumulator C 40 bits data alu C 40 bits barrel shifter C sac: shifter and count circuit. standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result of 16 bits 16 bits multiplication correctly. 2.3.1 general register (r0 to r7) the m pd77018a has eight 40 bits registers for operation input/output and load/store with memory. general register consists of the following three parts. C r0l to r7l (bit 15 to bit 0) C r0h to r7h (bit 31 to bit 16) C r0e to r7e (bit 39 to bit 32) but each of rnl, rnh and rne are treated as a register in the following conditions. (1) general register used as 40 bits register general registers are treated as 40 bits register, when they are used for the following aims. (a) operand for triminal operation (except for multiplier input) (b) operand for dyadic operation (except for multiplier and shift value) (c) operand for monadic operation (except for exponent instructions) (d) operand for operation (e) operand for conditional judge (f) destination for load instruction (with sign extension and 0 clear) head room 0 0 1 31 32 39 ssssssss result of multiplication among two's complement data
m pd77018a, 77019 18 (2) general register used as 32 bits register bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent instruction. (3) general register used as 24 bits register bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended sign for a load/store instruction. (4) general register used as 16 bits register bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims. (a) signed operand for multiplier (b) source/destination for load/store instruction bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims. (c) unsigned operand for multiplier (d) shift value for shift instruction (e) source/destination for load/store instruction (f) source/destination for inter-register transfer instruction (g) destination for immediate data set instruction (f) hardware loop times (5) general register used as 8 bits register bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/ store instruction. 2.3.2 mac: multiply accumulator mac multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. mac outputs 40 bits data. mac operates three types of multiplication: signed data signed data, signed data unsigned data and unsigned data unsigned data. result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right. 2.3.3 alu: arithmetic logic unit alu performs arithmetic operation and logic operation. both input/output data are 40 bits. 2.3.4 bsft: barrel shifter bsft performs shift right/left operation. both input/output data are 40 bits. there are two types of shift right operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in msb first. 2.3.5 sac: shifter and count circuit sac calculates and outputs shift value for normalization. sac is input 32 bits data and outputs the 40 bits data. then, bit 39 to bit 5 of output data is always 0.
19 m pd77018a, 77019 2.3.6 cjc: condition judge circuit cjc judges whether condition is true or false with 40 bits input data. a conditional instruction is executed when the result is true, and not executed when the result is false. 2.4 memory the m pd77018a has one instruction memory area (64k words 32 bits) and two data memory areas (64k words 16 bits each). it adopts harvard-type architecture, with instruction memory area and data memory areas separated. the m pd77018a has 2 sets of data addressing units, which are dedicated for addressing data memory area. each addressing unit consists of four data pointers, four index registers, a modulo register and addressing alu. x memory area addresses are specified by dp0 to dp3, and y memory area addresses are specified by dp4 to dp7. after memory access, dpn (with the same subscript), can be modified by dnn value. modulo operation is performed with dmx for dp0 to dp3, with dmy for dp4 to dp7.
m pd77018a, 77019 20 2.4.1 instruction ram outline the m pd77018a has an instruction rom (24k words 32 bits) and instruction ram (256 words 32 bits). the m pd77019 has an instruction rom (24k words 32 bits) and instruction ram (4k words 32 bits). a system vector area is assigned to 64 words of the instruction ram. internal instruction ram is initialized and rewritten by boot program. boot up rom contains the program loading instruction code to internal instruction ram. caution when any data is accessed or stored to system address, normal operation of the device is not assured. 0300h 02ffh 0240h 023fh 0000h internal instruction rom (24k words) pd77019 system (24k words) pd77018a 4000h 3fffh system (24k words) a000h 9fffh 0200h 01ffh system (256 words) bootup rom (256 words) vector (64 words) system (11.5k words) internal instruction ram (4k words) system (256 words) bootup rom (256 words) vector (64 words) system (15.25k words) internal instruction ram (256 words) internal instruction rom (24k words) 0100h 00ffh mm 1200h 11ffh ffffh
21 m pd77018a, 77019 2.4.2 data memory outline the m pd77018a and the m pd77019 each has two data memory areas (64k words 16 bits each) in x and y memory areas. every memory areas consists of 3k words 16 bits data ram and 12k words 16 bits data rom . as the m pd77018a and the m pd77019 each has interface with the external data memory, 16 k words 16 bits external data memory space can be added to x/y memories. each data memory area includes on-chip peripheral area which consists of 64 words. when the external data memory area is accessed, instruction cycle can be 2 or more by wait function. caution when any data is accessed or stored to system address, normal operation of the device is not assured. 3840h 383fh 0000h system (1984 words) system (11k words) data ram (3k words) external data memory (16k words) pd77018a, 77019 peripheral (64 words) 4000h 3fffh ffffh system (20k words) 0c00h 0bffh 7000h 6fffh c000h bfffh data rom (12k words) 3800h 37ffh m
m pd77018a, 77019 22 2.4.3 data memory addressing there are following two types of data memory addressing. ? direct addressing the address is specified in the instruction field. ? indirect addressing the address is specified by the data pointer (dp). dp can get a bit reverse before addressing. it can update the dp value after accessing data memory. 2.5 on-chip peripheral circuit the m pd77018a includes serial interface, host interface, general input/output ports and wait cycle registers. they are mapped in both x and y memory areas, and are accessed as memory mapped i/o by the m pd77018a cpu. 2.5.1 serial interface outline the m pd77018a has 2 channel serial interfaces. serial i/o clock must be provided from external. frame length can be programmed independently to be 8 bits or 16 bits. msb first or lsb first can also be selected. data is input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal. 2.5.2 host interface outline the m pd77018a has 8 bits parallel ports as host interface to input/output data to and from host cpu and dma controller. when an external device accesses host interface, ha0 and ha1 pins; which are host address input pins; specifies bit 15 to bit 8 and bit 7 to bit 0. the m pd77018a includes 3 registers consisting of 16 bits, which are dedicated for input data, output data and status. the m pd77018a has three types of interface method for internal and external data; interrupts, polling and wait function. 2.5.3 general input/output ports outline general input/output ports consist of 4 bits. user can set each port as input or output. the m pd77018a includes two registers. one is 4 bits register for input/output data, and the other is 16 bits for control. 2.5.4 wait cycle register the wait cycle registers consist of 16 bits. it is used to set wait cycle number when external memory is accessed. when external data memory area (c000h - ffffh) is accessed, 0, 1, 3, or 7 wait cycle can be set. when external data memory area is accessed, wait cycle can be also set by wait pin.
23 m pd77018a, 77019 3. instructions 3.1 outline all m pd77018a instructions are one-word instructions, consisting of 32 bits. and they are executed in 16.6 ns (min.) per instruction. there are following 9 instruction types. (1) trinomial instructions : specify the acc operation. 3 of general registers are specified optionally as the operation object. (2) dyadic operation instructions : specify the acc, alu or shifter operation. 2 of general registers are specified optionally as the operation object. some instructions can specify a general register and immediate data. (3) monadic operation instructions : specify operations by alu. 1 general register is specified optionally as the operation object. (4) load/store instructions : transfer 16 bits data from memory to general registers, from general registers to memory and between general registers. (5) inter-register transfer instructions : transfer data between general register and other registers. (6) immediate data set instructions : set immediate data at general registers or each registers of address operation unit. (7) branch instructions : specify the direction of the program flow. (8) hardware loop instructions : specify times of instruction repeating. (9) control instructions : specify the control program.
m pd77018a, 77019 24 expression selectable registers ro, ro', ro" r0 - r7 rl, rl' r0l - r7l rh, rh' r0h - r7h re r0e - r7e reh r0eh - r7eh dp dp0 - dp7 dn dn0 - dn7 dm dmx, dmy dpx dp0 - dp3 dpy dp4 - dp7 dpx_mod dpn, dpn++, dpnC C, dpn##, dpn%%, !dpn## (n = 0 - 3) dpy_mod dpn, dpn++, dpnC C, dpn##, dpn%%, !dpn## (n = 4 - 7) dp_imm dpn##imm (n = 0 - 7) * content of memory address example when the content of dp0 register is 1000, * dp0 shows the content of memory address 1000. 3.2 instruction set and operation an operation is written according to the rules for expressing. an expression of instructions having two or more descriptions can have only one selected. (a) expressions and selectable registers expression and selectable registers are shown as follows.
25 m pd77018a, 77019 (b) modifying data pointers data pointers are modified after memory access. the results are valid immediately after instruction execution. it is impossible to modify without memory access. description operation dpn no operation: dpn value does not change. dpn++ dpn ? dpn+1 dpnC C dpn ? dpnC1 dpn## dpn ? dpn + dnn: adds dn0-dn7 corresponding to dp0-dp7 example dp0 ? dp0 + dn0 dpn%% (n = 0 - 3) dpn = ((dp l + dnn )mod (dmx + 1)) + dp h (n = 4 - 7) dpn = ((dp l + dnn )mod (dmy + 1)) + dp h !dpn## access memory after dpn value is bit-reversed after memory access, dpn ? dpn + dnn dpn##imm dpn ? dpn + imm (c) concurrent processing instructions shows concurrent processing instruction. instruction names are shown in abbreviation. tri : trinomial dyad : dyadic monad : monadic trans : inter-register transfer imm : immediate data set br : branch loop : hardware loop ctr : control (d) state of overflow flag (ov) the following marks show the m pd77018a overflow flag state. : not affected : 1 is set when the result of operation is overflow. caution if overflow does not occur after operation, ov is not reset, and keeps the state before operation. ?
m pd77018a, 77019 26 concurrent writing processing flag tri. dyad. monad. load/ trans. imm. br. loop. ctl. ov store trinomial dyadic multiply add ro = ro + rh * rh' ro ? ro+rh * rh' multiply sub ro = roCrh * rh' ro ? roCrh * rh' sign unsign ro = ro + rh * rl ro ? ro+rh * rl multiply add (rl should be a plus integral number.) unsign unsign ro=ro+rl * rl' ro ? ro+rl * rl' multiply add (rl and rl' should be a plus integral number.) 1 bit shift multiply add ro=(ro>>1)+rh * rh' ro ? +rh * rh' 16 bits shift multiply add ro = (ro>>16)+rh * rh' ro ? +rh * rh' multiply ro=rh * rh' ro ? rh * rh' add ro"=ro+ro' ro" ? ro+ro' immediate add ro'=ro+imm ro' ? ro+imm (imm 1 1) sub ro"=roCro' ro" ? roCro' immediate sub ro'=roCimm ro' ? roCimm (imm 1 1) arithmetic right shift ro'=ro sra rl ro' ? ro >> rl immediate arithmetic ro'=ro sra imm ro' ? ro >> imm right shift logic right shift ro'=ro srl rl ro' ? ro >> rl immediate logic right shift ro'=ro srl imm ro' ? ro >> imm logic left shift ro'=ro sll rl ro' ? ro << rl immediate logic left shift ro'=ro sll imm ro' ? ro << imm ro 2 ro 2 16 ?? ? ? ? ???? name mnemonic operation m pd77018a instruction set
27 m pd77018a, 77019 dyadic monadic concurrent writing processing flag tri. dyad. monad. load/ trans. imm. br. loop. ctl. ov store name mnemonic operation and ro" = ro & ro' ro" ? ro & ro' immediate and ro' = ro & imm ro' ? ro & imm or ro" = ro | ro' ro" ? ro | ro' immediate or ro' = ro | imm ro' ? ro | imm exclusive or ro" = ro ^ ro' ro" ? ro ^ ro' immediate exclusive or ro = ro ^ imm ro ? ro ^ imm less than ro" = lt(ro, ro') if(ro007fffffffh) {ro' ? 007fffffffh] else if, (ro007fff0000h) {ro' ? 007fff0000h} else if, (ro>ff80000000h) {ro' ? ff80000000h} else {ro' ? (ro + 8000h) & ffffff0000h} exponent ro' = exp (ro) ro' ? log 2 substitution ro' = ro ro' ? ro 1 ro ( ) ?? ? ?? ?
m pd77018a, 77019 28 monadic cumulation ro'+ = ro ro' ? ro'+ro degression ro'C = ro ro' ? ro'Cro division ro'/ = ro if (sign(ro')==sign(ro)) {ro' ? (ro'Cro)<<1} else {ro' ? (ro'+ro)< if (sign(ro')==0 {ro' ? ro'+1} parallel load/store ro= * dpx_mod ro'= * dpy_mod ro ? * dpx, ro' ? * dpy note 1, note 2 ro= * dpx_mod * dpy_mod=rh ro ? * dpx, * dpy ? rh * dpx_mod=rh ro= * dpy_mod * dpx ? rh, ro ? * dpy * dpx_mod=rh * dpy_mod=rh' * dpx ? rh, * dpy ? rh' section load/store dest= * dpx_mod dest'= * dpy_mod dest ? * dpx, dest' ? * dpy note 1, note 2, note 3 dest= * dpx_mod * dpy_mod=source dest ? * dpx, * dpy ? source * dpx_mod=source dest= * dpy_mod * dpx ? source, dest ? * dpy * dpx_mod=source * dpy_mod=source' * dpx ? source, * dpy ? source' concurrent writing processing flag tri. dyad. monad. load/ trans. imm. br. loop. ctl. ov store name mnemonic operation notes 1. one or both of a mnemonic pair can be written. 2. after execution of load/store, data is modified by mod. 3. one of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}. load/store ?? ?
29 m pd77018a, 77019 load/store inter-register transfer immediate data set direct addressing dest = * addr dest ? * addr load/store note 1 * addr = source * addr ? source immediate index dest = * dp_imm dest ? * dp load/store note 2 * dp_imm = source * dp ? source inter-register transfer dest = rl dest ? rl note 3 rl = source rl ? source immediate data set rl = imm rl ? imm (provided imm = 0-0xffff) dp = imm dp ? imm (provided imm = 0-0xffff) dn = imm dn ? imm (provided imm = 0-0xffff) dm = imm dm ? imm (provided imm = 1-0xffff) name mnemonic operation concurrent writing processing flag tri. dyad. monad. load/ trans. imm. br. loop. ctl. ov store notes 1. one of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add = . 2. one of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 3. any register except general registers should be selected as dest or source. 0: x-0xffff:x memory 0: y-0xffff:y memory
m pd77018a, 77019 30 concurrent writing processing flag tri. dyad. monad. load/ trans. imm. br. loop. ctl. ov store name mnemonic operation branch jump jmp imm pc ? imm inter-register indirect jump jmp dp pc ? dp subroutine call call imm sp ? sp + 1 stk ? pc + 1 pc ? imm inter-register indirect call dp sp ? sp + 1 subroutine call stk ? pc + 1 pc ? dp return ret pc ? stk sp ? sp C 1 return from interrupt reti pc ? stk stk ? sp C 1 restore the interrupt enable flag repeat rep count start rc ? count rf ? 0 repeat pc ? pc rc ? rc C 1 end pc ? pc + 1 rf ? 1 loop loop count start rc ? count (mnemonics more than two lines) rf ? 0 repeat pc ? pc rc ? rc C 1 end pc ? pc + 1 rf ? 1 loop pop lpop lc ? lsr3 le ? lsr2 ls ? lsr1 lsp ? lspC1 no operation nop pc ? pc + 1 halt halt cpu stop note1 stop stop cpu, pll, osc stop note2 if if (ro cond) conditional judge forget interrupt fint forget interrupt requests control hardware loop
31 m pd77018a, 77019 notes 1. the halt instruction causes all function except for clock and pll to halt. the system is placed in much less power consumption mode. the contents of internal registers and memories are maintained. halt is released by interrupt input. it takes several system clock to recover. 2. the stop instruction causes all function including clock and pll to stop. the system is placed in a minimum-power consumption mode. the contents of internal registers and memories are not maintained. after the stop instruction is executed, pin status is maintained. stop is released by hardware reset. it takes a few ms to recover.
m pd77018a, 77019 32 4. electrical specifications absolute maximum ratings (t a = +25 ?c) parameters symbol conditions ratings unit power supply voltage v dd C0.5 to +4.6 v input voltage v i 2.7 v v dd 3.6 v C0.5 to +4.1 v v i < v dd +0.5 v output voltage v o C0.5 to +4.6 v storage temperature t stg C65 to +150 ?c operating ambient temperature t a C40 to +85 ?c caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. recommended operating conditions parameters symbol conditions min. typ. max. unit operating voltage v dd m pd77018a t cc 3 19.0 ns 2.7 3.0 3.6 v t cc 3 16.6 ns 3.0 3.3 3.6 v m pd77019 t cc 3 20.0 ns 2.7 3.0 3.6 v t cc 3 16.6 ns 3.0 3.3 3.6 v input voltage v i 0v dd v capacitance (t a = +25 ?c, v dd = 0 v) parameters symbol conditions min. typ. max. unit input capacitance c i 10 pf output capacitance c o 10 pf input/output capacitance c io 10 pf f = 1 mhz unmeasured pins returned to 0 v.
33 m pd77018a, 77019 dc characteristics (t a = C40 to +85 ?c, v dd = 2.7 to 3.6 v) parameters symbol conditions min. typ. max. unit high level input voltage v ih except for x1 0.7v dd v dd v high level x1 input voltage v ihc x1 input 0.8v dd v dd v low level input voltage v il 0 0.2v dd v high level output voltage v oh i oh = C2.0 ma 0.7v dd v i oh = C100 m a 0.8v dd v low level output voltage v ol i ol = 2.0 ma 0.2v dd v high level input leak current i lih except for tdi, tms, v i = v dd 10 m a low level input leak current i lil except for tdi, tms, v i = 0 v C10 m a pull-up pin current i pi tdi, tms, 0 v v i v dd C250 m a power supply current i dd m pd77018a active mode, t cc = 25 ns, tbd 125 note 1 ma v ih = v dd , v il = 0 v, no load m pd77019 active mode, t cc = 25 ns, tbd 150 note 1 ma v ih = v dd , v il = 0 v, no load i ddh m pd77018a halt mode, t cc = 200 ns, 13.5 note2 ma v ih = v dd , v il = 0 v, no load m pd77019 halt mode, t cc = 200 ns, 15 note 2 ma v ih = v dd , v il = 0 v, no load i dds stop mode, t a = +60c, v ih = v dd , v il = 0 v, 100 m a no load notes 1. the max. value is measured when a special program that max. switching required is executed, and v dd = 3.6 v condition. you can convert by each operation frequency f[mhz] on by each power supply v dd [v]. [ m pd77018a] max. current value (t a = +25c) = (1.15 v dd C 1.21) f + 8 [ma] [ m pd77019] max. current value (t a = +25c) = (1.40 v dd C 1.74) f + 18 [ma] 2. this value is measured when v dd = 3.6 v condition. you can convert by each operation frequency f[mhz] on by each power supply v dd [v]. [ m pd77018a] halt current value (t a = +25c) = (0.15 v dd C 0.25) f + 2 [ma] [ m pd77019] halt current value (t a = +25c) = (0.17 v dd C 0.38) f + 5.9 [ma] ac timing test points input (except for x1) 0.7v dd 0.45v dd 0.2v dd 0.7v dd 0.45v dd 0.2v dd test points x1 0.8v dd 0.5v dd 0.2v dd 0.8v dd 0.5v dd 0.2v dd test points output 0.7v dd 0.45v dd 0.2v dd 0.7v dd 0.45v dd 0.2v dd test points
m pd77018a, 77019 34 ac characteristics (t a = C40 to +85 ?c, v dd = 2.7 to 3.6 v) clock required timing condition (v dd = 2.7 v to 3.6 v) parameters symbol conditions min. typ. max. unit clkin cycle time t ccx m pd77018a pll multiple rate: 1 19 40 ns pll multiple rate: 2 38 80 ns pll multiple rate: 3 57 120 ns pll multiple rate: 4 76 160 ns pll multiple rate: 8 152 320 ns m pd77019 pll multiple rate: 1 20 40 ns pll multiple rate: 2 40 80 ns pll multiple rate: 3 60 120 ns pll multiple rate: 4 80 160 ns pll multiple rate: 8 160 320 ns clkin high level width t wcxh 8t ccx C 8 ns C 2t rfcx note clkin low level width t wcxl 8t ccx C 8 ns C 2t rfcx note clkin rise/fall time t rfcx 15 ns note 0.5t ccx C t rfcx 3 8 (min.) required timing condition (v dd = 3.0 v to 3.6 v) parameters symbol conditions min. typ. max. unit clkin cycle time t ccx pll multiple rate: 1 16.6 40 ns pll multiple rate: 2 33.3 80 ns pll multiple rate: 3 50 120 ns pll multiple rate: 4 66.6 160 ns pll multiple rate: 8 133 320 ns clkin high level width t wcxh 6.5 t ccx C 6.5 ns C 2t rfcx note clkin low level width t wcxl 6.5 t ccx C 6.5 ns C 2t rfcx note clkin rise/fall time t rfcx 15 ns note 0.5t ccx C t rfcx 3 6.5 (min.) switching characteristics parameters symbol conditions min. typ. max. unit internal clock cycle time t cc active mode t ccx /n note ns halt mode 8t ccx /n note ns clkout cycle time t cco t cc ns clkout level width t wco 0.5t cco C 5 ns clkout rise/fall time t rfco 5ns note n: pll multiple rate (n = 1, 2, 3, 4, 8)
35 m pd77018a, 77019 x1 x2 c1 c2 x1 x2 external clock supply nu nu: not use. leave open. oscillator circuit resonator recommended circuit ceramic or crystal resonator external clock cautions 1. when using system clock oscillator, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as gnd. ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillator. 2. when using ceramic resonator or crystal resonator, frequency multiple rate should be specified to as 1 by mask option. the device does not operate in other frequency multiple rate. recommended oscillator circuit constants tbd
m pd77018a, 77019 36 reset, interrupt required timing condition parameters symbol conditions min. typ. max. unit reset low level width t w(rl) crystal resonator is input, 3 note 1 ms at power on or stop mode external clock is input, 100 note 1 m s at power on or stop mode active mode or halt mode 4t cc note 2 ns reset recovery time t rec(r) 4t cc ns int1-int4 low level width t w(intl) 3t cc note 2 ns int1-int4 recovery time t rec(int) 3t cc ns notes 1. the t w(rl) indicates a time between crystal resonator or oscillator starts to provide clock and pll becomes stable. the t w(rl) depends on the rating of crystal resonator or oscillator. at power on, the t w(rl) is measured after the point that power supply voltage reaches to 2.7v. 2. note that, during halt mode, t cc is extended to 8 times as long as that of active mode.
37 m pd77018a, 77019 clock input/output timing internal clock x1 clkout t ccx t wcxh t wcxl t rfcx t rfcx t cc t cco t wco t rfco t rfco t wco reset timing interrupt timing reset t w(rl) t rec(r) int1 - int4 t w(intl) t rec(int)
38 m pd77018a, 77019 external data memory access required timing condition parameters symbol conditions min. typ. max. unit read data setup time t suddrd 15 ns read data hold time t hddrd 0ns wait setup time t suwa 12 ns wait hold time t hwa 0ns switching characteristics parameters symbol conditions min. typ. max. unit address output delay time t dda 8ns address output hold time t hda 0ns mrd output delay time t ddr 8ns mrd hold time t hdr 0ns write data output valid time t vddwd 16 ns write data output hold time t hddwd 0ns mwr output delay time t ddw 0.25t cc C 5 ns mwr setup time t sudw 0ns mwr low level width t wdwl 0.5t cc C 3 ns + t cdw note mwr high level width t wdwh 0.5t cc C 5 ns note t cdw : data wait cycle external data memory access timing (read) t suddrd t hdr t hwa clkout da0 - da13, x/y d0 - d15 mrd wait t dda t ddr t suwa t suwa t hwa t hddrd t hda
m pd77018a, 77019 39 external data memory access timing (write) t hwa clkout da0 - da13, x/y d0 - d15 mwr wait t dda t suwa t suwa t hwa t wdwh t wdwl t hddwd t ddw t sudw hi-z hi-z t vddwd t vddwd t hda
40 m pd77018a, 77019 bus arbitration required timing condition parameters symbol conditions min. typ. max. unit holdrq setup time t suhrq 12 ns holdrq hold time t hhrq 0ns switching characteristics parameters symbol conditions min. typ. max. unit bstb hold time t hbs 0ns bstb output delay time t dbs 12 ns holdak output delay time t dhak 12 ns data hold time when bus arbitration t h(bs-d) 30 ns data valid time after bus arbitration t v(bs-d) 15 ns
m pd77018a, 77019 41 bus arbitration timing (bus idle) clkout t suhrq bstb holdrq holdak x/y, da0 - da13, mrd, mwr t hbs (bus busy) bus idle t dbs t dhak t h(bs-d) t hhrq t suhrq bus release bus idle (bus busy) t hhrq t v(bs-d) t dhak hi-z
42 m pd77018a, 77019 bus arbitration timing (bus busy) clkout t suhrq bstb holdrq holdak x/y, da0 - da13, mrd, mwr (bus busy) bus busy t hbs t dhak t suhrq bus idle bus idle (bus busy) t hhrq t v(bs-d) t dhak bus release t hhrq t dbs t h(bs-d) hi-z
m pd77018a, 77019 43 serial interface required timing condition parameters symbol conditions min. typ. max. unit sck input cycle time t csc 2t cc ns sck input high/low level width t wsc 25 ns sck input rise/fall time t rfsc 20 ns soen recovery time t recsoe 20 ns soen hold time t hsoe 0ns sien recovery time t recsie 20 ns sien hold time t hsie 0ns si setup time t susi 20 ns si hold time t hsi 0ns switching characteristics parameters symbol conditions min. typ. max. unit sorq output delay time t dsor 30 ns sorq hold time t hsor 0ns so valid time t vso 30 ns so hold time t hso 0ns siak output delay time t dsia 30 ns siak hold time t hsia 0ns notes for serial clock serial clock inputs sck1 and sck2 are sensitive to any kind of interfering signals (noise on power supply, induced voltage, etc.). spurious signals can cause malfunction of the device. special care for the serial clock design should be taken. careful grounding, decoupling and short wiring of sck1 and sck2 are recommended. intersection of sck1 and sck2 with other serial interface lines or close wiring to lines carrying high frequency signals or large changing currents should be avoided. it considers for the serial clock to make a waveform stable especially about the rising and falling. example 1. good example straight rising form and falling form example 2. no good example it doesn? bound. it doesn? make noise one above another. example 3. no good example it doesn? make a stair stepping.
44 m pd77018a, 77019 serial output timing 1 sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t hso t vso t vso t hsoe t recsoe t recsoe t hsoe t dsor t wsc t wsc t csc t hsor t rfsc hi-z hi-z
m pd77018a, 77019 45 serial output timing 2 (continual output) sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t vso t hsoe t recsoe t dsor t wsc t wsc t csc t hsor t rfsc last hi-z t hso
46 m pd77018a, 77019 serial input timing 1 sck1, sck2 siak1 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t recsie t hsie t recsie t hsie t hsia t susi t hsi 1st 2nd t rfsc t rfsc 3rd
m pd77018a, 77019 47 serial input timing 2 (continual input) sck1, sck2 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t recsie t hsie t hsia t susi t hsi 1st 3rd t rfsc t rfsc last laste1 2nd siak1
48 m pd77018a, 77019 host interface required timing condition parameters symbol conditions min. typ. max. unit hrd delay time t dhr 0ns hrd width t whr 2t cc ns hcs, ha0, ha1 read hold time t hhcar 0ns hcs, ha0, ha1 write hold time t hhcaw 0ns hrd, hwr recovery time t rechs 2t cc ns hwr delay time t dhw 0ns hwr width t whw 2t cc ns hwr hold time t hhdw 0ns hwr setup time t suhdw 20 ns switching characteristics parameters symbol conditions min. typ. max. unit hre, hwe output delay time t dhe 30 ns hre, hwe hold time t hhe 30 ns hrd valid time t vhdr 30 ns hrd hold time t hhdr 0ns
m pd77018a, 77019 49 host interface timing (read) clkout hrd t dhe t hhdr t hhcar t rechs t vhdr t whr t dhr t hhe hcs, ha0, ha1 hd0 - hd7 hre hi-z hi-z
50 m pd77018a, 77019 host interface timing (write) clkout hwr t dhe t hhdw t hhcaw t rechs t whw t dhw t hhe hcs, ha0, ha1 hd0 - hd7 hwe t suhdw
m pd77018a, 77019 51 general input/output ports required timing condition parameters symbol conditions min. typ. max. unit port input setup time t supi 20 ns port input hold time t hpi 10 ns switching characteristics parameters symbol conditions min. typ. max. unit port output delay time t dpo 030ns general input/output ports timing clkout p0 - p3 (output) p0 - p3 (input) t dpo t supi t hpi
52 m pd77018a, 77019 debugging interface (jtag) required timing condition parameters symbol conditions min. typ. max. unit tck cycle time t ctck 4t cc ns tck high/low level width t wtck 50 ns tck rise/fall time t rftck 20 ns tms, tdi setup time t sudi 10 ns tms, tdi hold time t hdi 0ns input pin setup time t sujin 10 ns input pin hold time t hjin 0 ns switching characteristics parameters symbol conditions min. typ. max. unit tdo output delay time t ddo 30 ns output pin output delay time t djout 30 ns debugging interface timing remark for the details of jtag, refer to ieee1149.1. t ctck t wtck t wtck t sudi t hdi valid valid valid t ddo t sujin t hjin valid t djout t rftck t rftck tck tms, tdi tdo capture state update state
m pd77018a, 77019 53 5. package drawing 100 pin plastic tqfp (fine pitch) ( 14) item millimeters inches a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 s100gc-50-9eu-1 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.0?.1 0.039 +0.005 ?.004 q 0.1?.05 0.004?.002 +0.055 ?.045 b c d j h i g f p n l k m q r r3 3 +7 ? +7 ? detail of lead end m 75 76 50 26 25 51 100 1 d f 1.0 16.0?.2 0.630?.008 0.039 g 1.0 0.039 h 0.22 0.009?.002 i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) +0.05 ?.04
54 m pd77018a, 77019 6. recommended soldering conditions when soldering these products, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. for more details, refer to our document semiconductor device mounting technology manual (c10535e) . surface mount device m pd77018agc- -9eu: 100-pin plastic tqfp (fine pitch) (14 14mm) m pd77019gc- -9eu: 100-pin plastic tqfp (fine pitch) (14 14mm) peak temperature: 235 ?c or below (package surface temperature), reflow time: 30 seconds or less (at 210 ?c or higher), maximum number of reflow processes : 2 times, exposure limit note : 3 days (10 hours pre-baking is required at 125 ?c afterwards). peak temperature: 215 ?c or below (package surface temperature), reflow time: 40 seconds or less (at 200 ?c or higher), maximum number of reflow processes : 2 times, exposure limit note : 3 days (10 hours pre-baking is required at 125 c afterwards). pin temperature : 300 ?c or below, heat time : 3 seconds or less (per each side of the device) process conditions symbol i nfrared ray reflow ir35-103-2 vapor phase soldering partial heating method vp15-103-2 note maximum allowable time from taking the soldering package out of dry pack to soldering. storage conditions: 25 c and relative humidity of 65 % or less. caution apply only one kind of soldering condition to a device, except for partial heating method, or the device will be damaged by heat stress.
m pd77018a, 77019 55 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd77018a, 77019 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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