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? semiconductor components industries, llc, 2009 july, 2009 ? rev. 0 1 publication order number: NB7VPQ16M/d NB7VPQ16M 1.8v/2.5v cml 12.5 gbps programmable pre-emphasis copper/cable driver with selectable equalizer receiver multi ? level inputs w/ internal termination description the NB7VPQ16M is a high performance single channel programmable pre ? emphasis cml driver with a selectable equalizer receiver that operates up to 14 gbps typical with a 1.8 v or 2.5 v power supply. when placed in series with a data/clock path, the NB7VPQ16M inputs will compensate the degraded signal transmitted across a fr4 pcb backplane or cable interconnect. therefore, the serial data rate is increased by reducing inter ? symbol interference (isi) caused by losses in copper interconnect or long cables. the pre ? emphasis buffer is controlled using a serial bus via the serial data in (sdin) and serial clock in (sclkin) control inputs and contains circuitry which provides sixteen programmable pre ? emphasis settings to select the optimal output compensation level. these selectable output levels will handle various backplane lengths and cable lines. the first four sdin bits (d3:d0) will digitally select 0 db through 12 db typical of de ? emphasis (see table 1). for cascaded applications, the shifted sdin and sclkin signals are presented at the sdout and sclkout pins. the 5 th ? bit (lsb) of the serial data bits allows for enabling the equalization function of the receiver. the differential data / clock inputs incorporate a pair of internal 50 termination resistors, in a 100 center ? tapped configuration, via the vt pin and will accept lvpecl, cml or lvds logic levels. this feature provides transmission line termination on ? chip, at the receiver end, eliminating external components. the NB7VPQ16M is a member of the gigacomm ? family of high performance data/clock products with pre ? emphasis/equalization (peeq). features ? maximum input data rate > 12.5 gbps ? maximum input clock frequency > 8 ghz ? drives up to 18 ? inches of fr4 ? (16) programmable output de ? emphasis levels; 0 db through 12 db ? 200 ps typical propagation delay ? differential cml outputs, 400 mv peak ? to ? peak, typical (pe = 0 db) ? operating range: v cc = 1.71 v to 2.625 v, gnd = 0 v ? internal output termination resistors, 50 ? qfn ? 16 package, 3 mm x 3 mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 15 of this data sheet. ordering information 16 nb7v pq16m alyw 1 figure 1. simplified logic diagram (note: microdot may be in either location) sdi dac pe eq sdout sclkout q sdin sclkin sload q in in vt 1
NB7VPQ16M http://onsemi.com 2 figure 2. detailed block diagram of NB7VPQ16M eq sclkout sdout sclkin sdin sload 4 ? bit dac d/a latch 5 ? bit shift register 0 1 2:1 mux pre ? emphasis control cml output multi ? level inputs lvpecl, lvds, cml in vt eqen in 50 50 (equalizer enable) eqen d0 d1 d2 d3 q q (2) (1) (3) (15) (14) (13) (6) (7) (11) (10) v ccd v cc gnd 20% figure 3. illustration of output waveform definition bit n ? 1 bit n bit n+1 bit n+2 pe = 0db pe = ? 12db 0v t pe 130ps q high q low q high q low q low q high q low q high v od0db v odpe 80% q q pe = 20log(v odpe /v od0db ) v od0db ? differential output voltage without pre ? emphasis v odpe ? differential output voltage with pre ? emphasis
NB7VPQ16M http://onsemi.com 3 table 1. typical pre ? emphasis control table, eq = 0, 25 c, v cc = 1.8 v decimal 4 ? bit pe pe output compensation in db approximate @ 1 ghz v odpe typ (mv) msb lsb d3 d2 d1 d0 00 0 0 0 0 0 db (default) 435 01 0 0 0 1 ? 1.0 db 390 02 0 0 1 0 ? 1.5 db 365 03 0 0 1 1 ? 2.0 db 345 04 0 1 0 0 ? 2.5 db 325 05 0 1 0 1 ? 3.0 db 310 06 0 1 1 0 ? 3.5 db 290 07 0 1 1 1 ? 4.0 db 275 08 1 0 0 0 ? 4.5 db 260 09 1 0 0 1 ? 5.0 db 245 10 1 0 1 0 ? 6.0 db 220 11 1 0 1 1 ? 7.0 db 195 12 1 1 0 0 ? 8.0 db 175 13 1 1 0 1 ? 9.0 db 155 14 1 1 1 0 ? 10.0 db 135 15 1 1 1 1 ? 12.0 db 110 table 2. equalizer enable function eqen function 0 in/in inputs by ? pass the equalizer section 1 inputs flow through the equalizer
NB7VPQ16M http://onsemi.com 4 figure 4. pin configuration (top view) v ccd sdout sclkout gnd v cc sdin sclkin sload v cc q q v cc vt in in gnd 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB7VPQ16M exposed pad (ep) table 3. pin description pin name i/o description 1 vt internal 50 ? termination pin for in and in 2 in lvpecl, cml, lvds input non ? inverted differential clock/data input. (note 1) 3 in lvpecl, cml, lvds input inverted differential clock/data input. (note 1) 4 gnd ? negative supply voltage; (note 2) 5 vccd ? positive supply voltage for serial bus logic and 5 ? bit dac; (note 2) 6 sdout lvcmos output serial data out 7 sclkout lvcmos output serial clock out 8 gnd ? negative supply voltage; (note 2) 9 vcc ? positive supply voltage for the analog circuitry and cml output buffer; (note 2) 10 q cml inverted differential output. (note 1) 11 q cml non ? inverted differential output. (note 1) 12 vcc ? positive supply voltage for the analog circuitry and cml output buffer; (note 2) 13 sload lvcmos input when the sload pin is low or left open (has internal pulldown resistor), the output of the shift register will input the 4 ? bit dac and set the eqen bit. when high, the input to the 4 ? bit dac is locked to the state prior to when sload went high. 14 sclkin lvcmos input serial clock in; pin will default low when left open (has internal pulldown resistor) 15 sdin lvcmos input serial data in; pin will default low when left open (has internal pulldown resistor) 16 vcc ? positive supply voltage for the analog circuitry and cml output buffer; (note 2) ep the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is also electrically connected to the die, and must be electrically and thermally connected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pin (v t ) is connected to a common termination voltage or left open, and if no input signal is applied on in/in input, then the device will be susceptible to self ? oscillation. q/q outputs have internal 50 source termination resistor. 2. all v cc, v ccd and gnd pins must be externally connected to a power supply voltage to guarantee proper device operation.
NB7VPQ16M http://onsemi.com 5 table 4. attributes characteristics value esd protection human body model machine model > 4 kv > 200 v internal input pulldown resistor 75 k moisture sensitivity, indefinite time out of drypack (note 3) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 416 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 5. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc, v ccd positive power supply gnd = 0 v 3.0 v v in positive input voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |in ? in | 1.89 v i out output current continuous surge 34 40 ma i in input current through r t (50 resistor) 40 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) tgsd 51 ? 6 (2s2p multilayer test board) with filled thermal vias 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w jc thermal resistance (junction ? to ? case) standard board qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7VPQ16M http://onsemi.com 6 table 6. dc characteristics positive cml output v cc = v ccd = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 5) symbol characteristic min typ max unit power supply current i cc power supply current, (inputs and outputs open) v cc = 2.5 v pe = 0db v cc = 1.8 v 95 80 120 100 ma i ccd power supply current for serial bus and dac pe = 0000 = 0db (inputs and outputs open) pe = 1111 = max 0 10 20 ma cml outputs pe = 0db (note 6, figure 22) v oh output high voltage v cc = 2.5 v v cc = 1.8 v v cc ? 30 2470 1770 v cc ? 10 2490 1790 v cc 2500 1800 mv v ol output low voltage v cc = 2.5 v v cc ? 600 1900 v cc ? 500 2000 v cc ? 400 2100 mv v cc = 1.8 v v cc ? 550 1250 v cc ? 450 1350 v cc ? 350 1450 data/clock inputs (in, in ) (note 7) (figure 6) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv i ih input high current ? 150 20 150 a i il input low current ? 150 5 150 a control inputs (sdin, sclkin, sload) v ih input high voltage for control pins v ccd x 0.65 v ccd mv v il input low voltage for control pins gnd v ccd x 0.35 mv i ih input high current ? 150 20 150 a i il input low current ? 150 5 150 a control outputs (sdout, sclkout) v oh output high voltage v cc ? 200 v cc mv v ol output low voltage gnd 200 mv termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs loaded with 50 to v cc for proper operation. 7. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
NB7VPQ16M http://onsemi.com 7 table 7. ac characteristics v cc = v ccd = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 8) symbol characteristic min typ max unit f datamax maximum input data rate 12.5 14 gbps f max maximum input clock frequency (note 9) v outpp 200 mv 8 ghz f sclkin serial clock input frequency 20 mhz vod 0db output voltage amplitude (see table 1) (@ v inppmin ) (see figure 3, note 9) f in 6.0 ghz f in 8.0 ghz 300 200 400 300 mv t pe pre ? emphasis width, tested at ? 12db pre ? emphasis 130 ps v cmr input common mode range (differential configuration, note 10) (figure 8) 1050 v cc mv t plh , t phl propagation delay to differential outputs, in/in to q/q 1 ghz, measured at differential cross ? point sclkin to sclkout 150 200 5 250 10 ps ns t dc output clock duty cycle (reference duty cycle = 50%) f in 5.0 ghz 45 50 55 % t s1 t s2 t s3 setup time @ 50 mhz (figures 9 and 10) sdin to sclkin sclkin to sload sload to in/in 5 5 10 ns t h1 t h2 t h3 hold time @ 50 mhz (figures 9 and 10) sdin to sclkin sclkin to sload 1 2 ns t pw_sload sload minimum pulse width (figure 10) 6 ns t jitter rj ? output random jitter (note 11) f in 8.0 ghz dj ? residual output deterministic jitter (note 12) (eq = 0, pe = 0 db) fr4 3?, f 12.5 gbps (figures 15 and 16) fr4 = 12?, f 6.5 gbps 0.1 0.8 10 10 ps rms ps pk ? pk v inpp input voltage swing (differential configuration) (note 9) 100 1200 mv t r , t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 35 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured using a 400 mv source, 50% duty cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps. (20% ? 80%); pe = 0 db, eqen = 0 9. input / output voltage swing is a single ? ended measurement operating in differential mode. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal. 11. additive rms jitter with 50% duty cycle clock signal. 12. peak ? to ? peak jitter with input nrz data at prbs23. figure 5. input structure 50 50 v t v cc in in
NB7VPQ16M http://onsemi.com 8 in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) figure 6. differential inputs driven differentially figure 7. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in)| in in figure 8. v cmr diagram v cmmin v cmmax in v cmr v cc gnd in v ildmax v ihdmax v inpp v ildtyp v ihdtyp v ildmin v ihdmin sclkin sdin sload sclkin figure 9. sdin/sclkin setup and hold time figure 10. sload set ? up and hold and t pwmin t s1 t h1 t s2 t h2 t pwmin
NB7VPQ16M http://onsemi.com 9 application information data inputs the differential in/in inputs of the NB7VPQ16M can accept lvpecl, cml, and lvds signal levels. the limitations for a differential input signal (lvds, lvpecl, or cml) is a minimum input swing of 100 mv (single ? ended measurement). within this condition, the input high voltage, v ih , can range from v cc down to 1.1 v. example interfaces are illustrated in figure 17. serial data interface the serial data interface (sdi) logic is implemented with a 5 ? bit shift register scheme. the register shifts once per rising edge of the sclkin input. the serial data input sdin must meet setup and hold timing as specified in the ac table. the configuration latches will capture the value of the shift register on the low ? to ? high edge of the sload input. the most significant bit (msb) is loaded first. see the programming timing diagram for more information. sdin / sclkin sdin is the serial data input pin; sclkin is the serial clock input pin. sload the sload pin performs the dac latch function. when low or left open, the dac latch will pass the shift register outputs to the input of the dac and the equalizer enable bit (eqen). on the low ? to ? high transition of sload, the input to the 4 ? bit dac is locked to the state prior to when sload went high, and will set the equalizer enable bit. the dac does not get programmed until sload goes high. the sload pin must remain in a high state to maintain the dac pre ? emphasis and the eqen settings. a low or open state resets the dac to 0 db pre ? emphasis setting and disables the eqen bit, regardless of sdin and sclkin values. the sload function is asynchronous. figure 11. timing diagram for single channel d3 d2 d1 d0 eqen 123 456789101112 1 2 345 6 7 891011 ///// ///// ///// ///// ///// ///// ///// ///// ///// ///// d3 d2 d1 d0 eqen ///// ///// ///// ///// 5 clock sclkin to sdout sdin sclkin sload sdout sclkout t pwmin pre ? emphasis selection the pre ? emphasis buffer is controlled using a serial bus via the sdin (serial data in) and sclkin (serial clock in) control inputs and contains circuitry which provides sixteen programmable pre ? emphasis levels to control the output compensation. the 4 ? bits (d3:d0) digitally select 0 db through 12 db of pre ? emphasis compensation (see table 1). the default state at start ? up is pe = 0 db. equalization enable (eqen) the equalizer enable (eqen) allows for enabling the equalizer function. the control of the equalizer function is realized by setting the 5th bit, eqen, of the 5 ? bit serial data. when eqen is set low (or open), the in/in inputs bypass the equalizer. when eqen is set high, the in/in inputs flow through the equalizer. the default state at start ? up is eqen = low. q/q outputs the differential outputs of the NB7VPQ16M, q and q , utilize common mode logic (cml) architecture. the outputs are designed to drive dif ferential transmission lines with nominal 50 characteristic impedance. external termination with a 50 resistor to v cc is recommended. see figures 22 and 23 for output termination scheme. alternatively, 100 line ? to ? line termination is also acceptable. power supply bypass information a clean power supply will optimize the performance of the NB7VPQ16M. the device provides separate v ccd and v cc power supply pins for the digital circuitry and cml outputs. placing a 0.01 f to 0.1 f bypass capacitor on each v cc and v ccd pin to ground will help ensure a noise free power supply. the purpose of this design technique is to isolate the cmos digital switching noise from the high speed input/output path.
NB7VPQ16M http://onsemi.com 10 cascade application sdout/sclkout sdout is the serial data output pin; sclkout is the serial clock output pin. these pins are the outputs of the 5 ? bit sdi shift register and will produce the sdin/sclkin signals after five serial clock cycles, see figure 12. the purpose of sdout and sclkout is for use in cascade applications, described below. figure 12. simplified cascaded serial data/clock timing diagram duta dutb d3 d2 d1 d0 eqen sdin sclkin sdout sclkout sdin sclkin sdout sclkout d2 d1 d0 eqen d3 12345 5 6789 5 clocks cascaded applications the NB7VPQ16M can be cascaded with multiple NB7VPQ16Ms in series for various equalizer/pre ? emphasis applications, as shown in figure 13. serial data in, sdina, is clocked with sclkina into the cascaded chain of the pre ? emphasis and equalizer shift registers, (duta, dutb and dutc), 5 ? bits per register. upon the rising edge of the 5 th clock of sclkina, the first valid data bit (d3) and 5 th clock will exit duta from sdouta and sclkouta and will be present at sdinb and sclkinb of dutb and so on. when sload is brought low, the pe shift registers of all devices are enabled and data is written into the NB7VPQ16Ms with the contents of the pe shift registers. when the data transfer is complete, sload is brought high and all NB7VPQ16Ms are updated simultaneously. after the pe control bits are clocked into their appropriate registers, the low ? to ? high transition of sload will latch the data bits for the pre ? emphasis dacs.
NB7VPQ16M http://onsemi.com 11 eqa pec peb eqc eqb cml cml sdoutc sclkoutc sdina sclkina sload sload sload dutc duta dutb dutc duta dutb xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 5 clocks 5 clocks 5 clocks sclkin to sclkout cml pea figure 13. simplified cascaded logic diagram ina inb inc qc qb qa sdinc sclkinc sdoutb sclkoutb sdouta sclkouta sdinb sclkinb serial data in serial clock in figure 14. simplified cascaded serial data/clock timing diagram d3c d2c d1c d0c eqc d3b d2b d1b d0b eqb d3a d2a d1a d0a eqa 123456789101112131415 d3c d2c d1c d0c eqc d3b d2b d1b d0b eqb d3a d2a d1a d0a eqa 1 2 3 4 5 6 7 8 9 10 111213 14 1516 1718 19 sclkin to sdout sdin sclkin sdout sclkout xxxxxxxxxxxxxxxxx t pd t pd duta dutb dutc sload t pwmin xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx t s3 in in
NB7VPQ16M http://onsemi.com 12 q NB7VPQ16M equalizer receiver eq = 0 and 1 digital oscilloscope q fr4 = 12? backplane 50 50 signal generator signal generator output signal generator output NB7VPQ16M after 12 ? inches of fr ? 4 NB7VPQ16M after 12 ? inches of fr ? 4 NB7VPQ16M output eq = 1 NB7VPQ16M output eq= 0 20 mv/div 28 ps/div 20 mv/div 28 ps/div 65 mv/div 28 ps/div 20 mv/div 28 ps/div 20 mv/div 28 ps/div 65 mv/div 28 ps/div figure 15. typical NB7VPQ16M equalizer application and interconnect; eye diagrams with prbs23 pattern at 6 gbps
NB7VPQ16M http://onsemi.com 13 q NB7VPQ16M pre ? emphasis driver digital oscilloscope q fr4 = 12? backplane 50 50 figure 16. typical NB7VPQ16M pre ? emphasis application interconnect; eye diagrams with prbs23 pattern at 6 gbps without and with pre ? emphasis signal generator signal generator output 20 mv/div 28 ps/div 20 mv/div 28 ps/div 65 mv/div 28 ps/div 20 mv/div 28 ps/div 20 mv/div 28 ps/div 65 mv/div 28 ps/div NB7VPQ16M output after 0 ? inches of fr ? 4 pe = 0 db NB7VPQ16M output after 12 ? inches of fr ? 4 pe = 0 db signal generator output NB7VPQ16M output after 0 ? inches of fr ? 4 pe = 6 db NB7VPQ16M output after 12 ? inches of fr ? 4 pe = 6 db
NB7VPQ16M http://onsemi.com 14 lvpecl driver v cc gnd z o = 50 v t = v cc ? 2 v z o = 50 NB7VPQ16M in 50 50 in gnd figure 17. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 NB7VPQ16M in 50 50 in gnd figure 18. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 NB7VPQ16M in 50 50 in gnd v cc figure 19. standard 50 load cml interface differential driver v cc gnd z o = 50 v t = v refac * z o = 50 NB7VPQ16M in 50 50 in gnd v cc figure 20. capacitor ? coupled differential interface (vt connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor single ? ended driver v cc gnd z o = 50 v t = v refac * NB7VPQ16M in 50 50 in gnd v cc figure 21. capacitor ? coupled single ? ended interface (vt connected to external v refac ) (open)
NB7VPQ16M http://onsemi.com 15 figure 22. typical cml output structure and termination v cco 50 50 16 ma 50 50 v cc (receiver) gnd figure 23. alternative output termination v cco 50 50 16 ma 100 gnd NB7VPQ16M NB7VPQ16M receiver receiver q q q q driver device receiver device qin figure 24. typical termination for cml output driver and device evaluation q in v cc 50 50 z = 50 z = 50 dut ordering information device package shipping ? NB7VPQ16Mmng qfn ? 16 (pb ? free) 123 units / rail NB7VPQ16Mmntxg qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7VPQ16M http://onsemi.com 16 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NB7VPQ16M/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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