View PD78095B_3488745.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. u12326ej3v0um00 (3rd edition) (o. d. no. ieu-849) date published june 1997 n printed in japan 78k/0 series 8-bit single-chip microcontrollers instructions for all 78k/0 series 1995
notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
caution: the following products are provided with an i 2 c bus interface circuit: m pd78002y subseries, m pd78014y subseries, m pd78018fy subseries m pd78054y subseries, m pd78058fy subseries, m pd78064y subseries m pd78075by subseries, m pd78078y subseries, m pd780018y subseries m pd780024y subseries, m pd780034y subseries, m pd780058y subseries m pd780308y subseries, m pd78070ay purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. fip and iebus are trademarks of nec corporation. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5
nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
major revisions in this edition page contents throughout added products, deleted products added products : m pd78014h, 78018fy, 78044f, 78044h, 78058f, 78058fy, 78064y, 78064b, 78075b, 78075by, 78078y, 78098b, 780018y, 780024, 780024y, 780034, 780034y, 780058, 780058y, 780228, 780308, 780308y, 780924, 780964 subseries and m pd78011f, 78012f, 78070a, 78070ay, 780001, 78p0914, 780206, 780208 deleted products: m pd78024, 78044, 78044a subseries p.11 add table 1-13 internal ram space of 78k/0 series products p.17 change table 1-14 external memory space of 78k/0 series products the mark shows major revised points.
introduction intended readership this manual has been prepared for user engineers who want to understand the functions of the 78k/0 series products and design and develop its application systems and programs. 78k/0 series products ? m pd78002 subseries : m pd78001b, 78002b ? m pd78002y subseries : m pd78001by, 78002by ? m pd78014 subseries : m pd78011b, 78012b, 78013, 78014, 78p014 ? m pd78014y subseries : m pd78011by, 78012by, 78013y, 78014y, 78p014y ? m pd78014h subseries : m pd78011h, 78012h, 78013h, 78014h ? m pd78018f subseries : m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f, 78p018f ? m pd78018fy subseries : m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78018fy, 78p018fy ? m pd78044f subseries : m pd78042f, 78043f, 78044f, 78045f, 78p048a ? m pd78044h subseries : m pd78044h, 78045h, 78046h, 78p048b ? m pd78054 subseries : m pd78052, 78053, 78054, 78p054, 78055, 78056, 78058, 78p058 ? m pd78054y subseries : m pd78052y, 78053y, 78054y, 78p054y, 78055y, 78056y, 78058y, 78p058y ? m pd78058f subseries : m pd78056f, 78058f, 78p058f ? m pd78058fy subseries : m pd78056fy, 78058fy, 78p058fy ? m pd78064 subseries : m pd78062, 78063, 78064, 78p064 ? m pd78064y subseries : m pd78062y, 78063y, 78064y, 78p064y ? m pd78064b subseries : m pd78064b, 78p064b ? m pd78070a : m pd78070a ? m pd78070ay : m pd78070ay ? m pd78075b subseries : m pd78074b, 78075b ? m pd78075by subseries : m pd78074by, 78075by ? m pd78078 subseries : m pd78076, 78078, 78p078 ? m pd78078y subseries : m pd78076y, 78078y, 78p078y ? m pd78083 subseries : m pd78081, 78082, 78p083 ? m pd78098 subseries : m pd78094, 78095, 78096, 78098a, 78p098a ? m pd78098b subseries note : m PD78095B, 78096b, 78098b, 78p098b ? m pd780001 : m pd78001 ? m pd780018y subseries note : m pd780016y, 780018y, 78p0018y ? m pd780024 subseries note : m pd780021, 780022, 780023, 780024 ? m pd780024y subseries note : m pd780021y, 780022y, 780023y, 780024y ? m pd780034 subseries note : m pd780031, 780032, 780033, 780034, 78f0034 ? m pd780034y subseries note : m pd780031y, 780032y, 780033y, 780034y, 78f0034y ? m pd780058 subseries note : m pd780053, 780054, 780055, 780056, 780058, 78f0058
? m pd780058y subseries note : m pd780053y, 780054y, 780055y, 780056y, 780058y, 78f0058y ? m pd780208 subseries note : m pd780204, 780205, 780206, 780208, 78p0208 ? m pd780228 subseries note : m pd780226, 780228, 78f0228 ? m pd780308 subseries note : m pd780306, 780308, 78p0308 ? m pd780308y subseries note : m pd780306y, 780308y, 78p0308y ? m pd78p0914 note : m pd78p0914 ? m pd780924 subseries note : m pd780921, 780922, 780923, 780924, 78f0924 ? m pd780964 subseries note : m pd780961, 780962, 780963, 780964, 78f0964 note under development purpose this manual is intended for the users to understand the various kinds of instruction functions of 78k/0 series products. organization this manual consists of the following contents. ? cpu functions ? instruction set ? explanation of instructions how to read this manual before reading this manual, you must have general knowledge of electric and logic circuits and microcontroller. ? to check the details of the functions of an instruction whose mnemonic is known: ? refer to appendices b and c instruction index . ? to check an instruction whose mnemonic is not known and whose general function is known: ? check the mnemonic in chapter 4 instruction set and then the functions in chapter 5 explanation of instructions . ? to learn about various kinds of 78k/0 series products instructions in general: ? read this manual in the order of contents. ? to learn about the hardware functions of 78k/0 series products: ? see the separate users manual (refer to related documents ). legend data representation weight : high digits on the left and low digits on the right note : description of note in the text caution : information requiring particular attention remark : additional explanatory material numeral representations : binary .............. xxxx or xxxxb decimal ........... xxxx hexadecimal ... xxxxh
related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? documents common for 78k/0 series document name japanese document number english document number user's manual instructions u12326j this manual application note note basic i iea-715 iea-1288 basic ii u10121j u10121e basic iii iea-767 u10182e floating-point operation program iea-718 iea-1289 selection guide u11126j u11126e instruction table c10903j instruction set c10904j note some subseries may not be covered. ? individual documents m pd78002, 78002y subseries document name japanese document number english document number m pd78001b, 78002b data sheet u10674j u10674e m pd78001by, 78002by data sheet ic-8571 ic-3173 user's manual u10039j u10039e special function register table iem-5556 m pd78014 subseries document name japanese document number english document number m pd78011b, 78012b, 78013, 78014 data sheet ic-8201 ic-3179 m pd78p014 data sheet ic-8111 ic-3098 user's manual u10085j u10085e special function register table iem-5527 m pd78014y subseries document name japanese document number english document number m pd78011by, 78012by, 78013y, 78014y data sheet ic-8573 ic-3405 m pd78p014y data sheet ic-8572 ic-3180 user's manual u10085j u10085e special function register table iem-5527
m pd78014h subseries document name japanese document number english document number m pd78011h, 78012h, 78013h, 78014h data sheet u11898j u11898e user's manual u12220j u12220e special function register table to be prepared C m pd78018f subseries document name japanese document number english document number m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f data sheet u10280j u10280e m pd78p018f data sheet u10955j u10955e user's manual u10659j u10659e special function register table iem-5594 m pd78018fy subseries document name japanese document number english document number m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy data sheet u10280j u10280e m pd78p018fy data sheet u10989j u10989e user's manual u10659j u10659e special function register table u10287j m pd78044f subseries document name japanese document number english document number m pd78042f, 78043f, 78044f, 78045f data sheet u10700j u10700e m pd78p048a data sheet u10611j u10611e user's manual u10908j u10908e special function register table u10701j m pd78044h subseries document name japanese document number english document number m pd78044h, 78045h, 78046h data sheet u10865j u10865e m pd78p048b data sheet to be prepared to be prepared user's manual u11756j u11756e
m pd78054 subseries document name japanese document number english document number m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet ic-8631 ic-3403 m pd78p054 data sheet ic-8635 ic-3216 m pd78p058 data sheet ic-8884 u10417e user's manual u11747j u11747e special function register table u10102j m pd78054y subseries document name japanese document number english document number m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y data sheet u10906j u10906e m pd78p054y preliminary product information ip-8719 ip-3205 m pd78p058y data sheet u10907j u10907e user's manual u11747j u11747e special function register table u10087j m pd78058f subseries document name japanese document number english document number m pd78056f, 78058f data sheet u11795j u11795e m pd78p058f data sheet u11796j u11796e user's manual u12068j u12068e special function register table to be prepared m pd78058fy subseries document name japanese document number english document number m pd78056fy, 78058fy data sheet u12325j u12325e m pd78p058fy data sheet u12076j u12076e user's manual u12068j u12068e special function register table to be prepared m pd78064 subseries document name japanese document number english document number m pd78062, 78063, 78064 data sheet ic-8632 ic-3244 m pd78p064 data sheet ic-8636 ic-3224 user's manual u10105j u10105e special function register table iem-5568
m pd78064y subseries document name japanese document number english document number m pd78062y, 78063y, 78064y data sheet ic-8704 u10337e m pd78p064y data sheet u10321j ip-3236 user's manual u10105j u10105e special function register table iem-5583 m pd78064b subseries document name japanese document number english document number m pd78064b data sheet u11590j u11590e m pd78p064b data sheet u11598j u11598e user's manual u10785j u10785e special function register table to be prepared m pd78070a document name japanese document number english document number m pd78070a data sheet u10326j u10326e user's manual ieu-907 u10200e special function register table u10133j m pd78070ay document name japanese document number english document number m pd78070ay data sheet u10542j u10542e user's manual ieu-907 u10200e special function register table u10134j m pd78075b subseries document name japanese document number english document number m pd78074b, 78075b data sheet u12017j u12017e user's manual to be prepared to be prepared special function register table to be prepared
m pd78075by subseries document name japanese document number english document number m pd78074by, 78075by data sheet to be prepared to be prepared user's manual to be prepared to be prepared special function register table to be prepared m pd78078 subseries document name japanese document number english document number m pd78076, 78078 data sheet u10167j u10167e m pd78p078 data sheet u10168j u10168e user's manual u10641j u10641e special function register table iem-5607 m pd78078y subseries document name japanese document number english document number m pd78076y, 78078y data sheet u10605j u10605e m pd78p078y data sheet u10606j u10606e user's manual u10641j u10641e special function register table u10257j m pd78083 subseries document name japanese document number english document number m pd78081, 78082 data sheet u11415j u11415e m pd78p083 data sheet u11006j u11006e user's manual u12176j u12176e special function register table iem-5599 m pd78098 subseries document name japanese document number english document number m pd78094, 78095, 78096, 78098a data sheet u10146j u10146e m pd78p098a data sheet u10203j u10203e user's manual ieu-854 ieu-1381 special function register table iem-5591
m pd780208 subseries document name japanese document number english document number m pd780204, 780205, 780206, 780208 data sheet u10436j ip-3540 m pd78p0208 data sheet u11295j ip-3475 user's manual u11302j u11302e special function register table u10997j m pd780001 document name japanese document number english document number m pd780001 data sheet u10324j u10324e user's manual u10885j u10885e special function register table to be prepared m pd780018y subseries document name japanese document number english document number m pd780016y, 780018y preliminary product information u11810j u11810e m pd78p0018y preliminary product information u11606j u11606e user's manual u11754j u11754e special function register table to be prepared m pd780024 subseries document name japanese document number english document number m pd780021, 780022, 780023, 780024 preliminary product information u12299j u12299e user's manual u12022j u12022e special function register table to be prepared m pd780024y subseries document name japanese document number english document number m pd780021y, 780022y, 780023y, 780024y preliminary product information u12165j u12165e user's manual u12022j u12022e special function register table to be prepared
m pd780034 subseries document name japanese document number english document number m pd780031, 780032, 780033, 780034 preliminary product information u12300j u12300e m pd78f0034 preliminary product information u11993j u11993e user's manual u12022j u12022e special function register table to be prepared m pd780034y subseries document name japanese document number english document number m pd780031y, 780032y, 780033y, 780034y preliminary product information u12166j u12166e m pd78f0034y preliminary product information u11994j u11994e user's manual u12022j u12022e special function register table to be prepared m pd780058 subseries document name japanese document number english document number m pd780053, 780054, 780055, 780056, 780058 preliminary product information u12182j u12182e m pd78f0058 preliminary product information u12092j u12092e user's manual u12013j u12013e special function register table to be prepared m pd780058y subseries document name japanese document number english document number m pd780053y, 780054y, 780055y, 780056y, 780058y preliminary product information to be prepared to be prepared m pd78f0058y preliminary product information u12324j u12324e user's manual u12013j u12013e special function register table to be prepared m pd780228 subseries document name japanese document number english document number m pd780226, 780228 preliminary product information u11797j u11797e m pd78f0228 preliminary product information u11971j u11971e user's manual u12012j u12012e special function register table to be prepared
m pd780308 subseries document name japanese document number english document number m pd780306, 780308 preliminary product information u12183j u12183e m pd78p0308 preliminary product information u11776j u11776e user's manual u11377j u11377e special function register table to be prepared m pd780308y subseries document name japanese document number english document number m pd780306y, 780308y preliminary product information to be prepared to be prepared m pd78p0308y preliminary product information u11832j u11832e user's manual u11377j u11377e special function register table to be prepared m pd78p0914 document name japanese document number english document number m pd78p0914 preliminary product information u10058j u10058e user's manual to be prepared to be prepared special function register table u10866j m pd780924 subseries document name japanese document number english document number m pd780921, 780922, 780923, 780924 preliminary product information u11804j u11804e m pd78f0924 preliminary product information u11930j u11930e user's manual u12071j u12071e special function register table u12230j m pd780964 subseries document name japanese document number english document number m pd780961, 780962, 780963, 780964 preliminary product information u11879j u11879e m pd78f0964 preliminary product information u11956j u11956e user's manual u12071j u12071e special function register table u12230j caution the above related documents are subject to change without notice. be sure to use the latest version when designing your system.
C i C contents chapter 1 memory space ........................................................................................................ ......... 1 1.1 memory spaces ............................................................................................................. ....... 1 1.2 internal program memory (internal rom) space .............................................................. 1 1.3 vector table area ......................................................................................................... ....... 5 1.4 callt instruction table area .......................................................................................... 10 1.5 callf instruction entry area .......................................................................................... 10 1.6 internal data memory (internal ram) space ................................................................... 10 1.7 special function register (sfr) area ............................................................................. 16 1.8 external memory space .................................................................................................... 1 6 1.9 iebus tm register area ( m pd78098 and 78098b subseries only) ................................... 19 chapter 2 register ............................................................................................................ .............. 21 2.1 control registers ......................................................................................................... ...... 21 2.1.1 program counter (pc) .................................................................................................... .......... 21 2.1.2 program status word (psw) ............................................................................................... .... 21 2.1.3 stack pointer (sp) ...................................................................................................... .............. 23 2.2 general registers ......................................................................................................... ..... 24 2.3 special-function register (sfr) ...................................................................................... 26 chapter 3 addressing .......................................................................................................... ........... 27 3.1 instruction address addressing ...................................................................................... 27 3.1.1 relative addressing ..................................................................................................... ............ 27 3.1.2 immediate addressing .................................................................................................... ......... 28 3.1.3 table indirect addressing ............................................................................................... ........ 29 3.1.4 register addressing ..................................................................................................... ........... 30 3.2 operand address addressing .......................................................................................... 31 3.2.1 implied addressing ...................................................................................................... ............ 31 3.2.2 register addressing ..................................................................................................... ........... 32 3.2.3 direct addressing ....................................................................................................... .............. 33 3.2.4 short direct addressing ................................................................................................. .......... 34 3.2.5 special-function register (sfr) addressing .......................................................................... 35 3.2.6 register indirect addressing ............................................................................................ ...... 36 3.2.7 based addressing ........................................................................................................ ............ 37 3.2.8 based indexed addressing ................................................................................................ ..... 38 3.2.9 stack addressing ........................................................................................................ ............. 39 chapter 4 instruction set ..................................................................................................... ....... 41 4.1 operation ................................................................................................................. ........... 42 4.1.1 operand identifiers and description methods ...................................................................... 42 4.1.2 description of operation column ....................................................................................... .43 4.1.3 description of flag operation column ................................................................................. 4 3 4.1.4 description of clock column ........................................................................................... .... 44 4.1.5 operation list .......................................................................................................... .................. 45 4.1.6 instructions listed by addressing type .................................................................................. 78
C ii C 4.2 instruction codes ......................................................................................................... ..... 82 4.2.1 description of instruction code table ................................................................................... .82 4.2.2 instruction code list ................................................................................................... .............. 83 chapter 5 explanation of instructions ................................................................................. 91 5.1 8-bit data transfer instructions ....................................................................................... 93 5.2 16-bit data transfer instructions ..................................................................................... 96 5.3 8-bit operation instructions ............................................................................................. 9 9 5.4 16-bit operation instructions ......................................................................................... 108 5.5 multiply/divide instructions ............................................................................................ 11 2 5.6 increment/decrement instructions ................................................................................. 115 5.7 rotate instructions ....................................................................................................... ... 120 5.8 bcd adjust instructions ................................................................................................. 12 7 5.9 bit manipulation instructions ......................................................................................... 130 5.10 call return instructions ................................................................................................ 1 38 5.11 stack manipulation instructions ................................................................................... 146 5.12 unconditional branch instruction ................................................................................ 150 5.13 conditional branch instructions .................................................................................. 152 5.14 cpu control instructions .............................................................................................. 161 appendix a revision history ................................................................................................... .... 169 appendix b instruction index (mnemonic: by function) ................................................. 171 appendix c instruction index (mnemonic: in alphabetical order) ........................... 173
list of figures figure no. title page 2-1 program counter configuration ............................................................................................... .............. 21 2-2 program status word configuration ........................................................................................... ........... 21 2-3 stack pointer configuration ................................................................................................. ................... 23 2-4 data to be saved to stack memory ............................................................................................ ............ 23 2-5 data to be reset from stack memory .......................................................................................... .......... 23 2-6 general register configuration .............................................................................................. ................ 25 C iii C list of tables table no. title page 1-1 internal rom space of 78k/0 series products ................................................................................. ......... 2 1-2 vector table ( m pd78002, 78002y, 78014, 78014y, 78014h, 78018f, 78018fy subseries and m pd780001) ...................................................................................................................... .......................... 5 1-3 vector table ( m pd78044f, 78044h, 780208 subseries) ........................................................................... 5 1-4 vector table ( m pd78054, 78054y, 78058f, 78058fy, 78075b, 78075by, 78078, 78078y subseries and m pd78070a, 78070ay) ............................................................................................................. .......... 6 1-5 vector table ( m pd78064, 78064y, 78064b, 780308, 780308y, 780058, 780058y subseries) ................ 6 1-6 vector table ( m pd78083 subseries) .......................................................................................................... 7 1-7 vector table ( m pd78098, 78098b subseries) ............................................................................................ 7 1-8 vector table ( m pd780018y subseries) ...................................................................................................... 8 1-9 vector table ( m pd780024, 780024y, 780034, 780034y subseries) ......................................................... 8 1-10 vector table ( m pd780228 subseries) ........................................................................................................ 8 1-11 vector table ( m pd78p0914) ..................................................................................................................... .. 9 1-12 vector table ( m pd780924, 780964 subseries) .......................................................................................... 9 1-13 internal ram space of 78k/0 series products ................................................................................ ......... 11 1-14 external memory space of 78k/0 series products ............................................................................. ...... 17 2-1 general register absolute address correspondence table .................................................................... 24 4-1 operand identifiers and description methods ................................................................................. ......... 42
[memo] C iv C
1 chapter 1 memory space chapter 1 memory space 1.1 memory spaces the 78k/0 series product program memory map varies depending on the internal memory capacity. for details of memory mapped address area, refer to each product users manual . 1.2 internal program memory (internal rom) space each 78k/0 series product has internal rom in the address space shown below. program and table data, etc. are stored in rom. normally, this memory space is addressed by the program counter (pc).
2 chapter 1 memory space table 1-1. internal rom space of 78k/0 series products (1/3) 8 kbytes 16 kbytes 24 kbytes 32 kbytes 40 kbytes 48 kbytes 60 kbytes 0000h-1fffh 0000h-3fffh 0000h-5fffh 0000h-7fffh 0000h-9fffh 0000h-bfffh 0000h-efffh m pd78002 m pd78001b m pd78002b subseries m pd78002y m pd78001by m pd78002by subseries m pd78014 m pd78011b m pd78012b m pd78013 m pd78014, subseries m pd78p014 m pd78014y m pd78011by m pd78012by m pd78013y m pd78014y, subseries m pd78p014y m pd78014h m pd78011h m pd78012h m pd78013h m pd78014h subseries m pd78018f m pd78011f m pd78012f m pd78013f m pd78014f m pd78015f m pd78016f m pd78018f, subseries m pd78p018f m pd78018fy m pd78011fy m pd78012fy m pd78013fy m pd78014fy m pd78015fy m pd78016fy m pd78018fy, subseries m pd78p018fy m pd78044f m pd78042f m pd78043f m pd78044f m pd78045f m pd78p048a subseries m pd78044h m pd78044h m pd78045h m pd78046h m pd78p048b subseries m pd78054 m pd78052 m pd78053 m pd78054, m pd78055 m pd78056 m pd78058, subseries m pd78p054 m pd78p058 m pd78054y m pd78052y m pd78053y m pd78054y, m pd78055y m pd78056y m pd78058y, subseries m pd78p054y m pd78p058y m pd78058f m pd78056f m pd78058f, subseries m pd78p058f m pd78058fy m pd78056fy m pd78058fy, subseries m pd78p058fy m pd78064 m pd78062 m pd78063 m pd78064, subseries m pd78p064 m pd78064y m pd78062y m pd78063y m pd78064y, subseries m pd78p064y m pd78064b m pd78064b, subseries m pd78p064b remarks 1. the m pd78070a and 78070ay do not incorporate roms. 2. the internal rom capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims). subseries name capacity address space
3 chapter 1 memory space table 1-1. internal rom space of 78k/0 series products (2/3) 8 kbytes 16 kbytes 24 kbytes 32 kbytes 40 kbytes 48 kbytes 60 kbytes 0000h-1fffh 0000h-3fffh 0000h-5fffh 0000h-7fffh 0000h-9fffh 0000h-bfffh 0000h-efffh m pd78075b m pd78074b m pd78075b subseries m pd78075by m pd78074by m pd78075by subseries m pd78078 m pd78076 m pd78078, subseries m pd78p078 m pd78078y m pd78076y m pd78078y, subseries m pd78p078y m pd78083 m pd78081 m pd78082 m pd78p083 subseries m pd78098 m pd78094 m pd78095 m pd78096 m pd78098a, subseries m pd78p098a m pd78098b m PD78095B m pd78096b m pd78098b, subseries m pd78p098b m pd780001 m pd780001 m pd780018y m pd780016y m pd780018y, subseries m pd78p0018y m pd780024 m pd780021 m pd780022 m pd780023 m pd780024 subseries m pd780024y m pd780021y m pd780022y m pd780023y m pd780024y subseries m pd780034 m pd780031 m pd780032 m pd780033 m pd780034, subseries m pd78f0034 m pd780034y m pd780031y m pd780032y m pd780033y m pd780034y, subseries m pd78f0034y m pd780058 m pd780053 m pd780054 m pd780055 m pd780056 m pd780058, subseries m pd78f0058 m pd780058y m pd780053y m pd780054y m pd780055y m pd780056y m pd780058y, subseries m pd78f0058y m pd780208 m pd780204 m pd780205 m pd780206 m pd780208, subseries m pd78p0208 remark the internal rom capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims). subseries name capacity address space
4 chapter 1 memory space table 1-1. internal rom space of 78k/0 series products (3/3) 8 kbytes 16 kbytes 24 kbytes 32 kbytes 40 kbytes 48 kbytes 60 kbytes 0000h-1fffh 0000h-3fffh 0000h-5fffh 0000h-7fffh 0000h-9fffh 0000h-bfffh 0000h-efffh m pd780228 m pd780226 m pd780228, subseries m pd78f0228 m pd780308 m pd780306 m pd780308, subseries m pd78p0308 m pd780308y m pd780306y m pd780308y, subseries m pd78p0308y m pd78p0914 m pd78p0914 m pd780924 m pd780921 m pd780922 m pd780923 m pd780924, subseries m pd78f0924 m pd780964 m pd780961 m pd780962 m pd780963 m pd780964, subseries m pd78f0964 remark the internal rom capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims). subseries name capacity address space
5 chapter 1 memory space 1.3 vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16- bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. table 1-2. vector table ( m pd78002, 78002y, 78014, 78014y, 78014h, 78018f, 78018fy subseries and m pd780001) vector table address interrupt request vector table address interrupt request 0000h reset input 0010h intcsi1 note 2 0004h intwdt 0012h inttm3 0006h intp0 note 1 0014h inttm0 note 1, 2 0008h intp1 0016h inttm1 000ah intp2 0018h inttm2 000ch intp3 001ah intad note 2 000eh intcsi0 note 1 003eh brk instruction notes 1. excluding m pd780001 2. excluding m pd78002 and 78002y subseries table 1-3. vector table ( m pd78044f, 78044h, 780208 subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 0010h intcsi1 0004h intwdt 0012h inttm3 0006h intp0 0014h inttm0 0008h intp1 0016h inttm1 000ah intp2 0018h inttm2 000ch intp3/intud note 001ah intad 000eh intcsi0 note 001ch intks 003eh brk instruction note the m pd78044h subseries contain neither intud nor intcsi0.
6 chapter 1 memory space table 1-4. vector table ( m pd78054, 78054y, 78058f, 78058fy, 78075b, 78075by, 78078, 78078y subseries and m pd78070a, 78070ay) vector table address interrupt request vector table address interrupt request 0000h reset input 001ah intsr/intcsi2 0004h intwdt 001ch intst 0006h intp0 001eh inttm3 0008h intp1 0020h inttm00 000ah intp2 0022h inttm01 000ch intp3 0024h inttm1 000eh intp4 0026h inttm2 0010h intp5 0028h intad 0012h intp6 002ah inttm5 note 0014h intcsi0 002ch inttm6 note 0016h intcsi1 003eh brk instruction 0018h intser note only the m pd78075b, 78075by, 78078, and 78078y subseries table 1-5. vector table ( m pd78064, 78064y, 78064b, 780308, 780308y, 780058, 780058y subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 001ah intsr/intcsi2 0004h intwdt 001ch intst 0006h intp0 001eh inttm3 0008h intp1 0020h inttm00 000ah intp2 0022h inttm01 000ch intp3 0024h inttm1 000eh intp4 0026h inttm2 0010h intp5 0028h intad 0014h intcsi0 002ah intcsi1 note 2 0016h intcsi1 note 1 003eh brk instruction 0018h intser notes 1. only the m pd780058 and 780058y subseries 2. only the m pd780308 and 780308y subseries
7 chapter 1 memory space table 1-6. vector table ( m pd78083 subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 001ah intsr/intcsi2 0004h intwdt 001ch intst 0008h intp1 0028h intad 000ah intp2 002ah inttm5 000ch intp3 002ch inttm6 0018h intser 003eh brk instruction table 1-7. vector table ( m pd78098, 78098b subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 0018h intser 0004h intwdt 001ah intsr/intcsi2 0006h intp0 001ch intst 0008h intp1 001eh inttm3 000ah intp2 0020h inttm00 000ch intp3 0022h inttm01 000eh intp4 0024h inttm1 0010h intp5 0026h inttm2 0012h intp6 0028h intad 0014h intcsi0 002ah intie 0016h intcsi1 003eh brk instruction
8 chapter 1 memory space table 1-8. vector table ( m pd780018y subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 0020h inttm00 0004h intwdt 0022h inttm01 0006h intp0 0024h inttm1 0008h intp1 0026h inttm2 000ah intp2 0028h intad 000ch intp3 002ah inttm5 000eh intp4 002ch inttm6 0010h intp5 002eh intcsi4 0012h intp6 0030h intiic 0016h intcsi1 003eh brk instruction 001eh inttm3 table 1-9. vector table ( m pd780024, 780024y, 780034, 780034y subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 0018h intiic0 note2 0004h intwdt 001ah intwti 0006h intp0 001ch inttm00 0008h intp1 001eh inttm01 000ah intp2 0020h inttm50 000ch intp3 0022h inttm51 000eh intser0 0024h intad0 0010h intsr0 0026h intwt 0012h intst0 0028h intkr 0014h intcsi30 003eh brk instruction 0016h intcsi31 note 1 notes 1. only the m pd780024 and 780034 subseries 2. only the m pd780024y and 780034y subseries table 1-10. vector table ( m pd780228 subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 000eh intks 0004h intwdt 0010h intcsi3 0006h intp0 0012h inttm50 0008h intp1 0014h inttm51 000ah inttm10 0016h intad 000ch inttm11 003eh brk instruction
9 chapter 1 memory space table 1-11. vector table ( m pd78p0914) vector table address interrupt request vector table address interrupt request 0000h reset input 0012h inths 0004h intwdt 0014h inttm6 0006h intvs 0016h inttm7 0008h intp1 0018h inttm8 000ah intp2 001ah intcsi0 000ch inttm5 001ch intcsi1 000eh inttm1 001eh intad 0010h inttm2 003eh brk instruction table 1-12. vector table ( m pd780924, 780964 subseries) vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intst0 0004h intwdt 0016h intser1 0006h intp0 0018h intsr1 0008h intp1 001ah intst1 000ah intp2 001ch inttm50 000ch intp3 001eh inttm51 000eh inttm7 0020h inttm52 0010h intser0 0022h intad0 0012h intsr0 003eh brk instruction
10 chapter 1 memory space 1.4 callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). 1.5 callf instruction entry area the 2048-byte area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 1.6 internal data memory (internal ram) space the 78k/0 series products incorporate the following rams. for the rams incorporated in each product, see table 1-13 internal ram space of 78k/0 series products . (1) internal high-speed ram each 78k/0 series product incorporates an internal high-speed ram in the address space shown in table 1-13. in the 32-byte area fee0h to feffh of these areas, 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated. the internal high-speed ram can also be used as a stack memory. (2) buffer ram a buffer ram is allocated to each area shown in table 1-13. this ram is used to store the transfer/receive data of the serial interface channel 1 (3-wired serial i/o mode with automatic transfer/receive function). if not used in this mode, the buffer ram can also be used as an ordinary ram area. (3) ram for fip tm display a ram for fip display is allocated to each area shown in table 1-13. this ram can also be used as a normal ram. (4) internal expansion ram an internal expansion ram is allocated to each area shown in table 1-13. (5) ram for lcd display a ram for lcd display is allocated to each area shown in table 1-13. this ram can also be used as a normal ram.
11 chapter 1 memory space table 1-13. internal ram space of 78k/0 series products (1/5) subseries name products high-speed ram buffer ram extended ram ram for fip display ram for lcd display m pd78002 m pd78001b fe00h to feffh CCCC subseries (256 bytes) m pd78002b fd80h to feffh (384 bytes) m pd78002y m pd78001by fe00h to feffh CCCC subseries (256 bytes) m pd78002by fd80h to feffh (384 bytes) m pd78014 m pd78011b fd00h to feffh fac0h to fadfh CCC subseries m pd78012b (512 bytes) (32 bytes) m pd78013 fb00h to feffh m pd78014 (1024 bytes) m pd78p014 m pd78014y m pd78011by fd00h to feffh fac0h to fadfh CCC subseries m pd78012by (512 bytes) (32 bytes) m pd78013y fb00h to feffh m pd78014y (1024 bytes) m pd78p014y m pd78014h m pd78011h fd00h to feffh fac0h to fadfh CCC subseries m pd78012h (512 bytes) (32 bytes) m pd78013h fb00h to feffh m pd78014h (1024 bytes) m pd78018f m pd78011f fd00h to feffh fac0h to fadfh CCC subseries m pd78012f (512 bytes) (32 bytes) m pd78013f fb00h to feffh m pd78014f (1024 bytes) m pd78015f f600h to f7ffh m pd78016f (512 bytes) m pd78018f f400h to f7ffh m pd78p018f (1024 bytes) m pd78018fy m pd78011fy fd00h to feffh fac0h to fadfh CCC subseries m pd78012fy (512 bytes) (32 bytes) m pd78013fy fb00h to feffh m pd78014fy (1024 bytes) m pd78015fy f600h to f7ffh m pd78016fy (512 bytes) m pd78018fy f400h to f7ffh m pd78p018fy (1024 bytes) remark the internal high-speed ram capacity and expansion ram capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims) and internal expansion ram size switching register (ixs).
12 chapter 1 memory space table 1-13. internal ram space of 78k/0 series products (2/5) subseries name products high-speed ram buffer ram extended ram ram for fip display ram for lcd display m pd78044f m pd78042f fd00h to feffh fac0h to faffh C fa50h to fa7fh C subseries m pd78043f (512 bytes) (64 bytes) (48 bytes) m pd78044f fb00h to feffh m pd78045f (1024 bytes) m pd78p048a f400h to f7ffh (1024 bytes) m pd78044h m pd78044h fb00h to feffh CC fa50h to fa7fh C subseries m pd78045h (1024 bytes) (48 bytes) m pd78046h m pd78p048b f400h to f7ffh (1024 bytes) m pd78054 m pd78052 fd00h to feffh fac0h to fadfh CCC subseries (512 bytes) (32 bytes) m pd78053 fb00h to feffh m pd78054 (1024 bytes) m pd78p054 m pd78055 m pd78056 m pd78058 f400h to f7ffh m pd78p058 (1024 bytes) m pd78054y m pd78052y fd00h to feffh fac0h to fadfh CCC subseries m pd78053y (512 bytes) (32 bytes) m pd78054y fb00h to feffh m pd78055y (1024 bytes) m pd78056y m pd78058y f400h to f7ffh m pd78p058y (1024 bytes) m pd78058f m pd78056f fb00h to feffh fac0h to fadfh CCC subseries m pd78058f (1024 bytes) (32 bytes) m pd78p058f f400h to f7ffh (1024 bytes) m pd78058fy m pd78056fy fb00h to feffh fac0h to fadfh CCC subseries m pd78058fy (1024 bytes) (32 bytes) m pd78p058fy f400h to f7ffh (1024 bytes) remark the internal high-speed ram capacity and expansion ram capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims) and internal expansion ram size switching register (ixs).
13 chapter 1 memory space table 1-13. internal ram space of 78k/0 series products (3/5) subseries name products high-speed ram buffer ram extended ram ram for fip display ram for lcd display m pd78064 m pd78062 fd00h to feffh CCC fa58h to fa7fh subseries (512 bytes) (40 x 4 bits) m pd78063 fb00h to feffh m pd78064 (1024 bytes) m pd78p064 m pd78064y m pd78062y fd00h to feffh CCC fa58h to fa7fh subseries (512 bytes) (40 x 4 bits) m pd78063y fb00h to feffh m pd78064y (1024 bytes) m pd78p064y m pd78064b m pd78064b fb00h to feffh CCC fa58h to fa7fh subseries m pd78p064b (1024 bytes) (40 x 4 bits) m pd78070a m pd78070a fb00h to feffh fac0h to fadfh CCC m pd78070ay m pd78070ay (1024 bytes) (32 bytes) m pd78075b m pd78074b fb00h to feffh fac0h to fadfh CCC subseries m pd78075b (1024 bytes) (32 bytres) m pd78075by m pd78074by fb00h to feffh fac0h to fadfh CCC subseries m pd78075by (1024 bytes) (32 bytes) m pd78078 m pd78076 fb00h to feffh fac0h to fadfh f400h to f7ffh CC subseries m pd78078 (1024 bytes) (32 bytes) (1024 bytes) m pd78p078 m pd78078y m pd78076y fb00h to feffh fac0h to fadfh f400h to f7ffh CC subseries m pd78078y (1024 bytes) (32 bytes) (1024 bytes) m pd78p078y m pd78083 m pd78081 fe00h to feffh fac0h to fadfh CCC subseries (256 bytes) (32 bytes) m pd78082 fd80h to feffh (384 bytes) m pd78p083 fd00h to feffh (512 bytes) m pd78098 m pd78094 fb00h to feffh fac0h to fadfh CCC subseries m pd78095 (1024 bytes) (32 bytes) m pd78096 m pd78098a f000h to f7ffh m pd78p098a (2048 bytes) remark the internal high-speed ram capacity and expansion ram capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims) and internal expansion ram size switching register (ixs).
14 chapter 1 memory space table 1-13. internal ram space of 78k/0 series products (4/5) subseries name products high-speed ram buffer ram extended ram ram for fip display ram for lcd display m pd78098b m PD78095B fb00h to feffh fac0h to fadfh CCC subseries m pd78096b (1024 bytes) (32 bytes) m pd78098b f000h to f7ffh m pd78p098b (2048 bytes) m pd780001 m pd780001 fe40h to feffh CCCC (192 bytes) m pd780018y m pd780016y fb00h to feffh fac0h to fadfh f400h to f7ffh CC subseries m pd780018y (1024 bytes) (32 bytes) (1024 bytes) m pd78p0018y m pd780024 m pd780021 fd00h to feffh fac0h to fadfh CCC subseries m pd780022 (512 bytes) (32 bytes) m pd780023 fb00h to feffh m pd780024 (1024 bytes) m pd780024y m pd780021y fd00h to feffh fac0h to fadfh CCC subseries m pd780022y (512 bytes) (32 bytes) m pd780023y fb00h to feffh m pd780024y (1024 bytes) m pd780034 m pd780031 fd00h to feffh fac0h to fadfh CCC subseries m pd780032 (512 bytes) (32 bytes) m pd780033 fb00h to feffh m pd780034 (1024 bytes) m pd78f0034 m pd780034y m pd780031y fd00h to feffh fac0h to fadfh CCC subseries m pd780032y (512 bytes) (32 bytes) m pd780033y fb00h to feffh m pd780034y (1024 bytes) m pd78f0034y m pd780058 m pd780053 fb00h to feffh fac0h to fadfh CCC subseries m pd780054 (1024 bytes) (32 bytes) m pd780055 m pd780056 m pd780058 f400h to f7ffh m pd78f0058 (1024 bytes) remark the internal high-speed ram capacity and expansion ram capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims) and internal expansion ram size switching register (ixs).
15 chapter 1 memory space table 1-13. internal ram space of 78k/0 series products (5/5) subseries name products high-speed ram buffer ram extended ram ram for fip display ram for lcd display m pd780058y m pd780053y fb00h to feffh fac0h to fadfh CCC subseries m pd780054y (1024 bytes) (32 bytes) m pd780055y m pd780056y m pd780058y f400h to f7ffh m pd78f0058y (1024 bytes) m pd780208 m pd780204 fb00h to feffh fac0h to fadfh C fa30h to fa7fh C subseries m pd780205 (1024 bytes) (64 bytes) (80 bytes) m pd780206 m pd780208 f000h to f7ffh m pd78f0208 (2048 bytes) m pd780228 m pd780226 fb00h to feffh C f600h to f7ffh fa00h to fa5fh C subseries m pd780228 (1024 bytes) (512 bytes) (96 bytes) m pd78f0228 m pd780308 m pd780306 fb00h to feffh C f400h to f7ffh C fa58h to fa7fh subseries m pd780308 (1024 bytes) (1024 bytes) (40 4 bits) m pd78p0308 m pd780308y m pd780306y fb00h to feffh C f400h to f7ffh C fa58h to fa7fh subseries m pd780308y (1024 bytes) (1024 bytes) (40 4 bits) m pd78p0308y m pd78p0914 m pd78p0914 fd00h to feffh CCCC (512 bytes) m pd780924 m pd780921 fd00h to feffh CCCC subseries m pd780922 (512 bytes) m pd780923 fb00h to feffh m pd780924 (1024 bytes) m pd78f0924 m pd780964 m pd780961 fd00h to feffh CCCC subseries m pd780962 (512 bytes) m pd780963 fb00h to feffh m pd780964 (1024 bytes) m pd78f0964 remark the internal high-speed ram capacity and expansion ram capacity of prom versions can be changed by manipulating the value of the memory size switching register (ims) and internal expansion ram size switching register (ixs).
16 chapter 1 memory space 1.7 special function register (sfr) area an on-chip peripheral hardware special-function register (sfr) is allocated in the area ff00h to ffffh. (refer to each product users manual ). caution do not access addresses where the sfr is not assigned. if the address is carelessly accessed, the cpu may be deadlocked. 1.8 external memory space this is an external memory space which can be accessed by setting the memory extension mode register. this space allows program and table data storage, and peripheral device assignment. for products for which an external memory space can be used, refer to table 1-14 external memory space of 78k/0 series products .
17 chapter 1 memory space table 1-14. external memory space of 78k/0 series products (1/3) subseries name products address (capacity) m pd78002, 78002y subseries m pd78001b, 78001by 2000h to fa7fh (55936 bytes) m pd78002b, 78002by 4000h to fa7fh (47744 bytes) m pd78p014, 78p014y note 1 f000h to f3ffh (1024 bytes) m pd78014, 78014y subseries m pd78011b, 78011by 2000h to fa7fh (55936 bytes) m pd78012b, 78012by 4000h to fa7fh (47744 bytes) m pd78013, 78013y 6000h to fa7fh (39552 bytes) m pd78014, 78014y 8000h to fa7fh (31360 bytes) m pd78p014, 78p014y note 1 f000h to f3ffh (1024 bytes) m pd78014h subseries m pd78011h 2000h to fa7fh (55936 bytes) m pd78012h 4000h to fa7fh (47744 bytes) m pd78013h 6000h to fa7fh (39552 bytes) m pd78014h 8000h to fa7fh (31360 bytes) m pd78p018f notes 1, 2 f000h to f3ffh (1024 bytes) m pd78018f, 78018fy m pd78011f, 78011fy 2000h to fa7fh (55936 bytes) subseries m pd78012f, 78012fy 4000h to fa7fh (47744 bytes) m pd78013f, 78013fy 6000h to fa7fh (39552 bytes) m pd78014f, 78014fy 8000h to fa7fh (31360 bytes) m pd78015f, 78015fy a000h to f5ffh (22016 bytes) m pd78016f, 78016fy c000h to f5ffh (13824 bytes) m pd78018f, 78018fy note 2 f000h to f3ffh (1024 bytes) m pd78p018f, 78p018fy notes 1, 2 f000h to f3ffh (1024 bytes) m pd78054, 78054y subseries m pd78052, 78052y 4000h to fa7fh (47744 bytes) m pd78053, 78053y 6000h to fa7fh (39552 bytes) m pd78054, 78054y 8000h to fa7fh (31360 bytes) m pd78p054, 78p054y note 1 8000h to fa7fh (31360 bytes) m pd78055, 78055y a000h to fa7fh (23168 bytes) m pd78056, 78056y c000h to fa7fh (14976 bytes) m pd78058, 78058y note 2 f000h to f3ffh (1024 bytes) m pd78p058, 78p058y notes 1, 2 f000h to f3ffh (1024 bytes) m pd78058f, 78058fy m pd78056f, 78056fy c000h to fa7fh (14976 bytes) subseries m pd78058f, 78058fy note 2 f000h to f3ffh (1024 bytes) m pd78p058f, 78p058fy notes 1, 2 f000h to f3ffh (1024 bytes) m pd78070a, 78070ay m pd78070a, 78070ay 0000h to fa7fh (64128 bytes) notes 1. the external memory capacity of prom and flash memory versions can be changed by using the memory size switching register (ims). 2. when an internal rom is set to 60 kbytes, the area of f000h to f3ffh is not available. setting the internal rom to 56 kbytes or less enables the area of f000h to f3ffh to be used as an external memory.
18 chapter 1 memory space table 1-14. external memory space of 78k/0 series products (2/3) subseries name products address (capacity) m pd78075b, 78075by m pd78074b, 78074by 8000h to fa7fh (31360 bytes) subseries m pd78075b, 78075by a000h to fa7fh (23168 bytes) m pd78p078, 78p078y notes 1, 2 f000h to f3ffh (1024 bytes) m pd78078, 78078y subseries m pd78076, 78076y c000h to fa7fh (13312 bytes) m pd78078, 78078y note 2 f000h to f3ffh (1024 bytes) m pd78p078, 78p078y notes 1, 2 f000h to f3ffh (1024 bytes) m pd78098 subseries m pd78094 8000h to efffh (28672 bytes) m pd78095 a000h to efffh (20480 bytes) m pd78096 c000h to efffh (12288 bytes) m pd78098a note 3 e000h to efffh (4096 bytes) m pd78p098a notes 1, 3 e000h to efffh (4096 bytes) m pd78098b subseries m PD78095B a000h to efffh (20480 bytes) m pd78096b c000h to efffh (12288 bytes) m pd78098b note 3 e000h to efffh (4096 bytes) m pd78p098b notes 1, 3 e000h to efffh (4096 bytes) m pd780018y subseries m pd780016y c000h to fa7fh (13312 bytes) m pd780018y note 2 f000h to f3ffh (1024 bytes) m pd78p0018y notes 1, 2 f000h to f3ffh (1024 bytes) m pd780024, 780024y subseries m pd780021, 780021y 2000h to f7ffh (55296 bytes) m pd780022, 780022y 4000h to f7ffh (47104 bytes) m pd780023, 780023y 6000h to f7ffh (38912 bytes) m pd780024, 780024y 8000h to f7ffh (30720 bytes) m pd78f0034, 78f0034y note 1 8000h to f7ffh (30720 bytes) m pd780034, 780034y subseries m pd780031, 780031y 2000h to f7ffh (55296 bytes) m pd780032, 780032y 4000h to f7ffh (47104 bytes) m pd780033, 780033y 6000h to f7ffh (38912 bytes) m pd780034, 780034y 8000h to f7ffh (30720 bytes) m pd78f0034, 78f0034y note 1 8000h to f7ffh (30720 bytes) notes 1. the external memory capacity of prom and flash memory versions can be changed by using the memory size switching register (ims). 2. when an internal rom is set to 60 kbytes, the area of f000h to f3ffh is not available. setting the internal rom to 56 kbytes or less (or to 48 kbytes only for the m pd78p0018y) enables the area of f000h to f3ffh to be used as an external memory. 3. when an internal rom is set to 60 kbytes, the area of e000h to efffh is not available. by setting the internal rom to 56 kbytes or less, the internal rom can be used as an external memory within the range of the last address to efffh.
19 chapter 1 memory space table 1-14. external memory space of 78k/0 series products (3/3) subseries name products address (capacity) m pd780058, 780058y m pd780053, 780053y 6000h to fa7fh (39552 bytes) subseries m pd780054, 780054y 8000h to fa7fh (31360 bytes) m pd780055, 780055y a000h to fa7fh (23168 bytes) m pd780056, 780056y c000h to fa7fh (14976 bytes) m pd780058, 780058y note 2 f000h to f3ffh (1024 bytes) m pd78f0058, 78f0058y note 1 f000h to f3ffh (1024 bytes) m pd78p0914 m pd78p0914 note 1 8000h to f7ffh (30720 bytes) m pd780924 subseries m pd780921 6000h to fa7fh (55296 bytes) m pd780922 8000h to fa7fh (47104 bytes) m pd780923 a000h to fa7fh (38912 bytes) m pd780924 c000h to fa7fh (30720 bytes) m pd78f0924 note 1 f000h to f3ffh (30720 bytes) m pd780964 subseries m pd780961 6000h to fa7fh (55296 bytes) m pd780962 8000h to fa7fh (47104 bytes) m pd780963 a000h to fa7fh (38912 bytes) m pd780964 c000h to fa7fh (30720 bytes) m pd78f0964 note 1 f000h to f3ffh (30720 bytes) notes 1. the external memory capacity of prom and flash memory versions can be changed by using the memory size switching register (ims). 2. when an internal rom is set to 60 kbytes, the area of f000h to f3ffh is not available. setting the internal rom to 56 kbytes or less enables the area of f000h to f3ffh to be used as an external memory. 1.9 iebus tm register area ( m pd78098 and 78098b subseries only) iebus registers that are used to control the iebus controller are allocated to the area of f8e0h to f8ffh.
20 chapter 1 memory space [memo]
21 chapter 2 register chapter 2 register 2.1 control registers the control registers control the program sequence, statuses and stack memory. a program counter, a program status word and a stack pointer are control registers. 2.1.1 program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 2-1. program counter configuration 2.1.2 program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 2-2. program status word configuration 15 0 pc 70 ie z rbs1 ac rbs0 0 isp cy
22 chapter 2 register (1) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of cpu. when ie = 0, the ie is set to interrupt disable (di), and interrupts other than non-maskable interrupts are all disabled. when ie = 1, the ie is set to interrupt enable (ei), and an interrupt request acknowledge is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. this flag is reset (0) upon the di instruction execution or interrupt request acknowledgment and is set (1) upon execution of the ei instruction. (2) zero flag (z) when the operation result is zero, this flag is set to (1). it is reset to (0) in all other cases. (3) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sbl rbn instruction execution is stored. (4) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). it is reset to (0) in all other cases. (5) in-service priority flag (isp) this flag manages the priority of acknowledgeable, maskable vectored interrupts. when isp = 0, vectored interrupt requests specified to the low level with the priority specification flag register (pr) are disabled for acknowledgment. actual acknowledgment for interrupt requests is controlled by the state of the interrupt enable flag (ie). (6) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
23 chapter 2 register 2.1.3 stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 2-3. stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 2-4 and 2-5. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 2-4. data to be saved to stack memory figure 2-5. data to be reset from stack memory 15 0 sp interrupt and brk instructions psw pc15-pc8 pc15-pc8 pc7-pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callf and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7-pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs reti and retb instructions psw pc15-pc8 pc15-pc8 pc7-pc0 lower half register pairs ret instruction pop rp instruction sp pc7-pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
24 chapter 2 register 2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l and h). in addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16- bit register (ax, bc, de and hl). they can be described in terms of functional names (x, a, c, b, e, d, l, h, ax, bc, de and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. table 2-1. general register absolute address correspondence table register register bank name functional absolute absolute address bank name functional absolute absolute address name name name name bank0 h r7 feffh bank2 h r7 feefh l r6 fefeh l r6 feeeh d r5 fefdh d r5 feedh e r4 fefch e r4 feech b r3 fefbh b r3 feebh c r2 fefah c r2 feeah a r1 fef9h a r1 fee9h x r0 fef8h x r0 fee8h bank1 h r7 fef7h bank3 h r7 fee7h l r6 fef6h l r6 fee6h d r5 fef5h d r5 fee5h e r4 fef4h e r4 fee4h b r3 fef3h b r3 fee3h c r2 fef2h c r2 fee2h a r1 fef1h a r1 fee1h x r0 fef0h x r0 fee0h
25 chapter 2 register figure 2-6. general register configuration (a) absolute names (b) functional names bank0 bank1 bank2 bank3 feffh fee0h r0 15 0 7 0 16-bit processing 8-bit processing fee7h rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 fee8h feefh fef0h fef7h fef8h bank0 bank1 bank2 bank3 feffh fee0h x 15 0 7 0 16-bit processing 8-bit processing fee7h hl de bc ax a c b e d l h fee8h feefh fef0h fef7h fef8h
26 chapter 2 register 2.3 special-function register (sfr) unlike a general register, each special-function register has a special function. it is allocated in the 256-byte area ff00h to ffffh. the special-function register can be manipulated, like the general register, with the operation, transfer and bit manipulation instructions. manipulatable bit units (1, 8, and 16) differ depending on the special-function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. with the special function register, refer to each product users manual . caution do not access addresses where the sfr is not assigned. if the address is carelessly accessed, the cpu may be deadlocked.
27 chapter 3 addressing chapter 3 addressing 3.1 instruction address addressing an instruction address is determined by program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of each instruction, refer to chapter 5 explanation of instructions ). 3.1.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. in other words, in relative addressing, the value is relatively transferred to the range between C128 and +127 from the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 87 6 a jdisp8 when s = 0, a indicates all bits "0". when s = 1, a indicates all bits "1". ... pc is the start address of the next instruction of a br instruction.
28 chapter 3 addressing 3.1.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. the call !addr16 and br !addr16 instructions can be branched to all memory spaces. the callf !addr11 instruction is branched to the area of 0800h to 0fffh. [illustration] in case of call !addr16, br !addr16 instruction in case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10? 11 10 00001 643 callf fa 7?
29 chapter 3 addressing 3.1.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by the low-order-5- bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) and branched. when the callt [addr5] instruction is executed, a table indirect addressing is performed. executing this instruction enables the value to be branched to all memory spaces referencing the address stored to the memory table of 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4? instruction code
30 chapter 3 addressing 3.1.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
31 chapter 3 addressing 3.2 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.2.1 implied addressing [function] this addressing automatically specifies to an address the register which functions as an accumulator (a and ax) in the general register. of the 78k/0 series instruction words, the following instructions employ implied addressings. instruction register to be specified by implied addressing mulu note a register for multiplicand and ax register for product storage divuw note ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction ror4/rol4 a register for storage of digit data which undergoes digit rotation note the m pd78002/78002y subseries have no mulu/divuw instructions. [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
32 chapter 3 addressing 3.2.2 register addressing [function] register addressing accesses the general-purpose register as an operand. the general-purpose register to be accessed is specified by the register bank selection flags (rbs0 and rbs1) and the register specification codes (rn and rpn) among instruction codes. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 1 100010 incw de; when selecting the de register pair for rp instruction code 1 0 000100 register specification code register specification code
33 chapter 3 addressing 3.2.3 direct addressing [function] direct addressing directly addresses the memory indicated by the immediate data in the instruction word. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h [illustration] instruction code 1 0 0 0 1110op code 0000000000h 11111110feh memory 0 7 op code addr16 (lower) addr16 (upper)
34 chapter 3 addressing 3.2.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte fixed space fe20h to ff1fh. an internal high-speed ram and a special-function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the entire sfr area. ports which are frequently accessed in a program, a compare register of the timer/event counter and a capture register of the timer/event counter are mapped in the area ff00h through ff1fh, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe30h, #50h; when setting saddr to fe30h and the immediate data to 50h [illustration] instruction code 00010001op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a when 8-bit immediate data is 20h to ffh, a = 0. when 8-bit immediate data is 00h to 1fh, a = 1.
35 chapter 3 addressing 3.2.5 special-function register (sfr) addressing [function] the memory-mapped special-function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) [description example] mov pm0, a; when selecting pm0 for sfr [illustration] instruction code 11110110op code 00100000 20h (sfr-offset) 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
36 chapter 3 addressing 3.2.6 register indirect addressing [function] the register indirect addressing addresses memory with register pair contents specified as an operand. the register pair to be accessed is specified by the register bank selection flags (rbs0 and rbs1) and the register pair specification in instruction codes. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 1 0 000101 [illustration] 15 0 8 d 7 e 0 7 7 0 a de memory memory address specified with register pair de contents of memory to be addressed are transferred
37 chapter 3 addressing 3.2.7 based addressing [function] 8-bit immediate data is added to the contents of the hl register pair as a base register and the sum is used to address the memory. the hl register pair to be accessed is in the register bank specified with the register bank select flag (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 10101110 00010000
38 chapter 3 addressing 3.2.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the hl register pair as a base register and the sum is used to address the memory. the hl, b, and c registers to be accessed are registers in the register bank specified with the register bank select flag (rbs0 to rbs1). addition is performed by expanding the b or c register as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl+b], [hl+c] [description example] in the case of mov a, [hl+b] instruction code 1 0 101011
39 chapter 3 addressing 3.2.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de instruction code 10110101
40 chapter 3 addressing [memo]
41 chapter 4 instruction set chapter 4 instruction set this chapter covers the list of 78k/0 series instruction set. the instructions are common to all the 78k/0 series products.
42 chapter 4 instruction set 4.1 operation 4.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and are described as they are. each symbol has the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 4-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbols (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even addresses only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note ffd0h to ffdfh are not addressable. remark refer to each product users manual for symbols of special function registers.
43 chapter 4 instruction set 4.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : flag indicating non-maskable interrupt servicing in progress ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) v : logical sum (or) v : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 4.1.3 description of flag operation column (blank) : unchanged 0 : cleared to 0 1 : set to 1 : set/cleared according to the result r : previously saved value is restored v
44 chapter 4 instruction set 4.1.4 description of clock column the number of clock cycles during instruction execution is outlined as follows. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). (1) classification of clock column the number of instruction clocks differs in the following two cases. <1> when the internal high-speed ram area is accessed, or in the instruction with no data access <2> when an area except the internal high-speed ram area is accessed (2) when n or m is written in clock column n indicates the number of waits when external memory expansion area is read. m indicates the number of waits when external memory expansion area is written to. (3) number of clocks if program is stored in external rom <1> when no wait cycle is inserted the number of clocks is the same as when the program is stored in the internal rom area. <2> when wait cycle is inserted the number of clocks differs depending on the product. there are the following three product groups classified according to the number of clocks. ? with m pd78002, 78002y, 78014, 78014y, 78014h, 78018f, 78018fy, 78p0914 subseries the number of clocks increases by the number of bytes number of wait cycles 2 , as compared with when the program is stored in the internal rom area. ? m pd78054, 78054y, 78058f, 78058fy, 78075b, 78075by, 78078, 78078y, 78098, 78098b, 780018y, 780024, 780024y, 780034, 780034y, 780058, 780058y, 780308, 780308y, 780924, 780964 subseries the number of clocks increases by the number of bytes number of wait cycles , as compared with when the program is stored in the internal rom area. ? m pd78070a, 78070ay the m pd78070a and 78070ay do not incorporate an internal rom area. the number of clocks depends on the instruction (see 4.1.5 operation list (4) ). the number of clocks during instruction execution differs in the product. these are divided into the following four groups. ? m pd78002, 78002y, 78014, 78014y, 78014h, 78018f, 78018fy subseries and m pd780001, 78p0914 ? m pd78044f, 78044h, 78064, 78064y, 78064b, 780208, 780228 subseries ? m pd78054, 78054y, 78058f, 78058fy, 78075b, 78075by, 78078, 78078y, 78083, 78098, 78098b, 780018y, 780024, 780024y, 780034, 780034y, 780058, 780058y, 780308, 780308y, 780924, 780964 subseries ? m pd78070a, 78070ay the operation list for each product is shown below.
45 chapter 4 instruction set 4.1.5 operation list (1) m pd78002/78002y/78014/78014y/78014h/78018f/78018fy subseries and m pd780001, 78p0914 instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit data mov r,#byte 2 8 C r ? byte transfer saddr,#byte 3 12 14 (saddr) ? byte sfr,#byte 3 C 14 sfr ? byte a,r note 3 14 Ca ? r r,a note 3 14 Cr ? a a,saddr 2 8 10 a ? (saddr) saddr,a 2 8 10 (saddr) ? a a,sfr 2 C 10 a ? sfr sfr,a 2 C 10 sfr ? a a,!addr16 3 16 18+2n a ? (addr16) !addr16,a 3 16 18+2m (addr16) ? a psw,#byte 3 C 14 psw ? byte a,psw 2 C 10 a ? psw psw,a 2 C 10 psw ? a a,[de] 1 8 10+2n a ? (de) [de],a 1 8 10+2m (de) ? a a,[hl] 1 8 10+2n a ? (hl) [hl],a 1 8 10+2m (hl) ? a a,[hl+byte] 2 16 18+2n a ? (hl+byte) [hl+byte],a 2 16 18+2m (hl+byte) ? a a,[hl+b] 1 12 14+2n a ? (hl+b) [hl+b],a 1 12 14+2m (hl+b) ? a a,[hl+c] 1 12 14+2n a ? (hl+c) [hl+c],a 1 12 14+2m (hl+c) ? a notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to.
46 chapter 4 instruction set 8-bit data xch a,r note 3 14 Ca ? r transfer a,saddr 2 8 12 a ? (saddr) a,sfr 2 C 12 a ? (sfr) a,!addr16 3 16 20+2n+2m a ? (addr16) a,[de] 1 8 12+2n+2m a ? (de) a,[hl] 1 8 12+2n+2m a ? (hl) a,[hl+byte] 2 16 20+2n+2m a ? (hl+byte) a,[hl+b] 2 16 20+2n+2m a ? (hl+b) a,[hl+c] 2 16 20+2n+2m a ? (hl+c) 16-bit data movw rp,#word 3 12 C rp ? word transfer saddrp,#word 4 16 20 (saddrp) ? word sfrp,#word 4 C 20 sfrp ? word ax,saddrp 2 12 16 ax ? (saddrp) saddrp,ax 2 12 16 (saddrp) ? ax ax,sfrp 2 C 16 ax ? sfrp sfrp,ax 2 C 16 sfrp ? ax ax,rp note 4 18 Ca x ? r p rp,ax note 4 1 8 C rp ? ax ax,!addr16 3 20 24+4n ax ? (addr16) !addr16,ax 3 20 24+4m (addr16) ? ax xchw ax,rp note 4 1 8 C ax ? rp 8-bit add a,#byte 2 8 C a, cy ? a+byte operation saddr,#byte 3 12 16 (saddr), cy ? (saddr) + byte a,r note 3 2 8 C a,cy ? a+r r,a 2 8 C r,cy ? r+a a,saddr 2 8 10 a,cy ? a+(saddr) a,!addr16 3 16 18+2n a,cy ? a+(addr16) a,[hl] 1 8 10+2n a,cy ? a+(hl) a,[hl+byte] 2 16 18+2n a,cy ? a+(hl+byte) a,[hl+b] 2 16 18+2n a, cy ? a+(hl+b) a,[hl+c] 2 16 18+2n a,cy ? a+(hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. 4. only when rp = bc, de or hl. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
47 chapter 4 instruction set 8-bit addc a,#byte 2 8 C a,cy ? a+byte+cy operation saddr,#byte 3 12 16 (saddr), cy ? (saddr)+byte+cy a,r note 3 2 8 C a,cy ? a+r+cy r,a 2 8 C r,cy ? r+a+cy a,saddr 2 8 10 a,cy ? a+(saddr)+cy a,!addr16 3 16 18+2n a,cy ? a+(addr16)+cy a,[hl] 1 8 10+2n a,cy ? a+(hl)+cy a,[hl+byte] 2 16 18+2n a,cy ? a+(hl+byte)+cy a,[hl+b] 2 16 18+2n a,cy ? a+(hl+b)+cy a,[hl+c] 2 16 18+2n a,cy ? a+(hl+c)+cy sub a,#byte 2 8 C a,cy ? aCbyte saddr,#byte 3 12 16 (saddr),cy ? (saddr)C byte a,r note 3 2 8 C a,cy ? aCr r,a 2 8 C r,cy ? rCa a,saddr 2 8 10 a,cy ? aC(saddr) a,!addr16 3 16 18+2n a,cy ? aC(addr16) a,[hl] 1 8 10+2n a,cy ? aC(hl) a,[hl+byte] 2 16 18+2n a,cy ? aC(hl+byte) a,[hl+b] 2 16 18+2n a,cy ? aC(hl+b) a,[hl+c] 2 16 18+2n a,cy ? aC(hl+c) subc a,#byte 2 8 C a,cy ? aCbyteCcy saddr,#byte 3 12 16 (saddr),cy ? (saddr)CbyteCcy a,r note 3 2 8 C a,cy ? aCrCcy r,a 2 8 C r,cy ? rCaCcy a,saddr 2 8 10 a,cy ? aC(saddr)Ccy a,!addr16 3 16 18+2n a,cy ? aC(addr16)Ccy a,[hl] 1 8 10+2n a,cy ? aC(hl)Ccy a,[hl+byte] 2 16 18+2n a,cy ? aC(hl+byte)Ccy a,[hl+b] 2 16 18+2n a,cy ? aC(hl+b)Ccy a,[hl+c] 2 16 18+2n a,cy ? aC(hl+c)Ccy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
48 chapter 4 instruction set 8-bit and a,#byte 2 8 C a ? a byte operation saddr,#byte 3 12 16 (saddr) ? (saddr) byte a,r note 3 28 Ca ? a r r,a 2 8 C r ? r a a,saddr 2 8 10 a ? a (saddr) a,!addr16 3 16 18+2n a ? a (addr16) a,[hl] 1 8 10+2n a ? a (hl) a,[hl+byte] 2 16 18+2n a ? a (hl+byte) a,[hl+b] 2 16 18+2n a ? a (hl+b) a,[hl+c] 2 16 18+2n a ? a (hl+c) or a,#byte 2 8 C a ? a byte saddr,#byte 3 12 16 (saddr) ? (saddr) byte a,r note 3 28 Ca ? a r r,a 2 8 C r ? r a a,saddr 2 8 10 a ? a (saddr) a,!addr16 3 16 18+2n a ? a (addr16) a,[hl] 1 8 10+2n a ? a (hl) a,[hl+byte] 2 16 18+2n a ? a (hl+byte) a,[hl+b] 2 16 18+2n a ? a (hl+b) a,[hl+c] 2 16 18+2n a ? a (hl+c) xor a,#byte 2 8 C a ? a byte saddr,#byte 3 12 16 (saddr) ? (saddr) byte a,r note 3 28 Ca ? a r r,a 2 8 C r ? r a a,saddr 2 8 10 a ? a (saddr) a,!addr16 3 16 18+2n a ? a (addr16) a,[hl] 1 8 10+2n a ? a (hl) a,[hl+byte] 2 16 18+2n a ? a (hl+byte) a,[hl+b] 2 16 18+2n a ? a (hl+b) a,[hl+c] 2 16 18+2n a ? a (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
49 chapter 4 instruction set 8-bit cmp a,#byte 2 8 C aCbyte operation saddr,#byte 3 12 16 (saddr)Cbyte a,r note 3 2 8 C aCr r,a 2 8 C rCa a,saddr 2 8 10 aC(saddr) a,!addr16 3 16 18+2n aC(addr16) a,[hl] 1 8 10+2n aC(hl) a,[hl+byte] 2 16 18+2n aC(hl+byte) a,[hl+b] 2 16 18+2n aC(hl+b) a,[hl+c] 2 16 18+2n aC(hl+c) 16-bit addw ax,#word 3 12 C ax,cy ? ax+word operation subw ax,#word 3 12 C ax,cy ? axCword cmpw ax,#word 3 12 C axCword multiply/ mulu note 4 x 2 32 C ax ? a x divide divuw note 4 c 2 50 C ax (quotient), c (remainder) ? ax ? c increment/ inc r14Cr ? r+1 decrement saddr 2 8 12 (saddr) ? (saddr)+1 dec r14Cr ? rC1 saddr 2 8 12 (saddr) ? (saddr)C1 incw rp 1 8 C rp ? rp+1 decw rp 1 8 C rp ? rpC1 rotate ror a,1 1 4 C (cy, a 7 ? a 0 , a mC1 ? a m ) 1 rol a,1 1 4 C (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a,1 1 4 C (cy ? a 0 , a 7 ? cy, a mC1 ? a m ) 1 rolc a,1 1 4 C (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 ror4 [hl] 2 20 24+2n+2m a 3C0 ? (hl) 3C0 , (hl) 7C4 ? a 3C0 , (hl) 3C0 ? (hl) 7C4 rol4 [hl] 2 20 24+2n+2m a 3C0 ? (hl) 7C4 , (hl) 3C0 ? a 3C0 , (hl) 7C4 ? (hl) 3C0 bcd adjust adjba 2 8 C decimal adjust accumulator after addition adjbs 2 8 C decimal adjust accumulator after subtract notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. 4. the m pd78002/78002y subseries have no mulu/divuw instructions. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
50 chapter 4 instruction set bit mov1 cy,saddr.bit 3 12 14 cy ? (saddr.bit) manipulation cy,sfr.bit 3 C 14 cy ? sfr.bit cy,a.bit 2 8 C cy ? a.bit cy,psw.bit 3 C 14 cy ? psw.bit cy,[hl].bit 2 12 14+2n cy ? (hl).bit saddr.bit,cy 3 12 16 (saddr.bit) ? cy sfr.bit,cy 3 C 16 sfr.bit ? cy a.bit,cy 2 8 C a.bit ? cy psw.bit,cy 3 C 16 psw.bit ? cy [hl].bit,cy 2 12 16+2n+2m (hl).bit ? cy and1 cy,saddr.bit 3 12 14 cy ? cy (saddr.bit) cy,sfr.bit 3 C 14 cy ? cy sfr.bit cy,a.bit 2 8 C cy ? cy a.bit cy,psw.bit 3 C 14 cy ? cy psw.bit cy,[hl].bit 2 12 14+2n cy ? cy (hl).bit or1 cy,saddr.bit 3 12 14 cy ? cy (saddr.bit) cy,sfr.bit 3 C 14 cy ? cy sfr.bit cy,a.bit 2 8 C cy ? cy a.bit cy,psw.bit 3 C 14 cy ? cy psw.bit cy,[hl].bit 2 12 14+2n cy ? cy (hl).bit xor1 cy,saddr.bit 3 12 14 cy ? cy (saddr.bit) cy,sfr.bit 3 C 14 cy ? cy sfr.bit cy,a.bit 2 8 C cy ? cy a.bit cy,psw.bit 3 C 14 cy ? cy psw.bit cy,[hl].bit 2 12 14+2n cy ? cy (hl).bit set1 saddr.bit 2 8 12 (saddr.bit) ? 1 sfr.bit 3 C 16 sfr.bit ? 1 a.bit 2 8 C a.bit ? 1 psw.bit 2 C 12 psw.bit ? 1 [hl].bit 2 12 16+2n+2m (hl).bit ? 1 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
51 chapter 4 instruction set bit clr1 saddr.bit 2 8 12 (saddr.bit) ? 0 manipulation sfr.bit 3 C 16 sfr.bit ? 0 a.bit 2 8 C a.bit ? 0 psw.bit 2 C 12 psw.bit ? 0 [hl].bit 2 12 16+2n+2m (hl).bit ? 0 set1 cy 1 4 C cy ? 11 clr1 cy 1 4 C cy ? 00 not1 cy 1 4 C cy ? cy call return call !addr16 3 14 C (spC1) ? (pc+3) h , (spC2) ? (pc+3) l , pc ? addr16, sp ? spC2 callf !addr11 2 10 C (spC1) ? (pc+2) h , (spC2) ? (pc+2) l , pc 15C11 ? 00001, pc 10C0 ? addr11, sp ? spC2 callt [addr5] 1 12 C (spC1) ? (pc+1) h , (spC2) ? (pc+1) l , pc h ? (00000000, addr5+1), pc l ? (00000000, addr5), sp ? spC2 brk 1 12 C (spC1) ? psw, (spC2) ? (pc+1) h , (spC3) ? (pc+1) l , pc h ? (003fh), pc l ? (003eh), sp ? spC3, ie ? 0 ret 112 Cpc h ? (sp+1), pc l ? (sp), sp ? sp+2 reti 112 Cpc h ? (sp+1), pc l ? (sp), r r r psw ? (sp+2), sp ? sp+3, nmis ? 0 retb 112 Cpc h ? (sp+1), pc l ? (sp), r r r psw ? (sp+2), sp ? sp+3 stack push psw 1 4 C (spC1) ? psw, sp ? spC1 manipulation rp 1 8 C (spC1) ? rp h , (spC2) ? rp l , sp ? spC2 pop psw 1 4 C psw ? (sp), sp ? sp+1 r r r rp 1 8 C rp h ? (sp+1), rp l ? (sp), sp ? sp+2 movw sp,#word 4 C 20 sp ? word sp, ax 2 C 16 sp ? ax ax, sp 2 C 16 ax ? sp unconditional br !addr16 3 12 C pc ? addr16 branch $addr16 2 12 C pc ? pc+2+jdisp8 ax 2 16 C pc h ? a, pc l ? x notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
52 chapter 4 instruction set conditional bc $addr16 2 12 C pc ? pc+2+jdisp8 if cy=1 branch bnc $addr16 2 12 C pc ? pc+2+jdisp8 if cy=0 bz $addr16 2 12 C pc ? pc+2+jdisp8 if z=1 bnz $addr16 2 12 C pc ? pc+2+jdisp8 if z=0 bt saddr.bit,$addr16 3 16 18 pc ? pc+3+jdisp8 if (saddr.bit)=1 sfr.bit,$addr16 4 C 22 pc ? pc+4+jdisp8 if sfr.bit=1 a.bit,$addr16 3 16 C pc ? pc+3+jdisp8 if a.bit=1 psw.bit,$addr16 3 C 18 pc ? pc+3+jdisp8 if psw.bit=1 [hl].bit,$addr16 3 20 22+2n pc ? pc+3+jdisp8 if (hl).bit=1 bf saddr.bit,$addr16 4 20 22 pc ? pc+4+jdisp8 if (saddr.bit)=0 sfr.bit,$addr16 4 C 22 pc ? pc+4+jdisp8 if sfr.bit=0 a.bit,$addr16 3 16 C pc ? pc+3+jdisp8 if a.bit=0 psw.bit,$addr16 4 C 22 pc ? pc+4+jdisp8 if psw.bit=0 [hl].bit,$addr16 3 20 22+2n pc ? pc+3+jdisp8 if (hl).bit=0 btclr saddr.bit,$addr16 4 20 24 pc ? pc+4+jdisp8 if (saddr.bit)=1 then reset (saddr.bit) sfr.bit,$addr16 4 C 24 pc ? pc+4+jdisp8 if sfr.bit=1 then reset sfr.bit a.bit,$addr16 3 16 C pc ? pc+3+jdisp8 if a.bit=1 then reset a.bit psw.bit,$addr16 4 C 24 pc ? pc+4+jdisp8 if psw.bit=1 then reset psw.bit [hl].bit,$addr16 3 20 24+2n+2m pc ? pc+3+jdisp8 if (hl).bit=1 then reset (hl).bit dbnz b,$addr16 2 12 C b ? bC1, then pc ? pc+2+jdisp8 if b 1 0 c,$addr16 2 12 C c ? cC1, then pc ? pc+2+jdisp8 if c 1 0 saddr,$addr16 3 16 20 (saddr) ? (saddr)C1, then pc ? pc+3+jdisp8 if (saddr) 1 0 cpu sel rbn 2 8 C rbs1,0 ? n control nop 1 4 C no operation ei 2 C 12 ie ? 1 (enable interrupt) di 2 C 12 ie ? 0 (disable interrupt) halt 2 12 C set halt mode stop 2 12 C set stop mode notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
53 chapter 4 instruction set (2) m pd78044f/78044h/78064/78064y/78064b/780208/780228 subseries instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit data mov r,#byte 2 4 C r ? byte transfer saddr,#byte 3 6 7 (saddr) ? byte sfr,#byte 3 C 7 sfr ? byte a,r note 3 12 Ca ? r r,a note 3 12 Cr ? a a,saddr 2 4 5 a ? (saddr) saddr,a 2 4 5 (saddr) ? a a,sfr 2 C 5 a ? sfr sfr,a 2 C 5 sfr ? a a,!addr16 3 8 9 a ? (addr16) !addr16,a 3 8 9 (addr16) ? a psw,#byte 3 C 7 psw ? byte a,psw 2 C 5 a ? psw psw,a 2 C 5 psw ? a a,[de] 1 4 5 a ? (de) [de],a 1 4 5 (de) ? a a,[hl] 1 4 5 a ? (hl) [hl],a 1 4 5 (hl) ? a a,[hl+byte] 2 8 9 a ? (hl+byte) [hl+byte],a 2 8 9 (hl+byte) ? a a,[hl+b] 1 6 7 a ? (hl+b) [hl+b],a 1 6 7 (hl+b) ? a a,[hl+c] 1 6 7 a ? (hl+c) [hl+c],a 1 6 7 (hl+c) ? a xch a,r note 3 12 Ca ? r a,saddr 2 4 6 a ? (saddr) a,sfr 2 C 6 a ? (sfr) a,!addr16 3 8 10 a ? (addr16) a,[de] 1 4 6 a ? (de) a,[hl] 1 4 6 a ? (hl) a,[hl+byte] 2 8 10 a ? (hl+byte) a,[hl+b] 2 8 10 a ? (hl+b) a,[hl+c] 2 8 10 a ? (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
54 chapter 4 instruction set 16-bit data movw rp,#word 3 6 C rp ? word transfer saddrp,#word 4 8 10 (saddrp) ? word sfrp,#word 4 C 10 sfrp ? word ax,saddrp 2 6 8 ax ? (saddrp) saddrp,ax 2 6 8 (saddrp) ? ax ax,sfrp 2 C 8 ax ? sfrp sfrp,ax 2 C 8 sfrp ? ax ax,rp note 3 1 4 C ax ? rp rp,ax note 3 1 4 C rp ? ax ax,!addr16 3 10 12 ax ? (addr16) !addr16,ax 3 10 12 (addr16) ? ax xchw ax,rp note 3 1 4 C ax ? rp 8-bit add a,#byte 2 4 C a,cy ? a+byte operation saddr,#byte 3 6 8 (saddr),cy ? (saddr)+byte a,r note 4 2 4 C a,cy ? a+r r,a 2 4 C r,cy ? r+a a,saddr 2 4 5 a,cy ? a+(saddr) a,!addr16 3 8 9 a,cy ? a+(addr16) a,[hl] 1 4 5 a,cy ? a+(hl) a,[hl+byte] 2 8 9 a,cy ? a+(hl+byte) a,[hl+b] 2 8 9 a,cy ? a+(hl+b) a,[hl+c] 2 8 9 a,cy ? a+(hl+c) addc a,#byte 2 4 C a,cy ? a+byte+cy saddr,#byte 3 6 8 (saddr),cy ? (saddr)+byte+cy a,r note 4 2 4 C a,cy ? a+r+cy r,a 2 4 C r,cy ? r+a+cy a,saddr 2 4 5 a,cy ? a+(saddr)+cy a,!addr16 3 8 9 a,cy ? a+(addr16)+cy a,[hl] 1 4 5 a,cy ? a+(hl)+cy a,[hl+byte] 2 8 9 a,cy ? a+(hl+byte)+cy a,[hl+b] 2 8 9 a,cy ? a+(hl+b)+cy a,[hl+c] 2 8 9 a,cy ? a+(hl+c)+cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. only when rp = bc, de or hl. 4. except r = a. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
55 chapter 4 instruction set 8-bit sub a,#byte 2 4 C a,cy ? aCbyte operation saddr,#byte 3 6 8 (saddr),cy ? (saddr)Cbyte a,r note 3 2 4 C a,cy ? aCr r,a 2 4 C r,cy ? rCa a,saddr 2 4 5 a,cy ? aC(saddr) a,!addr16 3 8 9 a,cy ? aC(addr16) a,[hl] 1 4 5 a,cy ? aC(hl) a,[hl+byte] 2 8 9 a,cy ? aC(hl+byte) a,[hl+b] 2 8 9 a,cy ? aC(hl+b) a,[hl+c] 2 8 9 a,cy ? aC(hl+c) subc a,#byte 2 4 C a,cy ? aCbyteCcy saddr,#byte 3 6 8 (saddr),cy ? (saddr)CbyteCcy a,r note 3 2 4 C a,cy ? aCrCcy r,a 2 4 C r,cy ? rCaCcy a,saddr 2 4 5 a,cy ? aC(saddr)Ccy a,!addr16 3 8 9 a,cy ? aC(addr16)Ccy a,[hl] 1 4 5 a,cy ? aC(hl)Ccy a,[hl+byte] 2 8 9 a,cy ? aC(hl+byte)Ccy a,[hl+b] 2 8 9 a,cy ? aC(hl+b)Ccy a,[hl+c] 2 8 9 a,cy ? aC(hl+c)Ccy and a,#byte 2 4 C a ? a byte saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9 a ? a (addr16) a,[hl] 1 4 5 a ? a (hl) a,[hl+byte] 2 8 9 a ? a (hl+byte) a,[hl+b] 2 8 9 a ? a (hl+b) a,[hl+c] 2 8 9 a ? a (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
56 chapter 4 instruction set 8-bit or a,#byte 2 4 C a ? a byte operation saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9 a ? a (addr16) a,[hl] 1 4 5 a ? a (hl) a,[hl+byte] 2 8 9 a ? a (hl+byte) a,[hl+b] 2 8 9 a ? a (hl+b) a,[hl+c] 2 8 9 a ? a (hl+c) xor a,#byte 2 4 C a ? a byte saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9 a ? a (addr16) a,[hl] 1 4 5 a ? a (hl) a,[hl+byte] 2 8 9 a ? a (hl+byte) a,[hl+b] 2 8 9 a ? a (hl+b) a,[hl+c] 2 8 9 a ? a (hl+c) cmp a,#byte 2 4 C aCbyte saddr,#byte 3 6 8 (saddr)Cbyte a,r note 3 2 4 C aCr r,a 2 4 C rCa a,saddr 2 4 5 aC(saddr) a,!addr16 3 8 9 aC(addr16) a,[hl] 1 4 5 aC(hl) a,[hl+byte] 2 8 9 aC(hl+byte) a,[hl+b] 2 8 9 aC(hl+b) a,[hl+c] 2 8 9 aC(hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
57 chapter 4 instruction set 16-bit addw ax,#word 3 6 C ax,cy ? ax+word operation subw ax,#word 3 6 C ax,cy ? axCword cmpw ax,#word 3 6 C axCword multiply/ mulu x 2 16 C ax ? a x divide divuw c 2 25 C ax (quotient), c (remainder) ? ax ? c increment/ inc r12Cr ? r+1 decrement saddr 2 4 6 (saddr) ? (saddr)+1 dec r12Cr ? rC1 saddr 2 4 6 (saddr) ? (saddr)C1 incw rp 1 4 C rp ? rp+1 decw rp 1 4 C rp ? rpC1 rotate ror a,1 1 2 C (cy,a 7 ? a 0 , a mC1 ? a m ) 1 rol a,1 1 2 C (cy,a 0 ? a 7 , a m+1 ? a m ) 1 rorc a,1 1 2 C (cy ? a 0 , a 7 ? cy, a mC1 ? a m ) 1 rolc a,1 1 2 C (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 ror4 [hl] 2 10 12 a 3C0 ? (hl) 3C0 , (hl) 7C4 ? a 3C0 , (hl) 3C0 ? (hl) 7C4 rol4 [hl] 2 10 12 a 3C0 ? (hl) 7C4 , (hl) 3C0 ? a 3C0 , (hl) 7C4 ? (hl) 3C0 bcd adjust adjba 2 4 C decimal adjust accumulator after addition adjbs 2 4 C decimal adjust accumulator after subtract bit mov1 cy,saddr.bit 3 6 7 cy ? (saddr.bit) manipulation cy,sfr.bit 3 C 7 cy ? sfr.bit cy,a.bit 2 4 C cy ? a.bit cy,psw.bit 3 C 7 cy ? psw.bit cy,[hl].bit 2 6 7 cy ? (hl).bit saddr.bit,cy 3 6 8 (saddr.bit) ? cy sfr.bit,cy 3 C 8 sfr.bit ? cy a.bit,cy 2 4 C a.bit ? cy psw.bit,cy 3 C 8 psw.bit ? cy [hl].bit,cy 2 6 8 (hl).bit ? cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
58 chapter 4 instruction set bit and1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) manipulation cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7 cy ? cy (hl).bit or1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7 cy ? cy (hl).bit xor1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7 cy ? cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) ? 1 sfr.bit 3 C 8 sfr.bit ? 1 a.bit 2 4 C a.bit ? 1 psw.bit 2 C 6 psw.bit ? 1 [hl].bit 2 6 8 (hl).bit ? 1 clr1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 C 8 sfr.bit ? 0 a.bit 2 4 C a.bit ? 0 psw.bit 2 C 6 psw.bit ? 0 [hl].bit 2 6 8 (hl).bit ? 0 set1 cy 1 2 C cy ? 11 clr1 cy 1 2 C cy ? 00 not1 cy 1 2 C cy ? cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
59 chapter 4 instruction set call return call !addr16 3 7 C (spC1) ? (pc+3) h , (spC2) ? (pc+3) l , pc ? addr16, sp ? spC2 callf !addr11 2 5 C (spC1) ? (pc+2) h , (spC2) ? (pc+2) l , pc 15C11 ? 00001, pc 10C0 ? addr11, sp ? spC2 callt [addr5] 1 6 C (spC1) ? (pc+1) h , (spC2) ? (pc+1) l , pc h ? (00000000,addr5+1), pc l ? (00000000,addr5), sp ? spC2 brk 1 6 C (spC1) ? psw, (spC2) ? (pc+1) h , (spC3) ? (pc+1) l , pc h ? (003fh), pc l ? (003eh), sp ? spC3, ie ? 0 ret 16 Cpc h ? (sp+1), pc l ? (sp), sp ? sp+2 reti 16 Cpc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3, nmis ? 0 retb 16 Cpc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3 stack push psw 1 2 C (spC1) ? psw, sp ? spC1 manipulation rp 1 4 C (spC1) ? rp h , (spC2) ? rp l , sp ? spC2 pop psw 1 2 C psw ? (sp), sp ? sp+1 r r r rp 1 4 C rp h ? (sp+1), rp l ? (sp), sp ? sp+2 movw sp,#word 4 C 10 sp ? word sp, ax 2 C 8 sp ? ax ax, sp 2 C 8 ax ? sp unconditional br !addr16 3 6 C pc ? addr16 branch $addr16 2 6 C pc ? pc+2+jdisp8 ax 2 8 C pc h ? a, pc l ? x conditional bc $addr16 2 6 C pc ? pc+2+jdisp8 if cy = 1 branch bnc $addr16 2 6 C pc ? pc+2+jdisp8 if cy = 0 bz $addr16 2 6 C pc ? pc+2+jdisp8 if z = 1 bnz $addr16 2 6 C pc ? pc+2+jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
60 chapter 4 instruction set conditional bt saddr.bit,$addr16 3 8 9 pc ? pc+3+jdisp8 if (saddr.bit) = 1 branch sfr.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if sfr.bit = 1 a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit = 1 psw.bit,$addr16 3 C 9 pc ? pc+3+jdisp8 if psw.bit = 1 [hl].bit,$addr16 3 10 11 pc ? pc+3+jdisp8 if (hl).bit = 1 bf saddr.bit,$addr16 4 10 11 pc ? pc+4+jdisp8 if (saddr.bit) = 0 sfr.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if sfr.bit = 0 a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit = 0 psw.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if psw.bit = 0 [hl].bit,$addr16 3 10 11 pc ? pc+3+jdisp8 if (hl).bit = 0 btclr saddr.bit,$addr16 4 10 12 pc ? pc+4+jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit,$addr16 4 C 12 pc ? pc+4+jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit = 1 then reset a.bit psw.bit,$addr16 4 C 12 pc ? pc+4+jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit,$addr16 3 10 12 pc ? pc+3+jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b,$addr16 2 6 C b ? bC1, then pc ? pc+2+jdisp8 if b 1 0 c,$addr16 2 6 C c ? cC1, then pc ? pc+2+jdisp8 if c 1 0 saddr,$addr16 3 8 10 (saddr) ? (saddr)C1, then pc ? pc+3+jdisp8 if (saddr) 1 0 cpu sel rbn 2 4 C rbs1, 0 ? n control nop 1 2 C no operation ei 2 C 6 ie ? 1 (enable interrupt) di 2 C 6 ie ? 0 (disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remark 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
61 chapter 4 instruction set (3) m pd78054, 78054y, 78058f, 78058fy, 78075b, 78075by, 78078, 78078y, 78083, 78098, 78098b, 780018y, 780024, 780024y, 780034, 780034y, 780058, 780058y, 780308, 780308y, 780924, 780964 subseries instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit data mov r,#byte 2 4 C r ? byte transfer saddr,#byte 3 6 7 (saddr) ? byte sfr,#byte 3 C 7 sfr ? byte a,r note 3 12 Ca ? r r,a note 3 12 Cr ? a a,saddr 2 4 5 a ? (saddr) saddr,a 2 4 5 (saddr) ? a a,sfr 2 C 5 a ? sfr sfr,a 2 C 5 sfr ? a a,!addr16 3 8 9+n a ? (addr16) !addr16,a 3 8 9+m (addr16) ? a psw,#byte 3 C 7 psw ? byte a,psw 2 C 5 a ? psw psw,a 2 C 5 psw ? a a,[de] 1 4 5+n a ? (de) [de],a 1 4 5+m (de) ? a a,[hl] 1 4 5+n a ? (hl) [hl],a 1 4 5+m (hl) ? a a,[hl+byte] 2 8 9+n a ? (hl+byte) [hl+byte],a 2 8 9+m (hl+byte) ? a a,[hl+b] 1 6 7+n a ? (hl+b) [hl+b],a 1 6 7+m (hl+b) ? a a,[hl+c] 1 6 7+n a ? (hl+c) [hl+c],a 1 6 7+m (hl+c) ? a notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to.
62 chapter 4 instruction set 8-bit data xch a,r note 4 12 Ca ? r transfer a,saddr 2 4 6 a ? (saddr) a,sfr 2 C 6 a ? sfr a,!addr16 3 8 10+n+m a ? (addr16) a,[de] 1 4 6+n+m a ? (de) a,[hl] 1 4 6+n+m a ? (hl) a,[hl+byte] 2 8 10+n+m a ? (hl+byte) a,[hl+b] 2 8 10+n+m a ? (hl+b) a,[hl+c] 2 8 10+n+m a ? (hl+c) 16-bit data movw rp,#word 3 6 C rp ? word transfer saddrp,#word 4 8 10 (saddrp) ? word sfrp,#word 4 C 10 sfrp ? word ax,saddrp 2 6 8 ax ? (saddrp) saddrp,ax 2 6 8 (saddrp) ? ax ax,sfrp 2 C 8 ax ? sfrp sfrp,ax 2 C 8 sfrp ? ax ax,rp note 3 1 4 C ax ? rp rp,ax note 3 1 4 C rp ? ax ax,!addr16 3 10 12+2n ax ? (addr16) !addr16,ax 3 10 12+2m (addr16) ? ax xchw ax,rp note 3 1 4 C ax ? rp 8-bit add a,#byte 2 4 C a,cy ? a+byte operation saddr,#byte 3 6 8 (saddr), cy ? (saddr)+byte a,r note 4 2 4 C a,cy ? a+r r,a 2 4 C r,cy ? r+a a,saddr 2 4 5 a,cy ? a+(saddr) a,!addr16 3 8 9+n a,cy ? a+(addr16) a,[hl] 1 4 5+n a,cy ? a+(hl) a,[hl+byte] 2 8 9+n a,cy ? a+(hl+byte) a,[hl+b] 2 8 9+n a,cy ? a+(hl+b) a,[hl+c] 2 8 9+n a,cy ? a+(hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. only when rp = bc, de or hl. 4. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
63 chapter 4 instruction set 8-bit addc a,#byte 2 4 C a,cy ? a+byte+cy operation saddr,#byte 3 6 8 (saddr),cy ? (saddr)+byte+cy a,r note 3 2 4 C a,cy ? a+r+cy r,a 2 4 C r,cy ? r+a+cy a,saddr 2 4 5 a,cy ? a+(saddr)+cy a,!addr16 3 8 9+n a,cy ? a+(addr16)+cy a,[hl] 1 4 5+n a,cy ? a+(hl)+cy a,[hl+byte] 2 8 9+n a,cy ? a+(hl+byte)+cy a,[hl+b] 2 8 9+n a,cy ? a+(hl+b)+cy a,[hl+c] 2 8 9+n a,cy ? a+(hl+c)+cy sub a,#byte 2 4 C a,cy ? aCbyte saddr,#byte 3 6 8 (saddr),cy ? (saddr)Cbyte a,r note 3 2 4 C a,cy ? aCr r,a 2 4 C r,cy ? rCa a,saddr 2 4 5 a,cy ? aC(saddr) a,!addr16 3 8 9+n a,cy ? aC(addr16) a,[hl] 1 4 5+n a,cy ? aC(hl) a,[hl+byte] 2 8 9+n a,cy ? aC(hl+byte) a,[hl+b] 2 8 9+n a,cy ? aC(hl+b) a,[hl+c] 2 8 9+n a,cy ? aC(hl+c) subc a,#byte 2 4 C a,cy ? aCbyteCcy saddr,#byte 3 6 8 (saddr),cy ? (saddr)CbyteCcy a,r note 3 2 4 C a,cy ? aCrCcy r,a 2 4 C r,cy ? rCaCcy a,saddr 2 4 5 a,cy ? aC(saddr)Ccy a,!addr16 3 8 9+n a,cy ? aC(addr16)Ccy a,[hl] 1 4 5+n a,cy ? aC(hl)Ccy a,[hl+byte] 2 8 9+n a,cy ? aC(hl+byte)Ccy a,[hl+b] 2 8 9+n a,cy ? aC(hl+b)Ccy a,[hl+c] 2 8 9+n a,cy ? aC(hl+c)Ccy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
64 chapter 4 instruction set 8-bit and a,#byte 2 4 C a ? a byte operation saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9+n a ? a (addr16) a,[hl] 1 4 5+n a ? a (hl) a,[hl+byte] 2 8 9+n a ? a (hl+byte) a,[hl+b] 2 8 9+n a ? a (hl+b) a,[hl+c] 2 8 9+n a ? a (hl+c) or a,#byte 2 4 C a ? a byte saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9+n a ? a (addr16) a,[hl] 1 4 5+n a ? a (hl) a,[hl+byte] 2 8 9+n a ? a (hl+byte) a,[hl+b] 2 8 9+n a ? a (hl+b) a,[hl+c] 2 8 9+n a ? a (hl+c) xor a,#byte 2 4 C a ? a byte saddr,#byte 3 6 8 (saddr) ? (saddr) byte a,r note 3 24 Ca ? a r r,a 2 4 C r ? r a a,saddr 2 4 5 a ? a (saddr) a,!addr16 3 8 9+n a ? a (addr16) a,[hl] 1 4 5+n a ? a (hl) a,[hl+byte] 2 8 9+n a ? a (hl+byte) a,[hl+b] 2 8 9+n a ? a (hl+b) a,[hl+c] 2 8 9+n a ? a (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
65 chapter 4 instruction set 8-bit cmp a,#byte 2 4 C aCbyte operation saddr,#byte 3 6 8 (saddr)Cbyte a,r note 3 2 4 C aCr r,a 2 4 C rCa a,saddr 2 4 5 aC(saddr) a,!addr16 3 8 9+n aC(addr16) a,[hl] 1 4 5+n aC(hl) a,[hl+byte] 2 8 9+n aC(hl+byte) a,[hl+b] 2 8 9+n aC(hl+b) a,[hl+c] 2 8 9+n aC(hl+c) 16-bit addw ax,#word 3 6 C ax,cy ? ax+word operation subw ax,#word 3 6 C ax,cy ? axCword cmpw ax,#word 3 6 C axCword multiply/ mulu x 2 16 C ax ? a x divide divuw c 2 25 C ax (quotient), c (remainder) ? ax ? c increment/ inc r12Cr ? r+1 decrement saddr 2 4 6 (saddr) ? (saddr)+1 dec r12Cr ? rC1 saddr 2 4 6 (saddr) ? (saddr)C1 incw rp 1 4 C rp ? rp+1 decw rp 1 4 C rp ? rpC1 rotate ror a,1 1 2 C (cy, a 7 ? a 0 , a mC1 ? a m ) 1 rol a,1 1 2 C (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a,1 1 2 C (cy ? a 0 , a 7 ? cy, a mC1 ? a m ) 1 rolc a,1 1 2 C (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 ror4 [hl] 2 10 12+n+m a 3C0 ? (hl) 3C0 , (hl) 7C4 ? a 3C0 , (hl) 3C0 ? (hl) 7C4 rol4 [hl] 2 10 12+n+m a 3C0 ? (hl) 7C4 , (hl) 3C0 ? a 3C0 , (hl) 7C4 ? (hl) 3C0 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
66 chapter 4 instruction set bcd adjba 2 4 C decimal adjust accumulator after addition adjust adjbs 2 4 C decimal adjust accumulator after subtract bit mov1 cy,saddr.bit 3 6 7 cy ? (saddr.bit) manipulation cy,sfr.bit 3 C 7 cy ? sfr.bit cy,a.bit 2 4 C cy ? a.bit cy,psw.bit 3 C 7 cy ? psw.bit cy,[hl].bit 2 6 7+n cy ? (hl).bit saddr.bit,cy 3 6 8 (saddr.bit) ? cy sfr.bit,cy 3 C 8 sfr.bit ? cy a.bit,cy 2 4 C a.bit ? cy psw.bit,cy 3 C 8 psw.bit ? cy [hl].bit,cy 2 6 8+n+m (hl).bit ? cy and1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7+n cy ? cy (hl).bit or1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7+n cy ? cy (hl).bit xor1 cy,saddr.bit 3 6 7 cy ? cy (saddr.bit) cy,sfr.bit 3 C 7 cy ? cy sfr.bit cy,a.bit 2 4 C cy ? cy a.bit cy,psw.bit 3 C 7 cy ? cy psw.bit cy,[hl].bit 2 6 7+n cy ? cy (hl).bit notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
67 chapter 4 instruction set bit set1 saddr.bit 2 4 6 (saddr.bit) ? 1 manipulation sfr.bit 3 C 8 sfr.bit ? 1 a.bit 2 4 C a.bit ? 1 psw.bit 2 C 6 psw.bit ? 1 [hl].bit 2 6 8+n+m (hl).bit ? 1 clr1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 C 8 sfr.bit ? 0 a.bit 2 4 C a.bit ? 0 psw.bit 2 C 6 psw.bit ? 0 [hl].bit 2 6 8+n+m (hl).bit ? 0 set1 cy 1 2 C cy ? 11 clr1 cy 1 2 C cy ? 00 not1 cy 1 2 C cy ? cy call return call !addr16 3 7 C (spC1) ? (pc+3) h , (spC2) ? (pc+3) l , pc ? addr16, sp ? spC2 callf !addr11 2 5 C (spC1) ? (pc+2) h , (spC2) ? (pc+2) l , pc 15C11 ? 00001, pc 10C0 ? addr11, sp ? spC2 callt [addr5] 1 6 C (spC1) ? (pc+1) h , (spC2) ? (pc+1) l , pc h ? (00000000,addr5+1), pc l ? (00000000, addr5), sp ? spC2 brk 1 6 C (spC1) ? psw, (spC2) ? (pc+1) h , (spC3) ? (pc+1) l , pc h ? (003fh), pc l ? (003eh), sp ? spC3, ie ? 0 ret 16 Cpc h ? (sp+1), pc l ? (sp), sp ? sp+2 reti 16 Cpc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3, nmis ? 0 retb 16 Cpc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
68 chapter 4 instruction set stack push psw 1 2 C (spC1) ? psw, sp ? spC1 manipulation rp 1 4 C (spC1) ? rp h , (spC2) ? rp l , sp ? spC2 pop psw 1 2 C psw ? (sp), sp ? sp+1 r r r rp 1 4 C rp h ? (sp+1), rp l ? (sp), sp ? sp+2 movw sp,#word 4 C 10 sp ? word sp,ax 2 C 8 sp ? ax ax,sp 2 C 8 ax ? sp unconditional br !addr16 3 6 C pc ? addr16 branch $addr16 2 6 C pc ? pc+2+jdisp8 ax 2 8 C pc h ? a, pc l ? x conditional bc $addr16 2 6 C pc ? pc+2+jdisp8 if cy=1 branch bnc $addr16 2 6 C pc ? pc+2+jdisp8 if cy=0 bz $addr16 2 6 C pc ? pc+2+jdisp8 if z=1 bnz $addr16 2 6 C pc ? pc+2+jdisp8 if z=0 bt saddr.bit,$addr16 3 8 9 pc ? pc+3+jdisp8 if (saddr.bit)=1 sfr.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if sfr.bit=1 a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit=1 psw.bit,$addr16 3 C 9 pc ? pc+3+jdisp8 if psw.bit=1 [hl].bit,$addr16 3 10 11+n pc ? pc+3+jdisp8 if (hl).bit=1 bf saddr.bit,$addr16 4 10 11 pc ? pc+4+jdisp8 if (saddr.bit)=0 sfr.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if sfr.bit=0 a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit=0 psw.bit,$addr16 4 C 11 pc ? pc+4+jdisp8 if psw.bit=0 [hl].bit,$addr16 3 10 11+n pc ? pc+3+jdisp8 if (hl).bit=0 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy
69 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy conditional btclr saddr.bit,$addr16 4 10 12 pc ? pc+4+jdisp8 if (saddr.bit)=1 branch then reset (saddr.bit) sfr.bit,$addr16 4 C 12 pc ? pc+4+jdisp8 if sfr.bit=1 then reset sfr.bit a.bit,$addr16 3 8 C pc ? pc+3+jdisp8 if a.bit=1 then reset a.bit psw.bit,$addr16 4 C 12 pc ? pc+4+jdisp8 if psw.bit=1 then reset psw.bit [hl].bit,$addr16 3 10 12+n+m pc ? pc+3+jdisp8 if (hl).bit=1 then reset (hl).bit dbnz b,$addr16 2 6 C b ? bC1, then pc ? pc+2+jdisp8 if b 1 0 c,$addr16 2 6 C c ? cC1, then pc ? pc+2+jdisp8 if c 1 0 saddr,$addr16 3 8 10 (saddr) ? (saddr)C1, then pc ? pc+3+jdisp8 if (saddr) 1 0 cpu sel rbn 2 4 C rbs1,0 ? n control nop 1 2 C no operation ei 2 C 6 ie ? 1 (enable interrupt) di 2 C 6 ie ? 0 (disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. number of clock cycles is when there is a program in the internal rom area. 3. n indicates the number of waits when the external memory expansion area is read. 4. m indicates the number of waits when the external memory expansion area is written to.
70 chapter 4 instruction set (4) m pd78070a, 78070ay instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit data mov r,#byte 2 4+2n C r ? byte transfer saddr,#byte 3 6+3n 7+3n (saddr) ? byte sfr,#byte 3 C 7+3n sfr ? byte a,r note 3 1 2+n C a ? r r,a note 3 1 2+n C r ? a a,saddr 2 4+2n 5+2n a ? (saddr) saddr,a 2 4+2n 5+2n (saddr) ? a a,sfr 2 C 5+2n a ? sfr sfr,a 2 C 5+2n sfr ? a a,!addr16 3 8+3n 9+4n a ? (addr16) !addr16,a 3 8+3n 9+3n+m (addr16) ? a psw,#byte 3 C 7+3n psw ? byte a,psw 2 C 5+2n a ? psw psw,a 2 C 5+2n psw ? a a,[de] 1 4+n 5+2n a ? (de) [de],a 1 4+n 5+n+m (de) ? a a,[hl] 1 4+n 5+2n a ? (hl) [hl],a 1 4+n 5+n+m (hl) ? a a,[hl+byte] 2 8+2n 9+3n a ? (hl+byte) [hl+byte],a 2 8+2n 9+2n+m (hl+byte) ? a a,[hl+b] 1 6+n 7+2n a ? (hl+b) [hl+b],a 1 6+n 7+n+m (hl+b) ? a a,[hl+c] 1 6+n 7+2n a ? (hl+c) [hl+c],a 1 6+n 7+n+m (hl+c) ? a xch a,r note 3 1 2+n C a ? r a,saddr 2 4+2n 6+2n a ? (saddr) a,sfr 2 C 6+2n a ? (sfr) a,!addr16 3 8+3n 10+4n+m a ? (addr16) a,[de] 1 4+n 6+2n+m a ? (de) a,[hl] 1 4+n 6+2n+m a ? (hl) a,[hl+byte] 2 8+2n 10+3n+m a ? (hl+byte) a,[hl+b] 2 8+2n 10+3n+m a ? (hl+b) a,[hl+c] 2 8+2n 10+3n+m a ? (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched. 3. m indicates the number of waits when the external memory expansion area is written to.
71 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 16-bit data movw rp,#word 3 6+3n C rp ? word transfer saddrp,#word 4 8+4n 10+4n (saddrp) ? word sfrp,#word 4 C 10+4n sfrp ? word ax,saddrp 2 6+2n 8+2n ax ? (saddrp) saddrp,ax 2 6+2n 8+2n (saddrp) ? ax ax,sfrp 2 C 8+2n ax ? sfrp sfrp,ax 2 C 8+2n sfrp ? ax ax,rp note 3 1 4+n C ax ? rp rp,ax note 3 1 4+n C rp ? ax ax,!addr16 3 10+3n 12+5n ax ? (addr16) !addr16,ax 3 10+3n 12+2m+3n (addr16) ? ax xchw ax,rp note 3 1 4+n C ax ? rp 8-bit add a,#byte 2 4+2n C a,cy ? a+byte operation saddr,#byte 3 6+3n 8+3n (saddr), cy ? (saddr)+byte a,r note 4 2 4+2n C a,cy ? a+r r,a 2 4+2n C r,cy ? r+a a,saddr 2 4+2n 5+2n a,cy ? a+(saddr) a,!addr16 3 8+3n 9+4n a,cy ? a+(addr16) a,[hl] 1 4+n 5+2n a,cy ? a+(hl) a,[hl+byte] 2 8+2n 9+3n a,cy ? a+(hl+byte) a,[hl+b] 2 8+2n 9+3n a,cy ? a+(hl+b) a,[hl+c] 2 8+2n 9+3n a,cy ? a+(hl+c) addc a,#byte 2 4+2n C a,cy ? a+byte+cy saddr,#byte 3 6+3n 8+3n (saddr),cy ? (saddr)+byte+cy a,r note 4 2 4+2n C a,cy ? a+r+cy r,a 2 4+2n C r,cy ? r+a+cy a,saddr 2 4+2n 5+2n a,cy ? a+(saddr)+cy a,!addr16 3 8+3n 9+4n a,cy ? a+(addr16)+cy a,[hl] 1 4+n 5+2n a,cy ? a+(hl)+cy a,[hl+byte] 2 8+2n 9+3n a,cy ? a+(hl+byte)+cy a,[hl+b] 2 8+2n 9+3n a,cy ? a+(hl+b)+cy a,[hl+c] 2 8+2n 9+3n a,cy ? a+(hl+c)+cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. only when rp = bc, de, or hl 4. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched. 3. m indicates the number of waits when the external memory expansion area is written to.
72 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit sub a,#byte 2 4+2n C a,cy ? aCbyte operation saddr,#byte 3 6+3n 8+3n (saddr),cy ? (saddr)Cbyte a,r note 3 2 4+2n C a,cy ? aCr r,a 2 4+2n C r,cy ? rCa a,saddr 2 4+2n 5+2n a,cy ? aC(saddr) a,!addr16 3 8+3n 9+4n a,cy ? aC(addr16) a,[hl] 1 4+n 5+2n a,cy ? aC(hl) a,[hl+byte] 2 8+2n 9+3n a,cy ? aC(hl+byte) a,[hl+b] 2 8+2n 9+3n a,cy ? aC(hl+b) a,[hl+c] 2 8+2n 9+3n a,cy ? aC(hl+c) subc a,#byte 2 4+2n C a,cy ? aCbyteCcy saddr,#byte 3 6+3n 8+3n (saddr),cy ? (saddr)CbyteCcy a,r note 3 2 4+2n C a,cy ? aCrCcy r,a 2 4+2n C r,cy ? rCaCcy a,saddr 2 4+2n 5+2n a,cy ? aC(saddr)Ccy a,!addr16 3 8+3n 9+4n a,cy ? aC(addr16)Ccy a,[hl] 1 4+n 5+2n a,cy ? aC(hl)Ccy a,[hl+byte] 2 8+2n 9+3n a,cy ? aC(hl+byte)Ccy a,[hl+b] 2 8+2n 9+3n a,cy ? aC(hl+b)Ccy a,[hl+c] 2 8+2n 9+3n a,cy ? aC(hl+c)Ccy and a,#byte 2 4+2n C a ? a byte saddr,#byte 3 6+3n 8+3n (saddr) ? (saddr) byte a,r note 3 2 4+2n C a ? a r r,a 2 4+2n C r ? r a a,saddr 2 4+2n 5+2n a ? a (saddr) a,!addr16 3 8+3n 9+4n a ? a (addr16) a,[hl] 1 4+n 5+2n a ? a (hl) a,[hl+byte] 2 8+2n 9+3n a ? a (hl+byte) a,[hl+b] 2 8+2n 9+3n a ? a (hl+b) a,[hl+c] 2 8+2n 9+3n a ? a (hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched.
73 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 8-bit or a,#byte 2 4+2n C a ? a byte operation saddr,#byte 3 6+3n 8+3n (saddr) ? (saddr) byte a,r note 3 2 4+2n C a ? a r r,a 2 4+2n C r ? r a a,saddr 2 4+2n 5+2n a ? a (saddr) a,!addr16 3 8+3n 9+4n a ? a (addr16) a,[hl] 1 4+n 5+2n a ? a (hl) a,[hl+byte] 2 8+2n 9+3n a ? a (hl+byte) a,[hl+b] 2 8+2n 9+3n a ? a (hl+b) a,[hl+c] 2 8+2n 9+3n a ? a (hl+c) xor a,#byte 2 4+2n C a ? a byte saddr,#byte 3 6+3n 8+3n (saddr) ? (saddr) byte a,r note 3 2 4+2n C a ? a r r,a 2 4+2n C r ? r a a,saddr 2 4+2n 5+2n a ? a (saddr) a,!addr16 3 8+3n 9+4n a ? a (addr16) a,[hl] 1 4+n 5+2n a ? a (hl) a,[hl+byte] 2 8+2n 9+3n a ? a (hl+byte) a,[hl+b] 2 8+2n 9+3n a ? a (hl+b) a,[hl+c] 2 8+2n 9+3n a ? a (hl+c) cmp a,#byte 2 4+2n C aCbyte saddr,#byte 3 6+3n 8+3n (saddr)Cbyte a,r note 3 2 4+2n C aCr r,a 2 4+2n C rCa a,saddr 2 4+2n 5+2n aC(saddr) a,!addr16 3 8+3n 9+4n aC(addr16) a,[hl] 1 4+n 5+2n aC(hl) a,[hl+byte] 2 8+2n 9+3n aC(hl+byte) a,[hl+b] 2 8+2n 9+3n aC(hl+b) a,[hl+c] 2 8+2n 9+3n aC(hl+c) notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. 3. except r = a. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched.
74 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy 16-bit addw ax,#word 3 6+3n C ax,cy ? ax+word operation subw ax,#word 3 6+3n C ax,cy ? axCword cmpw ax,#word 3 6+3n C axCword multiply/ mulu x 2 16+2n C ax ? a x divide divuw c 2 25+2n C ax (quotient), c (remainder) ? ax ? c increment/ inc r 1 2+n C r ? r+1 decrement saddr 2 4+2n 6+2n (saddr) ? (saddr)+1 dec r 1 2+n C r ? rC1 saddr 2 4+2n 6+2n (saddr) ? (saddr)C1 incw rp 1 4+n C rp ? rp+1 decw rp 1 4+n C rp ? rpC1 rotate ror a,1 1 2+n C (cy, a 7 ? a 0 , a mC1 ? a m ) 1 rol a,1 1 2+n C (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a,1 1 2+n C (cy ? a 0 , a 7 ? cy, a mC1 ? a m ) 1 rolc a,1 1 2+n C (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 ror4 [hl] 2 10+2n 12+3n+m a 3C0 ? (hl) 3C0 , (hl) 7C4 ? a 3C0 , (hl) 3C0 ? (hl) 7C4 rol4 [hl] 2 10+2n 12+3n+m a 3C0 ? (hl) 7C4 , (hl) 3C0 ? a 3C0 , (hl) 7C4 ? (hl) 3C0 bcd adjba 2 4+2n C decimal adjust accumulator after addition adjust adjbs 2 4+2n C decimal adjust accumulator after subtract bit mov1 cy,saddr.bit 3 6+3n 7+3n cy ? (saddr.bit) manipulation cy,sfr.bit 3 C 7+3n cy ? sfr.bit cy,a.bit 2 4+2n C cy ? a.bit cy,psw.bit 3 C 7+3n cy ? psw.bit cy,[hl].bit 2 6+2n 7+3n cy ? (hl).bit saddr.bit,cy 3 6+3n 8+3n (saddr.bit) ? cy sfr.bit,cy 3 C 8+3n sfr.bit ? cy a.bit,cy 2 4+2n C a.bit ? cy psw.bit,cy 3 C 8+3n psw.bit ? cy [hl].bit,cy 2 6+2n 8+3n+m (hl).bit ? cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched. 3. m indicates the number of waits when the external memory expansion area is written to.
75 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy bit and1 cy,saddr.bit 3 6+3n 7+3n cy ? cy (saddr.bit) manipulation cy,sfr.bit 3 C 7+3n cy ? cy sfr.bit cy,a.bit 2 4+2n C cy ? cy a.bit cy,psw.bit 3 C 7+3n cy ? cy psw.bit cy,[hl].bit 2 6+2n 7+3n cy ? cy (hl).bit or1 cy,saddr.bit 3 6+3n 7+3n cy ? cy (saddr.bit) cy,sfr.bit 3 C 7+3n cy ? cy sfr.bit cy,a.bit 2 4+2n C cy ? cy a.bit cy,psw.bit 3 C 7+3n cy ? cy psw.bit cy,[hl].bit 2 6+2n 7+3n cy ? cy (hl).bit xor1 cy,saddr.bit 3 6+3n 7+3n cy ? cy (saddr.bit) cy,sfr.bit 3 C 7+3n cy ? cy sfr.bit cy,a.bit 2 4+2n C cy ? cy a.bit cy,psw.bit 3 C 7+3n cy ? cy psw.bit cy,[hl].bit 2 6+2n 7+3n cy ? cy (hl).bit set1 saddr.bit 2 4+2n 6+2n (saddr.bit) ? 1 sfr.bit 3 C 8+3n sfr.bit ? 1 a.bit 2 4+2n C a.bit ? 1 psw.bit 2 C 6+2n psw.bit ? 1 [hl].bit 2 6+2n 8+3n+m (hl).bit ? 1 clr1 saddr.bit 2 4+2n 6+2n (saddr.bit) ? 0 sfr.bit 3 C 8+3n sfr.bit ? 0 a.bit 2 4+2n C a.bit ? 0 psw.bit 2 C 6+2n psw.bit ? 0 [hl].bit 2 6+2n 8+3n+m (hl).bit ? 0 set1 cy 1 2+n C cy ? 11 clr1 cy 1 2+n C cy ? 00 not1 cy 1 2+n C cy ? cy notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched. 3. m indicates the number of waits when the external memory expansion area is written to.
76 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy call return call !addr16 3 7+3n C (spC1) ? (pc+3) h , (spC2) ? (pc+3) l , pc ? addr16, sp ? spC2 callf !addr11 2 5+2n C (spC1) ? (pc+2) h , (spC2) ? (pc+2) l , pc 15C11 ? 00001, pc 10C0 ? addr11, sp ? spC2 callt [addr5] 1 6+n C (spC1) ? (pc+1) h , (spC2) ? (pc+1) l , pc h ? (00000000,addr5+1), pc l ? (00000000, addr5), sp ? spC2 brk 1 6+n C (spC1) ? psw, (spC2) ? (pc+1) h , (spC3) ? (pc+1) l , pc h ? (003fh), pc l ? (003eh), sp ? spC3, ie ? 0 ret 1 6+n C pc h ? (sp+1), pc l ? (sp), sp ? sp+2 reti 1 6+n C pc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3, nmis ? 0 retb 1 6+n C pc h ? (sp+1), pc l ? (sp), psw ? (sp+2), r r r sp ? sp+3 stack push psw 1 2+n C (spC1) ? psw, sp ? spC1 manipulation rp 1 4+n C (spC1) ? rp h , (spC2) ? rp l , sp ? spC2 pop psw 1 2+n C psw ? (sp), sp ? sp+1 r r r rp 1 4+n C rp h ? (sp+1), rp l ? (sp), sp ? sp+2 movw sp,#word 4 C 10+4n sp ? word sp,ax 2 C 8+2n sp ? ax ax,sp 2 C 8+2n ax ? sp unconditional br !addr16 3 6+3n C pc ? addr16 branch $addr16 2 6+2n C pc ? pc+2+jdisp8 ax 2 8+2n C pc h ? a, pc l ? x conditional bc $addr16 2 6+2n C pc ? pc+2+jdisp8 if cy=1 branch bnc $addr16 2 6+2n C pc ? pc+2+jdisp8 if cy=0 bz $addr16 2 6+2n C pc ? pc+2+jdisp8 if z=1 bnz $addr16 2 6+2n C pc ? pc+2+jdisp8 if z=0 notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched.
77 chapter 4 instruction set instruction clock flag mnemonic operands byte operation group note 1 note 2 zaccy conditional bt saddr.bit,$addr16 3 8+3n 9+3n pc ? pc+3+jdisp8 if (saddr.bit)=1 branch sfr.bit,$addr16 4 C 11+4n pc ? pc+4+jdisp8 if sfr.bit=1 a.bit,$addr16 3 8+3n C pc ? pc+3+jdisp8 if a.bit=1 psw.bit,$addr16 3 C 9+3n pc ? pc+3+jdisp8 if psw.bit=1 [hl].bit,$addr16 3 10+3n 11+4n pc ? pc+3+jdisp8 if (hl).bit=1 bf saddr.bit,$addr16 4 10+4n 11+4n pc ? pc+4+jdisp8 if (saddr.bit)=0 sfr.bit,$addr16 4 C 11+4n pc ? pc+4+jdisp8 if sfr.bit=0 a.bit,$addr16 3 8+3n C pc ? pc+3+jdisp8 if a.bit=0 psw.bit,$addr16 4 C 11+4n pc ? pc+4+jdisp8 if psw.bit=0 [hl].bit,$addr16 3 10+3n 11+4n pc ? pc+3+jdisp8 if (hl).bit=0 btclr saddr.bit,$addr16 4 10+4n 12+4n pc ? pc+4+jdisp8 if (saddr.bit)=1 then reset (saddr.bit) sfr.bit,$addr16 4 C 12+4n pc ? pc+4+jdisp8 if sfr.bit=1 then reset sfr.bit a.bit,$addr16 3 8+3n C pc ? pc+3+jdisp8 if a.bit=1 then reset a.bit psw.bit,$addr16 4 C 12+4n pc ? pc+4+jdisp8 if psw.bit=1 then reset psw.bit [hl].bit,$addr16 3 10+3n 12+4n+m pc ? pc+3+jdisp8 if (hl).bit=1 then reset (hl).bit dbnz b,$addr16 2 6+2n C b ? bC1, then pc ? pc+2+jdisp8 if b 1 0 c,$addr16 2 6+2n C c ? cC1, then pc ? pc+2+jdisp8 if c 1 0 saddr,$addr16 3 8+3n 10+3n (saddr) ? (saddr)C1, then pc ? pc+3+jdisp8 if (saddr) 1 0 cpu sel rbn 2 4+2n C rbs1,0 ? n control nop 1 2+n C no operation ei 2 C 6+2n ie ? 1 (enable interrupt) di 2 C 6+2n ie ? 0 (disable interrupt) halt 2 6+2n C set halt mode stop 2 6+2n C set stop mode notes 1. when the internal high-speed ram area is accessed or in the instruction with no data access. 2. when an area except the internal high-speed ram area is accessed. remarks 1. 1 instruction clock cycle is 1 cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). 2. n indicates the number of waits per byte when the external memory expansion area is read or fetched. 3. m indicates the number of waits when the external memory expansion area is written to.
78 chapter 4 instruction set 4.1.6 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu note , divuw note , inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note the m pd78002/78002y subseries have no mulu/divuw instructions.
79 chapter 4 instruction set 2nd operand [hl+byte] #byte a r note 1 sfr saddr !addr16 psw [de] [hl] [hl+b] $addr16 1 none 1st operand [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu note2 c divuw note2 notes 1. except r = a. 2. the m pd78002/78002y subseries have no mulu/divuw instructions.
80 chapter 4 instruction set 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1` btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de or hl. (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr
81 chapter 4 instruction set (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instructions br call callf callt br br bc bnc bz bnz compound instructions bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
82 chapter 4 instruction set 4.2 instruction codes 4.2.1 description of instruction code table rrprb r 2 r 1 r 0 reg p 1 p 0 reg-pair rb 1 rb 0 reg-bank 0 0 0 r0 x 0 0 rp0 ax 0 0 rb0 0 0 1 r1 a 0 1 rp1 bc 0 1 rb1 0 1 0 r2 c 1 0 rp2 de 1 0 rb2 0 1 1 r3 b 1 1 rp3 hl 1 1 rb3 100r4e 101r5d 110r6l 111r7h bn : immediate data corresponding to bit data : 8-bit immediate data corresponding to byte low/high byte : 16-bit immediate data corresponding to word saddr-offset : 16-bit address lower 8-bit offset data corresponding to saddr sfr-offset : sfr 16-bit address lower 8-bit offset data low/high addr : 16-bit immediate data corresponding to addr16 jdisp : signed twos complement data (8 bits) of relative address distance between the start and branch addresses of the next instruction fa 10-0 : 11 bits of immediate data corresponding to addr11 ta 4-0 : 5 bits of immediate data corresponding to addr5
83 chapter 4 instruction set 4.2.2 instruction code list instruction mnemonic operands operation code group b1 b2 b3 b4 8-bit data mov r,#byte 1010 0 r 2 r 1 r 0 data transfer saddr,#byte 0001 0001 saddr-offset data sfr,#byte 0001 0011 sfr-offset data a,r note 0110 0 r 2 r 1 r 0 r,a note 0111 0 r 2 r 1 r 0 a,saddr 1111 0000 saddr-offset saddr,a 1111 0010 saddr-offset a,sfr 1111 0100 sfr-offset sfr,a 1111 0110 sfr-offset a,!addr16 1000 1110 low addr high addr !addr16,a 1001 1110 low addr high addr psw,#byte 0001 0001 0001 1110 data a,psw 1111 0000 0001 1110 psw,a 1111 0010 0001 1110 a,[de] 1000 0101 [de],a 1001 0101 a,[hl] 1000 0111 [hl],a 1001 0111 a,[hl+byte] 1010 1110 data [hl+byte],a 1011 1110 data a,[hl+b] 1010 1011 [hl+b],a 1011 1011 a,[hl+c] 1010 1010 [hl+c],a 1011 1010 xch a,r note 0011 0 r 2 r 1 r 0 a,saddr 1000 0011 saddr-offset a,sfr 1001 0011 sfr-offset a,!addr16 1100 1110 low addr high addr a,[de] 0000 0101 a,[hl] 0000 0111 a,[hl+byte] 1101 1110 data a,[hl+b] 0011 0001 1000 1011 a,[hl+c] 0011 0001 1000 1010 note except r = a.
84 chapter 4 instruction set 16-bit data movw rp,#word 0001 0p 1 p 0 0 low byte high byte transfer saddrp,#word 1110 1110 saddr-offset low byte high byte sfrp,#word 1111 1110 sfr-offset low byte high byte ax,saddrp 1000 1001 saddr-offset saddrp,ax 1001 1001 saddr-offset ax,sfrp 1010 1001 sfr-offset sfrp,ax 1011 1001 sfr-offset ax,rp note 1 1100 0p 1 p 0 0 rp,ax note 1 1101 0p 1 p 0 0 ax,!addr16 0000 0010 low addr high addr !addr16,ax 0000 0011 low addr high addr xchw ax,rp note 1 1110 0p 1 p 0 0 8-bit add a,#byte 0000 1101 data operation saddr,#byte 1000 1000 saddr-offset data a,r note 2 0110 0001 0000 1 r 2 r 1 r 0 r,a 0110 0001 0000 0 r 2 r 1 r 0 a,saddr 0000 1110 saddr-offset a,!addr16 0000 1000 low addr high addr a,[hl] 0000 1111 a,[hl+byte] 0000 1001 data a,[hl+b] 0011 0001 0000 1011 a,[hl+c] 0011 0001 0000 1010 addc a,#byte 0010 1101 data saddr,#byte 1010 1000 saddr-offset data a,r note 2 0110 0001 0010 1 r 2 r 1 r 0 r,a 0110 0001 0010 0 r 2 r 1 r 0 a,saddr 0010 1110 saddr-offset a,!addr16 0010 1000 low addr high addr a,[hl] 0010 1111 a,[hl+byte] 0010 1001 data a,[hl+b] 0011 0001 0010 1011 a,[hl+c] 0011 0001 0010 1010 instruction mnemonic operands operation code group b1 b2 b3 b4 notes 1. only when rp = bc, de or hl. 2. except r = a.
85 chapter 4 instruction set 8-bit sub a,#byte 0001 1101 data operation saddr,#byte 1001 1000 saddr-offset data a,r note 0110 0001 0001 1 r 2 r 1 r 0 r,a 0110 0001 0001 0 r 2 r 1 r 0 a,saddr 0001 1110 saddr-offset a,!addr16 0001 1000 low addr high addr a,[hl] 0001 1111 a,[hl+byte] 0001 1001 data a,[hl+b] 0011 0001 0001 1011 a,[hl+c] 0011 0001 0001 1010 subc a,#byte 0011 1101 data saddr,#byte 1011 1000 saddr-offset data a,r note 0110 0001 0011 1 r 2 r 1 r 0 r,a 0110 0001 0011 0 r 2 r 1 r 0 a,saddr 0011 1110 saddr-offset a,!addr16 0011 1000 low addr high addr a,[hl] 0011 1111 a,[hl+byte] 0011 1001 data a,[hl+b] 0011 0001 0011 1011 a,[hl+c] 0011 0001 0011 1010 and a,#byte 0101 1101 data saddr,#byte 1101 1000 saddr-offset data a,r note 0110 0001 0101 1 r 2 r 1 r 0 r,a 0110 0001 0101 0 r 2 r 1 r 0 a,saddr 0101 1110 saddr-offset a,!addr16 0101 1000 low addr high addr a,[hl] 0101 1111 a,[hl+byte] 0101 1001 data a,[hl+b] 0011 0001 0101 1011 a,[hl+c] 0011 0001 0101 1010 instruction mnemonic operands operation code group b1 b2 b3 b4 note except r = a.
86 chapter 4 instruction set 8-bit or a,#byte 0110 1101 data operation saddr,#byte 1110 1000 saddr-offset data a,r note 0110 0001 0110 1 r 2 r 1 r 0 r,a 0110 0001 0110 0 r 2 r 1 r 0 a,saddr 0110 1110 saddr-offset a,!addr16 0110 1000 low addr high addr a,[hl] 0110 1111 a,[hl+byte] 0110 1001 data a,[hl+b] 0011 0001 0110 1011 a,[hl+c] 0011 0001 0110 1010 xor a,#byte 0111 1101 data saddr,#byte 1111 1000 saddr-offset data a,r note 0110 0001 0111 1 r 2 r 1 r 0 r,a 0110 0001 0111 0 r 2 r 1 r 0 a,saddr 0111 1110 saddr-offset a,!addr16 0111 1000 low addr high addr a,[hl] 0111 1111 a,[hl+byte] 0111 1001 data a,[hl+b] 0011 0001 0111 1011 a,[hl+c] 0011 0001 0111 1010 cmp a,#byte 0100 1101 data saddr,#byte 1100 1000 saddr-offset data a,r note 0110 0001 0100 1 r 2 r 1 r 0 r,a 0110 0001 0100 0 r 2 r 1 r 0 a,saddr 0100 1110 saddr-offset a,!addr16 0100 1000 low addr high addr a,[hl] 0100 1111 a,[hl+byte] 0100 1001 data a,[hl+b] 0011 0001 0100 1011 a,[hl+c] 0011 0001 0100 1010 instruction mnemonic operands operation code group b1 b2 b3 b4 note except r = a.
87 chapter 4 instruction set 16-bit addw ax,#word 1100 1010 low byte high byte operation subw ax,#word 1101 1010 low byte high byte cmpw ax,#word 1110 1010 low byte high byte multiply/ mulu note x 0011 0001 1000 1000 divide divuw note c 0011 0001 1000 0010 increment/ inc r 0100 0 r 2 r 1 r 0 decrement saddr 1000 0001 saddr-offset dec r 0101 0 r 2 r 1 r 0 saddr 1001 0001 saddr-offset incw rp 1000 0 p 1 p 0 0 decw rp 1001 0 p 1 p 0 0 rotate ror a,1 0010 0100 rol a,1 0010 0110 rorc a,1 0010 0101 rolc a,1 0010 0111 ror4 [hl] 0011 0001 1001 0000 rol4 [hl] 0011 0001 1000 0000 bcd adjba 0110 0001 1000 0000 adjust adjbs 0110 0001 1001 0000 bit mov1 cy,saddr.bit 0111 0001 0 b 2 b 1 b 0 0100 saddr-offset manipulation cy,sfr.bit 0111 0001 0 b 2 b 1 b 0 1100 sfr-offset cy,a.bit 0110 0001 1 b 2 b 1 b 0 1100 cy,psw.bit 0111 0001 0 b 2 b 1 b 0 0100 0001 1110 cy,[hl].bit 0111 0001 1 b 2 b 1 b 0 0100 saddr.bit,cy 0111 0001 0 b 2 b 1 b 0 0001 saddr-offset sfr.bit,cy 0111 0001 0 b 2 b 1 b 0 1001 sfr-offset a.bit,cy 0110 0001 1 b 2 b 1 b 0 1001 psw.bit,cy 0111 0001 0 b 2 b 1 b 0 0001 0001 1110 [hl].bit,cy 0111 0001 1 b 2 b 1 b 0 0001 and1 cy,saddr.bit 0111 0001 0 b 2 b 1 b 0 0101 saddr-offset cy,sfr.bit 0111 0001 0 b 2 b 1 b 0 1101 sfr-offset cy,a.bit 0110 0001 1 b 2 b 1 b 0 1101 cy,psw.bit 0111 0001 0 b 2 b 1 b 0 0101 0001 1110 cy,[hl].bit 0111 0001 1 b 2 b 1 b 0 0101 instruction mnemonic operands operation code group b1 b2 b3 b4 note the m pd78002/78002y subseries have no mulu/divuw instructions.
88 chapter 4 instruction set bit or1 cy,saddr.bit 0111 0001 0 b 2 b 1 b 0 0110 saddr-offset manipulation cy,sfr.bit 0111 0001 0 b 2 b 1 b 0 1110 sfr-offset cy,a.bit 0110 0001 1 b 2 b 1 b 0 1110 cy,psw.bit 0111 0001 0 b 2 b 1 b 0 0110 0001 1110 cy,[hl].bit 0111 0001 1 b 2 b 1 b 0 0110 xor1 cy,saddr.bit 0111 0001 0 b 2 b 1 b 0 0111 saddr-offset cy,sfr.bit 0111 0001 0 b 2 b 1 b 0 1111 sfr-offset cy,a.bit 0110 0001 1 b 2 b 1 b 0 1111 cy,psw.bit 0111 0001 0 b 2 b 1 b 0 0111 0001 1110 cy,[hl].bit 0111 0001 1 b 2 b 1 b 0 0111 set1 saddr.bit 0 b 2 b 1 b 0 1010 saddr-offset sfr.bit 0111 0001 0 b 2 b 1 b 0 1010 sfr-offset a.bit 0110 0001 1 b 2 b 1 b 0 1010 psw.bit 0 b 2 b 1 b 0 1010 0001 1110 [hl].bit 0111 0001 1 b 2 b 1 b 0 0010 clr1 saddr.bit 0 b 2 b 1 b 0 1011 saddr-offset sfr.bit 0111 0001 0 b 2 b 1 b 0 1011 sfr-offset a.bit 0110 0001 1 b 2 b 1 b 0 1011 psw.bit 0 b 2 b 1 b 0 1011 0001 1110 [hl].bit 0111 0001 1 b 2 b 1 b 0 0011 set1 cy 0010 0000 clr1 cy 0010 0001 not1 cy 0000 0001 call return call !addr16 1001 1010 low addr high addr callf !addr11 0 fa 10C8 1100 fa 7C0 callt [addr5] 1 1 ta 4C0 1 brk 1011 1111 ret 1010 1111 retb 1001 1111 reti 1000 1111 stack push psw 0010 0010 manipulation rp 1011 0 p 1 p 0 1 pop psw 0010 0011 rp 1011 0 p 1 p 0 0 movw sp,#word 1110 1110 0001 1100 low byte high byte sp,ax 1001 1001 0001 1100 ax,sp 1000 1001 0001 1100 instruction mnemonic operands operation code group b1 b2 b3 b4
89 chapter 4 instruction set unconditional br !addr16 1001 1011 low addr high addr branch $addr16 1111 1010 jdisp ax 0011 0001 1001 1000 conditional bc $addr16 1000 1101 jdisp branch bnc $addr16 1001 1101 jdisp bz $addr16 1010 1101 jdisp bnz $addr16 1011 1101 jdisp bt saddr.bit,$addr16 1 b 2 b 1 b 0 1 1 0 0 saddr-offset jdisp sfr.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0110 sfr-offset jdisp a.bit,$addr16 0011 0001 0 b 2 b 1 b 0 1110 jdisp psw.bit,$addr16 1 b 2 b 1 b 0 1100 0001 1110 jdisp [hl].bit,$addr16 0011 0001 1 b 2 b 1 b 0 0110 jdisp bf saddr.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0011 saddr-offset jdisp sfr.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0111 sfr-offset jdisp a.bit,$addr16 0011 0001 0 b 2 b 1 b 0 1111 jdisp psw.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0011 0001 1110 jdisp [hl].bit,$addr16 0011 0001 1 b 2 b 1 b 0 0111 jdisp btclr saddr.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0001 saddr-offset jdisp sfr.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0101 sfr-offset jdisp a.bit,$addr16 0011 0001 0 b 2 b 1 b 0 1101 jdisp psw.bit,$addr16 0011 0001 0 b 2 b 1 b 0 0001 0001 1110 jdisp [hl].bit,$addr16 0011 0001 1 b 2 b 1 b 0 0101 jdisp dbnz b,$addr16 1000 1011 jdisp c,$addr16 1000 1010 jdisp saddr,$addr16 0000 0100 saddr-offset jdisp cpu sel rbn 0110 0001 11 rb 1 1 rb 0 000 control nop 0000 0000 ei 0111 1010 0001 1110 di 0111 1011 0001 1110 halt 0111 0001 0001 0000 stop 0111 0001 0000 0000 instruction mnemonic operands operation code group b1 b2 b3 b4
90 chapter 4 instruction set [memo]
91 chapter 5 explanation of instructions chapter 5 explanation of instructions this chapter covers the explanation of the 78k/0 series products instructions. each instruction is described with a mnemonic, including description of multiple operands. the basic configuration of instruction description is shown on the next page. for the number of instruction bytes and the operation code, refer to chapter 4 instruction set . all the instructions are common to the 78k/0 series products.
92 chapter 5 explanation of instructions description example mnemonic full name move mov byte data transfer meaning of instruction [instruction format] mov dst, src: indicates the basic description format of the instruction. [operation] dst ? src: indicates instruction operation using symbols. [operand] indicates operands which can be specified with this instruction. refer to 4.1 operation for the description of each operand symbol. mnemonic operand(dst,src) mnemonic operand(dst,src) mov r, #byte mov a, psw a, saddr [hl], a saddr, a a, [hl+byte] psw, #byte [hl+c], a [flag] indicates the flag operation which changes by instruction execution. each flag operation symbol is shown in the legend. zaccy legend symbol description blank unchanged 0 cleared to 0 1 set to 1 x set or cleared according to the result r previously saved value is restored [description] : describes the instruction operation in detail. ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. [description example] mov a, #4dh; 4dh is transferred to a register. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
93 chapter 5 explanation of instructions 5.1 8-bit data transfer instructions the following instructions are 8-bit data transfer instructions. mov ... 94 xch ... 95
94 chapter 5 explanation of instructions move mov byte data transfer [instruction format] mov dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) mov r, #byte mov a, psw saddr, #byte psw, a sfr, #byte a, [de] a, r note [de], a r, a note a, [hl] a, saddr [hl], a saddr, a a, [hl+byte] a, sfr [hl+byte], a sfr, a a, [hl+b] a, !addr16 [hl+b], a !addr16, a a, [hl+c] psw, #byte [hl+c], a note except r = a [flag] psw, #byte and psw, all other operand a operands combinations z ac cy z ac cy [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. ? none of the interrupts is acknowledged between the mov psw, #byte instruction/the mov psw, a instruction and the next one instruction. [description example] mov a, #4dh; 4dh is transferred to a register.
95 chapter 5 explanation of instructions exchange xch byte data exchange [instruction format] xch dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) xch a, r note xch a, [hl] a, saddr a, [hl+byte] a, sfr a, [hl+b] a, !addr16 a, [hl+c] a, [de] note except r = a [flag] zaccy [description] ? the 1st and 2nd operand contents are exchanged. [description example] xch a, febch; the a register contents and address febch contents are exchanged.
96 chapter 5 explanation of instructions 5.2 16-bit data transfer instructions the following instructions are 16-bit data transfer instructions. movw ... 97 xchw ... 98
97 chapter 5 explanation of instructions move word movw word data transfer [instruction format] movw dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) movw rp, #word movw sfrp, ax saddrp, #word ax, rp note sfrp, #word rp, ax note ax, saddrp ax, !addr16 saddrp, ax !addr16, ax ax, sfrp note only when rp = bc, de or hl [flag] zaccy [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. [description example] movw ax, hl; the hl register contents are transferred to the ax register. [caution] only an even address can be specified. an odd address cannot be specified.
98 chapter 5 explanation of instructions exchange word xchw word data exchange [instruction format] xchw dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) xchw ax, rp note note only when rp = bc, de or hl [flag] zaccy [description] ? the 1st and 2nd operand contents are exchanged. [description example] xchw ax, bc; the memory contents of ax register are exchanged with those of the bc register.
99 chapter 5 explanation of instructions 5.3 8-bit operation instructions the following are 8-bit operation instructions. add ... 100 addc ... 101 sub ... 102 subc ... 103 and ... 104 or ... 105 xor ... 106 cmp ... 107
100 chapter 5 explanation of instructions add add byte data addition [instruction format] add dst, src [operation] dst, cy ? dst + src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) add a, #byte add a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? the destination operand (dst) specified with the 1st operand is added to the source operand (src) specified with the 2nd operand and the result is stored in the cy flag and the destination operand (dst). ? if the addition result shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the addition generates a carry out of bit 7, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? if the addition generates a carry for bit 4 out of bit 3, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). [description example] add cr10, #56h; 56h is added to the cr10 register and the result is stored in the cr10 register.
101 chapter 5 explanation of instructions add with carry addc addition of byte data with carry [instruction format] addc dst, src [operation] dst, cy ? dst + src + cy [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) addc a, #byte addc a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? the destination operand (dst) specified with the 1st operand, the source operand (src) specified with the 2nd operand and the cy flag are added and the result is stored in the destination operand (dst) and the cy flag. the cy flag is added to the least significant bit. this instruction is mainly used to add two or more bytes. ? if the addition result shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the addition generates a carry out of bit 7, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? if the addition generates a carry for bit 4 out of bit 3, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). [description example] addc a, [hl+b]; the a register contents and the contents at address (hl register + (b register)) and the cy flag are added and the result is stored in the a register.
102 chapter 5 explanation of instructions subtract sub byte data subtraction [instruction format] sub dst, src [operation] dst, cy ? dst C src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) sub a, #byte sub a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? the source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst) and the cy flag. the destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst). ? if the subtraction shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the subtraction generates a borrow out of bit 7, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? if the subtraction generates a borrow for bit 3 out of bit 4, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). [description example] sub d, a; the a register is subtracted from the d register and the result is stored in the d register.
103 chapter 5 explanation of instructions subtract with carry subc subtraction of byte data with carry [instruction format] subc dst, src [operation] dst, cy ? dst C src C cy [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) subc a, #byte subc a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? the source operand (src) specified with the 2nd operand and the cy flag are subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst). the cy flag is subtracted from the least significant bit. this instruction is mainly used for subtraction of two or more bytes. ? if the subtraction shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the subtraction generates a borrow out of bit 7, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? if the subtraction generates a borrow for bit 3 out of bit 4, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). [description example] subc a, [hl]; the (hl register) address contents and the cy flag are subtracted from the a register and the result is stored in the a register.
104 chapter 5 explanation of instructions and and logical product of byte data [instruction format] and dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) and a, #byte and a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? bit-wise logical product is obtained from the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst). ? if the logical product shows that all bits are 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). [description example] and febah, #11011100b; bit-wise logical product of febah contents and 11011100b is obtained and the result is stored at febah.
105 chapter 5 explanation of instructions or or logical sum of byte data [instruction format] or dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) or a, #byte or a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? bit-wise logical sum is obtained from the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst). ? if the logical sum shows that all bits are 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). [description example] or a, fe98h; bit-wise logical sum of the a register and fe98h is obtained and the result is stored in the a register.
106 chapter 5 explanation of instructions exclusive or xor exclusive logical sum of byte data [instruction format] xor dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) xor a, #byte xor a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? bit-wise exclusive logical sum is obtained from the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst). logical negation of all bits of the destination operand (dst) is possible by selecting #0ffh for the source operand (src) with this instruction. ? if the exclusive logical sum shows that all bits are 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). [description example] xor a, l; bit-wise exclusive logical sum of the a and l registers is obtained and the result is stored in the a register.
107 chapter 5 explanation of instructions compare cmp byte data comparison [instruction format] cmp dst, src [operation] dst C src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) cmp a, #byte cmp a, !addr16 saddr, #byte a, [hl] a, r note a, [hl+byte] r, a a, [hl+b] a, saddr a, [hl+c] note except r = a [flag] zaccy [description] ? the source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand. the subtraction result is not stored anywhere and only the z, ac and cy flags are changed. ? if the subtraction result is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the subtraction generates a borrow out of bit 7, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? if the subtraction generates a borrow for bit 3 out of bit 4, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). [description example] cmp fe38h, #38h; 38h is subtracted from the contents at address fe38h and only the flags are changed (comparison of contents at address fe38h and the immediate data).
108 chapter 5 explanation of instructions 5.4 16-bit operation instructions the following are 16-bit operation instructions. addw ... 109 subw ... 110 cmpw ... 111
109 chapter 5 explanation of instructions add word addw word data addition [instruction format] addw dst, src [operation] dst, cy ? dst + src [operand] mnemonic operand(dst,src) addw ax, #word [flag] zaccy [description] ? the destination operand (dst) specified with the 1st operand is added to the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst). ? if the addition result shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the addition generates a carry out of bit 15, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? as a result of addition, the ac flag becomes undefined. [description example] addw ax, #abcdh; abcdh is added to the ax register and the result is stored in the ax register.
110 chapter 5 explanation of instructions subtract word subw word data subtraction [instruction format] subw dst, src [operation] dst, cy ? dst C src [operand] mnemonic operand(dst,src) subw ax, #word [flag] zaccy [description] ? the source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst) and the cy flag. the destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst). ? if the subtraction shows that dst is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the subtraction generates a borrow out of bit 15, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? as a result of subtraction, the ac flag becomes undefined. [description example] subw ax, #abcdh; abcdh is subtracted from the ax register contents and the result is stored in the ax register.
111 chapter 5 explanation of instructions compare word cmpw word data comparison [instruction format] cmpw dst, src [operation] dst C src [operand] mnemonic operand(dst,src) cmpw ax, #word [flag] zaccy [description] ? the source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand. the subtraction result is not stored anywhere and only the z, ac and cy flags are changed. ? if the subtraction result is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the subtraction generates a borrow out of bit 15, the cy flag is set to (1). in all other cases, the cy flag is cleared to (0). ? as a result of subtraction, the ac flag becomes undefined. [description example] cmpw ax, #abcdh; abcdh is subtracted from the ax register and only the flags are changed (comparison of the ax register and the immediate data).
112 chapter 5 explanation of instructions 5.5 multiply/divide instructions the following are multiply/divide instructions. mulu ... 113 divuw ... 114 caution the m pd78002/78002y subseries have no mulu/divuw instructions.
113 chapter 5 explanation of instructions multiply unsigned mulu unsigned multiplication of data [instruction format] mulu src [operation] ax ? a src [operand] mnemonic operand(src) mulu x [flag] zaccy [description] ? the a register contents and the source operand (src) data are multiplied as unsigned data and the result is stored in the ax register. [description example] mulu x; the a register contents and the x register contents are multiplied and the result is stored in the ax register.
114 chapter 5 explanation of instructions divide unsigned word divuw unsigned division of word data [instruction format] divuw dst [operation] ax (quotient), dst (remainder) ? ax ? dst [operand] mnemonic operand(dst) divuw c [flag] zaccy [description] ? the ax register contents are divided with the destination operand (dst) contents and the quotient and the remainder are stored in the ax register and the destination operand (dst), respectively. division is executed using the ax register and destination operand (dst) contents as unsigned data. however, when the destination operand (dst) is 0, the x register contents are stored in the c register and ax becomes 0ffffh. [description example] divuw c; the ax register contents are divided by the c register contents and the quotient and the remainder are stored in the ax register and the c register, respectively.
115 chapter 5 explanation of instructions 5.6 increment/decrement instructions the following are increment/decrement instructions. inc ... 116 dec ... 117 incw ... 118 decw ... 119
116 chapter 5 explanation of instructions increment inc byte data increment [instruction format] inc dst [operation] dst ? dst + 1 [operand] mnemonic operand(dst) inc r saddr [flag] zaccy [description] ? the destination operand (dst) contents are incremented by only one. ? if the increment result is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the increment generates a carry for bit 4 out of bit 3, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). ? because this instruction is frequently used for increment of a counter for repeated operations and an indexed addressing offset register, the cy flag contents are not changed (to hold the cy flag contents in multiple- byte operation). [description example] inc b; the b register is incremented.
117 chapter 5 explanation of instructions decrement dec byte data decrement [instruction format] dec dst [operation] dst ? dst C 1 [operand] mnemonic operand(dst) dec r saddr [flag] zaccy [description] ? the destination operand (dst) contents are decremented by only one. ? if the decrement result is 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). ? if the decrement generates a carry for bit 3 out of bit 4, the ac flag is set to (1). in all other cases, the ac flag is cleared to (0). ? because this instruction is frequently used for decrement of a counter for repeated operations and an indexed addressing offset register, the cy flag contents are not changed (to hold the cy flag contents in multiple- byte operation). ? if dst is the b or c register or saddr, and it is not desired to change the ac and cy flag contents, the dbnz instruction can be used. [description example] dec fe92h; the contents at address fe92h are decremented.
118 chapter 5 explanation of instructions increment word incw word data increment [instruction format] incw dst [operation] dst ? dst + 1 [operand] mnemonic operand(dst) incw rp [flag] zaccy [description] ? the destination operand (dst) contents are incremented by only one. ? because this instruction is frequently used for increment of a register (pointer) used for addressing, the z, ac and cy flag contents are not changed. [description example] incw hl; the hl register is incremented.
119 chapter 5 explanation of instructions decrement word decw word data decrement [instruction format] decw dst [operation] dst ? dst C 1 [operand] mnemonic operand (dst) decw rp [flag] zaccy [description] ? the destination operand (dst) contents are decremented by only one. ? because this instruction is frequently used for decrement of a register (pointer) used for addressing, the z, ac and cy flag contents are not changed. [description example] decw de; the de register is decremented.
120 chapter 5 explanation of instructions 5.7 rotate instructions the following are rotate instructions. ror ... 121 rol ... 122 rorc ... 123 rolc ... 124 ror4 ... 125 rol4 ... 126
121 chapter 5 explanation of instructions rotate right ror byte data rotation to the right [instruction format] ror dst, cnt [operation] (cy, dst 7 ? dst 0 , dst mC1 ? dst m ) one time [operand] mnemonic operand(dst,cnt) ror a, 1 [flag] zaccy [description] ? the destination operand (dst) contents specified with the 1st operand are rotated to the right just once. ? the lsb (bit 0) contents are simultaneously rotated to msb (bit 7) and transferred to the cy flag. [description example] ror a, 1; the a register contents are rotated one bit to the right. cy 0 7
122 chapter 5 explanation of instructions rotate left rol byte data rotation to the left [instruction format] rol dst, cnt [operation] (cy, dst 0 ? dst 7 , dst m+1 ? dst m ) one time [operand] mnemonic operand(dst,cnt) rol a, 1 [flag] zaccy [description] ? the destination operand (dst) contents specified with the 1st operand are rotated to the left just once. ? the msb (bit 7) contents are simultaneously rotated to lsb (bit 0) and transferred to the cy flag. [description example] rol a, 1; the a register contents are rotated to the left by one bit. cy 0 7
123 chapter 5 explanation of instructions rotate right with carry rorc byte data rotation to the right with carry [instruction format] rorc dst, cnt [operation] (cy ? dst 0 , dst 7 ? cy, dst mC1 ? dst m ) one time [operand] mnemonic operand(dst,cnt) rorc a, 1 [flag] zaccy [description] ? the destination operand (dst) contents specified with the 1st operand are rotated just once to the right with carry. [description example] rorc a, 1; the a register contents are rotated to the right by one bit including the cy flag. cy 0 7
124 chapter 5 explanation of instructions rotate left with carry rolc byte data rotation to the left with carry [instruction format] rolc dst, cnt [operation] (cy ? dst 7 , dst 0 ? cy, dst m+1 ? dst m ) one time [operand] mnemonic operand(dst,cnt) rolc a, 1 [flag] zaccy [description] ? the destination operand (dst) contents specified with the 1st operand are rotated just once to the left with carry. [description example] rolc a, 1; the a register contents are rotated to the left by one bit including the cy flag. cy 0 7
125 chapter 5 explanation of instructions rotate right digit ror4 digit rotation to the right [instruction format] ror4 dst [operation] a 3-0 ? (dst) 3-0 , (dst) 7-4 ? a 3-0 , (dst) 3-0 ? (dst) 7-4 [operand] mnemonic operand(dst) ror4 [hl] note note specify an area other than the sfr area as operand [hl]. [flag] zaccy [description] the lower 4 bits of the a register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the right. the higher 4 bits of the a register remain unchanged. [description example] ror4 [hl]; rightward digit rotation is executed with the memory contents specified with the a and hl registers. a (hl) 7430 7430 before execution 1010 0011 1100 0101 after execution 1010 0101 0011 1100 0 0 3 4 7 dst 3 4 7 a
126 chapter 5 explanation of instructions rotate left digit rol4 digit rotation to the left [instruction format] rol4 dst [operation] a 3-0 ? (dst) 7-4 , (dst) 3-0 ? a 3-0 , (dst) 7-4 ? (dst) 3-0 [operand] mnemonic operand(dst) rol4 [hl] note note specify an area other than the sfr area as operand [hl]. [flag] zaccy [description] ? the lower 4 bits of the a register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the left. the higher 4 bits of the a register remain unchanged. [description example] rol4 [hl]; leftward digit rotation is executed with the memory contents specified with the a and hl registers. a (hl) 7430 7430 before execution 0001 0010 0100 1000 after execution 0001 0100 1000 0010 0 0 3 4 7 dst 3 4 7 a
127 chapter 5 explanation of instructions 5.8 bcd adjust instructions the following are bcd adjust instructions. adjba ... 128 adjbs ... 129
128 chapter 5 explanation of instructions decimal adjust register for addition adjba decimal adjustment of addition result [instruction format] adjba [operation] decimal adjust accumulator for addition [operand] none [flag] zaccy [description] ? the a register, cy flag and ac flag are decimally adjusted from their contents. this instruction carries out an operation having meaning only when the bcd (binary coded decimal) data is added and the addition result is stored in the a register (in all other cases, the instruction carries out an operation having no meaning). see the table below for the adjustment method. ? if the adjustment result shows that the a register contents are 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). condition operation a 3 to a 0 9a 7 to a 4 9 and cy = 0 a ? a, cy ? 0, ac ? 0 ac = 0 a 7 to a 4 3 10 or cy = 1 a ? a+01100000b, cy ? 1, ac ? 0 a 3 to a 0 3 10 a 7 to a 4 < 9 and cy = 0 a ? a+00000110b, cy ? 0, ac ? 1 ac = 0 a 7 to a 4 3 9 or cy = 1 a ? a+01100110b, cy ? 1, ac ? 1 ac = 1 a 7 to a 4 9 and cy = 0 a ? a+00000110b, cy ? 0, ac ? 0 a 7 to a 4 3 10 or cy = 1 a ? a+01100110b, cy ? 1, ac ? 0
129 chapter 5 explanation of instructions decimal adjust register for subtraction adjbs decimal adjustment of subtraction result [instruction format] adjbs [operation] decimal adjust accumulator for subtraction [operand] none [flag] zaccy [description] ? the a register, cy flag and ac flag are decimally adjusted from their contents. this instruction carries out an operation having meaning only when the bcd (binary coded decimal) data is subtracted and the subtraction result is stored in the a register (in all other cases, the instruction carries out an operation having no meaning). see the table below for the adjustment method. ? if the adjustment result shows that the a register contents are 0, the z flag is set to (1). in all other cases, the z flag is cleared to (0). condition operation ac = 0 cy = 0 a ? a, cy ? 0, ac ? 0 cy = 1 a ? aC01100000b, cy ? 1, ac ? 0 ac = 1 cy = 0 a ? aC00000110b, cy ? 0, ac ? 0 cy = 1 a ? aC01100110b, cy ? 1, ac ? 0
130 chapter 5 explanation of instructions 5.9 bit manipulation instructions the following are bit manipulation instructions. mov1 ... 131 and1 ... 132 or1 ... 133 xor1 ... 134 set1 ... 135 clr1 ... 136 not1 ... 137
131 chapter 5 explanation of instructions move single bit mov1 1 bit data transfer [instruction format] mov1 dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) mnemonic operand(dst,src) mov1 cy, saddr.bit mov1 saddr.bit, cy cy, sfr.bit sfr.bit, cy cy, a.bit a.bit, cy cy, psw.bit psw.bit, cy cy, [hl].bit [hl].bit, cy [flag] dst = cy psw.bit in all other cases z ac cy z ac cy z ac cy [description] ? bit data of the source operand (src) specified with the 2nd operand is transferred to the destination operand (dst) specified with the 1st operand. ? when the destination operand (dst) is cy or psw.bit, only the corresponding flag is changed. [description example] mov1 p3.4, cy; the cy flag contents are transferred to bit 4 of port 3.
132 chapter 5 explanation of instructions and single bit and1 1 bit data logical product [instruction format] and1 dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) and1 cy, saddr.bit cy, sfr.bit cy, a.bit cy, psw.bit cy, [hl].bit [flag] zaccy [description] ? logical product of bit data of the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand is obtained and the result is stored in the destination operand (dst). ? the operation result is stored in the cy flag (because of the destination operand (dst)). [description example] and1 cy, fe7fh.3; logical product of fe7fh bit 3 and the cy flag is obtained and the result is stored in the cy flag.
133 chapter 5 explanation of instructions or single bit or1 1 bit data logical sum [instruction format] or1 dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) or1 cy, saddr.bit cy, sfr.bit cy, a.bit cy, psw.bit cy, [hl].bit [flag] zaccy [description] ? logical sum of bit data of the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand is obtained and the result is stored in the destination operand (dst). ? the operation result is stored in the cy flag (because of the destination operand (dst)). [description example] or1 cy, p2.5; logical sum or port 2 bit 5 and the cy flag is obtained and the result is stored in the cy flag.
134 chapter 5 explanation of instructions exclusive or single bit xor1 1 bit data exclusive logical sum [instruction format] xor1 dst, src [operation] dst ? dst src [operand] mnemonic operand(dst,src) xor1 cy, saddr.bit cy, sfr.bit cy, a.bit cy, psw.bit cy, [hl].bit [flag] zaccy [description] ? exclusive logical sum of bit data of the destination operand (dst) specified with the 1st operand and the source operand (src) specified with the 2nd operand is obtained and the result is stored in the destination operand (dst). ? the operation result is stored in the cy flag (because of the destination operand (dst)). [description example] xor1 cy, a.7; exclusive logical sum of a register bit 7 and the cy flag is obtained and the result is stored in the cy flag.
135 chapter 5 explanation of instructions set single bit (carry flag) set1 1 bit data set [instruction format] set1 dst [operation] dst ? 1 [operand] mnemonic operand(dst) set1 saddr.bit sfr.bit a.bit psw.bit [hl].bit cy [flag] dst = psw.bit dst = cy in all other cases z ac cy z ac cy z ac cy 1 [description] ? the destination operand (dst) is set to (1). ? when the destination operand (dst) is cy or psw.bit, only the corresponding flag is set to (1). [description example] set1 fe55h.1; bit 1 of fe55h is set to (1).
136 chapter 5 explanation of instructions clear single bit (carry flag) clr1 1 bit data clear [instruction format] clr1 dst [operation] dst ? 0 [operand] mnemonic operand(dst) clr1 saddr.bit sfr.bit a.bit psw.bit [hl].bit cy [flag] dst = psw.bit dst = cy in all other cases z ac cy z ac cy z ac cy 0 [description] ? the destination operand (dst) is cleared to (0). ? when the destination operand (dst) is cy or psw.bit, only the corresponding flag is cleared to (0). [description example] clr1 p3.7; bit 7 of port 3 is cleared to (0).
137 chapter 5 explanation of instructions not single bit (carry flag) not1 1 bit data logical negation [instruction format] not1 dst [operation] dst ? dst [operand] mnemonic operand(dst) not1 cy [flag] zaccy [description] ? the cy flag is inverted. [description example] not1 cy; the cy flag is inverted.
138 chapter 5 explanation of instructions 5.10 call return instructions the following are call return instructions. call ... 139 callf ... 140 callt ... 141 brk ... 142 ret ... 143 reti ... 144 retb ... 145
139 chapter 5 explanation of instructions call call subroutine call (16 bit direct) [instruction format] call target [operation] (spC1) ? (pc+3) h , (spC2) ? (pc+3) l , sp ? spC2, pc ? target [operand] mnemonic operand(target) call !addr16 [flag] zaccy [description] ? this is a subroutine call with a 16-bit absolute address or a register indirect address. ? the start address (pc+3) of the next instruction is saved in the stack and is branched to the address specified with the target operand (target). [description example] call !3059h; subroutine call to 3059h
140 chapter 5 explanation of instructions call flag callf subroutine call (11 bit direct specification) [instruction format] callf target [operation] (spC1) ? (pc+2) h , (spC2) ? (pc+2) l , sp ? spC2, pc ? target [operand] mnemonic operand(target) callf !addr11 [flag] zaccy [description] ? this is a subroutine call which can only be branched to addresses 0800h to 0fffh. ? the start address (pc+2) of the next instruction is saved in the stack and is branched in the range of addresses 0800h to 0fffh. ? only the lower 11 bits of an address are specified (with the higher 5 bits fixed to 00001b). ? the program size can be compressed by locating the subroutine at 0800h to 0fffh and using this instruction. if the program is in the external memory, the execution time can be decreased. [description example] callf !0c2ah; subroutine call to 0c2ah
141 chapter 5 explanation of instructions call table callt subroutine call (refer to the call table) [instruction format] callt [addr5] [operation] (spC1) ? (pc+1) h , (spC2) ? (pc+1) l , sp ? spC2, pc h ? (00000000, addr5+1) pc l ? (00000000, addr5) [operand] mnemonic operand([addr5]) callt [addr5] [flag] zaccy [description] ? this is a subroutine call for call table reference. ? the start address (pc+1) of the next instruction is saved in the stack and is branched to the address indicated with the word data of a call table (the higher 8 bits of address are fixed to 00000000b and the next 5 bits are specified with addr5). [description example] callt [40h]; subroutine call to the word data addresses 0040h and 0041h.
142 chapter 5 explanation of instructions break brk software vectored interrupt [instruction format] brk [operation] (spC1) ? psw, (spC2) ? (pc+1) h , (spC3) ? (pc+1) l , ie ? 0, sp ? spC3, pc h ? (3fh), pc l ? (3eh) [operand] none [flag] zaccy [description] ? this is a software interrupt instruction. ? psw and the next instruction address (pc+1) are saved in the stack. after that, the ie flag is cleared to (0) and the saved data is branched to the address indicated with the word data at the vector address (003eh). because the ie flag is cleared to (0), the subsequent maskable vectored interrupts are disabled. ? the retb instruction is used to return from the software vectored interrupt generated with this instruction.
143 chapter 5 explanation of instructions return ret return from subroutine [instruction format] ret [operation] pc l ? (sp), pc h ? (sp+1), sp ? sp+2 [operand] none [flag] zaccy [description] ? this is a return instruction from the subroutine call made with the call, callf and callt instructions. ? the word data saved in the stack returns to the pc, and the program returns from the subroutine.
144 chapter 5 explanation of instructions return from interrupt reti return from hardware vectored interrupt [instruction format] reti [operation] pc l ? (sp), pc h ? (sp+1), psw ? (sp+2), sp ? sp+3, nmis ? 0 [operand] none [flag] zaccy rrr [description] ? this is a return instruction from the vectored interrupt. ? the data saved in the stack returns to the pc and the psw, and the program returns from the interrupt service routine. ? this instruction cannot be used for return from the software interrupt with the brk instruction. ? none of interrupts are acknowledged between this instruction and the next instruction to be executed. ? the nmis flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the reti instruction. [caution] when the return from non-maskable interrupt servicing is performed by an instruction other than the reti instruction, the nmis flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts) except software interrupts can be acknowledged.
145 chapter 5 explanation of instructions return from break retb return from software vectored interrupt [instruction format] retb [operation] pc l ? (sp), pc h ? (sp+1), psw ? (sp+2), sp ? sp+3 [operand] none [flag] zaccy rrr [description] ? this is a return instruction from the software interrupt generated with the brk instruction. ? the data saved in the stack returns to the pc and the psw, and the program returns from the interrupt service routine. ? none of interrupts are acknowledged between this instruction and the next instruction to be executed.
146 chapter 5 explanation of instructions 5.11 stack manipulation instructions the following are stack manipulation instructions. push ... 147 pop ... 148 movw sp, src ... 149 movw ax, sp ... 149
147 chapter 5 explanation of instructions push push push [instruction format] push src [operation] when src = rp when src = psw (spC1) ? src h , (spC1) ? src (spC2) ? src l ,sp ? spC1 sp ? spC2 [operand] mnemonic operand(src) push psw rp [flag] zaccy [description] ? the data of the register specified with the source operand (src) is saved in the stack. [description example] push ax; ax register contents are saved in the stack.
148 chapter 5 explanation of instructions pop pop pop [instruction format] pop dst [operation] when dst = rp when dst = psw dst l ? (sp), dst ? (sp) dst h ? (sp+1), sp ? sp+1 sp ? sp+2 [operand] mnemonic operand(dst) pop psw rp [flag] dst =rp psw z ac cy z ac cy rrr [description] ? data is returned from the stack to the register specified with the destination operand (dst). ? when the operand is psw, each flag is replaced with stack data. ? none of interrupts are acknowledged between the pop psw instruction and the subsequent instruction. [description example] pop ax; the stack data is returned to the ax register.
149 chapter 5 explanation of instructions movw sp, src move word movw ax, sp word data transfer with stack pointer [instruction format] movw dst, src [operation] dst ? src [operand] mnemonic operand(dst,src) movw sp, #word sp, ax ax, sp [flag] zaccy [description] ? this is an instruction to manipulate the stack pointer contents. ? the source operand (src) specified with the 2nd operand is stored in the destination operand (dst) specified with the 1st operand. [description example] movw sp, #fe1fh; fe1fh is stored in the stack pointer.
150 chapter 5 explanation of instructions 5.12 unconditional branch instruction unconditional branch instruction is shown below. br ... 151
151 chapter 5 explanation of instructions branch br unconditional branch [instruction format] br target [operation] pc ? target [operand] mnemonic operand(target) br !addr16 ax $addr16 [flag] zaccy [description] ? this is an instruction to branch unconditionally. ? the word data of the target address operand (target) is transferred to pc and branched. [description example] br ax; the ax register contents are branched as address.
152 chapter 5 explanation of instructions 5.13 conditional branch instructions conditional branch instructions are shown below. bc ... 153 bnc ... 154 bz ... 155 bnz ... 156 bt ... 157 bf ... 158 btclr ... 159 dbnz ... 160
153 chapter 5 explanation of instructions branch if carry bc conditional branch with carry flag (cy = 1) [instruction format] bc $addr16 [operation] pc ? pc+2+jdisp8 if cy = 1 [operand] mnemonic operand($addr16) bc $addr16 [flag] zaccy [description] ? when cy = 1, data is branched to the address specified with the operand. when cy = 0, no processing is carried out and the subsequent instruction is executed. [description example] bc $300h; when cy = 1, data is branched to 0300h (with the start of this instruction set in the range of addresses 027fh to 037eh).
154 chapter 5 explanation of instructions branch if not carry bnc conditional branch with carry flag (cy = 0) [instruction format] bnc $addr16 [operation] pc ? pc+2+jdisp8 if cy = 0 [operand] mnemonic operand($addr16) bnc $addr16 [flag] zaccy [description] ? when cy = 0, data is branched to the address specified with the operand. when cy = 1, no processing is carried out and the subsequent instruction is executed. [description example] bnc $300h; when cy = 0, data is branched to 0300h (with the start of this instruction set in the range of addresses 027fh to 037eh).
155 chapter 5 explanation of instructions branch if zero bz conditional branch with zero flag (z = 1) [instruction format] bz $addr16 [operation] pc ? pc+2+jdisp8 if z = 1 [operand] mnemonic operand($addr16) bz $addr16 [flag] zaccy [description] ? when z = 1, data is branched to the address specified with the operand. when z = 0, no processing is carried out and the subsequent instruction is executed. [description example] dec b bz $3c5h; when the b register is 0, data is branched to 03c5h (with the start of this instruction set in the range of addresses 0344h to 0443h).
156 chapter 5 explanation of instructions branch if not zero bnz conditional branch with zero flag (z = 0) [instruction format] bnz $addr16 [operation] pc ? pc+2+jdisp8 if z = 0 [operand] mnemonic operand($addr16) bnz $addr16 [flag] zaccy [description] ? when z = 0, data is branched to the address specified with the operand. when z = 1, no processing is carried out and the subsequent instruction is executed. [description example] cmp a, #55h bnz $0a39h; if the a register is not 0055h, data is branched to 0a39h (with the start of this instruction set in the range of addresses 09b8h to 0ab7h).
157 chapter 5 explanation of instructions branch if true bt conditional branch by bit test (byte data bit = 1) [instruction format] bt bit, $addr16 [operation] pc ? pc+b+jdisp8 if bit = 1 [operand] mnemonic operand(bit,$addr16) b(number of bytes) bt saddr.bit, $addr16 3 sfr.bit, $addr16 4 a.bit, $addr16 3 psw.bit, $addr16 3 [hl].bit, $addr16 3 [flag] zaccy [description] ? if the 1st operand (bit) contents have been set to (1), data is branched to the address specified with the 2nd operand ($addr16). if the 1st operand (bit) contents have not been set to (1), no processing is carried out and the subsequent instruction is executed. [description example] bt fe47h.3, $55ch; when bit 3 at address fe47h is 1, data is branched to 055ch (with the start of this instruction set in the range of addresses 04dah to 05d9h).
158 chapter 5 explanation of instructions branch if false bf conditional branch by bit test (byte data bit = 0) [instruction format] bf bit, $addr16 [operation] pc ? pc+b+jdisp8 if bit = 0 [operand] mnemonic operand(bit,$addr16) b(number of bytes) bf saddr.bit, $addr16 4 sfr.bit, $addr16 4 a.bit, $addr16 3 psw.bit, $addr16 4 [hl].bit, $addr16 3 [flag] zaccy [description] ? if the 1st operand (bit) contents have been cleared to (0), data is branched to the address specified with the 2nd operand ($addr16). if the 1st operand (bit) contents have not been cleared to (0), no processing is carried out and the subsequent instruction is executed. [description example] bf p2.2, $1549h; when bit 2 of port 2 is 0, data is branched to address 1549h (with the start of this instruction set in the range of addresses 14c6h to 15c5h).
159 chapter 5 explanation of instructions branch if true and clear btclr conditional branch and clear by bit test (byte data bit = 1) [instruction format] btclr bit, $addr16 [operation] pc ? pc+b+jdisp8 if bit = 1, then bit ? 0 [operand] mnemonic operand(bit,$addr16) b(number of bytes) btclr saddr.bit, $addr16 4 sfr.bit, $addr16 4 a.bit, $addr16 3 psw.bit, $addr16 4 [hl].bit, $addr16 3 [flag] bit =psw.bit in all other cases z ac cy z ac cy [description] ? if the 1st operand (bit) contents have been set to (1), they are cleared to (0) and branched to the address specified with the 2nd operand. if the 1st operand (bit) contents have not been set to (1), no processing is carried out and the subsequent instruction is executed. ? when the 1st operand (bit) is psw.bit, the corresponding flag contents are cleared to (0). [description example] btclr psw.0, $356h; when bit 0 (cy flag) of psw is 1, the cy flag is cleared to 0 and branched to address 0356h (with the start of this instruction set in the range of addresses 02d4h to 03d3h).
160 chapter 5 explanation of instructions decrement and branch if not zero dbnz conditional loop (r1 1 0) [instruction format] dbnz dst, $addr16 [operation] dst ? dstC1, then pc ? pc+b+jdisp16 if dst r1 1 0 [operand] mnemonic operand(dst,$addr16) b(number of bytes) dbnz b, $addr16 2 c, $addr16 2 saddr, $addr16 3 [flag] zaccy [description] ? one is subtracted from the destination operand (dst) contents specified with the 1st operand and the subtraction result is stored in the destination operand (dst). ? if the subtraction result is not 0, data is branched to the address indicated with the 2nd operand ($addr16). when the subtraction result is 0, no processing is carried out and the subsequent instruction is executed. ? the flag remains unchanged. [description example] dbnz b, $1215h; the b register contents are decremented. if the result is not 0, data is branched to 1215h (with the start of this instruction set in the range of addresses 1194h to 1293h).
161 chapter 5 explanation of instructions 5.14 cpu control instructions the following are cpu control instructions. sel rbn ... 162 nop ... 163 ei ... 164 di ... 165 halt ... 166 stop ... 167
162 chapter 5 explanation of instructions select register bank sel rbn register bank selection [instruction format] sel rbn [operation] rbs0, rbs1 ? n; (n = 0-3) [operand] mnemonic operand(rbn) sel rbn [flag] zaccy [description] ? the register bank specified with the operand (rbn) is made a register bank for use with the next instruction onward. ? rbn ranges from rb0 to rb3. [description example] sel rb2; register bank 2 is selected as one for used with the next instruction onward.
163 chapter 5 explanation of instructions no operation nop no operation [instruction format] nop [operation] no operation [operand] none [flag] zaccy [description] ? only the time is consumed without processing.
164 chapter 5 explanation of instructions enable interrupt ei interrupt enabled [instruction format] ei [operation] ie ? 1 [operand] none [flag] zaccy [description] ? the maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (ie) to (1)). ? none of interrupts are acknowledged between this instruction and the next one instruction. ? if this instruction is executed, vectored interrupt acknowledgment with another source can be disabled. for details, refer to interrupt functions in each product users manual .
165 chapter 5 explanation of instructions disable interrupt di interrupt disabled [instruction format] di [operation] ie ? 0 [operand] none [flag] zaccy [description] ? maskable interrupt acknowledgment with vectored interrupt is disabled (with the interrupt enable flag (ie) cleared to (0)). ? none of interrupts are acknowledged between this instruction and the next one instruction. ? for details of interrupt service, refer to interrupt functions in each product users manual .
166 chapter 5 explanation of instructions halt halt halt mode set [instruction format] halt [operation] set halt mode [operand] none [flag] zaccy [description] ? this instruction is used to set the halt mode to stop the cpu operation clock. total power consumption of the system can be decreased with intermittent operations through a combination with the normal operation mode.
167 chapter 5 explanation of instructions stop stop stop mode set [instruction format] stop [operation] set stop mode [operand] none [flag] zaccy [description] ? this instruction is used to set the stop mode to stop the main system clock oscillator and to stop the whole system. power dissipation can be minimized to an ultra-low level with only leakage current.
168 chapter 5 explanation of instructions [memo]
169 appendix a revision history the following table shows the revision history of the previous editions. the applied to: column describes the chapters of each edition. edition major revision from the previous edition applied to: 2nd added the following versions: throughout m pd78055 and 78p058, and m pd78018f, 78044a, 78054y, 78078, 78083, 78098, and 780208 subseries added the english documentation no. to the related documents introduction added the iebus register area (the m pd78098 subseries only) chapter 1 memory space added the description of the number of clocks when the chapter 4 instruction set external rom contains the program to the clock column. added notes to the description of the ror4 and rol4 chapter 5 explanation instructions in the rotate instruction. of instructions change the operation of the adjba and adjbs instructions in the bcd adjust instruction. 3rd added the following versions: throughout m pd78014h, 78018fy, 78044f, 78044h, 78058f, 78058fy, 78064y, 78064b, 78075b, 78075by, 78078y, 78098b, 780018y, 780024, 780024y, 780034, 780034y, 780058, 780058y, 780228, 780308, 780308y, 780924, and 780964 subseries, and m pd78011f, 78012f, 78070a, 78070ay, 780001, 78p0914, 780206, and 780208 deleted the following versions m pd78024, 78044, and 78044a subseries added table of all internal ram spaces of each model chapter 1 memory space change the format of external memory space table
170 [memo]
171 appendix b instruction index (mnemonic: by function) [8-bit data transfer instructions] mov ... 94 xch ... 95 [16-bit data transfer instructions] movw ... 97 xchw ... 98 [8-bit operation instructions] add ... 100 addc ... 101 sub ... 102 subc ... 103 and ... 104 or ... 105 xor ... 106 cmp ... 107 [16-bit operation instructions] addw ... 109 subw ... 110 cmpw ... 111 [multiply/divide instructions] mulu ... 113 divuw ... 114 [increment/decrement instructions] inc ... 116 dec ... 117 incw ... 118 decw ... 119 [rotate instructions] ror ... 121 rol ... 122 rorc ... 123 rolc ... 124 ror4 ... 125 rol4 ... 126 [bcd adjust instructions] adjba ... 128 adjbs ... 129 [bit manipulation instructions] mov1 ... 131 and1 ... 132 or1 ... 133 xor1 ... 134 set1 ... 135 clr1 ... 136 not1 ... 137 [call return instructions] call ... 139 callf ... 140 callt ... 141 brk ... 142 ret ... 143 reti ... 144 retb ... 145 [stack manipulation instructions] push ... 147 pop ... 148 movw sp, src ... 149 movw ax, sp ... 149
172 [unconditional branch instruction] br ... 151 [conditional branch instructions] bc ... 153 bnc ... 154 bz ... 155 bnz ... 156 bt ... 157 bf ... 158 btclr ...159 dbnz ... 160 [cpu control instructions] sel rbn ... 162 nop ... 163 ei ... 164 di ... 165 halt ... 166 stop ... 167 appendix b instruction index (mnemonic: by function)
173 appendix c instruction index (mnemonic: in alphabetical order) [a] add ... 100 addc ... 101 addw ... 109 adjba ... 128 adjbs ... 129 and ... 104 and1 ... 132 [b] bc ... 153 bf ... 158 bnc ... 154 bnz ... 156 br ... 151 brk ... 142 bt ... 157 btclr ... 159 bz ... 155 [c] call ... 139 callf ... 140 callt ... 141 clr1 ... 136 cmp ... 107 cmpw ... 111 [d] dbnz ... 160 dec ... 117 decw ... 119 di ... 165 divuw ... 114 [e] ei ... 164 [h] halt ... 166 [i] inc ... 116 incw ... 118 [m] mov ... 94 movw ... 97 movw ax, sp ... 149 movw sp, src ... 149 mov1 ... 131 mulu ... 113 [n] nop ... 163 not1 ... 137 [o] or ... 105 or1 ... 133 [p] pop ... 148 push ... 147 [r] ret ... 143 retb ... 145 reti ... 144 rol ... 122 rolc ... 124 rol4 ... 126 ror ... 121 rorc ... 123 ror4 ... 125
174 [s] sel rbn ... 162 set1 ... 135 stop ... 167 sub ... 102 subc ... 103 subw ... 110 [x] xch ... 95 xchw ... 98 xor ... 106 xor1 ... 134 appendix c instruction index (mnemonic: in alphabetical order)
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-889-1689 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 96.8 name company from: tel. fax facsimile message

▲Up To Search▲

Price & Availability of PD78095B

	To Download PD78095B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .