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sy89538l 3.3v, precision lvpecl and lvds programmable multiple output bank clock synthesizer and fanout buffer with zero delay precision edge is a registered trademark of micrel, inc. mlf and micro leadframe are registered trademarks of amkor technology. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 general description the sy89538l integrated programmable clock synthesizer and fanout is part of a precision pll- based clock generation family optimized for enterprise switch, router, and multiprocessor server applications. this family is ideal for generating internal system timing requirements up to 750mhz for multiple asics, fpgas, and npus. these devices integrate the following blocks into a single monolithic ic: ? pll (phase-lock-loop) based synthesizer ? zero-delay mux and feedback capability ? 1:4 lvpecl fanout ? 1:3 lvds fanout ? clock generator (dividers) ? logic translation (lvpecl, lvds) ? five-independently programmable output banks this level of integration minimizes additive jitter and part-to-part skew associated with discrete alternatives, resulting in superior system-level timing with reduced board space and power. for applications that do not requi re a zero-delay function, see the sy89537l. all support documentation can be found on micrel?s web site at: www.micrel.com . applications ? enterprise routers, switches, servers and workstations ? parallel processor-based systems ? internal system clock generation for asics, npus and fpgas markets ? lan/wan ? enterprise servers ? test and measurement precision edge ? features ? integrated programmable sy nthesizer with multiple output dividers, fanout buffers, and clock drivers ? zero-delay capability: 29.375mhz to 756mhz ? reference clock input: 9.325mhz to 756mhz ? input mux accepts a reference and a crystal (xtal) source ? ideal for reference backup clock source or system test frequency source ? patent-pending unique input mux isolates xtal and reference inputs which minimizes crosstalk ? guaranteed ac performance: ? output frequency range: 29.375mhz to 756mhz ? <150ps pp total jitter ? <6ps rms cycle-to-cycle jitter (xtal input) ? <8ps pp deterministic jitter ? <0.7ps rms crosstalk induced jitter ? <75ps output-to-output skew ? ttl/cmos-compatible control logic ? five-independently programmable output frequency banks: ? four differential lvpecl output banks ? one differential lvds output bank with three output pairs ? output bank synchronization control pin ? output enable ? 3.3v 10% power supply (2.5v output capable) ? guaranteed over the industrial temperature range (-40c to +85c) ? available in a 64-pin epad-tqfp
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 2 typical application functional block diagram
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 3 ordering information (1) part number package type operating range package marking lead finish sy89538lhy h64-1 industrial sy89538lhy with pb-free bar-line indicator matte-sn pb-free sy89538lhytr (2) h64-1 industrial sy89538lhy with pb-free bar-line indicator matte-sn pb-free sy89538lhz h64-1 commercial sy89538lhz with pb-free bar-line indicator matte-sn pb-free SY89538LHZTR (2) h64-1 commercial sy89538lhz with pb-free bar-line indicator matte-sn pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 64-pin epad tqfp (h64-1)
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 4 pin description power pin number pin name pin function 1 vcca analog pll power pin. connects to ?quiet? 3.3v supply. 3.3v power pins must be connected together on the pcb. bypass with 0.1f//0.01f low esr capacitors and place them as close to the vcca pin as possible. 6, 56 vccd digital logic core power pin. vccd connects to a 3.3v supply. all power pins must be connected together on the pcb. bypass with 0.1f//0.01f low esr capacitors and place them as close to the vccd pin as possible. 19, 40, 43, 51 vcco lvds and lvpecl output driver power pins. these outputs can be powered from a 2.5v or 3.3v supply. connect all vcco pins to the same power supply: 3.3v 10% or 2.5v 5%. all power pins must be conn ected together on the pcb. bypass with 0.1f//0.01f low esr capacitor and place them as close to the vcco pin as possible. 15 gnda analog pll ground. connect to ?quiet? gr ound. gnda and gnd must be connected together on the pcb. 16, 30, 31, 47, 55 gnd, exposed pad ground: gnd pins and exposed pad must both be connected to the same ground plane. control and configuration pin number pin name pin function 62 lr analog input/output. provides the referenc e voltage for the pll loop filter and is used with the lf pin. see ?external loop filter considerations? for recommended loop filter values. 63 lf analog input/output. provides the loop filt er node for the pll. see ?external loop filter considerations? for recommended loop filter values. 2, 7 rsel1, rsel0 ttl/cmos reference input pre-scalar and zero delay mux divider select inputs. the two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8. rsel0 is the lsb bit. see ?reference input divider and zero delay mux divider select table? for proper decoding. the threshold voltage v th = v cc /2. internal 25k ? pull-up. the default logic is high. 10 insel ttl/cmos input select control. selects either xtal or reference (rfck) input. internal 25k ? pull-up. the default is logic high, and selects the xtal input. the threshold voltage v th = v cc /2. logic high: xtal select logic low: reference input select 36 lsel ttl/cmos input select control signal fo r the lvds lout0-lout2 outputs. lsel, dsel, and len are used together to decode the selection and post divider of the lvds outputs. internal 25k ? pull-up. see ?lvds output post-divider and frequency select table? for proper decoding. the threshold voltage v th = v cc /2. the default logic is high. 37 len ttl/cmos input enable pin. used to cont rol the lout0-lout2 outputs and acts as a frequency select pin. len, dsel, and lsel are used together to decode the selection and post divide of the lvds output bank, see the ?lvds output post- divider and frequency select table? for proper decoding. internal 25k ? pull-up. when disabled, lout0-lout2 outputs are low, and the complimentary outputs are high. the threshold voltage v th = v cc /2. the default logic is high. 23 25 57 59 psel0 psel1 psel2 psel3 ttl/cmos input select control signals for the pecl pout0-pout3 outputs. pselx, dsel and penx are used together to deco de the selection and post divider of the pecl outputs. pselx pins include an internal 25k ? pull-up. the threshold voltage v th = v cc /2. see "lvpecl output post-divider and frequency select table? for proper decoding.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 5 pin description control and configuration (continued) pin number pin name pin function 24 26 58 60 pen0 pen1 pen2 pen3 ttl/cmos input enable pin. used to c ontrol the pecl pout0-pout3 outputs and as a frequency select pins. penx, pselx, and dsel are used together; see the ?lvpecl output post-divider and frequency select table? for proper decoding. penx contains internal 25k ? pull-up. when disabled, pecl0-pecl3 outputs are a logic low. the threshold voltage v th = v cc /2. 46 sync ttl/cmos output bank synchroniz ation control. internal 25k ? pull-up. the default state is high. after any bank has been pr ogrammed, all pecl and lvds outputs are synchronized when the sync control pin is toggled with a high-low-high transition. see ?synchronization? sect ion for details. the threshold voltage v th = v cc /2. 5 fbsel ttl/cmos input select control. selects ei ther internal or exte rnal feedback (zero-delay function). internal 25k ? pull-up. the threshold voltage v th = v cc /2. default is logic high, and selects internal feedback. logic high: internal feedback (f rom the programmable divider) logic low: external feedback (from the fbin inputs) 28 33 35 pd_4 pd_2 pd_0 ttl/cmos programmable divider-select control. internal 25k ? pull-down. def ault is logic low. the threshold voltage v th = v cc /2. see ?programmable-divider select table? for proper decoding. 27 29 34 pd_5 pd_3 pd_1 ttl/cmos programmable divider-select control. internal 25k ? pull-up. default is logic high. the threshold voltage v th = v cc /2. see ?programmable-divider select table? for proper decoding. 13, 14 pdsel1, pdsel0 ttl/cmos pre-divider select input. internal 25k ? pull-up. this two-bit input divider scales the vco/2 frequency. see ?pre-div ider frequency select table? for proper decoding. the threshold voltage v th = v cc /2. 22 dsel ttl/cmos post-divider option control. internal 25k ? pull-up. default is logic high. the threshold voltage v th = v cc /2. logic high: all lvpecl and lvds outputs op erate with their respective output frequency control (pselx, penx, lsel, len). logic low: internal pll is disabled, refere nce and xtal signals by-passes the pll through a /1, /4, and /16 post-divider. see ?lvpecl and lvds output post-div ider and frequency select table? for proper decoding.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 6 pin description input/output pin number pin name pin function 3, 4 fbin, /fbin external feedback input used as the zero delay input. output feeds into the inputs to configure the device in zero-delay mode, wh ich forces the output frequency to the same frequency of the rfck frequency. requires external termination. see ?zero delay fbin input? section for more details. 8, 9 rfck, /rfck reference clock differential input. input accepts any input, single-ended or differential: ttl/cmos, lvpecl, lvds , hstl, and sstl. rfck requires an external termination. see ?input interface? and ?input termination? sections for more details. 11, 12 xtal2, xtal1 crystal input. directly connect a series re sonant crystal across inputs. see ?quartz crystal oscillator specification? table. plac e crystal as close to the input as possible, keep xtal and traces away from adjacent noisy traces to minimize noise coupling, and place the xtal on the same side as the sy89538l (component side). 17, 18 20, 21 49, 50 52, 53 pout0, /pout0 pout1, /pout1 pout2, /pout2 pout3, /pout3 100k lvpecl output drivers. terminate all lvpecl outputs with 50 ? to v cco ?2v. each output pair has a respective output frequency control (pselx, penx, dsel). see ?lvpecl output post-divider and frequenc y select table? for proper decoding. for low-jitter applications, unused lvpecl output pairs should be terminated with pull-down resistors. see ?output termination recommendations? section for termination detail. 38, 39 41, 42 44, 45 lout0, /lout0 lout1, /lout1 lout2, /lout2 differential lvds-compatible output drivers. output termination is 100 ? across the pair. for low-jitter applications, unused lvds output pairs should be terminated with 100 ? across the pair. see ?output termination recommendations? section for details. 32, 48, 54, 61, 64 nc no connect. input driver select table rsel1 rsel0 internal reference clock zero-delay mux divider 0 0 rfck / 8 fbin / 8 0 1 rfck / 4 fbin / 4 1 0 rfck / 2 fbin / 2 1 1 rfck / 1 fbin / 1 table 1. reference input divider and zero-delay mux divider select table pre-divider frequency select table pdsel1 pdsel0 pre-div-out frequency 0 0 (vco/2) / 5 0 1 (vco/2) / 4 1 0 (vco/2) / 3 1 1 (vco/2) / 2 table 2. pre-divider select table
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 7 output and frequency select tables pselx penx dsel poutx 0 0 0 disable output (high) 0 1 0 f ref-div / 4 1 0 0 f ref-div / 16 1 1 0 f ref-div / 1 0 0 1 disable output (low) 0 1 1 f pre-div / 2 1 0 1 f pre-div / 8 1 1 1 f pre-div / 1 table 3. lvpecl output post-div ider and frequency select table lsel len dsel loutx 0 0 0 disable output (high) 0 1 0 f ref-div / 4 1 0 0 f ref-div / 16 1 1 0 f ref-div / 1 0 0 1 disable output (low) 0 1 1 f pre-div / 2 1 0 1 f pre-div / 8 1 1 1 f pre-div / 1 table 4. lvds output post-divider and frequency select table programmable-divider select table pd_5 pd_4 pd_3 pd_2 pd_1 pd_0 6-bit prog. divider f vco 0 0 0 0 0 ? 0 0 0 0 0 ? 1 1 1 1 1 ? 0 0 0 0 1 ? 0 0 1 1 0 ? 0 1 0 1 0 ? 8 9 10 11 12 ? f ref x 32 f ref x 36 f ref x 40 f ref x 44 f ref x 48 ? ? 1 1 1 1 1 ? ? 0 0 0 0 0 ? ? 1 1 1 1 1 ? ? 0 0 0 0 1 ? ? 0 0 1 1 0 ? ? 0 1 0 1 0 ? ? 40 41 42 43 44 ? ? f ref x 160 f ref x 164 f ref x 168 f ref x 172 f ref x 176 ? ? 1 1 1 1 1 ? 1 1 1 1 1 ? 1 1 1 1 1 ? 0 1 1 1 1 ? 1 0 0 1 1 ? 1 0 1 0 1 ? 59 60 61 62 63 ? f ref x 236 f ref x 240 f ref x 244 f ref x 248 f ref x 252 table 5. programmable-divider select table note: see ?reference input frequency and valid programmabl e divider range? section for more details.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 8 absolute maximum ratings (1) supply voltage (v ccd , v cca , v cco ) ...... ?0.5v to +4.0v input voltage (rfck, fbin)................... ?0.5v to v cc xtal input voltage (v xtal1, 2 ) ......... v cc ?1.9v to v cc output current (i out ) lvpecl outputs (surge) .........................100ma lvpecl outputs (c ontinuous)...................50ma lvds out puts ........................................... 10ma lead temperature (solderi ng, 20 sec.) .......... +260c storage temperature (t s ) ................. ?65c to 150c operating ratings (2) supply voltage v cco a and v cco c ............................... +3.0v to +3.6v v cco b ............................................. +2.375v to +3.6v ambient temperature (t a )....................... ?40c to +85c package thermal resistance (junction-to-ambient) with die attach soldered to gnd: tqfp ( ja ) still-air ......................................23c/w tqfp ( ja ) 200lfpm.....................................18c/w tqfp ( ja ) 500lfpm.....................................15c/w with die attach not soldered to gnd (3): tqfp ( ja ) still-air ......................................44c/w tqfp ( ja ) 200lfpm.....................................36c/w tqfp ( ja ) 500lfpm.....................................30c/w package thermal resistance (junction-to-board) tqfp ( jc ) ....................................................7c/w dc electrical characteristics (4) power supply t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cca pll power supply note 5 3.0 3.3 3.6 v v ccd control logic supply voltage note 5 3.0 3.3 3.6 v output supply voltag e 2.375 2.5 2.625 v v cco 3.0 3.3 3.6 v i cc power supply current no load, max. v cc , note 6 240 300 ma i cca analog supply current max. v cc 10 ma i cco output supply current no load, max. v cc 55 ma i ccd digital supply current max. v cc 175 ma lvcmos/lvttl input control logic v cca = v ccd = +3.3v 10%, v cco = +2.5v 5% or +3.3v 10%; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current v in = v cc ?125 150 a i il input low current v in = 0.5v ?300 a notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ra tings conditions for extended periods ma y affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. it is recommended that the user always solder the ex posed die pad to a ground plane for enhanced heat dissipation. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 5. v cca and v ccd are not internally connected. they must be connected together on the pcb. 6. i cc = i cca + i cco + i ccd .
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 9 reference clock inputs/ external feedback inputs v cca = v ccd = +3.3v 10%, v cco = +2.5v 5% or +3.3v 10%; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v ih input high voltage rfck, /rfck fbin, /fbin v ccd + 0.3 v v il input low voltage rfck, /rfck fbin, /fbin ?0.3 v v in input voltage swing rfck, /rfck, fbin, /fbin see figure 1a. 100 mv v diff_in differential input voltage swing rfck, /rfck, fbin, /fbin see figure 1b. 200 mv 100k lvpecl output dc el ectrical characteristics v cca = v ccd = +3.3v 10%, v cco = +2.5v 5% or +3.3v 10%, r l = 50 ? into v cco ?2v; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage v cco ?1.075 v cco ?0.830 v v ol output low voltage v cco ?1.860 v cco ?1.570 v v out output voltage swing see figure 1a. 550 800 mv v diff_out differential output voltage swing see figure 1b. 1100 1600 mv lvds output dc electrical characteristics v cca = v ccd = +3.3v 10%, v cco = +2.5v 5% or +3.3v 10%, r l = 100 ? across the pair; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v out output voltage swing see figure 1a. 250 325 mv v diff-out differential output voltage swing see figure 1b. 500 650 mv v ocm output common mode voltage 1.125 1.275 v ? v ocm change in common mode voltage 25 mv
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 10 ac electrical characteristics v cca = v ccd = +3.3v 10%; v cco = +2.5v 5% or +3.3v 10%, r l (lvds) = 100 ? across the output pairs, r l (lvpecl) = 50 ? into v cco ?2v; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units xtal input frequency range note 7 14 18 mhz reference input frequency range see table 8 9.325 756 mhz f in zero delay input frequency range see table 9 29.375 756 mhz insel = low 9.325 94.5 mhz f ref phase detector operating frequency range insel = high 14 18 mhz f out output frequency range 29.375 756 mhz f vco internal vco frequency range 2352 3024 mhz t skew output-to-output note 8 15 75 ps t lock minimum pll lock time 10 ms loop filter optimized for cycle-to-cycle jitter ? r = 50 ? ? c1 = 0.47f ? c2 = 1000pf note 9 4 6 ps rms note 9 5 14 ps rms note 10 80 150 ps pp 1-sigma cycle-to-cycle jitter (xtal input) 1-sigma cycle-to-cycle jitter (rfck reference) total jitter spur -35 dbc@ fphase t jitter xtal/rfck crosstalk-induced jitter note 11 0.7 ps rms bw pll bandwidth see table 10 14 f ref 18 11.1 38.4 khz t dc f out duty cycle 43 50 57 % t r, t f output rise/fall time (20% to 80%) lvpecl 100 250 400 ps output rise/fall time (20% to 80%) lvds 80 150 300 ps t pw_sync_min minimum sync pulse width see ?synchronization? section 8 internal clock cycle t pd_sync synchronization delay see ?synchronization? section 8 internal clock cycle notes: 7. fundamental mode, series resonant crystal. 8. the output-to-output skew is defined as the worst-case diffe rence between any outputs within a single device operating at th e same voltage and temperature. 9. cycle-to-cycle jitter definition: the va riation of periods between adjacent cycles, t n ? t n-1 where t is the time between rising edges of the output signal. 10. total jitter definition: with an ideal clock input of frequency micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 11 single-ended and di fferential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 12 functional description overall function the sy89538l integrated programmable clock synthesizer and fanout buffer wi th zero delay is part of a precision pll-based clock generation family optimized for internal system clock generation (fpgas, asics, npu). inputs xtal the sy89538l features a fu lly integrated on-board oscillator, which minimizes system implementation cost. the oscillator is a seri es resonant, multi-vibrator type crystal driver designed to drive a 14mhz to 18mhz series resonant crystal, see table 6 and 7 for more details on the crystal frequency range and specifications. xtal (mhz) f vco (ghz) min. max. x r ref min. max. 14 18 168 2.352 3.024 table 6. xtal frequency range and valid programmable range table min. typ. max. units frequency range (fundamental mode- series resonant) 14 18 mhz frequency tolerance @ 25c 30 50 ppm frequency stability over 0c to 70c 50 100 ppm operating temperature range -40 +85 c storage temperature range -55 +125 c aging (per yr/1 st 3yrs) 5 ppm equivalent series resistance (esr) 50 ? drive level 100 w table 7. quartz crystal oscillator specifications oscillator tips 1. mount the crystal as close to the sy89538l as possible to minimize parasitic effects. 2. mount the crystal on the same plane as the sy89538l to minimize on via hole inductance. 3. to minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces. 4. keep the crystal and its traces away from adjacent noisy traces to minimize noise coupling. figure 2 below illustrates how to interface the crystal with the sy89538l. figure 2. crystal interface quartz crystal selection: note: raltron series resonant: as-16.666-s-smd-t-mi (2) raltron rfck the input mux drives the plls phase detector, which expects a frequency between 9.325mhz and 94.5mhz. therefore, reference clock maximum input frequency is 756mhz when the reference divider is set to a divide-by-8 and the reference clock minimum frequency is 9.325mhz when t he reference divider is set to a divide-by-1. given that the vco frequency range is from 2.352ghz to 3.024ghz, the minimum and maximum frequency range of rfck can be calculated as follows: minimum output frequency (9.33mhz input): () 2 pr pr ? ? = by div r postdivide edivider vider feedbackdi edivider f f phase out ( ) ( )() () () () 2 8 5 2 2 63 33 . 9 = mhz f out mhz f out 4 . 29 = maximum output frequen cy (756mhz input): ()() () () () 2 1 2 2 2 8 8 756 ? ? ? ? ? ? = mhz f out mhz f out 756 =
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 13 table 8 summarizes the input reference frequency and associated divider values: f rfck (mhz) f ref (mhz) f vco (ghz) ref-div = 1 ref-div = 8 x f ref min. max. min. max. 73.5 756 32 73.5 94.5 2.352 3.024 65.3 672 36 65.3 84.0 2.352 3.024 58.8 605 40 58.8 75.6 2.352 3.024 53.5 550 44 53.5 68.7 2.352 3.024 49.0 504 48 49.0 63.0 2.352 3.024 ? ? ? ? ? ? ? 14.7 151 160 14.7 18.9 2.352 3.024 14.3 148 164 14.3 18.4 2.352 3.024 14.0 144 168 14.0 18.0 2.352 3.024 13.7 141 172 13.7 17.6 2.352 3.024 13.4 137 176 13.4 17.2 2.352 3.024 ? ? ? ? ? ? ? 9.97 103 236 9.97 12.8 2.352 3.024 9.80 101 240 9.80 12.6 2.352 3.024 9.64 99.1 244 9.64 12.4 2.352 3.024 9.48 97.5 248 9.48 12.2 2.352 3.024 9.33 96.0 252 9.33 12.0 2.352 3.024 table 8. reference input frequency and valid programmable divider range table
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 14 zero delay fbin input the sy89538l features a zero delay mux that forces the output to be at the same phase relationship as the reference. this effectively configures the sy89538l as a zero delay buffer when fbsel is logic high and the output is fed into the feedback input fbin as shown in figures 3a and 3b. figure 3a. zero delay mode (lvds output) figure 3b. zero delay mode (lvpecl output) how does zero delay work? from the block diagram, divider fbk divider ref. fbin rfck f f and f f fbk ref = = when the pll is locked, f ref = f fbk and since ref. divider = fbk divider, f rfck is forced to equal f fbin . in zero delay mode, f out is fed into fbin, therefore, f rfck is forced to equal f out .
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 15 ref-divider = 1 ref-divider = 2 ref-divider = 4 ref-divider = 8 f vco (mhz) f out (mhz) f ref (mhz) f ref (mhz) f ref (mhz) f ref (mhz) min. max. post- divider pre- divider min. max. min. max. min. max. min. max. min. max. 2.35 3.02 1 2 588.0 755.0 588.0 755.0 294.0 377.5 147.0 188.8 73.5 94.4 2.35 3.02 1 3 392.0 503.0 392.0 503.0 196.0 251.5 98.0 125.8 49.0 62.9 2.35 3.02 1 4 294.0 378.0 294.0 378.0 147.0 189.0 73.5 94.5 36.8 47.3 2.35 3.02 1 5 235.0 302.0 235.0 302.0 117.5 151.0 58.8 75.5 29.4 37.8 2.35 3.02 2 2 294.0 378.0 294.0 378.0 147.0 189.0 73.5 94.5 36.8 47.3 2.35 3.02 2 3 196.0 252.0 196.0 252.0 98.0 126.0 49.0 63.0 24.5 31.5 2.35 3.02 2 4 147.0 189.0 147.0 189.0 73.5 94.5 36.8 47.3 18.4 23.6 2.35 3.02 2 5 118.0 151.0 118.0 151.0 59.0 75.5 29.5 37.8 14.8 18.9 2.35 3.02 8 2 73.4 94.4 73.4 94.4 36.7 47.2 18.4 23.6 not valid 11.8 2.35 3.02 8 3 49.0 62.9 49.0 62.9 24.5 31.5 12.3 15.7 not valid not valid 2.35 3.02 8 4 36.7 47.2 36.7 47.2 18.4 23.6 not valid 11.8 not valid not valid 2.35 3.02 8 5 29.4 37.8 29.4 37.8 14.7 18.9 not valid not valid not valid not valid table 9. zero delay divider cases considerations when in zero delay mode: ? the input and output frequency range is 29.375mhz to 756mhz ? the phase detector frequency range is 9.325mhz to 94.5mhz ? there are cases in which certain divider combinations at certain frequencies are not valid, see table 9 for more details ? systematic phase offs et is caused by added and parasitic capacitance ? phase offset is introduced by increased trace length ? phase offset second order effects can be introduced with high r die-electric constants since the velocity of electromagnetic waves slows down as the die-electric constant increases
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 16 external loop filter considerations the sy89538l features an ex ternal pll loop filter that allows the users to tailor the pll?s behavior. it is recommended that ceramic capacitors with npo or x7r dielectric be used, since they have very low effective series resistance. for applications that require ultra-low cycle-to-cycle jitter, use the components shown in figure 4. larger values of the zero capacitor (capacitor shown in parallel) results in less cycle-to- cycle jitter, however the total jitter increases as the value of the zero capacitor increases. in addition, as the zero capacitor increases, loop stability decreases as the zero capacitor begins to dominate over the pole capacitor (capacitor in series with the damping resistor). the external loop filter allows the user to change the loop filter values for specific jitter requirements. using a smaller resistor in the loop filter decreases the pll?s loop bandwidth. this results in less noise from the pll input, but potentially more noise from the vco. take care to keep the loop filter components on the same side of the board and as close as possible to the sy89538l?s lr and lf pins. to minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces. however, the benefit may not be significant in all applications. figure 4. loop filter power supply filtering techniques as with any high-speed integrated circuit, power supply filtering is very important. at a minimum, vcca, vccd, and all vcco pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. to achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in figure 5. figure 5. recommended power supply filter note: for v cca and v ccd use ferrite bead, 200ma, murata p/n blm21a1025. for v cco use ferrite bead3a, 0.025 ? dc, murata, p/n blm31p005.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 17 synchronization output synchronization controlled by sync timing diagram the sync control input is used to synchronize all divider outputs of the post divider. when a high-low transition is applied to the sync control input the outputs are disabled when all post-divider outputs are low, see ?output synchronization controlled by sync timing diagram? for details. once sync is asserted with a rising e dge, the outputs are enabled when all internal divider stages are reaching their low state. this ensures a simultaneous switching of all outputs with the next low-high transition of the pre-divider clock.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 18 pll loop stability for the loop filter configurations shown in figure 4, table 10 below summarizes t he pll?s loop stability in terms of damping factor, natural frequency, and bandwidth, and illustrates the pole and zero cutoff frequencies determined by the loop filter when the sy89538l is driven by a 14mhz to 18mhz crystal when the feedback divider is effectively 168. parameter units vcc 3 3 3 3.3 3.3 3.3 3.6 3.6 3.6 v rm temperature -40 -40 -40 25 25 25 85 85 85 c die temperature -18 -18 -18 55 55 55 125 125 125 c vco frequency 2352 2800 3024 2352 2800 3024 2352 2800 3024 mhz charge pump current 1.80e-04 1.80e-04 1.80e-04 1.80e-04 1.80e-0 4 1.80e-04 1.80e-04 1.80e-04 1.80e-04 a loop filter resistor 50 50 50 50 50 50 50 50 50 ohms zero capacitor 4.70e-07 4.70e-07 4.70e-07 4.70e-0 7 4.70e-07 4.70e-07 4.70e-07 4.70e-07 4.70e-07 f pole capacitor 1.00e-10 1.00e-09 1.00e-09 1.00e-0 9 1.00e-09 1.00e-09 1.00e-09 1.00e-09 1.00e-09 f vco gain (kvco) 3.20e+09 4.50e+09 4.50e+09 2. 80e+09 3.30e+09 3.10e+09 2.30e +09 1.70e+09 1.30e+09 hz/v feedback divider 168 168 168 168 168 168 168 168 168 integer phase detector frequency 14 16 18 14 16 18 14 16 18 mhz damping factor 1.0 1.2 1.2 0. 9 1.0 1.0 0.9 0.7 0.6 natural frequency 13600.29 16127.95 16127.95 12721.90 13811.16 13386.09 11530.20 9912.83 8668.52 hz ratio=phase detector freq / fc 513 417 469 586 568 681 714 1103 1623 table 10. pll loop stability (1) note: 1. feedback divider = 168 = 42 (6-bit programmable divider) x di vide-by-2 x divide-by-2. reference frequency = 14, 16, and 18mh z.
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 19 figure 6 shows the open and closed loop gain of the sy89538l. the closed loop-gain plot shows that the sy89538l when configured with the recommended loop filter values has essentially no jitter peaking near the -3db point. in addition, the open loop curve shows the frequency at which unity gain occurs for a typical case of the sy89538l with v cc = 3.3v at t a = 25c. at unity gain, figure 7 can be used to determine the phase margin or stab ility of the sy89538l. figure 6. open and closed loop gain at v cc = 3.3v, t a = 25c figure 7. phase margin plot at v cc = 3.3v, t a = 25c figure 8 illustrates the vco fr equency versus the loop filter control voltage at 3.3v, t a = 25c. the normal loop filter control voltage is -300mv to +300mv. figure 9 illustrates the vco gain curve at v cc = 3.3v, t a = 25c. with this set of information, determining the loop stability with ot her sets of loop filter configurations is possible. figure 8. loop filter control voltage vs. frequency at 3.3v, t a = 25c figure 9. frequency vs. loop filter control voltage at 3.3v, t a = 25c input interface rfck and fbin are designed to accept any differential or single-ended input signal 300mv above v cc or 300mv below gnd. rfck and fbin should not be left floating. tie either the true or complement input to gnd, but not both. a logic zero is achieved by connecting the complement input to gnd with the true input floating. for ttl input, tie a 2.5k ? resistor between the complement input and gnd. lvds, cml and hstl differential signals may be connected directly to the reference inputs. figure 10. simplified input structure db phase margin () frequency (hz) frequency (hz)
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 20 input termination (rfck and fbin) figure 11a. lvpecl interface (dc-coupled) figure 11b. lvpecl interface (ac-coupled) figure 11c. cml interface (dc-coupled) figure 11d. cml interface (ac-coupled) figure 11e. lvds (dc-coupled) figure 11f. 2.5v lvpecl (dc-coupled) figure 11g. 2.5v cml (dc-coupled) figure 11h. single-ended input interface
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 21 output bank and frequency control there are five independently programmable output frequency banks, four di fferential lvpecl output banks and one differential lvds output bank with three output pairs. each bank has frequency control dsel, selx and enx to generate different divider ratios (see ?lvpecl and lv ds output post-divider frequency select? tables). it can be programmed for pass-through, internal divided vco clock divide-by- /2, /8 or disable state. when disabled, the non- inverted output goes to static low and the inverted output goes to static high. output logic characteristics see ?output termination recommendations? for proper termination. when lvpecl single-ended output is desired, the unused complimentary output should be terminated. unused lvpecl output pairs can be left floating. lvds output pairs should be terminated with 100 ? across the pair. in order to minimize jitter and skew, unused lvds output banks and unused lvds output pairs should be terminated with 100 ? across each pair. lvpecl outputs: ? typical voltage swing is 800mv into 50 ? . ? common mode voltage is v cco ?1.3v. lvds outputs: ? typical voltage swing is 325mv into 100 ? . ? common mode voltage is 1.2v. output terminati on recommendations lvpecl lvpecl has high input impeda nce, very low output (open emitter) impedance, and small signal swing which results in low emi. lvpecl is ideal for driving 50 ? -and-100 ? -controlled impedance transmission lines. there are several techniques for terminating the lvpecl output: single-ended termination, parallel termination thevenin-equivalent, 3-resistor y-termination, and ac-coupled termination. single-ended lvpecl termination unused output pairs may be left floating. terminating single-ended and unused outputs will enhance the performance. terminate lvpecl outputs by 50 ? to v cc ?2v. the unused input terminal must be biased to v cc ?1.3v using a resistor net work. see figure 11h for more details. dc-coupled lvpecl parallel termination terminate lvpecl by an output impedance of 50 ? to v cc ?2v. termination resistor values are a function of v cc . for a 3.3v supply, the optimal parallel combination is 130 ? ||82 ? . see figure 12a for details. the lvpecl output can also be terminated with three 50 ? resistors as shown in figure 12b. a 0.1f low esr decoupling capacitor from v cc to y-junction is recommended in order to reduce noise in the signal. ac-coupled lvpecl termination while terminating an ac-coupled lvpecl signal, pull- down resistor is used to cr eate a dc current path to gnd to produce an output swing. for 3.3v supply, 100 ? provides the necessary pull-down. at the final destination, proper termination to create a v cc ?1.3v termination bias is required 82 ? ||130 ? . please refer to figure 12c. figure 12a. lvpecl parallel thevenin-equivalent figure 12b. lvpecl parallel termination figure 12c. lvpecl ac-coupled parallel thevenin-equivalent
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 22 lvds lvds specifies a small swing of 325mv typical, on a nominal 1.2v common mode above ground. the common mode voltage has tight limits to permit large variations in ground between an lvds driver and receiver. also, change in common mode voltage, as a function of lvds input, is kept to a minimum, to keep emi low conveniently to asks and fpgas. each lvds output pair requires 100 ? across the differential pair at the end destination (often intended integrated into the asic). related product and su pport documentation part number function data sheet link sy89537l 3.3v, precision lvpecl and lvds programmable, multiple output bank clock synthesizer and fanout buffer with zero delay http://www.micrel.com/product-info/products/sy89537l.shtml hbw solutions new products and applications www.micrel.com/product-info/ products/solutions.shtml mlf tm application note www.amkor.com/p roducts/notes_papers/mlfappnote.pdf
micrel, inc. sy89538l january 2008 m9999-010808-e hbwhelp@micrel.com or (408) 955-1690 23 package information 64-pin epad-tqfp (h64-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life s upport appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2006 micrel, incorporated.

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