256k x 32 static ram modu le cym1841 b cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05261 rev. *a revised april 24, 2003 features ? high-density 8-megabit sram module 32-bit standard footprint supports densities from 16k x 32 through 1m x 32 high-speed cmos srams ? access time of 12 ns low active power ? 5.3w (max.) at 25 ns smd technology ttl-compatible inputs and outputs low profile ? max. height of 0.58 in. available in zip, simm, and angled simm footprint 72-pin simm version compatible with 1m x 32 (cym1851) functional description the cym1841b is a high-performance 8-megabit static ram module organized as 256k words by 32 bits. this module is constructed from two 256k x 16 srams in soj packages mounted on an epoxy laminate board with pins. four chip selects (cs 1 , cs 2 , cs 3 , cs 4 ) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. writing to each byte is accomplished when the appropriate chip select (cs ) and write enable (we ) inputs are both low. data on the input/output pins (i/o) is written into the memory location specified on the address pins (a 0 through a 17 ). reading the device is accomplished by taking the chip select (cs ) low while write enable (we ) remains high. under these conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (i/o). the data input/output pins stay at the high-impedance state when write enable is low or the appropriate chip selects are high. two pins (pd 0 and pd 1 ) are used to identify module memory density in applications where alternate versions of the jedec-standard modules can be interchanged. a 72-pin simm is offered for compatibility with the 1m x 32 cym1851. this version is socket upgradable to the cym1851. both the 64-pin and 72-pin simm modules are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. logic block diagram (1841b) a 0 ?a 17 oe cs 3 i/o 16 ?i/o 23 cs 1 18 8 8 8 8 cs 2 cs 4 i/o 24 ?i/o 31 i/o 0 ?i/o 7 i/o 8 ?i/o 15 pd 0 ?gnd pd 1 ?gnd pd 2 ? open (72-pin only) pd 3 ? open (72-pin only) we 256k x 16 sram 256k x 16 sram
cym1841 b document #: 38-05261 rev. *a page 2 of 9 selection guide 1841b-15 1841b-20 1841b-25 1841b-35 1841b-45 unit maximum access time 15 20 25 35 45 ns maximum operating current 400 380 380 340 340 ma maximum standby current 80 80 80 80 80 ma pin configurations cs we simm top view nc a 4 pd 3 pd 2 pd 0 gnd i/o 0 pd 1 i/o 1 i/o 8 i/o 2 i/o 9 i/o 3 v cc a 7 i/o 11 i/o 10 a 0 i/o 6 gnd nc a 15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 i/o 7 we a 8 a 9 i/o 4 i/o 5 a 14 cs 1 cs 3 a 16 gnd i/o 16 i/o 17 a 12 a 13 i/o 20 i/o 21 i/o 22 i/o 14 i/o 15 a 1 a 2 i/o 12 i/o 13 2 i/o 18 i/o 19 a 10 a 11 cs 4 a 17 oe i/o 24 i/o 25 v cc a 6 i/o 28 i/o 29 i/o 26 i/o 27 a 3 a 5 66 68 70 65 67 69 i/o 23 gnd a 19 i/o 30 i/o 31 a 18 72 71 nc nc zip/simm top view pd 0 v cc i/o 0 pd 1 i/o 1 i/o 8 i/o 2 i/o 9 i/o 3 i/o 10 v cc i/o 11 a 7 a 8 a 9 a 1 a 0 a 2 cs 2 gnd cs 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 a 14 cs 1 i/o 4 i/o 5 i/o 6 7 cs 3 a 16 gnd i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd gnd a i/o 12 i/o 13 i/o 14 i/o 15 a 17 a 10 a 11 a 12 a 13 oe i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 a 3 a 4 a 5 a 6 64-pin 72-pin 15 i/o
cym1841 b document #: 38-05261 rev. *a page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 55c to +125c ambient temperature with power applied .................................................... ? 10c to +85c supply voltage to ground potential .................? 0.5v to +7.0v dc voltage applied to outputs in high z state ..................................................... ? 0.5v to +7.0v dc input voltage ................................................. ? 0.5v to +7.0v operating range range ambient temperature v cc commercial 0c to +70c 5v 10% electrical characteristics over the operating range parameter description test conditions 1841b - 15 1841b-20 1841b -25, 35, 45 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc 2.2 v cc 2.2 v cc v v il input low voltage ?0.5 0.8 ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?3 +3 ?3 +3 ?3 +3 ua i oz output leakage current gnd < v o < v cc , output disabled ?2 +2 ?2 +2 ?2 +2 ua i cc v cc operating supply current v cc = max., i out = 0 ma, cs < v il 400 380 340 ma i sb1 automatic cs power-down current [1] max. v cc , cs > v ih , min. duty cycle = 100% 80 80 80 ma i sb2 automatic cs power-down current [1] max. v cc , cs > v cc ? 0.2v, v in > v cc ? 0.2v, or v in < 0.2v 6 6 6 ma capacitance [2] parameter description test conditions max. unit c in input capacitance [3] t a = 25c, f = 1 mhz, v cc = 5.0v 16 pf c out output capacitance 16 pf ac test loads and waveforms notes: 1. a pull-up resistor to v cc on the cs input is required to keep the device deselected during v cc power-up, otherwise i sb will exceed values given. 2. tested on a sample basis. 3. 20 pf on cs , 70 pf all others. 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) <5ns <5 n s output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 ? equivalent to: th venin equivalent 1.73v
cym1841 b document #: 38-05261 rev. *a page 4 of 9 switching characteristics over the operating range [4] parameter description 1841b-15 1841b-20 1841b-25 unit min. max. min. max. min. max. read cycle t rc read cycle time 15 20 25 ns t aa address to data valid 15 20 25 ns t oha output hold from address change 3 3 3 ns t acs cs low to data valid 15 20 25 ns t doe oe low to data valid 7 8 8 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z 7 8 8 ns t lzcs cs low to low z [5] 3 4 4 ns t hzcs cs high to high z [5, 6] 7 8 8 ns t pd cs high to power-down 15 18 18 write cycle [7] t wc write cycle time 15 20 25 ns t scs cs low to write end 10 15 20 ns t aw address set-up to write end 10 18 20 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 2 2 2 ns t pwe we pulse width 12 15 15 ns t sd data set-up to write end 7 8 8 ns t hd data hold from write end 1 2 2 ns t lzwe we high to low z 0 0 0 ns t hzwe we low to high z [6] 0 6 0 8 0 8 ns switching characteristics over the operating range [4] parameter description 1841b-35 1841b-45 unit min. max. min. max. read cycle t rc read cycle time 35 45 ns t aa address to data valid 35 45 ns t oha data hold from address change 3 3 ns t acs cs low to data valid 35 45 ns t doe oe low to data valid 25 30 ns t lzoe oe low to low z 0 0 ns t hzoe oe low to high z 15 15 ns t lzcs cs low to low z [5] 10 10 ns t hzcs cs high to high z [5, 6] 20 20 ns t pd cs high to power-down 35 45 ns write cycle [7] t wc write cycle time 35 45 ns notes: 4. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. at any given temperature and voltage condition, t hzcs is less than t lzcs for any given device. these parameters are guaranteed by design and not 100% tested. 6. t hzcs and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 7. the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cym1841 b document #: 38-05261 rev. *a page 5 of 9 t scs cs low to write end 30 40 ns t aw address set-up to write end 30 40 ns t ha address hold from write end 2 2 ns t sa address set-up to write start 2 2 ns t pwe we pulse width 30 35 ns t sd data set-up to write end 20 25 ns t hd data hold from write end 2 2 ns t lzwe we high to low z 0 0 ns t hzwe we low to high z [6] 0 15 0 15 ns switching waveforms read cycle no. 1 [8, 9] read cycle no. 2 [8, 10] notes: 8. we is high for read cycle. 9. device is continuously selected, cs = v il and oe = v il . 10. address valid prior to or coincident with cs transition low. switching characteristics over the operating range (continued) [4] parameter description 1841b-35 1841b-45 unit min. max. min. max. previous data valid data valid t rc t aa t oha address data out data valid t rc t acs t doe t lzoe t lzcs high impedance t hzoe t hzcs high impedance data out oe cs
cym1841 b document #: 38-05261 rev. *a page 6 of 9 write cycle no. 1 (we controlled) [7] write cycle no. 2 (cs controlled) [7, 11] truth table cs we oe input/output mode h x x high z deselect/power-down l h l data out read l l x data in write l h h high z deselect note: 11. if cs goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t wc data valid data undefined high impedance t scs t aw t sa t pwe t ha t hd t hzwe t lzwe t sd cs we address data in data out t wc data valid data undefined high impedance t scs t aw t pwe t ha t hd t hzwe t sd cs we address data in data out t sa
cym1841 b document #: 38-05261 rev. *a page 7 of 9 ordering information speed (ns) ordering code package name package type operating range 15 cym1841bpm-15c pm03 64-pin plastic simm module commercial cym1841bpz-15c pz08 64-pin plastic zip module cym1841bp7-15c pm50 72-pin plastic simm module 20 cym1841bpm-20c pm03 64-pin plastic simm module commercial CYM1841BPZ-20C pz08 64-pin plastic zip module cym1841bp7-20c pm50 72-pin plastic simm module 25 cym1841bpm-25c pm03 64-pin plastic simm module commercial cym1841bpz-25c pz08 64-pin plastic zip module cym1841bp7-25c pm50 72-pin plastic simm module 35 cym1841bpm-35c pm03 64-pin plastic simm module commercial cym1841bpz-35c pz08 64-pin plastic zip module cym1841bp7-35c pm50 72-pin plastic simm module 45 cym1841bpm-45c pm03 64-pin plastic simm module commercial cym1841bpz-45c pz08 64-pin plastic zip module cym1841bp7-45c pm50 72-pin plastic simm module
cym1841 b document #: 38-05261 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams 64-pin zip module ? pz08 51-41310-** 64-pin plastic simm module ? pm03 51-41368-** 72-pin plastic simm module ? pm50 51-41375-**
cym1841 b document #: 38-05261 rev. *a page 9 of 9 document history page document title: cym1841b 256k x 32 static ram module document number: 38-05261 rev. ecn no. issue date orig. of change description of change ** 114352 3/22/02 dsg change from spec number: 38-m-00031 to 38-05261 *a 125739 04/28/03 cs changed iix and ioz unit to ua from ma and amended incorrected values shown on pages 2, 3 and 4.
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