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vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 2 of 12 document revision history 1: document revision from to date description changed by checked by a 2008.11.19 first release. (based on lcd counter drawing: cog-demo1003 (rev.0)) philip cheng tim wong
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 3 of 12 contents page no. 1. general description 4 2. mechanical specifications 4 3. interface signals 7 4. absolute maximum ratings 8 4.1 electrical maximum ratings - for ic only 8 4.2 environmental condition 8 5. electrical specifications 9 5.1 typical electrical characteristics 9 5.2 timing specifications 10 5.3 power-up sequence 11 5.4 power-down sequence 11 6. lcd cosmetic conditions 12 7. remark 12
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 4 of 12 varitronix limited preliminary specification of lcd module type model no.: COG-VL248160-02 1. general description ? 248x160 dots, fstn, black & white, positive, transflective, lcd graphic module. ? viewing angle: 12 o?clock. ? driving scheme: 1/160 duty, 1/12 bias. ? ?ultra chip? uc1698u (cog) lcd controller-driver. ? 8-bit parallel bus (8080). ? logic voltage: +3v. ? white led02 backlight. 2. mechanical specifications the mechanical detail is shown in fig. 1 and summarized in table 1 below. table 1 parameter specifications unit outline dimensions 63.0(w) x 66.7(h) x 8.3(d) mm viewing area 57.0(w) x 41.0(h) mm active area 53.31(w) x 35.19(h) mm display format 248(horizontal) x 160(vertical) dots dot size 0.205(w) x 0.21(h) mm dot spacing 0.01(w) x 0.01(h) mm dot pitch 0.215(w) x 0.22(h) mm weight approx. tbd grams
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 5 of 12 figure 1: outline drawing.
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 6 of 12 COG-VL248160-02 lcd graphic display 248 x 160 dots 80 'ultra chip' uc1698u (cog) lcd controller- driver 80 248 white led02 backlight vdd rd wr 8 d7 ~ d0 tst4 rs cs rst vss k a figure 2: block diagram
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 7 of 12 3. interface signals table 2 pin no. symbol description 1 nc 2 nc no connection. 3 vss ground. 4 vdd power supply. 5 tst4 test control. this pin has on-chip pull-up resistor. leave it open during normal operation. tst4 is also used as one of the high voltage power supply for mtp programming operation. for cog designs, please wire out tst4 with trace resistance between 30~50 ? . 6 nc no connection. 7 cs ______ cs ______ (cs0). chip select. chip is selected when cs ______ = ?l?. when the chip is not selected, d[7:0] will be high impedance. 8 rst ________ rst ________ (rst). when rst ________ =?l?, all control registers are re-initialized by their default states. since uc1698u has built-in power-on reset and software reset commands, rst ________ pin is not required for proper chip operation. an rc filter has been included on-chip. there is no need for external rc noise filter. when rst ________ is not used, connect the pin to vdd. 9 rs rs(cd). select control data or display data for read/write operation. ?l?: control data ?h?: display data 10 wr _______ 11 rd ________ rd ________ ,wr _______ (wr[1:0]) controls the read/write operation of the host interface. wr _______ (wr0):write. rd ________ (wr1):read. 12 d7 13 d6 14 d5 15 d4 16 d3 17 d2 18 d1 19 d0 bi-directional bus for parallel host interface. 20 vss ground. - a anode of led backlight. - k cathode of led backlight.
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 8 of 12 4. absolute maximum ratings 4.1 electrical maximum ratings - for ic only table 3 parameter symbol min. max. unit supply voltage vdd - vss -0.3 +4.0 v lcd driving voltage(-25 c to +75 c) vlcd -0.3 +19.8 v digital input voltage vin -0.4 vdd+0.5 v note: 1.) the modules may be destroyed if they are used beyond the absolute maximum ratings. 2.) vdd is based on vss = 0v. 4.2 environmental condition table 4 operating temperature (topr) storage temperature (tstg) (note 1) item min. max. min. max. remark ambient temperature -10 c +70 c -40 c +80 c dry humidity (note 1) 90% max. rh for ta 40 c < 50% rh for 40 c < ta maximum operating temperature no condensation vibration (iec 68-2-6) cells must be mounted on a suitable connector frequency: 10 55 hz amplitude: 0.75 mm duration: 20 cycles in each direction. 3 directions shock (iec 68-2-27) half-sine pulse shape pulse duration: 11 ms peak acceleration: 981 m/s 2 = 100g number of shocks: 3 shocks in 3 mutually perpendicular axes. 3 directions note 1: product cannot sustain at extreme storage conditions for long time.
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 9 of 12 5. electrical specifications 5.1 typical electrical characteristics at ta = 25 c, vdd=3v5% , vss=0v. table 5 parameter symbol conditions min. typ. max. unit supply voltage (logic) vdd-vss 2.85 3 3.15 v ta = -10 c, vdd=3v, note 1 - tbd - v ta = +25 c, vdd=3v, note 1 - tbd - v lcd driving voltage (built-in) vlcd ta = +70 c, vdd=3v, note 1 - tbd - v input logic high v ih 0.8 vdd - - v input logic low v il - - 0.2vdd v character mode - tbd - ma supply current (logic & lcd) idd checker board mode - tbd - ma supply voltage of white led02 backligh t vled - 5 - v luminance(on the backlight surface) forward current =tbdma number of led chips =tbd - tbd - cd/m 2 note 1 : there is tolerance in optimum lcd driving voltage during production and it will be within the specified range.
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 10 of 12 5.2 timing specifications 5.2.1 reset characteristics at ta = -10 c to +70 c, vdd=3v5%, vss = 0v refer to fig. 3 , the reset characteristics. table 6 figure 3: reset characteristics. 5.2.2 parallel bus timing characteristics (for 8080 mcu) at ta = -10 c to +70 c , vdd=3v5%, vss = 0v refer to fig. 4, parallel bus timing characteristics (for 8080 mcu) table 7 figure 4: parallel bus timing characteristics (for 8080 mcu)
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 11 of 12 5.3 power-up sequence uc1698u power-up sequence is simplified by builtin ?power ready? flags and the automatic invocation of system-reset command after power-on-reset . system programmers are only required to wait 150 ms before the cpu starting to issue commands to uc1698u. no additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to ram or any other commands. however, while turning on vdd, vdd2/3 should be started not later than vdd. delay allowance between vdd and vdd2/3 is illustrated as figure 7. figure 5: reference power-up sequence 5.4 power-down sequence to prevent the charge stored in capacitors cbx+, cbx?, and cl from damaging the lcd, when vdd is switched off, use reset mode to enable the built-in draining circuit and discharge these capacitors. the draining resistor is 10k ? for both vlcd and vb+. it is recommended to wait 3 x rc for vlcd and 1.5 x rc for vb+. for example, if cl is 0.1uf, then the draining time required for vlcd is ~3ms. when internal vlcd is not used, uc1698u will not drain vlcd during reset. system designers need to make sure external vlcd source is properly drained off before turning off vdd. figure 6:reference power-down sequence figure 7: delay allowance between vdd and vdd2/3
vl-ps-COG-VL248160-02 rev.a (cog-vl248160) nov/2008 page 12 of 12 6. lcd cosmetic conditions refer to the document: tbd. note: lcd size of the product is tbd. 7. remark ?varitronix limited reserves the right to change this specification.? tel:(852) 2197-6000. fax:(852) 2343-9555. url:http://www.varitronix.com - end -

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