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83006 / 52506hkim no.a0118-1/17 ver.1.00 lc863548c, LC863540C lc863532c, lc863528c lc863524c, lc863520c lc863516c overview the lc863548c/40c/32c/28c/24c/20c/16c are 8-bit single chip microcontrollers with the following on-chip functional blocks : ? cpu : operable at a minimu m bus cycle time of 0.424 s ? on-chip rom capacity program rom : 48k/40k/32k/28k/24k/20k/16k-bytes cgrom : 16k-bytes ? on-chip ram capacity : 640/512-bytes ? osd ram : 176 9-bits ? on-screen display controller ? four channels 6-bit ad converter ? three channels 7-bit pwm ? two channels 16-bit timer/counter, 14-bit base timer ? iic-bus compliant serial interface circuit (multi-master type) ? rom correction function ? 13-source 8-vectored interrupt system ? integrated system clock generator and display clock generator only one x?tal oscillator (32.768khz) for p ll reference is used for both generators. all of the above functions are fabricated on a single chip. ordering number : ena0118a cmos ic 48k/40k/32k/28k/24k/ 20k/16k-byte rom, cgrom16k-byte on-chip 640/512-byte ram and 176 9-bit osd ram 8-bit 1-chip microcontroller trademarks iic is a trademark of phili p s cor p oration. n ote : this product includes the iic bus inte rface circuit. if you intend to use the iic bus interface, pleas e notify us of thi s in advance of our receiving your program rom code order. purchase of sanyo iic components conveys a license under the philips iic patents rights to use these components in an iic system, provided that the sy stem conforms to the iic standard specification as defined by philips. any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before usingany sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-2/17 features ? read-only memory (rom) : 49152 8-bits/40960 8-bits/32768 8-bits/ 28672 8-bits/24576 8-bits/20480 8-bits/ 16384 8-bits for program 16128 8-bits for cgrom ? random access memory (ram) : 512 8-bits (working area) : lc863548c/40c 384 8-bits (working area) : lc863532c/28c/24c/20c/16c 128 8-bits (working or rom correction function) 176 9-bits (for crt display) ? osd functions ? screen display : 36 characters 8 lines (by software) ? ram : 176 words (9-bits per word) display area : 36 words 4 lines control area : 8 words 4 lines ? characters up to 252 kinds of 16 32 dot character fonts (4 ch aracters including 1 test char acter are not programmable) each font can be divided into two parts and used as two fonts (ex. 16 16 dot character font 2) ? various character attributes character colors : 16 colors (analog mode : l vp-p output) /8 colors (digital mode) character background colors : 16 colors (analog mode : l vp-p output) /8 colors (digital mode) fringe/shadow colors : 16 colors (analog mode : l vp-p output) /8 colors (digital mode) full screen colors : 16 colors (analog mode : l vp-p output) /8 colors (digital mode) rounding underline italic character (slanting) ? attribute can be changed without spacing ? vertical display start line number can be set for each row independently (rows can be overlapped) ? horizontal display start position can be set for each row independently ? horizontal pitch (9 to 16 dots) *1 and vertical pitch (1 to 32 dots) can be set for each row independently ? different display modes can be set for each row independently caption ? text mode/osd mode 1/osd mode 2 (quarter size) /simplified graphic mode ? ten character sizes *1 horez. vert. = (1 1), (1 2), (2 2), (2 4), (0.5 0.5) (1.5 1), (1.5 2), (3 2), (3 4), (0.75 0.5) ? shuttering and sc rolling on each row ? simplified graphic display *1 note : range depends on display mode : refer to the manual for details. ? bus cycle time/instruction-cycle time bus cycle time instruction cycle time clock divider system clock oscillation oscillation frequency voltage 0.424 s 0.848 s 1/2 internal vco (ref : x'tal 32.768khz) 14.156mhz 4.5v to 5.5v 7.5 s 15.0 s 1/2 internal rc 800khz 4.5v to 5.5v 91.55 s 183.1 s 1/1 crystal 32.768khz 4.5v to 5.5v 183.1 s 366.2 s 1/2 crystal 32.768khz 4.5v to 5.5v ? ports ? input/output ports : 4 ports (24 terminals) data direction programmable in nibble units : 1 port (8 terminals) (if the n-ch open drain output is selected by option, the corresponding port data can be read in output mode.) data direction programmable for each bit individually : 3 ports (16 terminals) ? ad converter ? 4-channels 6-bit ad converters
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-3/17 ? serial interfaces ? iic-bus compliant serial in terface (multi-master type) consists of a single built-in circuit with two i/o channels . the two data lines and two clock lines can be connected internally. ? pwm output ? 3-channels 7-bit pwm ? timer ? timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-b it programmable prescaler mode 0 : two 8-bit timers with a programmable prescaler mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter mode 2 : 16-bit timer with a programmable prescaler mode 3 : 16-bit counter the resolution of timer is 1 tcyc. ? timer 1 : 16-bit timer/ pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : a variable-bit pwm (9 to 16 bits) in mode 0/1, the resolution of timer/pwm is 1 tcyc in mode 2/3, the resolution of timer/pwm is selectable by program ; tcyc or 1/2 tcyc ? base timer generate every 500ms overflow for a clock application (using 32.768khz crystal oscillation for the base timer clock) generate every 976 s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768khz crystal oscillation for the base timer clock) clock for the base timer is selectable from 32.768khz cr ystal oscillation, system clock or programmable prescaler output of timer 0 ? remote control receiver circuit (conn ected to the p73/in t3/t0in terminal) ? noise rejection function ? polarity switching ? watchdog timer external rc circuit is required interrupt or system reset is activated when the timer overflows ? rom correction function max 128-bytes/2 addresses ? interrupts ? 13 sources 8 vectored interrupts 1. external interrupt int0 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8-bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8-bits) 6. timer t1h, timer t1l 7. vertical synchronous signal interrupt ( vs ), horizontal line ( hs ) 8. iic, software ? interrupt priority control three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. low or high priority can be assigned to the interrupts from 3 to 8 listed above. for the external interrupt int0 and int1 , low or highest priority can be set.
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-4/17 ? sub-routine stack level ? a maximum of 128 levels (stack is built in the internal ram) ? multiplication/division instruction ? 16-bits 8-bits (7 instruction cycle times) ? 16-bits 8-bits (7 instruction cycle times) ? 3 oscillation circuits ? built-in rc oscillation circuit used for the system clock ? built-in vco circuit used for the system clock and osd ? x?tal oscillation circuit used for base timer, system clock and pll reference ? standby function ? halt mode the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this mode can be released by the interrupt request or the system reset. ? hold mode the hold mode is used to stop the oscillations ; rc (internal), vco, and x?tal oscillations. this mode can be released by the following conditions. 1. pull the reset terminal ( res ) to low level. 2. feed the selected level to either p70/int0 or p71/int1. ? package ? mfp36sdj (lead-free type) ? dip36s (lead-free type) ? development tools ? flash eeprom : lc86f3548a ? evaluation chip : lc863096 ? emulator : eva86000 (main) + ecb863200a (evaluation chip board) + sub863400a (sub board) + pod36-cable (cable) + pod36-dip (for dip36s) or pod36-mfp (for mfp36sdj)
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-5/17 package dimensions unit : mm 3263 package dimensions unit : mm 3170a sanyo : mfp36sdj(375mil) 1 18 36 19 0.8 15.2 0.3 0.65 10.5 7.9 0.25 (0.8) 2.45max 0.1 (2.25) 3.95max (3.25) 0.51min 3.0 32.4 8.6 0.95 0.25 (1.1) 1.78 0.48 10.16 118 36 19 sanyo : dip36s(400mil)
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-6/17 pin assignment p03 p02 p01 p00 p17/pwm p16/pwm3 p15/pwm2 p14/pwm1 p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p32 p31 bl b g r p10/sda0 p11/sclk0 p12/sda1 p13/sclk1 v ss xt1 xt2 v dd p04/an4 p05/an5 p06/an6 p07/an7 res filt p33 p30 vs hs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 top view lc863548c LC863540C lc863532c lc863528c lc863524c lc863520c lc863516c
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-7/17 system block diagram interrupt control standby control clock generator x?tal vco rc pll ir pla rom pc acc b register c register alu psw rar ram stack pointer port 0 watch dog timer rom correct control xram bus interface port 1 port 3 port 7 osd control circuit vram cgrom iic timer 0 base timer adc int0 to 3 noise rejection filter pwm timer 1
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-8/17 pin description pin name i/o function option v ss - negative power supply xt1 i input terminal for crystal oscillator xt2 o output terminal for crystal oscillator v dd - positive power supply res i reset terminal filt o filter terminal for pll vs i vertical synchronization signal input terminal hs i horizontal synchronization signal input terminal r o red (r) output terminal of rgb image output g o green (g) output terminal of rgb image output b o blue (b) output terminal of rgb image output bl o fast blanking control signal switch tv image signal and caption/osd image signal port 0 p00 to p07 i/o ? 8-bit input/output port input/output can be specified in nibble unit (if the n-ch open drain output is selected by option, the corresponding port data can be read in output mode.) ? other functions ad converter input port (p04 to p07 : 4-channels) pull-up resistor provided/not provided output format cmos/nch-od port 1 ? 8-bit input/output port input/output can be specified for each bit (programmable pull-up resister provided) ? other functions p10 p11 p12 p13 p14 p15 p16 p17 iic0 data i/o iic0 clock output iic1 data i/o iic1 clock output pwm1 output pwm2 output pwm3 output timer 1 (pwm) output p10 to p17 i/o output format cmos/nch-od port 3 p30 to p33 i/o ? 4-bit input/output port input/output can be specified for each bit (cmos output/input with programmable pull-up resister) port 7 ? 4-bit input/output port input or output can be specified for each bit p70 : i/o with programmable pull-up resister p71 to p73 : cmos output/input with programmable pull-up resister ? other function p70 p71 p72 p73 int0 input/hold release input/ nch-tr. output for watchdog timer int1 input/hold release input int2 input/timer 0 event input int3 input (noise rejection filter connected) / timer 0 event input interrupt receiver format, vector addresses rising falling rising/ falling h level l level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h p70 p71 to p73 i/o int3 enable enable enable disable disable 1bh note : a capacitor of at least 10 f must be inserted between v dd and v ss when using this ic. continued on next page.
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-9/17 continued from preceding page. ? output form and existence of pull-up resistor for all ports can be specified for each bit. ? programmable pull-up resistor is always connected regardless of port option, cmos or n-ch open drain output in port 1. ? port status in reset terminal i/o pull-up resistor status at selecting cmos output option port 0 i pull-up resistor off, on after reset release port 1 i programmable pull-up resistor off absolute maximum ratings / ta = 25c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd -0.3 +6.5 input voltage v i (1) res , hs , vs -0.3 v dd +0.3 output voltage v o (1) r, g, b, bl, filt -0.3 v dd +0.3 input/output voltage v io ports 0, 1, 3, 7 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 3, 7 ? cmos output ? for each pin. -4 peak output current ioph(2) r, g, b, bl ? cmos output ? for each pin. -5 ioah(1) ports 0, 1 the total of all pins. -20 ioah(2) ports 3, 7 the total of all pins. -10 high level output current total output current ioah(3) r, g, b, bl the total of all pins. -12 iopl(1) ports 0, 1, 3 for each pin. 20 iopl(2) port 7 for each pin. 15 peak output current iopl(3) r, g, b, bl for each pin. 5 ioal(1) ports 0, 1 the total of all pins. 40 ioal(2) ports 3, 7 the total of all pins. 20 low level output current total output current ioal(3) r, g, b, bl the total of all pins. 12 ma mfp36sdj 360 maximum power dissipation pd max dip36s ta = -10 to +70c 610 mw operating temperature range topr -10 +70 storage temperature range tstg -55 +125 c recommended operating range / ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit v dd (1) 0.844 s tcyc 0.852 s 4.5 5.5 operating supply voltage range v dd (2) v dd 4 s tcyc 400 s 4.5 5.5 hold voltage v hd v dd rams and the registers data are kept in hold mode. 2.0 5.5 v ih (1) port 0 output disable 4.5 to 5.5 0.6v dd v dd v ih (2) ? ports 1, 3 (schumitt) ? port 7 (schumitt) port input/interrupt ? res , hs , vs (schumitt) output disable 4.5 to 5.5 0.75v dd v dd high level input voltage v ih (3) port 70 watchdog timer input output disable 4.5 to 5.5 v dd -0.5 v dd v continued on next page.
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-10/17 continued from preceding page. limits parameter symbol pins conditions v dd [v] min typ max unit v il (1) port 0 output disable 4.5 to 5.5 v ss 0.2v dd v il (2) ? ports 1, 3 (schumitt) ? port 7 (schumitt) port input/interrupt ? res , hs , vs (schumitt) output disable 4.5 to 5.5 v ss 0.25v dd low level input voltage v il (3) port 70 watchdog timer input output disable 4.5 to 5.5 v ss 0.6v dd v tcyc(1) ? all functions operating 4.5 to 5.5 0.844 0.848 0.852 operation cycle time tcyc(2) ? osd is not operating 4.5 to 5.5 0.844 400 s oscillation frequency range fmrc internal rc oscillation 4.5 to 5.5 0.4 0.8 3.0 mhz electrical characteristics / ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 3, 7 ? output disable ? pull-up mos tr. off ? v in = v dd (including the off-leak current of the output tr.) 4.5 to 5.5 1 high level input current i ih (2) ? res ? hs , vs ? v in = v dd 4.5 to 5.5 1 i il (1) ports 0, 1, 3, 7 ? output disable ? pull-up mos tr. off ? v in = v ss (including the off- leak current of the output tr.) 4.5 to 5.5 -1 low level input current i il (2) ? res ? hs , vs v in = v ss 4.5 to 5.5 -1 a v oh (1) ? cmos output of ports 0, 1, 3, 71 to 73 i oh = -1.0ma 4.5 to 5.5 v dd -1 high level output voltage v oh (2) r, g, b, bl i oh = -0.1ma r. g. b : digital mode 4.5 to 5.5 v dd -0.5 v ol (1) ports 0, 1, 3, 71 to 73 i ol = 10ma 4.5 to 5.5 1.5 v ol (2) ports 0, 3, 71 to 73 i ol = 1.6ma 4.5 to 5.5 0.4 v ol (3) ? r, g, b, bl ? port 1 i ol = 3.0ma r. g. b : digital mode 4.5 to 5.5 0.4 low level output voltage v ol (4) port 70 i ol = 1ma 4.5 to 5.5 0.4 v pull-up mos tr. resistance rpu ? ports 0, 1, 3, 7 v oh = 0.9v dd 4.5 to 5.5 13 38 80 k ? bus terminal short circuit resistance (scl0 to scl1, sda0 to sda1) rbs ? p10 to p12 ? p11 to p13 4.5 to 5.5 130 300 ? hysteresis voltage vhis ? ports 1, 3, 7 ? res ? hs , vs output disable 4.5 to 5.5 0.1v dd v pin capacitance cp all pins ? f = 1mhz ? every other terminals are connected to v ss . ? ta = 25c 4.5 to 5.5 10 pf
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-11/17 iic input/output conditions / ta = -10c to +70c, v ss = 0v standard high speed parameter symbol min max min max unit scl frequency fscl 0 100 0 400 khz bus free time between stop to start tbuf 4.7 - 1.3 - s hold time of start, restart condition thd ; sta 4.0 - 0.6 - s l time of scl tlow 4.7 - 1.3 - s h time of scl thigh 4.0 - 0.6 - s set-up time of restart condition tsu ; sta 4.7 - 0.6 - s hold time of sda thd ; dat 0 - 0 0.9 s set-up time of sda tsu ; dat 250 - 100 - ns rising time of sda, scl tr - 1000 20 + 0.1cb 300 ns falling time of sda, scl tf - 300 20 + 0.1cb 300 ns set-up time of stop condition tsu ; sto 4.0 - 0.6 - s refer to figure 7 note : cb : total capacitance of all bus (unit : pf) pulse input conditions / ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) ?int0, int1 ?int2/t0in ? interrupt acceptable ? timer 0-countable 4.5 to 5.5 1 tpih(2) tpil(2) int3/t0in (1 tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer 0-countable 4.5 to 5.5 2 tpih(3) tpil(3) int3/t0in (16 tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer 0-countable 4.5 to 5.5 32 tpih(4) tpil(4) int3/t0in (64 tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer 0-countable 4.5 to 5.5 128 tcyc tpil(5) res reset acceptable 4.5 to 5.5 200 high/low level pulse width tpih(6) tpil(6) hs , vs ? display position controllable (note) ? the active edge of hs and vs must be apart at least 1 tcyc. ? refer to figure 4. 4.5 to 5.5 3 s rising/falling time tthl ttlh hs refer to figure 4. 4.5 to 5.5 500 ns ad converter characteristics / ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 6 bit absolute precision et (note) 1 lsb conversion time tcad vref selection to conversion finish 1-bit conversion time = 2 tcyc 1.69 s analog input voltage range vain v ss v dd v iainh vain = v dd 1 analog port input current iainl an4 to an7 vain = v ss 4.5 to 5.5 -1 a note : absolute precision does not include quantizing error (1/2lsb).
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-12/17 analog mode rgb characteristics / ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit low level output 0.45 0.5 0.55 intensity output 0.90 1.0 1.10 analog output voltage r. g. b analog output mode hi level output 1.35 1.5 1.65 v time setting r. g. b 70% 10pf load 5.0 50 ns sample current dissipation characteristics / ta = -10c to +70c, v ss = 0v the sample current dissipation characteristics are the measurement result of sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. the currents through the output transistors and the pull-up mos transistors are ignored. limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) v dd ? fmx?tal = 32.768khz x?tal oscillation ? system clock : vco ? vco for osd operating ? osd is digital mode ? internal rc oscillation stops 4.5 to 5.5 9 22 iddop(2) v dd ? fmx?tal = 32.768khz x?tal oscillation ? system clock : vco ? vco for osd operating ? osd is analog mode ? internal rc oscillation stops 4.5 to 5.5 18 32 ma current dissipation during basic operation (note 3) iddop(3) v dd ? fmx?tal = 32.768khz x?tal oscillation ? system clock : x?tal (instruction cycle time : 366.2 s) ? vco for system vco for osd, internal rc oscillation stop ? data slicer, ad converters stop 4.5 to 5.5 65 300 a iddhalt(1) v dd ? halt mode ? fmx?tal = 32.768khz x?tal oscillation ? system clock : vco ? vco for osd stops ? internal rc oscillation stops 4.5 to 5.5 3 9 ma iddhalt(2) v dd ? halt mode ? fmx?tal = 32.768khz x?tal oscillation ? vco for system stops ? vco for osd stops ? system clock : internal rc 4.5 to 5.5 300 1000 current dissipation in halt mode (note 3) iddhalt(3) v dd ? halt mode ? fmx?tal = 32.768khz x?tal oscillation ? vco for system stops ? vco for osd stops ? system clock : x?tal (instruction cycle time : 366.2 s) 4.5 to 5.5 57 200 a current dissipation in hold mode (note 3) iddhold v dd ? hold mode ? all oscillation stop s. 4.5 to 5.5 0.05 20 a note 3 : the currents through the output transistors and the pull-up mos transistors are ignored.
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-13/17 recommended oscillation circui t and sample characteristics the sample oscillation circuit characteristics in the table below is based on the following conditions : ? recommended circuit parameters are verified by an oscillator manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluatio n with the recommended circuit parameters connected externally. recommended oscillation circuit and sample characteristics (ta = -10 to +70c) recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rf rd operating supply voltage range typ max notes 32.768khz seiko epson c-002rx 18pf 18pf open 390k ? 4.5 to 5.5v 1.0s 1.5s notes : the oscillation stabilizing time period is the time until the vco oscillation for the internal system becomes stable after the following conditions. (refer to figure 2.) 1. the v dd becomes higher than the minimum operating voltage after the power is supplied. 2. the hold mode is released. the sample oscillation circuit characteristics may differ applications. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of th e application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and the operating supply vo ltage range are based on the operating temperature of -10c to +70c. for the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. ? when using the oscillator which is not shown in the samp le oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by th e noise or wiring capacity becau se the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (xt1 terminal xt 2 terminal) and external parts should be as short as possible. ? the capacitors? v ss should be allocated close to the microcontrolle r?s gnd terminal and be away from other gnd. ? the signal lines with rapid state changes or with large cu rrent should be allocated away from the oscillation circuit. figure 1 recommended oscillation circuit c1 rd c2 x ? tal xt2 xt1 rf
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-14/17 figure 2 oscillation stabilizing time power supply res internal rc resonato r oscillation xt1, xt2 vco for system operation mode reset time v dd v dd limit 0v unfixed instruction execution mode reset tmsvco stable tmsvco stable valid instruction execution mode hold hold release xt1, xt2 vco for system operation mode internal rc resonato r oscillation
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-15/17 figure 3 pulse input timing condition - 1 figure 4 pulse input timing condition - 2 figure 5 recommended interface circuit tpih (1) to (4) tpil (1) to (5) tpil(6) tpil(6) ttlh 0.75v dd 0.25v dd more than 1tcyc hs vs lc863548c hs 10k ? c536 hs
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-16/17 figure 6 filt recommended circuit note : place filt parts on board as clos e to the microcontroller as possible. s : start condition tsp : spike suppression standard mode : not exist p : stop condition high speed mode : less than 50ns sr : restart condition figure 7 iic timing figure 8 r. g. b. analog output equivalent circuit sd a scl p s s r p tbuf thd ; sta tr tlow thd ; dat thigh tf tsu ; dat tsu ; sta thd ; sta tsp tsu ; sto filt 100 ? 1m ? 2.2 f 33000pf + - pad i 1ma r 500 ? ii
lc863548c/40c/32c/28c/24c/20c/16c no.a0118-17/17 ps specifications of any and all sanyo semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high- quality high-reliability products. however, any and all semiconductor products fail with some probabi lity. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. sanyo semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides i nformation as of may, 2006. specificati ons and information her ein are subject to change without notice.

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