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data sheet ics8s89834aki revision a february 4, 2010 1 ?2010 integrated device technology, inc. low skew, 2- t o-4 lvcmos/lvttl-to- lvpecl/ecl clock multiplexer ics8s89834i general description the ics8s89834i is a high speed 2-to-4 lvcmos/lvttl-to-lvpecl/ecl clock multiplexer. the ics8s89834i is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the device also has an output enable pin which may be useful for system test and debug purposes. the ics8s89834i is packaged in a small 3mm x 3mm 16-pin vfqfn package which makes it ideal for use in space-constrained applications. features ? four differential lvpecl/ecl output pairs ? two lvcmos/lvttl clock inputs ? maximum output frequency: 1ghz ? output skew: 30ps (maximum) ? part-to-part skew: 100ps (maximum) ? propagation delay: 550ps (maximum) ? additive phase jitter, rms: 0.12ps (typical) ? full 3.3v and 2.5v operating supply modes ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package hiperclocks? ic s ics8s89834i 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment d ck q q0 nq0 q1 nq1 q2 nq2 q3 nq3 in1 in2 en sel pullup pullup pullup pullup 1 0 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 q1 nq1 q2 nq2 in1 sel nc in2 q3 nq3 v cc en q0 v cc v ee nq0
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 2 ?2010 integrated device technology, inc. table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q1, nq1 output differential output pair. lvpecl/ecl interface levels. 3, 4 q2, nq2 output differential output pair. lvpecl/ecl interface levels. 5, 6 q3, nq3 output differential output pair. lvpecl/ecl interface levels. 7, 14 v cc power positive supply pins. 8 en input pullup synchronizing clock enable. when low, q ou tputs will go low and nq outputs will go high on the next low transition at in inputs. input threshold is v cc /2v. includes a 37k ? pullup resistor. default state is high wh en left floating. the internal latch is clocked on the falling edge of the input signal in1, in2. lvttl/lvcmos in terface levels. 9 in2 input pullup single-ended clock input. lvcmos/lvttl interface levels. 10 nc unused no connect. 11 sel input pullup select clock input. when low, sele cts in2 and when high selects in1. lvcmos/lvttl interface levels. 12 in1 input pullup single-ended clock input. lvcmos/lvttl interface levels. 13 v ee power negative supply pin. 15, 16 q0, nq0 output differe ntial output pair. lvpecl/ecl interface levels. symbol parameter test conditions minimum typical maximum units r pullup input pullup resistor 37 k ?
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 3 ?2010 integrated device technology, inc. function tables table 3a. control input function table note: en switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1. figure 1. en timing diagram table 3b. truth table note 1: on next negative transition of the input signal (in). table 3c. sel control function table . inputs outputs en selected sour ce q[0:3] nq[0:3] 0 in1, in2 disabled; low disabled; high 1 in1, in2 enabled enabled enabled disabled en in1, in2 nqx qx inputs outputs in1, in2 in1, in2 en q[0:3] nq[0:3] 0x101 1x110 x0101 x1110 xx00 (note 1) 1 (note 1) sel input selected 0in2 1in1
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 4 ?2010 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 10%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4c. lvcmos/lvttl dc characteristics, v cc = 2.5v 5% or 3.3v 10%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v (lvpecl mode, v ee = 0v) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0v) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o continuos current surge current 50ma 100ma operating temperature range, t a -40c to +85c package thermal impedance, ja , (junction-to-ambient) 74.7 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 2.97 3.3 3.63 v i ee power supply current 52 ma symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 2.375 2.5 2.625 v i ee power supply current 52 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current v cc = v in = 3.63v or 2.625v 10 a i il input low current v cc = 3.63v or 2.625v, v in = 0v -150 a
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 5 ?2010 integrated device technology, inc. table 4d. lvpecl dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc - 2v. ac electrical characteristics table 5. ac characteristics, v cc = 2.5v 5% or or 3.3v 10%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when t he device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters are measured at 1ghz unless otherwise noted. note 1: measured from v cc /2 of the input to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same frequency and with equa l load conditions. using the same type of inputs on each devi ce, the outputs are measured at the differential cross points. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.145 v cc ? 0.80 v v ol output low voltage; note 1 v cc ? 1.945 v cc ? 1.60 v v out output voltage swing 0.6 1.0 v v diff_out differential output voltage swing 1.2 2.0 v symbol parameter test conditions minimum typical maximum units f max maximum frequency 1ghz t plh propagation delay; low-to-high; note 1 250 550 ps t phl propagation delay; high-to-low; note 1 300 550 ps t sw switchover time sel to q 300 550 ps t sk(o) output skew; note 2, 3 30 ps t sk(pp) part-to-part skew; note 3, 4 100 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 200mhz integration range: (12khz - 20mhz) 0.12 ps t s clock enable setup time en to in1, in2 300 ps t h clock enable hold time en to in1, in2 500 ps t r / t f output rise/fall time 20% to 80% 50 250 ps odc output duty cycle f max < 622mhz 48 52 % f max 622mhz 45 55 %
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 6 ?2010 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10khz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". additive phase jitter @ 200mhz 12khz to 20mhz = 0.12ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 7 ?2010 integrated device technology, inc. parameter measureme nt information 3.3v lvpecl output load ac test circuit part-to-part skew setup & hold time 2.5v lvpecl output load ac test circuit output skew propagation delay scope qx nqx lvpecl v ee v cc 2v -1.3v0.33v nqx qx nqy qy t sk(pp) part 1 part 2 t hold t set-up v dd 2 in1, in2 en scope qx nqx lvpecl v ee v cc 2v -0.5v 0.125v t sk(o) qx nqx qy nqy tp lh tp hl nq0:nq3 q0:q3 in1, in2
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 8 ?2010 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time differential output voltage swing switch over output duty cycle/pulse width/period application information recommendations for unused input and output pins inputs: in inputs for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the in input to ground. lvcmos control pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. 20% 80% 80% 20% t r t f v out nq0:nq3 q0:q3 v in , v out 800mv (typical) v diff_in , v diff_out 1600mv (typical) t sw nq0:nq3 q0:q3 sel in2 in1 t pw t period t pw t period odc = x 100% nq0:nq3 q0:q3
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 9 ?2010 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 2. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 2. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 10 ?2010 integrated device technology, inc. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 11 ?2010 integrated device technology, inc. termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 12 ?2010 integrated device technology, inc. power considerations this section provides information on power dissipation and junction temperature for the ics8s89834i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8s89834i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.63v * 52ma = 188.76mw power (outputs) max = 32mw w/loaded output pair if all outputs are loaded, the total power is 4 * 32mw = 128mw total power_ max = (3.63v, with all outputs s witching) = 188.76mw + 128mw = 316.76mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.317w * 74.7c/w = 108.7c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 13 ?2010 integrated device technology, inc. 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 5. figure 5. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.80v (v cc_max ? v oh_max ) = 0.80v for logic low, v out = v ol_max = v cc_max ? 1.60v (v cc_max ? v ol_max ) = 1.60v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.80v)/50 ? ] * 0.80v = 19.20mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v co_max ? v ol_max ) = [(2v ? 1.60v)/50 ? ] * 1.60v = 12.80mw total power dissipation per output pair = pd_h + pd_l = 32mw v out v cc v cc - 2v q1 rl 50
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 14 ?2010 integrated device technology, inc. reliability information table 6. ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ics8s89834i is: 351 this device is pin and function compatible and a suggested replacement for ics889834. ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 15 ?2010 integrated device technology, inc. package outline and package dimensions package outline - k suffix for 16 lead vfqfn table 7. package dimensions reference document: jede c publication 95, mo-220 jedec variation: veed-2/-4 all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 4 d & e 3.00 basic d2 & e2 1.00 1.80 e 0.50 basic l 0.30 0.50 top vie w index a re a d cham fer 4x 0.6 x 0.6 max optional a 0. 0 8 c c a3 a1 seating plan e e2 e2 2 l (n -1)x e (r e f.) (ref.) n & n eve n n e d2 2 d2 (ref.) n& n od d 1 2 e 2 (typ.) if n & n are eve n (n -1)x e (re f.) b thermal bas e n de d de de e anvil singulation or sawn singulation n-1 n chamfer 1 2 n-1 1 2 n radius n-1 1 2 n aa dd cc bb 4 4 4 4 4 4 bottom view w/type b id bottom view w/type c id bottom view w/type a id there are 3 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type b: dummy pad between pin 1 and n. 3. type c: mouse bite on the paddle (near pin 1)
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer ics8s89834aki revision a february 4, 2010 16 ?2010 integrated device technology, inc. ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8S89834AKILF 834a ?lead-free? 16 lead vfqfn tube -40 c to 85 c 8S89834AKILFt 834a ?lead-free? 16 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics8s89834i data sheet low skew, 2-to-4 lv cmos/lvttl-to-lvpecl/ecl clock multiplexer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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