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vcxo jitter attenuator & ics810252i-03 idt ? / ics ? vcxo jitter attenuator/multiplier 1 ics810252aki-03 rev. b october 24, 2007 preliminary femtoclock? multiplier g eneral d escription the ics810252i-03 is a member of the hiperclocks? family of high performance clock solutions from idt. the ics810252i-03 is a pll based synchronous multiplier that is optimized for pdh or sonet to ethernet clock jitter attenuation and frequency translation. the device contains two internal frequency multiplication stages that are cascaded in series. the first stage is a vcxo pll that is optimized to provide reference clock jitter attenuation. the second stage is a femtoclock? frequency m ultiplier that provides the low jitter, high frequency ethernet output clock that easily meets gigabit and 10 gigabit ethernet jitter requirements. pre-divider and output divider multiplication ratios are selected using device selection control pins. the multiplication ratios are optimized to support most common clock rates used in pdh, sonet and ethernet applications. the vcxo requires the use of an external, inexpensive pullable crystal. the vcxo uses external passive loop filter components which allows configuration of the pll loop bandwidth and damping characteristics. the device is packaged in a space-saving 32-vfqfn package and supports industrial temperature range. p in a ssignment hiperclocks? ic s f eatures ? two lvcmos/lvttl outputs, 15 impedance each output supports independent frequency selection at 25mhz, 62.5mhz, 125mhz, and 156.25mhz ? two differential inputs support the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? accepts input frequencies from 8khz to 155.52mhz including 8khz, 1.544mhz, 2.048mhz, 19.44mhz, 25mhz, 77.76mhz, 125mhz and 155.52mhz ? attenuates the phase jitter of the input clock by using a low- cost pullable funamental mode vcxo crystal ? vcxo pll bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection ? femtoclock frequency multiplier provides low jitter, high frequency output ? absolute pull range: 50ppm ? femtoclock vco frequency: 625mhz ? rms phase jitter @ 125mhz, using a 25mhz crystal (12khz - 20mhz): 1.5ps (typical) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd v ddo _ qb qb gnd v ddo _ qa qa gnd odasel_0 ics810252i-03 pdsel_2 pdsel_1 pdsel_0 v dd v dda odbsel_1 odbsel_0 odasel_1 nclk1 clk1 v dd nclk0 clk0 xtal_out xtal_in v ddx lf1 lf0 iset gnd clk_sel v dd reserved gnd 32-lead vfqfn 5mm x 5mm x 0.925 package body k package top view 32-lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? vcxo jitter attenuator/multiplier 2 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary b lock d iagram charge pump vcxo phase detector qa output divider 00 = 25 01 = 5 10 = 4 11 = 10 vcxo feedback divider 3125 vcxo input pre-divider vcxo jitter attenuation pll xt al_in xt al_out lf1 lf0 iset loop filter odasel_[1:0] clk0 pdsel_[2:0] nclk0 0 1 25mhz 2 qb output divider 00 = 25 01 = 5 10 = 4 11 = 10 odbsel_[1:0] 2 femtoclock pll 625mhz 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 clk1 nclk1 clk_sel pulldown pullup
idt ? / ics ? vcxo jitter attenuator/multiplier 3 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v , x d d v , , a q _ o d d v b q _ o d d v 5 6 4 . 3 =d b tf p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o 5 1 t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 f l , 1 f l g o l a n a t u p t u o / t u p n i . s n i p e d o n n o i t c e n n o c r e t l i f p o o l 3t e s i g o l a n a t u p t u o / t u p n i . n i p g n i t t e s t n e r r u c p m u p e g r a h c , 8 1 , 8 , 4 4 2 , 1 2 d n gr e w o p. d n u o r g y l p p u s r e w o p 5l e s _ k l ct u p n in w o d l l u p . 1 k l c n / 1 k l c s t c e l e s h g i h n e h w . t c e l e s k c o l c t u p n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 0 k l c n / 0 k l c s t c e l e s , w o l n e h w 7 2 , 2 1 , 6v d d r e w o p. s n i p y l p p u s r e w o p e r o c 7d e v r e s e rd e v r e s e r. t c e n n o c t o n o d . n i p d e v r e s e r , 9 , 0 1 1 1 , 2 _ l e s d p , 1 _ l e s d p 0 _ l e s d p t u p n ip u l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s r e d i v i d - e r p . a 3 e l b a t e e s 3 1v a d d r e w o p. n i p y l p p u s g o l a n a , 4 1 5 1 , 1 _ l e s b d o 0 _ l e s b d o t u p n in w o d l l u p . b 3 e l b a t e e s . t u p t u o b k n a b r o f s n i p t c e l e s y c n e u q e r f . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 6 1 7 1 , 1 _ l e s a d o 0 _ l e s a d o t u p n in w o d l l u p . b 3 e l b a t e e s . t u p t u o a k n a b r o f s n i p t c e l e s y c n e u q e r f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 1a qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c d e d n e - e l g n i s a k n a b 5 1 . e c n a d e p m i t u p t u o 0 2v a q _ o d d r e w o p. t u p t u o k c o l c a q r o f n i p y l p p u s r e w o p t u p t u o 2 2b qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c d e d n e - e l g n i s b k n a b 5 1 . e c n a d e p m i t u p t u o 3 2v b q _ o d d r e w o p. t u p t u o k c o l c b q r o f n i p y l p p u s r e w o p t u p t u o 5 21 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w e g a t l o v s a i b 2 / 6 21 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 8 20 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w e g a t l o v s a i b 2 / 9 20 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n , 0 3 1 3 , t u o _ l a t x n i _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 2 3v x d d r e w o p. p m u p e g r a h c o x c v r o f n i p y l p p u s r e w o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? vcxo jitter attenuator/multiplier 4 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 3a. p re -d ivider f unction t able t able 3b. o utput d ivider f unction t able s t u p n i e u l a v r e d i v i d - e r p 2 _ l e s d p1 _ l e s d p0 _ l e s d p 000 1 00 1 3 9 1 010 6 5 2 011 0 3 4 2 10 0 5 2 1 3 10 1 0 2 7 9 110 5 2 6 5 1 111 ) t l u a f e d ( 0 4 4 9 1 s t u p n i e u l a v r e d i v i d t u p t u o 1 _ l e s x d o0 _ l e s x d o 00 ) t l u a f e d ( 5 2 01 5 10 4 11 0 1
idt ? / ics ? vcxo jitter attenuator/multiplier 5 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 3c. f requency f unction t able t u p n i y c n e u q e r f ) z h m ( r e d i v i d - e r p e u l a v o x c v y c n e u q e r f ) z h m ( k c o l c o t m e f r e d i v i d k c a b d e e f e u l a v k c o l c o t m e f y c n e u q e r f o c v ) z h m ( r e d i v i d t u p t u o e u l a v y c n e u q e r f t u p t u o ) z h m ( 8 0 0 . 015 25 25 2 65 25 2 8 0 0 . 015 25 25 2 65 5 2 1 8 0 0 . 015 25 25 2 64 5 2 . 6 5 1 8 0 0 . 015 25 25 2 60 15 . 2 6 4 4 5 . 13 9 15 25 25 2 65 25 2 4 4 5 . 13 9 15 25 25 2 65 5 2 1 4 4 5 . 13 9 15 25 25 2 64 5 2 . 6 5 1 4 4 5 . 13 9 15 25 25 2 60 15 . 2 6 8 4 0 . 26 5 25 25 25 2 65 25 2 8 4 0 . 26 5 25 25 25 2 65 5 2 1 8 4 0 . 26 5 25 25 25 2 64 5 2 . 6 5 1 8 4 0 . 26 5 25 25 25 2 60 15 . 2 6 4 4 . 9 10 3 4 25 25 25 2 65 25 2 4 4 . 9 10 3 4 25 25 25 2 65 5 2 1 4 4 . 9 10 3 4 25 25 25 2 64 5 2 . 6 5 1 4 4 . 9 10 3 4 25 25 25 2 60 15 . 2 6 5 25 2 1 35 25 25 2 65 25 2 5 25 2 1 35 25 25 2 65 5 2 1 5 25 2 1 35 25 25 2 64 5 2 . 6 5 1 5 25 2 1 35 25 25 2 60 15 . 2 6 6 7 . 7 70 2 7 95 25 25 2 65 25 2 6 7 . 7 70 2 7 95 25 25 2 65 5 2 1 6 7 . 7 70 2 7 95 25 25 2 64 5 2 . 6 5 1 6 7 . 7 70 2 7 95 25 25 2 60 15 . 2 6 5 2 15 2 6 5 15 25 25 2 65 25 2 5 2 15 2 6 5 15 25 25 2 65 5 2 1 5 2 15 2 6 5 15 25 25 2 64 5 2 . 6 5 1 5 2 15 2 6 5 15 25 25 2 60 15 . 2 6 2 5 . 5 5 10 4 4 9 15 25 25 2 65 25 2 2 5 . 5 5 10 4 4 9 15 25 25 2 65 5 2 1 2 5 . 5 5 10 4 4 9 15 25 25 2 64 5 2 . 6 5 1 2 5 . 5 5 10 4 4 9 15 25 25 2 60 15 . 2 6
idt ? / ics ? vcxo jitter attenuator/multiplier 6 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 4a. p ower s upply dc c haracteristics , v dd = v ddo_qa = v ddo_qb = v ddx = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v ddo_qa = v ddo_qb = v ddx = 3.3v5%, t a = -40c to 85c note 1: outputs terminated with 50 to v ddo_qa,_qb /2. a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 32 lead vfqfn 37c/w (0 mps) 32 lead tqfp 32.2c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 1 1 . 0 ?3 . 3v d d v v , a q _ o d d v b q _ o d d e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v v x d d e g a t l o v y l p p u s p m u p e g r a h c5 3 1 . 33 . 35 6 4 . 3v i d d i + x d d p m u p e g r a h c d n a r e w o p t n e r r u c y l p p u s 8 5 1a m i a d d t n e r r u c y l p p u s g o l a n a 1 1a m i a q _ o d d i + b q _ o d d t n e r r u c y l p p u s t u p t u o 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n ie g a t l o v h g i h2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , l e s _ k l c , ] 1 : 0 [ _ l e s a d o ] 1 : 0 [ _ l e s b d o v d d v = n i v 5 6 4 . 3 =0 5 1a ] 2 : 0 { l e s d pv d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , l e s _ k l c , ] 1 : 0 [ _ l e s a d o ] 1 : 0 [ _ l e s b d o v d d v , v 5 6 4 . 3 = n i v 0 =5 -a ] 2 : 0 { l e s d pv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v
idt ? / ics ? vcxo jitter attenuator/multiplier 7 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 4c. d ifferential dc c haracteristics , v dd = v ddo_qa = v ddo_qb = v ddx = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i , 0 k l c n / 0 k l c 1 k l c n / 1 k l c v n i v = d d v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c , 0 k l cv n i v , v 0 = d d v 5 6 4 . 3 =5 -a 1 k l c n , 0 k l c nv n i v , v 0 = d d v 5 6 4 . 3 =0 5 1 -a v p p 1 e t o n ; e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v v : 1 e t o n l i . v 3 . 0 - n a h t s s e l e b t o n d l u o h s v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 5. ac c haracteristics , v dd = v ddo_qa = v ddo_qb = v ddx = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 8 0 0 . 02 5 . 5 5 1z h m f t u o y c n e u q e r f t u p t u o 5 25 2 . 6 5 1z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n l a t s y r c z h m 5 2 , z h m 5 2 1 : e g n a r n o i t a r g e t n i z h m 0 2 - z h k 2 1 5 . 1s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 0 6s p c d oe l c y c y t u d t u p t u o 0 5% t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p t k c o l e m i t k c o l l l p 0 0 1s m . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . s n o i t d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m
idt ? / ics ? vcxo jitter attenuator/multiplier 8 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary p arameter m easurement i nformation p hase j itter d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% -1.65v5% v dd , v ddo_qa, v ddo_qb, v ddx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power o utput s kew v dda 1.65v5% v cmr cross points v pp gnd nclk0, nclk1 v dd clk0, clk1 t sk(o) v ddo 2 v ddo 2 foutx fouty o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /tp eriod t period t pw t period odc = v ddo 2 x 100% t pw qa, qb clock outputs 20% 80% 80% 20% t r t f
idt ? / ics ? vcxo jitter attenuator/multiplier 9 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary a pplication i nformation p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics810252i-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v ddx , v dda , v ddo_qa and v ddo_qb should be individually connected to the power sup- ply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 re- sistor along with a 10mf and a .01mf bypass capacitor should be connected to each v dda pin. f igure 1. p ower s upply f iltering v dd v ddx v dda 3.3v 10 10 10f .01f .01f 10f .01f i nputs : c rystal i nputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. clk/nclk i nput for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utputs all unused lvcmos output can be left floating. there should be no trace attached.
idt ? / ics ? vcxo jitter attenuator/multiplier 10 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary f igure 2. s ingle e nded s ignal d riving d ifferential i nput figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
idt ? / ics ? vcxo jitter attenuator/multiplier 11 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary f igure 3c. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver f igure 3a. h i p er c lock s clk/nclk i nput d riven by an idt o pen e mitter h i p er c lock s lvhstl d river component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/nclk i nput d riven by a 3.3v hcsl d river zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 zo = 50 hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 f igure 3f. h i p er c lock s clk/nclk i nput d riven by a 2.5v sstl d river clk nclk hiperclocks sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
idt ? / ics ? vcxo jitter attenuator/multiplier 12 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary exposed pad expose metal pad (ground pad) ground plane solder signal trace signal trace therm al via solder m ask f igure 5. p.c. b oard for e xposed p ad t hermal r elease p ath e xample tqfp t hermal r elease p ath the expose metal pad provides heat transfer from the device to the p.c. board. the expose metal pad is ground pad connected to ground plane through thermal via. the exposed pad on the device to the exposed metal pad on the pcb is contacted through solder as shown in figure 5. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology. f igure 4. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base package, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? vcxo jitter attenuator/multiplier 13 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary f igure 6. s chematic of r ecommended l ayout l ayout g uideline figure 6 shows an example of the 810252i-03 application schematic. in this example, the device is operated at v dd = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver.
idt ? / ics ? vcxo jitter attenuator/multiplier 14 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a crystal, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines its resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal c l is lower than the total external capacitance, the vcxo will oscillate at a lower frequency than vcxo-pll l oop b andwidth s election t able h t d i w d n a b) z h m ( y c n e u q e r f l a t s y r cr s k ( )c s ) f (c p ) f (r t e s k ( ) ) w o l ( z h 0 5z h m 5 20 2 10 . 11 0 . 08 . 8 ) d i m ( z h 0 5z h m 5 21 2 21 . 01 0 0 . 01 2 . 2 ) h g i h ( z h 0 5 1z h m 5 20 8 61 . 01 0 0 0 . 01 2 . 2 c rystal c haracteristics vcxo c haracteristics t able l o b m y sr e t e m a r a pm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a r e p o f o e d o ml a t n e m a d n u f f n y c n e u q e r f5 2z h m f t e c n a r e l o t y c n e u q e r f0 2 m p p f s y t i l i b a t s y c n e u q e r f0 2 m p p e g n a r e r u t a r e p m e t g n i t a r e p o0 4 -5 8c c l e c n a t i c a p a c d a o l0 1f p c o e c n a t i c a p a c t n u h s4f p c o /c 1 o i t a r y t i l i b a l l u p0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e0 2 l e v e l e v i r d1w m c 5 2 @ g n i g ar a e y r e p 3 m p p l o b m y sr e t e m a r a pl a c i p y tt i n u k o x c v n i a g o x c v0 0 0 8v / z h c w o l _ v e c n a t i c a p a c r o t c a r a v w o l8f p c h g i h _ v e c n a t i c a p a c r o t c a r a v h g i h7 1f p the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the vcxo-pll loop bandwidth selection table shows r s , c s and c p values for recommended high, mid and low loop bandwidth configurations. the device has been characterized using these parameters. for other configurations, refer to the loop filter component selection for vcxo based plls application note. the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. lf0 lf1 iset xtal_in xtal_out r s c s c p r set c tune c tune 25mhz
idt ? / ics ? vcxo jitter attenuator/multiplier 15 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary r eliability i nformation t ransistor c ount the transistor count for ics810252i-03 is: 6597 t able 6a. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. 0 air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w t able 6b. ja vs . a ir f low t able for 32 l ead tqfp, e-p ad ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 32.2c/w 26.3c/w 24.7c/w
idt ? / ics ? vcxo jitter attenuator/multiplier 16 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary -hd version exposed pad down p ackage o utline - y s uffix for 32 l ead tqfp, e-p ad t able 7a. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s d h - a b a m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 2 . 1 1 a 5 0 . 00 1 . 05 1 . 0 2 a 5 9 . 00 . 15 0 . 1 b 0 3 . 05 3 . 00 4 . 0 c 9 0 . 0- -0 2 . 0 e , d c i s a b 0 0 . 9 1 e , 1 d c i s a b 0 0 . 7 2 e , 2 d . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0 3 d & 3 d 0 . 35 . 30 . 4
idt ? / ics ? vcxo jitter attenuator/multiplier 17 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary t able 7b. p ackage d imensions p ackage o utline and d imensions - k s uffix for 32 l ead vfqfn reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 0 . 5 2 e 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 7b below.
idt ? / ics ? vcxo jitter attenuator/multiplier 18 ics810252aki-03 rev. b october 24, 2007 ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 3 0 - i k a 2 5 2 0 1 83 0 i a 2 5 2 0 s c in f q f v d a e l 2 3y a r tc 5 8 o t c 0 4 - t 3 0 - i k a 2 5 2 0 1 83 0 i a 2 5 2 0 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 3 0 - i k a 2 5 2 0 1 8l 3 0 i a 2 5 2 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 3 0 - i k a 2 5 2 0 1 8l 3 0 i a 2 5 2 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - 3 0 - i y a 2 5 2 0 1 8d b td a p - e , p f q t d a e l 2 3y a r tc 5 8 o t c 0 4 - t 3 0 - i y a 2 5 2 0 1 8d b td a p - e , p f q t d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 3 0 - i y a 2 5 2 0 1 8l 3 0 i a 2 5 2 0 s c id a p - e , p f q t " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 3 0 - i y a 2 5 2 0 1 8l 3 0 i a 2 5 2 0 s c id a p - e , p f q t " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics810252i-03 vcxo jitter attenuator & femtoclock? mul tiplier preliminary

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